Instruction processing method and device and chip

Abstract

The invention provides an instruction processing method and device and a chip, and the method comprises the steps: enabling an MCU to transmit a first instruction group to a TPU when determining that a tensor processing unit TPU is in an idle state; wherein the first instruction group is acquired by the MCU under the condition that the TPU is in an occupied state, and the TPU is in the occupied state and is used for indicating the TPU to process the second instruction group, so that when the TPU processes the second instruction, the TPU is in the occupied state, and meanwhile, the MCU concurrently acquires the first instruction group; under the condition that the TPU is in the idle state, the MCU sends the first instruction group to the TPU, so that the TPU processes the first instruction group; when the TPU is in the occupied state, the MCU is not idle, and the first instruction group is acquired in parallel, so that the idle time of the MCU is shortened, the idle time of the TPU is also shortened, the processing efficiency of the instruction group is accelerated, and the delay is also reduced.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and in particular to an instruction processing method, apparatus and chip. Background Technology

[0002] In modern embedded systems and edge artificial intelligence (AI) applications, the microcontroller unit (MCU) typically plays the role of the core controller. It is responsible for system resource management, peripheral interaction, and coordinating the operation of different hardware modules. Meanwhile, the tensor processing unit (TPU), as a dedicated AI accelerator, focuses on performing high-intensity neural network computation tasks.

[0003] In the aforementioned computing architecture, the MCU improves the overall AI processing capability and energy efficiency of the system by offloading computationally intensive tasks to the TPU. However, during the collaborative work between the MCU and the TPU, the MCU spends a significant amount of time idle, resulting in low task processing efficiency. Summary of the Invention

[0004] To overcome the problems existing in the related technologies, this disclosure provides an instruction processing method, apparatus and chip to solve the problem of low task processing efficiency in the related technologies.

[0005] According to a first aspect of the present disclosure, an instruction processing method is provided, the method comprising:

[0006] When the microcontroller unit (MCU) determines that the tensor processing unit (TPU) is in an idle state, it sends a first instruction group to the TPU. The first instruction group is acquired by the MCU when the TPU is in an occupied state. The TPU being in an occupied state is used to instruct the TPU to process a second instruction group, and the TPU being in an idle state is used to instruct the TPU to complete the processing of the previous instruction group of the first instruction group.

[0007] In some embodiments, before the MCU sends the first instruction group to the TPU, the method further includes:

[0008] The MCU determines the second instruction group from at least one instruction group based on a first execution duration corresponding to at least one instruction group; wherein the first execution duration includes the time required for the TPU to execute the instruction group;

[0009] When the MCU determines that the TPU is in an idle state, it sends the second instruction group to the TPU for the TPU to process the second instruction group; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the second instruction group or that the TPU has been powered on for the first time.

[0010] In some embodiments, the MCU determines the second instruction group from at least one instruction group based on a first execution duration corresponding to at least one instruction group, including:

[0011] The MCU acquires the first execution duration corresponding to at least two of the instruction groups;

[0012] The MCU determines the maximum execution time based on at least two first execution durations;

[0013] The MCU uses the instruction group corresponding to the extreme execution time as the second instruction group.

[0014] In some embodiments, the MCU determines the second instruction group from at least one instruction group based on a first execution duration corresponding to at least one instruction group, including:

[0015] The MCU compares the first execution duration corresponding to the instruction group with a first preset threshold; wherein, the first preset threshold is related to the instruction group acquisition duration;

[0016] The MCU determines a first execution duration that is greater than or equal to the first preset threshold as the second execution duration;

[0017] The MCU uses the instruction group corresponding to the second execution duration as the second instruction group.

[0018] In some embodiments, the method further includes:

[0019] The MCU determines a first execution duration that is less than the first preset threshold as a fourth execution duration;

[0020] The MCU uses the instruction group corresponding to the fourth execution duration as the third instruction group;

[0021] When the MCU determines that the TPU is in an idle state, it sends the third instruction group to the TPU for the TPU to process; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the third instruction group or that the TPU has been powered on for the first time.

[0022] When the MCU determines that the TPU is in an idle state, it acquires a fourth instruction group; wherein, the TPU being in an idle state is used to instruct the TPU to complete the processing of the third instruction group.

[0023] In some embodiments, after the MCU sends the second instruction group to the TPU, the method further includes:

[0024] The MCU determines the index based on the third execution duration, instruction group transmission duration, and instruction group acquisition duration corresponding to the second instruction group;

[0025] The MCU acquires at least one fifth instruction group; wherein the number of the fifth instruction groups is an exponential number, and the at least one fifth instruction group includes the first instruction group;

[0026] The MCU determines the first instruction group from at least one of the fifth instruction groups.

[0027] In some embodiments, the MCU determines the index based on the third execution duration, instruction group transmission duration, and instruction group acquisition duration corresponding to the second instruction group, including:

[0028] The MCU obtains a first difference based on the third execution duration and the instruction group transmission duration;

[0029] The MCU rounds down the ratio of the first difference to the instruction group acquisition time to obtain the first ratio.

[0030] The MCU uses the first ratio as the index; and / or determines the index based on the first ratio and the number of instruction groups; wherein the number of instruction groups includes the number of instruction groups stored in memory.

[0031] In some embodiments, after the MCU sends the second instruction group to the TPU, the method further includes:

[0032] The MCU acquires at least one fifth instruction group; wherein the number of the fifth instruction groups is a preset number, and the at least one fifth instruction group includes the first instruction group.

[0033] In some embodiments, the method further includes:

[0034] The MCU determines the detection time based on the third execution duration corresponding to the second instruction group;

[0035] Based on the detection time, the MCU uses a probe to determine whether the TPU is in an occupied or idle state.

[0036] In some embodiments, the instruction set includes at least one executable instruction; the execution duration is determined based on at least one of the following:

[0037] The historical execution time corresponding to the historical instruction group;

[0038] The number of executable instructions included in the instruction set;

[0039] Executable instructions include opcodes;

[0040] TPU performance parameters.

[0041] Secondly, an instruction processing apparatus is provided, the apparatus comprising:

[0042] The MCU is used to send a first instruction group to the TPU when it is determined that the Tensor Processing Unit (TPU) is in an idle state; wherein, the first instruction group is obtained by the MCU when the TPU is in an occupied state, the occupied state is used to instruct the TPU to process a second instruction group, and the idle state is used to instruct the TPU to complete the processing of the previous instruction group of the first instruction group.

[0043] Thirdly, a chip is provided, the chip comprising the apparatus described in the second aspect above.

[0044] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0045] The MCU sends the second instruction group to the TPU, which processes it. While the TPU is processing the second instruction, it is in an occupied state, and simultaneously, the MCU concurrently acquires the first instruction group. When the TPU is idle, the MCU sends the first instruction group to it so that the TPU can process it. This ensures that the MCU is not idle while the TPU is occupied, as it concurrently acquires the first instruction group, reducing the MCU's idle time. Furthermore, when the TPU is idle, the MCU can send the next instruction group to it, further reducing the TPU's idle time. This improves the efficiency and performance of instruction group processing, increases the throughput of instruction groups, and reduces latency.

[0046] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0048] Figure 1This is a schematic diagram of an interaction between an MCU and a TPU in related technologies;

[0049] Figure 2 This is a flowchart of an instruction processing method provided in an embodiment of this disclosure;

[0050] Figure 3 This is a schematic diagram of an interaction between an MCU and a TPU provided in an embodiment of this disclosure;

[0051] Figure 4 This is a flowchart of another instruction processing method provided in this embodiment of the disclosure;

[0052] Figure 5 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of this disclosure;

[0053] Figure 6 This is a schematic diagram of the structure of a chip provided in an embodiment of this disclosure. Detailed Implementation

[0054] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0055] Figure 1 This is a schematic diagram of an interaction between an MCU and a TPU in related technologies, such as... Figure 1 As shown, the MCU typically sends tasks to the TPU in a synchronous blocking mode. That is, during cycles 00 to 01, the MCU acquires the first set of instructions; during cycles 01 to 02, the MCU sends the first set of instructions to the TPU to start the TPU task. Leftward slashes represent operations performed by the MCU, and rightward slashes represent operations performed by the TPU. Figure 1 The upper part represents the operations performed by the MCU in different cycles, and the lower part represents the operations performed by the TPU in different cycles.

[0056] During cycles 01 to 08, the TPU receives and executes the first set of instructions. During cycles 02 to 08, the TPU executes the first set of instructions. While the TPU is executing the first set of instructions, the MCU waits for the TPU to finish. When the first set of instructions is completed, the MCU will retrieve the second set of instructions in the next cycle (08 to 09). During cycles 08 to 09, the TPU has no tasks to execute, and its computing power is idle. Only during cycles 09 to 10 will the MCU send the second set of instructions to the TPU, and the TPU will then execute the second set of instructions.

[0057] In related technologies, as mentioned above Figure 1 The interaction between the MCU and TPU is usually synchronous. After the MCU sends instructions or data to the TPU, it enters a blocked state. This means that when the MCU sends a computation task request to the TPU, the MCU often has to wait for the TPU to complete the task before it can continue to execute its subsequent logic. This is a waste of MCU computing resources: while the TPU is busy computing, the MCU is in a waiting state, and its valuable processing power is idle. It cannot perform other important system management, data acquisition, or user interface processing tasks at the same time, which reduces the concurrency and responsiveness of the entire chip.

[0058] Low system throughput: Synchronous scheduling limits the parallelism of tasks; if there are multiple AI tasks in the chip that need to be processed by the TPU, or if the MCU needs to interact with the TPU frequently, the synchronous waiting mechanism will serialize these operations, which severely limits the overall throughput of the chip.

[0059] High latency and uncertainty: For applications with high real-time requirements, synchronous waiting can introduce unpredictable delays. When TPU task execution times fluctuate significantly, the MCU response time will also fluctuate, making it difficult to meet strict real-time requirements.

[0060] The MCU waits for the TPU to complete its task by polling or waiting for an interrupt. This interaction method, in terms of task scheduling and execution synchronization, results in the MCU remaining idle while the TPU is active, failing to fully utilize its resources.

[0061] To address the aforementioned issues, this disclosure provides an instruction processing method and chip. The method aims to allow the MCU to concurrently acquire the first instruction group while the TPU processes the second instruction group. Once the TPU has finished processing the first instruction group, it enters an idle state, and the MCU sends the first instruction group back to the TPU. This reduces the idle time of both the MCU and TPU, accelerates instruction group processing efficiency, improves the throughput of MCU-TPU collaborative instruction group processing, and effectively masks latency. The instruction processing method is described in detail below.

[0062] Figure 2 This is a flowchart of an instruction processing method provided in an embodiment of this disclosure, such as... Figure 2 As shown, it includes:

[0063] Step 202: When the microcontroller unit (MCU) determines that the tensor processing unit (TPU) is in an idle state, it sends the first instruction group to the TPU. The first instruction group is obtained by the MCU when the TPU is in an occupied state. The occupied state of the TPU is used to instruct the TPU to process the second instruction group. The idle state of the TPU is used to instruct the TPU to complete the processing of the previous instruction group of the first instruction group.

[0064] In this embodiment of the disclosure, the instruction processing method can be applied to a chip. The chip includes an MCU and a TPU, and also includes memory, which can be used to store instruction sets. The memory is connected to the MCU, and the MCU is used to retrieve instruction sets from the memory. The instruction set includes at least one executable instruction.

[0065] Memory can be used to store instruction groups categorized by task, with each instruction group corresponding to one task. For example, the first task instructs the calculation of the product between two matrices. When the first task is completed with 7 executable instructions, the first instruction group corresponding to the first task includes 7 executable instructions, and the TPU can process the first instruction group to obtain the first calculation result. The second task instructs the accumulation of numbers from 1 to 16. When the second task is completed with 8 executable instructions, the second instruction group corresponding to the second task includes 8 executable instructions, and the TPU can process the second instruction group to obtain the second calculation result. The third task instructs the calculation of the sum of the first and second calculation results, and the third instruction group corresponding to the third task includes 1 executable instruction.

[0066] That is, the number of executable instructions included in each instruction group can be different, or the same. Furthermore, there is no dependency between the first and second instruction groups, but a dependency exists between the first and third instruction groups; a dependency also exists between the second and third instruction groups. In other words, any two instruction groups may or may not have a dependency relationship.

[0067] The TPU can be in an occupied state or an idle state. When the TPU is in an occupied state, it means that the TPU is processing a group of instructions. When the TPU is in an idle state, it means that the TPU is not processing a group of instructions. That is, the TPU is in an occupied state every time it is processing a group of instructions, and it will be in an idle state after processing a group of instructions.

[0068] The MCU can be in an occupied or idle state. When the MCU is in an occupied state, it means that the MCU is fetching instruction sets from memory or sending instruction sets to the TPU. When the MCU is in an idle state, it means that the MCU is not fetching or sending instruction sets. The second instruction set refers to the instruction set that can be executed concurrently by the MCU. That is, while the TPU is processing the second instruction set, the MCU can concurrently fetch the first instruction set from memory.

[0069] For example, the second instruction group is the same as the first instruction group mentioned above. The MCU sends the first instruction group to the TPU: the TPU calculates the product between two matrices. When the TPU receives the first instruction group, its state changes from idle to occupied, and the TPU calculates the product of the two matrices; the MCU concurrently acquires the second instruction group; when the TPU obtains the first calculation result, its state changes from occupied to idle; after determining that the TPU is in an idle state, the MCU sends the second instruction group to the TPU, so that when the TPU is in an occupied state, i.e., processing the second instruction group, the MCU can concurrently acquire the first instruction group, which is the instruction group that the TPU will process next.

[0070] Of course, before the TPU processes the first instruction group, it can process the second instruction group, and the instruction group preceding the first instruction group can be the second instruction group; alternatively, before processing the first instruction group, the TPU can process an instruction group that is not the second instruction group, and the instruction group preceding the first instruction group may not be the second instruction group. That is, after the TPU processes the second instruction group, the next instruction group that the TPU processes can be the first instruction group, or it may not be the first instruction group.

[0071] In this embodiment, the MCU sends the second instruction group to the TPU, and the TPU processes the second instruction group. While the TPU is processing the second instruction, the TPU is in an occupied state, and simultaneously, the MCU concurrently acquires the first instruction group. When the TPU is in an idle state, the MCU sends the first instruction group to the TPU so that the TPU processes the first instruction group. Thus, while the TPU is in an occupied state, the MCU is not idle and concurrently acquires the first instruction group, reducing the idle time of the MCU. Furthermore, when the TPU is idle, the MCU can send the next instruction group to be processed to the TPU, which also reduces the idle time of the TPU, speeds up the processing efficiency and performance of instruction groups, increases the throughput of instruction groups, and reduces latency.

[0072] In this disclosure, the device used to store the instruction set can be memory, cache, register, memory, or other devices capable of reading and writing the instruction set; this disclosure uses the storage of instructions in memory as an example for illustration.

[0073] In some embodiments, before the MCU sends the first instruction group to the TPU, the method further includes steps 2011 to 2012, wherein:

[0074] Step 2011: The MCU determines a second instruction group from the at least one instruction group based on the first execution duration corresponding to the at least one instruction group; wherein the first execution duration includes the time required for the TPU to execute the instruction group;

[0075] Step 2012: When the MCU determines that the TPU is in an idle state, it sends the second instruction group to the TPU for the TPU to process the second instruction group; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the second instruction group or that the TPU has been powered on for the first time.

[0076] In this embodiment of the disclosure, each instruction group may correspond to a first execution duration, which is the estimated time required for the TPU to process the instruction group. When the instruction group is stored in memory, the first execution duration corresponding to the instruction group may be stored.

[0077] The first execution duration can be a single value or a range of values. For example, the first execution duration of one instruction group is 5 preset cycles, and the first execution duration of another instruction group is 4 to 6 preset cycles.

[0078] Table 1 is an example table of the correspondence between instruction groups and execution duration provided in the embodiments of this disclosure. As shown in Table 1, the estimated execution duration can represent the first execution duration of the instruction group. For example, the first execution duration of the first instruction group is 5 preset cycles, and the preset cycle may include a clock cycle.

[0079] Table 1. Example of the correspondence between instruction groups and execution duration.

[0080] instruction group Task Estimated execution time TPU calculation results First instruction group Used to calculate the product of the first matrix and the second matrix. 5 preset cycles First calculation result Second instruction group Used to calculate 1 + 2 + ... + 16 3 preset cycles Second calculation result The third instruction group Used to calculate the first calculation result + the second calculation result 1 preset cycle Third calculation result Fourth instruction group Used to calculate the square root of a number 4 to 6 preset cycles Fourth calculation result

[0081] As shown in Table 1 above, the TPU performs calculations on the first instruction group to obtain the first calculation result; it performs calculations on the second instruction group to obtain the second calculation result; the third instruction group has a dependency relationship with the first and second instruction groups, and the third instruction group can be completed within one preset cycle.

[0082] As shown in Table 1 above, the fourth instruction group has no dependency relationship with the first to third instruction groups. The estimated first execution time of the fourth instruction is 4 to 6 preset cycles. The TPU calculates the fourth instruction group and can obtain the fourth calculation result.

[0083] As shown in Table 1 above, the MCU can select the second instruction group from the four instruction groups, allowing the TPU to process some instruction groups while the MCU acquires the next instruction group; while processing other instruction groups, the MCU can be idle. Alternatively, the MCU can determine whether an instruction group is the second instruction group before sending it to the TPU; or, the MCU supports multi-threaded processing, allowing it to determine whether a sent instruction group is the second instruction group while sending it to the TPU, thus avoiding the problem of instruction groups not being sent to the TPU in a timely manner due to the need to determine whether an instruction group is the second instruction group; or, the MCU can determine whether an instruction group is the second instruction group after sending it to the TPU.

[0084] Before the MCU sends the second instruction set to the TPU, the TPU may be processing an instruction set preceding the second instruction set. After the TPU finishes processing the instruction set, it will be in an idle state, at which point the MCU sends the second instruction set to the TPU for processing. Alternatively, upon initial power-up of both the TPU and MCU, the MCU retrieves the second instruction set from memory and then sends it to the TPU; the second instruction set is the first instruction set processed by the TPU after power-up.

[0085] In some embodiments, step 2011 includes steps 301 to 303, wherein:

[0086] Step 301: The MCU obtains the first execution duration corresponding to at least two instruction groups;

[0087] Step 302: The MCU determines the maximum execution time based on at least two first execution durations;

[0088] Step 303: The MCU uses the instruction group corresponding to the maximum execution time as the second instruction group.

[0089] In this embodiment of the disclosure, the MCU can compare the first execution durations corresponding to multiple instruction groups to select a second instruction group from the multiple instruction groups. The maximum execution duration can refer to the largest first execution duration among at least two first execution durations.

[0090] When the first execution duration is a period of time, it includes a first sub-duration and a second sub-duration. The first sub-duration can refer to the minimum value that the first duration can take, and the second sub-duration can refer to the maximum value that the first duration can take. When the first execution duration is a period of time, either the first sub-duration or the second sub-duration of the first execution duration can be used for comparison; alternatively, an average sub-duration can be calculated based on the first and second sub-durations, and this average sub-duration can be used for comparison.

[0091] For example, as shown in Table 1 above, the MCU can obtain the first execution duration of four instruction groups from memory, or the MCU has already obtained four instruction groups and determines the first execution duration of each instruction group. The first execution duration of the fourth instruction group is a time period, with the first sub-duration being 4 preset cycles, the second sub-duration being 6 preset cycles, and the average sub-duration being 5 preset cycles. When the second sub-duration of the fourth instruction group is included in the comparison, the six first execution durations are arranged in order of length as follows: 6 preset cycles, 5 preset cycles, 3 preset cycles, and 1 preset cycle, with the maximum execution duration being 6 preset cycles. Therefore, the fourth instruction group can be considered the second instruction group.

[0092] Alternatively, when the first sub-duration of the fourth instruction group is included in the comparison, the six first execution durations are arranged in order of length as follows: 5 preset cycles, 4 preset cycles, 3 preset cycles, and 1 preset cycle, with a maximum execution duration of 5 preset cycles. In this case, the first instruction group can be designated as the second instruction group. When the average sub-duration of the fourth instruction group is included in the comparison, the six first execution durations are arranged in order of length as follows: 5 preset cycles, 5 preset cycles, 3 preset cycles, and 1 preset cycle, with a maximum execution duration of 5 preset cycles. In this case, the first instruction group and / or the fourth instruction group can be designated as the second instruction group.

[0093] Figure 3 This is a schematic diagram of an interaction between an MCU and a TPU provided in this disclosure, such as... Figure 3 As shown, within the 00 to 01 cycle, the MCU acquires the second instruction group; the first execution duration corresponding to the second instruction group can be greater than or equal to the first preset threshold.

[0094] The second instruction group is the first set of instructions received by the TPU. During cycles 01 to 02, the MCU sends the second instruction group to the TPU to start the TPU task. Alternatively, the MCU can configure the TPU based on the second instruction group so that the configured TPU can calculate the result of the first set of instructions. During cycles 01 to 08, the TPU receives and executes the second instruction group. During cycles 02 to 08, the TPU executes the first set of instructions. While the TPU is executing the first set of instructions, the MCU fetches the next instruction group from memory; that is, during cycles 02 to 03, the MCU fetches the first instruction group from memory. During cycles 03 to 08, the MCU waits for the TPU to finish executing the second instruction group and remains idle, thus... Figure 1 This reduces the time the MCU is idle. When the TPU is occupied, the MCU can use its resources to asynchronously prefetch the next instruction set.

[0095] When the TPU finishes executing the second instruction group, the MCU sends the prefetched first instruction group to the TPU, thus reducing the time the TPU is idle; and compared to Figure 1 This reduces the time the MCU takes to fetch an instruction set while the TPU is idle, thus eliminating the time the TPU waits for the MCU to fetch instructions. This improves the efficiency and performance of instruction set processing, reduces the processing time of instruction sets, and effectively increases the throughput of MCU-TPU collaboration, enabling the MCU and TPU to concurrently process different aspects of the overall task.

[0096] In some embodiments, after step 302, the method further includes steps 304 to 307, wherein:

[0097] Step 304: The MCU designates the instruction group corresponding to the first execution duration (excluding the maximum execution duration) as the sixth instruction group.

[0098] Step 305: When the MCU determines that the TPU is in an idle state, it sends the sixth instruction group to the TPU; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the sixth instruction group or that the TPU has been powered on for the first time.

[0099] Step 306: The TPU processes the sixth instruction group;

[0100] Step 307: If it is determined that the TPU is in an idle state, obtain the next instruction group; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the sixth instruction group.

[0101] In this embodiment of the disclosure, steps 303 and 304 belong to two different branches. Step 2012 can be executed according to the instruction group being the second instruction group; steps 305 to 307 can be executed according to the instruction group being the sixth instruction group. The sixth instruction group is used to indicate that concurrent operation of the MCU is not supported, that is, while the TPU processes the sixth instruction group, the MCU is in an idle state.

[0102] The next instruction set in step 307 refers to the instruction set that the MCU has not yet fetched from memory, and is also the instruction set that the MCU is about to fetch. The next instruction set fetched by the MCU can also be determined based on step 2011 whether it is an instruction set that supports concurrent operation of the MCU.

[0103] As shown in Table 1 above, and in conjunction with the above... Figure 3When the second instruction group is the first instruction group, the multiple sixth instruction groups include: the second instruction group, the third instruction group, and the fourth instruction group. When the TPU is in an idle state, the MCU can send the second instruction group, the third instruction group, or the fourth instruction group to the TPU. While the TPU is processing the second instruction group, the third instruction group, or the fourth instruction group, the MCU will not acquire the next instruction group.

[0104] The order in which the MCU sends the second, third, or fourth instruction group to the TPU can be out of order or according to the instruction group retrieval time. The instruction group retrieval time can refer to the order in which the MCU retrieves the instruction groups. If the MCU retrieves the instruction groups in the order of second, fourth, and third, the MCU can send the second instruction group to the TPU first, then the fourth, and finally the third. Alternatively, the instruction group retrieval time can be determined by the dependency relationship between the instruction groups. Since the second and third instruction groups are dependent, the instruction group retrieval time can be in the order of second, third, and fourth. The MCU can send the second instruction group to the TPU first, then the third, and finally the fourth.

[0105] The MCU can determine the maximum execution time from multiple first execution times, designating the instruction group corresponding to the maximum execution time as the second instruction group, and the instruction groups corresponding to the first execution times other than the maximum execution time as the sixth instruction group. Thus, the MCU can acquire the next instruction group while the TPU is processing the second instruction group. While the TPU is processing the second instruction group, the MCU is in an idle state, preventing the MCU from acquiring the next instruction group while the TPU is processing each instruction group, and preventing the MCU from storing a large number of unprocessed instruction groups.

[0106] In some embodiments, step 201 includes steps 401 to 403, wherein:

[0107] Step 401: The MCU compares the first execution duration corresponding to the instruction group with the first preset threshold; wherein, the first preset threshold is related to the instruction group acquisition duration;

[0108] Step 402, the MCU determines a first execution duration that is greater than or equal to a first preset threshold as the second execution duration;

[0109] Step 403: The MCU uses the instruction group corresponding to the second execution duration as the second instruction group.

[0110] In this embodiment of the disclosure, the instruction group acquisition time includes the time required for the MCU to acquire one instruction group from memory. The first preset threshold may be greater than or equal to the instruction group acquisition time.

[0111] The MCU fetching instruction sets from memory can include obtaining the address of the stored instruction set from memory. For example, if the address of the first instruction set in memory is between 0 and 1023, the MCU sends the address of the first instruction set in memory to the TPU. That is, even if the number of instructions included in each instruction set and the length of each instruction set are different, the instruction set fetching time required for each instruction set can be equal.

[0112] When comparing the first execution duration and the first preset threshold, if the first execution duration is a numerical value, the first execution duration and the first preset threshold can be compared directly; if the first execution duration is a duration range, the first sub-duration, the second sub-duration, or the average sub-duration can be compared with the first preset threshold.

[0113] The MCU can compare the first execution duration of each acquired instruction group with the first preset threshold. Assuming the instruction group acquisition duration is 1 preset cycle and the first preset threshold is 1.5 preset cycles, as shown in Table 1 above, the first execution durations corresponding to the first, second, and fourth instruction groups are all greater than the first preset threshold. The first execution durations corresponding to the first, second, and fourth instruction groups are all the second execution durations. The multiple second instruction groups are: the first instruction group, the second instruction group, and the fourth instruction group.

[0114] In some embodiments, the method further includes steps 404 to 408, wherein:

[0115] Step 404: The MCU determines the first execution duration, which is less than the first preset threshold, as the fourth execution duration;

[0116] Step 405: The MCU uses the instruction group corresponding to the fourth execution duration as the third instruction group;

[0117] Step 406: When the MCU determines that the TPU is in an idle state, it sends the third instruction group to the TPU; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the third instruction group or that the TPU has been powered on for the first time.

[0118] Step 407: The TPU processes the third instruction set;

[0119] Step 408: When the MCU determines that the TPU is in an idle state, it acquires the fourth instruction group; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the third instruction group.

[0120] In this embodiment of the disclosure, the fourth instruction group in step 408 refers to the instruction group that the MCU has not yet retrieved from memory, and is also the next instruction group that the MCU is about to retrieve. The fourth instruction group can be an instruction group that supports concurrent operation of the MCU, or it can be an instruction group that does not support concurrent operation of the MCU. That is, while the TPU is processing the fourth instruction group, the MCU can concurrently retrieve the next instruction group from memory according to the first execution duration corresponding to the fourth instruction group; or the MCU is in an idle state.

[0121] As shown in Table 1 above, and in conjunction with the above... Figure 1 The fourth execution time is one preset cycle, and the third instruction group is the third instruction group. When the TPU processes the second instruction group, the TPU is in an occupied state, and the MCU concurrently acquires the third instruction group; after the TPU finishes processing the second instruction group, the TPU will be in an idle state, and the MCU can send the third instruction group to the TPU; when the TPU processes the third instruction group, the TPU is in an occupied state; after the TPU finishes processing the third instruction group, the TPU is in an idle state, and the MCU acquires the fourth instruction group from memory.

[0122] Combining steps 401 to 408 above, the MCU will send the instructions to be processed to the TPU when the TPU is in an idle state. Assume the MCU can fetch one instruction set from memory at a time; that is, while the TPU is processing the first instruction set, the MCU can fetch the second instruction set from memory; while the TPU is processing the second instruction set, the MCU can fetch the third instruction set from memory; while the TPU is processing the third instruction set, the MCU can be in an idle state; after the TPU finishes processing the third instruction set, the MCU fetches the fourth instruction set from memory; while the TPU is processing the fourth instruction set, the MCU can fetch the next instruction set from memory.

[0123] Assume the MCU fetches two instruction sets from memory each time. That is, while the TPU is processing the first instruction set, the MCU can fetch the second and third instruction sets from memory; while the TPU is processing the second instruction set, the MCU can fetch the fourth and next instruction sets from memory; while the TPU is processing the third instruction set, the MCU can be in an idle state; after the TPU finishes processing the third instruction set, the MCU fetches two instruction sets from memory.

[0124] The MCU can determine whether the instruction group is the second instruction group or the third instruction group based on the first preset threshold and the first execution duration. The MCU can acquire the first instruction group while the TPU is processing the second instruction group. The MCU can acquire the fourth instruction group after the TPU has finished processing the third instruction group, so that the next instruction group will not be acquired concurrently when the first execution duration corresponding to the instruction group is too short.

[0125] In some embodiments, after the MCU sends the second instruction group to the TPU, steps 501 to 503 are further included, wherein:

[0126] Step 501: The MCU determines the index quantity based on the third execution duration, instruction group transmission duration, and instruction group acquisition duration corresponding to the second instruction group;

[0127] Step 502, the MCU acquires at least one fifth instruction group; wherein, the number of fifth instruction groups is an exponential number, and at least one fifth instruction group includes the first instruction group;

[0128] Step 503: The MCU determines the first instruction group from at least one fifth instruction group.

[0129] In this embodiment of the disclosure, the instruction group transmission duration refers to the time required for the MCU to send an instruction group to the TPU. The instruction group transmission duration can be a fixed value, meaning that the time required for the MCU to send each instruction group is the same. The time required for the MCU to send an instruction group is not affected by the number of executable instructions included in the instruction group or the length of the instruction group. The fetch quantity refers to the number of instruction groups to be fetched. The number of instruction groups to be fetched from memory can be determined by the third execution duration, the instruction group transmission duration, and the instruction group fetch duration. Therefore, the number of instruction groups that can be fetched each time can be dynamically determined by the third execution duration and the instruction group fetch duration.

[0130] As shown in Table 1 above, assuming the first instruction group is the first instruction group, the third execution duration is 5 preset cycles, the instruction group retrieval duration is 1 preset cycle, and the instruction group transmission duration is 1 preset cycle, and the exponent is taken as 2, that is, when the TPU processes the second instruction group, the MCU can retrieve two instruction groups from memory. Then, based on the instruction group retrieval time corresponding to the instruction group, the first instruction group is determined. The first instruction group in step 503 refers to the next instruction group sent to the TPU.

[0131] like Figure 3As shown, when the TPU processes the second instruction group, it requires 7 cycles, meaning the third execution time is 7 cycles, the instruction group sending time is 1 cycle, and the instruction group retrieval time for one instruction group from memory is 1 cycle. The MCU can retrieve instruction groups from memory within cycles 02 to 08. Within cycles 02 to 08, a maximum of 6 instruction groups can be retrieved from memory. This allows the MCU to fully utilize its resources while the TPU processes the second instruction group, retrieving as many instruction groups from memory as possible. This reduces the time required for the MCU to retrieve instruction groups from memory when multiple TPUs are idle, improving the processing speed and throughput of instruction groups, and also achieving effective latency masking.

[0132] In some embodiments, step 501 includes steps 5011 to 5013, wherein:

[0133] Step 5011: The MCU obtains the first difference based on the third execution duration and the instruction group transmission duration;

[0134] Step 5012: The MCU rounds the ratio of the first difference to the instruction group acquisition time to obtain the first ratio.

[0135] Step 5013: The MCU uses the first ratio as the index; and / or determines the index based on the first ratio and the number of instruction groups; wherein the number of instruction groups includes the number of instruction groups stored in memory.

[0136] In this embodiment of the disclosure, if the MCU executes steps 5011 to 5013, the first preset threshold in steps 401 to 404 can be made greater than or equal to the sum of the instruction group sending time and the instruction group acquisition time. That is, the difference between the first preset threshold and the instruction group sending time is calculated to obtain the second difference. The second difference being greater than or equal to the instruction group acquisition time means that within the second difference, the MCU can acquire at least one instruction group from memory.

[0137] The first difference is the maximum idle time the MCU can be in while the TPU is calculating the second instruction group. When the third execution time is a fixed value, the first difference can be obtained by subtracting the instruction group transmission time from the third execution time. When the third execution time is a range, the first difference can be obtained by subtracting the instruction group transmission time from the first sub-time, the second sub-time, or the average sub-time.

[0138] As shown in Table 1 above, when the second instruction group is the first instruction group, the third execution duration is 5 preset cycles, and the instruction group sending duration is 1 preset cycle, the index value is less than or equal to... The integer means that while the TPU is processing the first instruction group, the MCU can concurrently fetch four instruction groups from memory.

[0139] When the second instruction group is the fourth instruction group, the third execution duration is 4 to 6 preset cycles, and the instruction group transmission duration is 1 preset cycle, the difference between the second sub-duration and the instruction group transmission duration can be calculated, and the first difference is 5; the index value is less than or equal to The integer means that while the TPU is processing the fourth instruction group, the MCU can concurrently fetch 5 instruction groups from memory. Thus, while the TPU is calculating different second instruction groups, the MCU can dynamically fetch at least one fifth instruction group. At the same time, after the TPU finishes processing the second instruction group, the MCU can immediately send the first instruction group to the TPU, which also reduces the idle time of the TPU and speeds up the data processing rate and performance.

[0140] Because some instruction sets have dependencies, meaning that the result of one instruction set is the parameter required by another instruction set for calculation, the number of instruction sets stored in memory can change dynamically over time.

[0141] The exponent is taken as min[first ratio, number of instruction groups], meaning the exponent is the smaller of the first ratio and the number of instruction groups. When the first ratio is greater than the number of instruction groups, it means the number of instruction groups stored in memory is less than the number of instruction groups required by the MCU, and the memory can send the number of instruction groups to the MCU as a fifth instruction group, where the exponent is equal to the number of instruction groups. When the first ratio is less than or equal to the number of instruction groups, it means the number of instruction groups stored in memory is more than or equal to the number of instruction groups required by the MCU, and the memory can send the first ratio of instruction groups to the MCU as a fifth instruction group, where the exponent is equal to the first ratio.

[0142] This disclosure takes into account the number of instruction sets stored in memory and determines the index to be fetched by comparing a first ratio with the number of instruction sets. At least one of the following parameters may also be considered: the remaining storage space of the MCU, the number of unexecuted instruction sets stored in the MCU, etc., to determine the index to be fetched, so that the number of concurrent instruction fetches by the MCU is different, and the number of instruction sets fetched from memory will not exceed the number of instruction sets stored in memory, and the fetched instruction sets can be stored in the MCU, and the number of unexecuted instruction sets in the MCU will not be too large.

[0143] In some embodiments, after the MCU sends the second instruction group to the TPU, steps 601 to 602 are further included:

[0144] Step 601: The MCU acquires at least one fifth instruction group; wherein the number of fifth instruction groups is a preset number, and at least one fifth instruction group includes the first instruction group;

[0145] Step 602: The MCU determines the first instruction group from at least one fifth instruction group.

[0146] In this embodiment of the disclosure, the user or relevant personnel can set a preset number of concurrent instruction fetches by the MCU, so that the number of concurrent instruction fetches by the MCU can better meet the user's needs. For example, the preset number is equal to 1, that is, while the TPU is processing the second instruction group, the MCU can concurrently fetch 1 fifth instruction group from memory.

[0147] When determining the first instruction group from the first instruction group, it can be based on the instruction group acquisition time corresponding to each fifth instruction group. The instruction group acquisition time indicates the order in which the MCU receives each instruction group; the MCU can use the first received fifth instruction group as the first instruction group. Alternatively, the instruction group acquisition time indicates the dependency relationship between instruction groups; the MCU can use fifth instructions with strong dependencies as the first instruction group.

[0148] For example, when the instruction group fetch time represents the order in which the MCU receives each instruction group, referring to Table 1 above, the TPU is currently processing the first instruction group. The order in which the MCU fetches instruction groups from memory is the fourth instruction group, the second instruction group, and the third instruction group. The next instruction group sent to the TPU is the fourth instruction group, meaning the first instruction group is the fourth instruction group. When the instruction group fetch time represents the dependency relationship between instruction groups, the order in which the MCU fetches instruction groups from memory is the fourth instruction group, the second instruction group, and the third instruction group. However, since the parameters required to calculate the third instruction group are the first calculation result of the first instruction group and the second calculation result of the second instruction group, the second and third instruction groups have a strong dependency relationship. The next instruction group sent to the TPU is the second instruction group, and the next one after that is the third instruction group, meaning the first instruction group is the second instruction group.

[0149] Of course, if the time required to acquire the preset number of fifth instruction groups is longer than the third execution time, the MCU can acquire the preset number of fifth instruction groups first. Even if the TPU is in an idle state during the acquisition of the preset number of fifth instruction groups, the MCU will acquire the preset number of fifth instruction groups first, and then determine whether the TPU is in an idle state.

[0150] In some embodiments, the method further includes steps 701 to 702, wherein:

[0151] Step 701: The MCU determines the detection time based on the third execution duration corresponding to the second instruction group;

[0152] Step 702: Based on the detection time, the MCU uses a probe to determine whether the TPU is in an occupied or idle state.

[0153] In this embodiment of the disclosure, the MCU can determine whether the TPU is in an occupied or idle state using a probe. The MCU can determine the TPU's state in real time using the probe. Alternatively, the detection time can be determined first by a third execution duration, which refers to the time when the probe starts detecting, i.e., the probe's detection duration starts from the detection time and ends when the TPU is detected to be in an idle state. This can reduce the probe's detection duration and also reduce the power consumption of the probe.

[0154] For example, the MCU can start a countdown based on the third execution duration. When the countdown reaches 0, the MCU can determine the state of the TPU through a probe. When the third execution duration is a single value, the countdown can be started directly based on the third execution duration; when the third execution duration is a range of values, the countdown can be started based on the first sub-duration of the third execution duration, thereby reducing the energy consumption of determining the state of the TPU.

[0155] In some embodiments, the instruction set includes at least one executable instruction; the execution duration is determined based on at least one of the following:

[0156] The historical execution time corresponding to the historical instruction group;

[0157] The number of executable instructions included in the instruction set;

[0158] Executable instructions include opcodes;

[0159] TPU performance parameters.

[0160] In this embodiment of the disclosure, the execution time of an instruction group is affected by factors such as experience, device performance, the amount of data in the instruction group, and the complexity of the executable instructions. The first execution time of each instruction group can be determined by the MCU; the first execution time of each instruction group can be determined by a device connected to memory and having data processing capabilities.

[0161] Let's take the example of the MCU determining the first execution duration of each instruction group to illustrate this. After the MCU retrieves a seventh instruction group from memory, it can determine from the historical instruction groups whether there is an instruction group that is the same as the seventh instruction group. If so, the historical execution duration corresponding to the instruction group that is the same as the seventh instruction group is used as the first execution duration of the seventh instruction group.

[0162] When the first historical instruction group includes only a portion of the executable instructions of the seventh instruction group, but does not include the other portion of the executable instructions of the seventh instruction group; when the number of executable instructions in the seventh instruction group is greater than the number of executable instructions in the first historical instruction group, the first execution duration corresponding to the seventh instruction group is greater than the historical execution duration corresponding to the first historical instruction group.

[0163] Opcodes include, but are not limited to, at least one of the following: addition (ADD), subtraction (SUB), multiplication (MUL), division (DIV), square root, logarithm, exponentiation, trigonometric functions, etc. Different opcodes result in different computation times required by the TPU to calculate executable instructions. When the opcode is addition or subtraction, the TPU can complete the calculation within 1 to 3 preset cycles; when the opcode is multiplication, the TPU can complete the calculation within 3 to 8 preset cycles; when the opcode is division, the TPU can complete the calculation within 10 to 30 preset cycles, etc., which will not be elaborated further here.

[0164] The execution time of an instruction set can also be determined by the opcode and source operands included in the executable instruction. For example, an instruction set may include one executable instruction, which includes an opcode and two source operands. When performing addition and subtraction operations, if the source operands are all floating-point numbers, the TPU can complete the calculation within 2 to 3 preset cycles. If the source operands are all integers, the TPU can complete the calculation within 1 preset cycle.

[0165] TPU performance parameters reflect the performance of the TPU's instruction set. These parameters include, but are not limited to, at least one of the following: hardware parameters, pipeline parameters, and data transfer rate. For example, a TPU includes a dedicated arithmetic unit (ALU), which includes a multiply-accumulate unit. The multiply-accumulate unit compresses multiplication and other operations into one clock cycle, thus reducing the time required for multiplication calculations. Pipeline parameters reflect the rate at which the pipeline processes data in the TPU. When the TPU adopts a cutting-edge pipeline architecture (such as data forwarding technology), the processing time for executable instructions and the processing time for each instruction set can be shortened. The data transfer rate refers to the rate at which the MCU sends instruction sets to the TPU, or the rate at which the TPU receives instruction sets from the MCU. A higher data transfer rate reduces the time required to transmit instruction sets, shortens the processing time of instruction sets, and improves the processing efficiency of instruction sets.

[0166] In some embodiments, when the preset quantity is equal to 1, Figure 4 This is a flowchart of another instruction processing method provided in this disclosure embodiment, such as... Figure 4 As shown, steps 41 to 49 are included, wherein:

[0167] Step 41, instruction grouping;

[0168] Step 42, execution time estimation / identification;

[0169] Step 43: The MCU determines whether the execution time is the maximum value;

[0170] Step 44: The MCU waits for the TPU to finish executing and then sequentially executes the instruction fetch and instruction issue;

[0171] Step 45: Configure and start the TPU on the MCU;

[0172] Step 46: The MCU concurrently prefetches the next instruction group;

[0173] Step 47: After the MCU completes the prefetch, it queries the TPU status;

[0174] Step 48: The TPU will complete the execution of the instruction group corresponding to the maximum execution time.

[0175] Step 49: The MCU issues the next instruction group.

[0176] In this embodiment of the disclosure, the memory can group instructions. Instructions that complete the same task form an instruction group, and an instruction group may include at least one executable instruction. While storing instruction groups, the memory can also store a first execution duration corresponding to each instruction group. The first execution duration refers to the estimated time required for the TPU to execute the instruction group. For example, the memory can be connected to a device with the function of estimating the execution duration of instruction groups, and the device determines the first execution duration corresponding to each instruction group.

[0177] Alternatively, the MCU can read at least two instruction sets from memory and determine the first execution duration for each instruction set. For example, the MCU can retrieve the four instruction sets from memory shown in Table 1 above and then estimate the first execution duration for each instruction set.

[0178] Alternatively, the MCU can read the first execution duration corresponding to the four instruction groups from memory and determine the maximum value among the four first execution durations. For example, the MCU can obtain the first execution duration corresponding to the four instruction groups in Table 1 above from memory to determine the instruction group corresponding to the largest first execution duration.

[0179] For example, assuming the MCU is initially powered on, referring to Table 1 above, the MCU retrieves the first instruction group from memory; it retrieves the first execution duration corresponding to each of the four instruction groups in Table 1 from memory; the MCU determines whether the first execution duration corresponding to the first instruction group is the maximum value among the first execution durations corresponding to the four instruction groups; if it determines that the first execution duration corresponding to the first instruction group is the maximum value among the first execution durations corresponding to the four instruction groups, it sends the first instruction group to the TPU, that is, the MCU will configure the TPU according to the first instruction group so that the TPU can process the first instruction group.

[0180] Furthermore, after sending the first instruction set to the TPU, the MCU concurrently retrieves the next instruction set, that is, it retrieves the second instruction set from memory. While the TPU is processing the first instruction set, its state changes from occupied to idle. The MCU uses a probe to determine if the TPU is idle. If the TPU is in an occupied state, the MCU uses the probe to check if it is idle until it is detected that the TPU is idle. Once the TPU is found to be idle, the MCU sends the second instruction set to it. The TPU can also send the calculation result back to the MCU after processing the instruction set, that is, it sends the first calculation result obtained after calculating the first instruction set to the MCU.

[0181] When the TPU is processing the second instruction group, since the first execution time of the second instruction group is not the maximum value among the first execution times of the four instruction groups, the MCU will wait for the TPU to finish executing the second instruction group, that is, when the TPU is idle again, before fetching the third instruction group from memory and sending the third instruction group to the TPU.

[0182] The MCU compares the first execution durations corresponding to the four instruction groups. While the TPU processes the instruction group corresponding to the maximum of the four first execution durations, the MCU fetches the next instruction group from memory, thus significantly reducing scheduling latency and increasing throughput. By asynchronously starting TPU execution and prefetching the next instruction group from memory, the MCU's idle time is reduced. At the same time, since the MCU prefetches the next instruction from memory, the TPU can immediately receive the next instruction from the MCU after executing the previous instruction, which also significantly reduces the TPU's idle time and improves the effective duty cycle of the MCU and TPU. Furthermore, by overlapping the TPU execution latency with the MCU instruction prefetching, effective latency masking is achieved. By reducing idle time and effectively masking latency, the overall speed of MCU-TPU collaborative instruction group processing is improved. Moreover, a higher degree of parallelism is promoted between heterogeneous MCU-TPU collaboration, allowing the two devices to concurrently process different aspects of the overall task.

[0183] It also optimizes resource utilization and energy efficiency: ensuring that the MCU and TPU are active most of the time, thereby making more efficient use of their respective computing resources and improving resource utilization; and reducing the waste of preset cycles by minimizing MCU pause and idle time, thereby helping to improve the efficiency of the overall instruction set processing.

[0184] In this embodiment of the disclosure, the above steps can be combined to implement the instruction processing method. Steps 41 to 49 are only one combination method and do not limit the combination of each step to implement the instruction processing method.

[0185] In this disclosure, instruction groups one through seven merely represent the classification of instruction groups and do not indicate the order in which the MCU sends the instruction groups to the TPU; similarly, instruction groups one through four merely indicate the order of the instruction groups in Table 1 and do not indicate the order in which the MCU sends the instruction groups to the TPU. Furthermore, when determining the second instruction group from multiple instruction groups, the MCU does not send the second instruction group to the TPU first. Instead, while the TPU is executing the second instruction group, the MCU concurrently retrieves the next instruction group. For example, if the MCU has already retrieved the four instruction groups shown in Table 1 above from memory, and assuming the second instruction group is the fourth instruction group in Table 1, and the instruction group retrieval times are first instruction group, fourth instruction group, second instruction group, and third instruction group, the MCU will send the first instruction group when the TPU is idle; and send the second instruction group when the TPU is idle again.

[0186] Figure 5 This is a schematic diagram of the structure of an instruction processing device provided in an embodiment of this disclosure, as shown below. Figure 5 As shown, the instruction processing device 500 includes an MCU 501 and a TPU 502;

[0187] MCU 501 is used to send a first instruction group to TPU 502 when it is determined that TPU 502 is in an idle state; wherein, the first instruction group is obtained by MCU 501 when TPU is in an occupied state, TPU 502 being in an occupied state is used to instruct TPU 502 to process the second instruction group, and TPU being in an idle state is used to instruct TPU to complete the processing of the previous instruction group of the first instruction group.

[0188] In some embodiments, MCU 501 is configured to determine a second instruction group from at least one instruction group based on a first execution duration corresponding to at least one instruction group; wherein the first execution duration includes the duration required for TPU 502 to execute the instruction group; and, if it is determined that the TPU is in an idle state, send the second instruction group to the TPU for the TPU to process the second instruction group; wherein the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the second instruction group or that the TPU has been initially powered on.

[0189] In some embodiments, MCU 501 is used for:

[0190] Obtain the first execution duration corresponding to at least two instruction groups;

[0191] The maximum execution time is determined based on at least two initial execution times;

[0192] The instruction group corresponding to the maximum execution time is designated as the second instruction group.

[0193] In some embodiments, MCU 501 is used for:

[0194] Compare the first execution time corresponding to the instruction group with the first preset threshold; wherein, the first preset threshold is related to the instruction group acquisition time;

[0195] The first execution time, which is greater than or equal to the first preset threshold, is determined as the second execution time;

[0196] The instruction group corresponding to the second execution duration is designated as the second instruction group.

[0197] In some embodiments, the MCU 501 is configured to determine a first execution duration less than a first preset threshold as a fourth execution duration; to designate the instruction group corresponding to the fourth execution duration as a third instruction group; and to send the third instruction group to the TPU 502 when it is determined that the TPU 502 is in an idle state.

[0198] TPU 502 is used to process the third instruction group; wherein, the TPU being in an idle state indicates that the TPU has finished processing the previous instruction group of the third instruction group or that the TPU has been powered on for the first time;

[0199] MCU 501 is used to acquire the fourth instruction group when it is determined that TPU 502 is in an idle state; wherein, TPU 502 being in an idle state is used to indicate that TPU 502 has finished processing the third instruction group.

[0200] In some embodiments, MCU 501 is used for:

[0201] Based on the third execution duration, instruction group sending duration, and instruction group acquisition duration corresponding to the second instruction group, the index is determined;

[0202] Obtain at least one fifth instruction group; wherein the number of fifth instruction groups is an exponential number, and at least one fifth instruction group includes the first instruction group;

[0203] The first instruction group is determined from at least one fifth instruction group.

[0204] In some embodiments, MCU 501 is used for:

[0205] The first difference is obtained based on the third execution duration and the instruction group transmission duration;

[0206] The first ratio is obtained by rounding down the ratio of the first difference to the instruction group acquisition time.

[0207] The first ratio is used as the index; and / or, the index is determined based on the first ratio and the number of instruction sets; wherein the number of instruction sets includes the number of instruction sets stored in memory.

[0208] In some embodiments, the MCU 501 is configured to: acquire at least one fifth instruction group; wherein the number of fifth instruction groups is a preset number, and the at least one fifth instruction group includes a first instruction group.

[0209] In some embodiments, MCU 501 is used for:

[0210] The detection time is determined based on the third execution duration corresponding to the second instruction group;

[0211] Based on the detection time, the probe determines whether the TPU is in an occupied or idle state.

[0212] In some embodiments, the instruction set includes at least one executable instruction; the execution duration is determined based on at least one of the following:

[0213] The historical execution time corresponding to the historical instruction group;

[0214] The number of executable instructions included in the instruction set;

[0215] Executable instructions include opcodes;

[0216] TPU performance parameters.

[0217] Regarding the apparatus in the above embodiments, the specific manner in which each device performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0218] Figure 6 This is a schematic diagram of the structure of a chip provided in an embodiment of this disclosure, such as... Figure 6 As shown, chip 600 includes the aforementioned instruction processing device 500, which will not be described in detail here.

[0219] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0220] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An instruction processing method, characterized in that, The method includes: When the microcontroller unit (MCU) determines that the tensor processing unit (TPU) is in an idle state, it sends a first instruction group to the TPU. The first instruction group is acquired by the MCU when the TPU is in an occupied state. The TPU being in an occupied state is used to instruct the TPU to process a second instruction group, and the TPU being in an idle state is used to instruct the TPU to complete the processing of the previous instruction group of the first instruction group.

2. The method according to claim 1, characterized in that, Before the MCU sends the first instruction group to the TPU, it also includes: The MCU determines the second instruction group from at least one instruction group based on a first execution duration corresponding to at least one instruction group; wherein the first execution duration includes the time required for the TPU to execute the instruction group; When the MCU determines that the TPU is in an idle state, it sends the second instruction group to the TPU for the TPU to process the second instruction group; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the second instruction group or that the TPU has been powered on for the first time.

3. The method according to claim 2, characterized in that, The MCU determines the second instruction group from at least one instruction group based on a first execution duration corresponding to at least one instruction group, including: The MCU acquires the first execution duration corresponding to at least two of the instruction groups; The MCU determines the maximum execution time based on at least two first execution times; The MCU uses the instruction group corresponding to the extreme execution time as the second instruction group.

4. The method according to claim 2, characterized in that, The MCU determines the second instruction group from at least one instruction group based on a first execution duration corresponding to at least one instruction group, including: The MCU compares the first execution duration corresponding to the instruction group with a first preset threshold; wherein, the first preset threshold is related to the instruction group acquisition duration; The MCU determines a first execution duration that is greater than or equal to the first preset threshold as a second execution duration; The MCU uses the instruction group corresponding to the second execution duration as the second instruction group.

5. The method according to claim 4, characterized in that, The method further includes: The MCU determines a first execution duration that is less than the first preset threshold as a fourth execution duration; The MCU uses the instruction group corresponding to the fourth execution duration as the third instruction group; When the MCU determines that the TPU is in an idle state, it sends the third instruction group to the TPU for the TPU to process; wherein, the TPU being in an idle state is used to indicate that the TPU has finished processing the previous instruction group of the third instruction group or that the TPU has been powered on for the first time. When the MCU determines that the TPU is in an idle state, it acquires a fourth instruction group; wherein, the TPU being in an idle state is used to instruct the TPU to complete the processing of the third instruction group.

6. The method according to claim 2, characterized in that, After the MCU sends the second instruction group to the TPU, it also includes: The MCU determines the index based on the third execution duration, instruction group transmission duration, and instruction group acquisition duration corresponding to the second instruction group; The MCU acquires at least one fifth instruction group; wherein the number of the fifth instruction groups is an exponential number, and the at least one fifth instruction group includes the first instruction group; The MCU determines the first instruction group from at least one of the fifth instruction groups.

7. The method according to claim 6, characterized in that, The MCU determines the index based on the third execution duration, instruction group transmission duration, and instruction group acquisition duration corresponding to the second instruction group, including: The MCU obtains a first difference based on the third execution duration and the instruction group transmission duration; The MCU rounds down the ratio of the first difference to the instruction group acquisition time to obtain the first ratio. The MCU uses the first ratio as the index; and / or determines the index based on the first ratio and the number of instruction groups; wherein the number of instruction groups includes the number of instruction groups stored in memory.

8. The method according to claim 6, characterized in that, After the MCU sends the second instruction group to the TPU, it also includes: The MCU acquires at least one fifth instruction group; wherein the number of the fifth instruction groups is a preset number, and the at least one fifth instruction group includes the first instruction group.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: The MCU determines the detection time based on the third execution duration corresponding to the second instruction group; Based on the detection time, the MCU uses a probe to determine whether the TPU is in an occupied or idle state.

10. The method according to any one of claims 2 to 8, characterized in that, The instruction set includes at least one executable instruction; the execution time is determined based on at least one of the following: The historical execution time corresponding to the historical instruction group; The number of executable instructions included in the instruction set; Executable instructions include opcodes; TPU performance parameters.

11. An instruction processing apparatus, characterized in that, The device includes: The MCU is used to send a first instruction group to the TPU when it is determined that the Tensor Processing Unit (TPU) is in an idle state; wherein, the first instruction group is obtained by the MCU when the TPU is in an occupied state, the occupied state is used to instruct the TPU to process a second instruction group, and the idle state is used to instruct the TPU to complete the processing of the previous instruction group of the first instruction group.

12. A chip, characterized in that, The chip includes the device of claim 11.

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