BMC (Baseboard Management Controller) verification carrier plate and method for high-density computing blade

Abstract

The invention relates to a BMC verification carrier plate and method for a high-density computing blade, and designs a domestic Feiteng BMC verification carrier plate for the high-density computing blade, and the verification carrier plate design mainly comprises a BMC interface design, a basic verification module design, a multi-node serial port communication verification module design and a large-scale sensor monitoring verification module design. Verification and testing of functions of high-density calculation blade multi-node SOL, multi-node serial port caching, large-scale sensor state monitoring and the like are mainly supported, and the efficiency of parallel acquisition of multi-path large-scale monitoring data is fully tested.

Description

Technical Field

[0001] This invention belongs to the field of BMC design verification technology, and relates to a BMC verification carrier and method for high-density computing blades. Background Technology

[0002] High-density computing blades are computing devices specifically designed for ultra-large-scale data processing. The blade motherboard integrates multiple high-efficiency processors, memory, and other necessary components, enabling high-speed and efficient data processing. High-density computing blades require a Baseboard Management Controller (BMC) for out-of-band monitoring and management, enabling various functions such as status monitoring, configuration management, and debugging and maintenance. In the current context of domestic production, research and development of BMCs based on domestically produced embedded chips has begun in this field, with the Phytium E2000S being a commonly used chip. Before formally commencing BMC development, especially when selecting new main control chips or key supporting components, it is necessary to first design a BMC verification board to perform technical verification and key functional and performance testing of the selected devices.

[0003] Currently, there are BMC verification carrier boards available on the market for the Phytium E2000S (such as CB-E2K-BMC-D4), which bring out the USB, UART, I2C, SPI, GPIO, and JTAG interface signals of the E2000S to the board, enabling basic BMC function development and debugging. However, while existing BMC verification carrier boards fully expose various BMC interfaces, they only consider the verification scenarios of traditional server BMCs. For example, they only support single-node SOL (Serial over LAN) function verification, and each I2C interface can only connect to and verify a single sensor. They cannot effectively meet the verification requirements of high-density computing blade BMCs. Compared to traditional servers, which typically involve only a single node, high-density computing blades often contain 4 to 8 nodes and hundreds of status monitoring points. Therefore, existing Phytium BMC verification carrier boards are not entirely suitable for the testing and verification of high-density computing blade BMCs, such as being unable to verify multi-node SOL, multi-node serial port buffers, and large-scale sensor status monitoring. Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a BMC verification carrier board for high-density computing blades and a BMC verification method for high-density computing blades, which can verify multi-node SOL, multi-node serial port buffers and large-scale sensor status monitoring.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a BMC verification carrier board for high-density computing blades is provided, including a DDR4 SODIMM standard slot, a basic verification module, a multi-node serial communication verification module and a large-scale sensor monitoring verification module. Phytium BMC leads each signal to the verification carrier board through the DDR4 SODIMM standard slot. The basic verification module is used to verify the basic interface signals of Phytium BMC. The multi-node serial communication verification module is used to extend the USB signals of Phytium BMC into multiple UART signals to support serial communication of multiple nodes of high-density computing blades. The large-scale sensor monitoring verification module is used to verify the data acquisition efficiency of Phytium BMC for large-scale sensors by using multi-channel I2C group parallel verification.

[0006] In one embodiment, within the basic verification module: The Phytium BMC's 14 GPIO signals, 8 ADC signals, 4 PWM signals, 4 Tach signals, 1 JTAG signal, and 3 UART signals are connected to the verification carrier board through DDR4 SODIMM standard slots and brought out to the outside via headers. The two SPI signals of Phytium BMC are connected to the verification carrier board through the DDR4 SODIMM standard slot and are brought out to the outside through the flash socket; One SGMII signal and two RGMI signals of Phytium BMC are connected to the verification carrier board through DDR4 SODIMM standard slots and brought out to the outside via RJ45 interface.

[0007] In one embodiment, the multi-node serial communication verification module is equipped with two USB-to-serial chips. The input of each USB-to-serial chip is used to connect to one USB signal of Phytium BMC through a DDR4 SODIMM standard slot. The output of each USB-to-serial chip outputs four UART signals and leads them out to the outside through a three-pin header interface.

[0008] In one embodiment, the large-scale sensor monitoring and verification module is configured with five I2C switches. The input of each I2C switch is used to connect to three I2C signals of Phytium BMC through a DDR4 SODIMM standard slot. The output of each I2C switch is used to connect to eight temperature sensors and eight power chips, respectively. If the I2C switch is configured to connect to less than three I2C signals, it is configured to connect to two I2C signals. The I2C switch is used to select any one of the I2C signals to connect to the sensor.

[0009] On the other hand, a BMC verification method for high-density computing blades is also provided, based on any of the above-mentioned BMC verification carriers for high-density computing blades, the BMC verification method comprising the steps of: The signals of the Phytium BMC are routed to the verification carrier board via a DDR4 SODIMM standard slot. The basic interface signals of Phytium BMC are verified using the basic verification module; After expanding the USB signal of Phytium BMC into multiple UART signals using a multi-node serial communication verification module, serial communication of multiple nodes of high-density computing blades was carried out. The Phytium BMC's data acquisition efficiency for large-scale sensors was verified by using a multi-channel I2C group parallel verification method through a large-scale sensor monitoring and verification module.

[0010] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned BMC verification carrier board and method for high-density computing blades includes a domestically developed Phytium BMC verification carrier board for high-density computing blades. The verification carrier board design mainly includes BMC interface design, basic verification module design, multi-node serial communication verification module design, and large-scale sensor monitoring verification module design. It focuses on supporting the verification and testing of functions such as multi-node SOL, multi-node serial port buffering, and large-scale sensor status monitoring of high-density computing blades, and realizes the efficiency of parallel acquisition of multi-channel large-scale monitoring data. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structural composition of a BMC verification carrier for high-density computing blades in one embodiment. Figure 2 This is a flowchart illustrating a BMC verification method for high-density computing blades in one embodiment. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0014] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0015] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0016] In one embodiment, such as Figure 1 As shown, a BMC verification carrier board for high-density computing blades is provided, including a DDR4 SODIMM standard slot, a basic verification module, a multi-node serial communication verification module, and a large-scale sensor monitoring verification module. The Phytium BMC connects its signals to the verification carrier board via the DDR4 SODIMM standard slot. The basic verification module verifies the basic interface signals of the Phytium BMC. The multi-node serial communication verification module expands the USB signals of the Phytium BMC into multiple UART signals to support serial communication between multiple nodes of the high-density computing blades. The large-scale sensor monitoring verification module verifies the data acquisition efficiency of the Phytium BMC for large-scale sensors using a multi-channel I2C group parallel verification method.

[0017] As can be understood, this embodiment includes BMC interface design, basic verification module design, multi-node serial communication verification module design, and large-scale sensor monitoring verification module design. Specifically, this verification carrier board uses a DDR4 SODIMM (SmallOutline Dual In-line Memory Module) standard slot as the BMC interface design. The Phytium BMC uses this DDR4 SODIMM standard slot to route various signals from the Phytium BMC to the verification carrier board. This DDR4 SODIMM slot is a pluggable interface, facilitating the installation and removal of the BMC card.

[0018] The basic verification module design mainly verifies the basic interface signals of Phytium BMC. The basic interface signals of Phytium BMC, such as various GPIO signals, various ADC signals, various PWM signals, various Tach signals, JTAG signals, various UART signals, various SPI signals, SGMII signals, and various RGMI signals, are connected to the verification carrier board through DDR4 SODIMM standard slots so that the verification work required for each signal can be completed on the basic verification module.

[0019] Multi-node serial communication verification module design: Due to the limited number of native UART serial ports on the Phytium BMC, besides the one UART serial port needed for its own debugging, only two UART serial ports are available for serial communication with the compute nodes. This embodiment extends the USB signal of the Phytium BMC into a UART signal to support serial communication between multiple nodes of high-density compute blades; an appropriate number of USB-to-serial chips can be selected to implement the aforementioned extension of USB signals into UART signals.

[0020] Design of a Large-Scale Sensor Monitoring and Verification Module: For high-density computing blade monitoring scenarios, it is necessary to verify the data acquisition efficiency of the Phytium BMC for large-scale sensors. Considering both the sufficiency of the verification and the size of the verification substrate, this embodiment proposes a design concept of multi-channel I2C grouped parallel verification. Multiple I2C switches can be used to connect the 14 I2C signals of the Phytium BMC in groups, for example, but not limited to, connecting every 2 I2C signals to the input of each I2C switch, or every 3 I2C signals, or every 4 I2C signals. The specific grouping can be selected according to the design size requirements and cost constraints of the verification substrate. I2C switches are multi-channel switch chips used for I2C signal switching and distribution. These chips can flexibly implement the path selection and connection of each I2C signal.

[0021] The aforementioned BMC verification carrier board for high-density computing blades was designed as a domestic Phytium BMC verification carrier board for high-density computing blades. The design of the verification carrier board mainly includes BMC interface design, basic verification module design, multi-node serial communication verification module design, and large-scale sensor monitoring verification module design. It focuses on supporting the verification and testing of functions such as multi-node SOL, multi-node serial port buffering, and large-scale sensor status monitoring of high-density computing blades, and realizes the efficiency of parallel acquisition of multi-channel large-scale monitoring data.

[0022] In one embodiment, in the basic verification module: the 14 GPIO signals, 8 ADC signals, 4 PWM signals, 4 Tach signals, 1 JTAG signal, and 3 UART signals of the Phytium BMC are connected to the verification carrier board via DDR4 SODIMM standard slots and brought out externally via headers. The 2 SPI signals of the Phytium BMC are connected to the verification carrier board via DDR4 SODIMM standard slots and brought out externally via flash sockets. The 1 SGMII signal and 2 RGMI signals of the Phytium BMC are connected to the verification carrier board via DDR4 SODIMM standard slots and brought out externally via RJ45 interfaces.

[0023] Optionally, the Phytium BMC's 14 GPIO signals, 8 ADC signals, 4 PWM signals, 4 Tach signals, 1 JTAG signal, and 3 UART signals are connected to the verification carrier board via DDR4 SODIMM standard slots and brought out externally via headers. The Phytium BMC's 2 SPI signals are connected to the verification carrier board via DDR4 SODIMM standard slots and brought out externally via flash sockets; the Phytium BMC's 1 SGMII signal and 2 RGMI signals are connected to the verification carrier board via DDR4 SODIMM standard slots and brought out externally via RJ45 interfaces.

[0024] In one embodiment, the multi-node serial communication verification module is configured with two USB-to-serial chips. The input of each USB-to-serial chip is used to connect to one USB signal of Phytium BMC through a DDR4 SODIMM standard slot. The output of each USB-to-serial chip outputs four UART signals and leads them out to the outside through a three-pin header interface.

[0025] Specifically, firstly, the two USB signals of the Phytium BMC are connected to the verification carrier board via a DDR4 SODIMM standard slot. Then, two USB-to-serial chips are configured on the verification carrier board, and the two USB signals of the Phytium BMC are connected to the input terminals of these two USB-to-serial chips respectively. Finally, the output terminals of the two USB-to-serial chips each output four UART signals (a total of eight UART signals), which are brought out externally via a three-pin header interface. This design can support serial communication for up to eight computing nodes, while simplifying the structural configuration of the multi-node serial communication verification module.

[0026] In one embodiment, the large-scale sensor monitoring and verification module is configured with five I2C switches. The input of each I2C switch is used to connect to three I2C signals of the Phytium BMC through a DDR4 SODIMM standard slot. The output of each I2C switch is used to connect to eight temperature sensors and eight power chips, respectively. If the I2C switch is configured to connect to less than three I2C signals, it is configured to connect to two I2C signals. The I2C switch is used to select any one of the I2C signals to connect to the sensor.

[0027] Specifically, firstly, all 14 I2C signals of the Phytium BMC are connected to the verification carrier board via standard DDR4 SODIMM slots. Then, five I2C switches are configured on the verification carrier board, with the 14 I2C signals of the Phytium BMC grouped into one of these switches in groups of three. The output of each I2C switch is connected to eight temperature sensors and eight power supply chips. Finally, by toggling the I2C switches, one can select which I2C signal at the input end is connected to a sensor at the output end. This design allows for the verification of up to 80 sensors on five I2C lines at a time, effectively enabling large-scale sensor data acquisition and connection while simplifying the structural configuration of the large-scale sensor monitoring and verification module.

[0028] When performing BMC verification, the Phytium BMC to be verified can be directly connected to the aforementioned BMC verification carrier board for high-density computing blades. This allows for the effective verification of Phytium BMC's multi-node concurrent serial communication, large-scale sensor status monitoring, and other functions in high-density computing blade monitoring scenarios.

[0029] In one embodiment, such as Figure 2 As shown, a BMC verification method for high-density computing blades is also provided, based on any of the BMC verification carrier boards for high-density computing blades described in the previous embodiment. This BMC verification method includes steps S12 to S18: S12 connects the various signals of Phytium BMC to the verification carrier board via the DDR4 SODIMM standard slot; S14, use the basic verification module to verify the basic interface signals of Phytium BMC; S16, after expanding the USB signal of Phytium BMC into multiple UART signals using the multi-node serial communication verification module, serial communication of multiple nodes of high-density computing blades is carried out. S18 uses a multi-channel I2C group parallel verification method through a large-scale sensor monitoring and verification module to verify the data acquisition efficiency of Phytium BMC for large-scale sensors.

[0030] The aforementioned BMC verification method for high-density computing blades designed a domestic Phytium BMC verification carrier board for high-density computing blades. The verification carrier board design mainly includes BMC interface design, basic verification module design, multi-node serial communication verification module design, and large-scale sensor monitoring verification module design. It focuses on supporting the verification and testing of functions such as multi-node SOL, multi-node serial port buffering, and large-scale sensor status monitoring of high-density computing blades, and realizes the efficiency of parallel acquisition of multi-channel large-scale monitoring data.

[0031] It is understood that the explanations of the features in the BMC verification method for high-density computing blades described above can be understood by referring to the corresponding explanations in the various embodiments of the BMC verification carrier board for high-density computing blades described above. Each module in the BMC verification method for high-density computing blades described above can be implemented entirely or partially through software, hardware, or a combination thereof. The aforementioned components can be embedded in hardware or independently of a device with data processing capabilities, or stored in software in the memory of the aforementioned device, so that the processor can call and execute the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of computers already existing in the art.

[0032] It should be understood that, although the above process Figure 2 The steps in the diagram are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, the above process... Figure 2 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0033] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0034] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0035] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A BMC verification board for high-density compute blades, comprising: The BMC of Feiteng is connected to the verification board through the DDR4 SODIMM standard slot, and the signals are led out through the pin arrangement. The basic verification module is used for verifying the basic interface signals of the BMC of Feiteng, the multi-node serial communication verification module is used for expanding the USB signals of the BMC of Feiteng into multi-channel UART signals to support the serial communication of the multi-node of the high-density computing blade, and the large-scale sensor monitoring verification module is used for verifying the data acquisition efficiency of the BMC of Feiteng on the large-scale sensor in the form of multi-channel I2C grouping parallel verification.

2. The BMC verification board for high-density compute blade facing according to claim 1, wherein, In the basic verification module: The 14-channel GPIO signals, 8-channel ADC signals, 4-channel PWM signals, 4-channel Tach signals, 1-channel JTAG signal and 3-channel UART signal of the BMC of Feiteng are connected to the verification board through the DDR4 SODIMM standard slot and led out through the pin arrangement; The 2-channel SPI signals of the BMC of Feiteng are connected to the verification board through the DDR4 SODIMM standard slot and led out through the flash base; The 1-channel SGMII signal and 2-channel RGMI signal of the BMC of Feiteng are connected to the verification board through the DDR4 SODIMM standard slot and led out through the RJ45 interface.

3. The BMC verification board for high-density compute blade facing according to claim 1, wherein, In the multi-node serial communication verification module, two USB-to-serial chips are configured, the input end of each USB-to-serial chip is used for connecting the 1-channel USB signal of the BMC of Feiteng through the DDR4 SODIMM standard slot, and the output end of each USB-to-serial chip outputs 4-channel UART signals and leads out through the three-pin pin interface.

4. The BMC verification board for high-density compute blade facing according to claim 1, wherein, The large-scale sensor monitoring verification module is configured with five I2C switches, the input end of each I2C switch is used for connecting the 3-channel I2C signal of the BMC of Feiteng through the DDR4 SODIMM standard slot, and the output end of each I2C switch is used for connecting 8 temperature sensors and 8 power chips respectively; if the I2C signal configured to be connected to the I2C switch is less than 3 channels, the I2C switch is configured to connect 2-channel I2C signals.

5. A BMC verification method for high-density compute blades, characterized in that, The BMC verification method for the high-density computing blade based on any one of claims 1 to 4 comprises the steps of: leading the signals of the BMC of Feiteng to the verification board through the DDR4 SODIMM standard slot; verifying the basic interface signals of the BMC of Feiteng by using the basic verification module; expanding the USB signals of the BMC of Feiteng into multi-channel UART signals by using the multi-node serial communication verification module, and then carrying out the serial communication of the multi-node of the high-density computing blade; verifying the data acquisition efficiency of the BMC of Feiteng on the large-scale sensor by using the large-scale sensor monitoring verification module in the form of multi-channel I2C grouping parallel verification.

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