Manufacturing method of MIM capacitor

Abstract

The invention provides a manufacturing method of an MIM capacitor, and is applied to the technical field of semiconductors. According to the method, the bottom metal layer is formed through multiple film forming processes, and the temperature of the substrate is reduced to the preset value in the gaps of the film forming processes, so that the average temperature of the substrate in the forming process is reduced and is ensured to be lower than 270 DEG C, and the growth of metal grains in the bottom metal layer is inhibited. And meanwhile, in the process of forming the bottom metal layer, at least one of the deposition speed, the deposition power and the deposition vacuum degree of the film forming process is reduced to a preset value, so that the growth of metal grains in the bottom metal layer is further inhibited, the controllability and the stability of the deposition process of the bottom metal layer can be improved by reducing the deposition speed of the film forming process; by reducing the deposition vacuum degree of the film forming process, the shape of metal grains in the bottom metal layer can be more uniform, the bottom metal layer obtained through deposition is smoother, and meanwhile controllability is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a MIM capacitor. Background Technology

[0002] MIM (Metal-Insulator-Metal) capacitors are sandwich-structured components consisting of a bottom metal layer, a dielectric layer, and a top metal layer. They are characterized by stable capacitance, high accuracy, and excellent high-frequency performance, making them key components in radio frequency (RF) and communications fields. High-precision MIM capacitors place high demands on the smoothness and defect density of the interfaces between the constituent material layers, especially the bottom metal layer. Roughness and defects on the surface of the bottom metal layer will be transmitted throughout the entire MIM capacitor via the stacked structure, affecting its accuracy and hindering its widespread application. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a MIM capacitor. A bottom metal layer is formed through multiple film deposition processes, and the temperature of the substrate is reduced to a preset value between each film deposition process. This reduces the average temperature of the substrate during the formation process, ensuring it remains below 270°C, thereby suppressing the growth of metal grains in the bottom metal layer. Simultaneously, during the formation of the bottom metal layer, at least one of the deposition rate, deposition power, and deposition vacuum degree of the film deposition process is reduced to a preset value, further suppressing the growth of metal grains in the bottom metal layer. Reducing the deposition rate of the film deposition process also increases the controllability and stability of the bottom metal layer deposition process; reducing the deposition vacuum degree of the film deposition process results in a more uniform shape of the metal grains in the bottom metal layer, a smoother deposited bottom metal layer, and improved controllability.

[0004] To address the aforementioned technical problems, this invention provides a method for manufacturing a MIM capacitor, which may include at least the following steps:

[0005] Provide a base;

[0006] A bottom metal layer is formed on the substrate. The bottom metal layer includes sub-metal layers formed by multiple film deposition processes. After each film deposition process is completed, the temperature of the substrate is first reduced to a preset value before the next film deposition process is performed, so as to suppress the growth of metal grains in each sub-metal layer.

[0007] An inhibition layer is formed on the bottom metal layer.

[0008] Furthermore, the preset value ranges from 25℃ to 100℃.

[0009] Furthermore, during the formation of the bottom metal layer, the temperature of the substrate is less than 270°C.

[0010] Furthermore, the process of forming the bottom metal layer also includes:

[0011] At least one of the deposition rate, deposition power, and deposition vacuum degree of the film formation process is reduced to a preset value.

[0012] Furthermore, when the deposition rate of the film formation process is reduced, the preset value corresponding to the deposition rate is less than 200 Å / s.

[0013] Furthermore, when the deposition power of the film formation process is reduced, the preset value corresponding to the deposition power is less than 18KW.

[0014] Furthermore, when the deposition vacuum degree of the film formation process is reduced, the preset value corresponding to the deposition power is less than 6 mtorr.

[0015] Furthermore, the thickness of each of the sub-metal layers ranges from 950 Å to 1050 Å.

[0016] Furthermore, the material of the bottom metal layer includes aluminum and tantalum.

[0017] Furthermore, the material of the inhibition layer includes aluminum oxide and aluminum nitride.

[0018] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0019] In a method for manufacturing a MIM capacitor provided by the present invention, a bottom metal layer is formed on a substrate. The bottom metal layer includes sub-metal layers formed by multiple film deposition processes. After each film deposition process is completed, the temperature of the substrate is first reduced to a preset value before the next film deposition process is performed to suppress the growth of metal grains in each sub-metal layer. Finally, an inhibition layer is formed on the bottom metal layer.

[0020] In the method for fabricating a MIM capacitor provided by this invention, a bottom metal layer is formed through multiple film deposition processes. The temperature of the substrate is reduced to a preset value between each film deposition process, thereby lowering the average temperature of the substrate during the formation process to below 270°C, thus suppressing the growth of metal grains in the bottom metal layer. Simultaneously, during the formation of the bottom metal layer, at least one of the deposition rate, deposition power, and deposition vacuum degree of the film deposition process is reduced to a preset value, further suppressing the growth of metal grains in the bottom metal layer. Reducing the deposition rate of the film deposition process also increases the controllability and stability of the bottom metal layer deposition process; reducing the deposition vacuum degree of the film deposition process makes the shape of the metal grains in the bottom metal layer more uniform, resulting in a smoother bottom metal layer and improved controllability. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0022] Figure 1 A flowchart illustrating a method for manufacturing a MIM capacitor according to an embodiment of the present invention;

[0023] Figures 2a-2d This is a structural schematic diagram of a method for manufacturing a MIM capacitor according to an embodiment of the present invention.

[0024] The specific reference numerals in the attached figures are as follows:

[0025] 100 - Substrate; 101 - Bottom metal layer; 102 - Inhibition layer; 103 - Dielectric layer; 104 - Buffer layer; 105 - Top metal layer.

[0026] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0027] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0028] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the invention can be arbitrarily combined without conflict.

[0029] As described in the background section, high-precision MIM capacitors have very high requirements for the flatness and defect density of the interfaces of the constituent material layers, especially the bottom metal layer. The roughness and defects on the surface of the bottom metal layer will be transmitted to the entire MIM capacitor through the stacked structure. These roughness and defects transmitted to the entire MIM capacitor will affect the accuracy of the capacitor and hinder its application and promotion.

[0030] To address the above problems, this invention proposes an improved solution: a bottom metal layer is formed through multiple film deposition processes, with the substrate temperature reduced to a preset value between each process. This lowers the average substrate temperature during formation, ensuring it remains below 270°C, thereby suppressing the growth of metal grains in the bottom metal layer. Simultaneously, during the formation of the bottom metal layer, at least one of the deposition rate, deposition power, and deposition vacuum level of the film deposition process is reduced to a preset value, further suppressing the growth of metal grains. Reducing the deposition rate also increases the controllability and stability of the bottom metal layer deposition process; reducing the deposition vacuum level results in more uniform metal grain shapes in the bottom metal layer, a smoother deposited bottom metal layer, and improved controllability.

[0031] refer to Figure 1 As shown, Figure 1 This is a schematic flowchart illustrating the method for manufacturing a MIM capacitor according to an embodiment of the present invention; wherein, the method for manufacturing a MIM capacitor may include the following steps:

[0032] Step S201, provide a substrate;

[0033] Step S202: A bottom metal layer is formed on the substrate. The bottom metal layer includes sub-metal layers formed by multiple film deposition processes. After each film deposition process is completed, the temperature of the substrate is first reduced to a preset value before the next film deposition process is performed, so as to suppress the growth of metal grains in each sub-metal layer.

[0034] Step S203: An inhibition layer is formed on the bottom metal layer;

[0035] Step S204: A dielectric layer is formed on the suppression layer;

[0036] Step S205: A buffer layer is formed on the dielectric layer;

[0037] Step S206: A top metal layer is formed on the buffer layer;

[0038] Step S207: Perform rapid thermal annealing on the substrate.

[0039] The method for manufacturing the MIM capacitor proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention can also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0040] See Figure 2a In step S201 above, a substrate 100 is first provided. The substrate 100 can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Alternatively, it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate. Exemplarily, the substrate 100 in this embodiment is preferably silicon-on-insulator.

[0041] Continue reading Figure 2aIn step S202 above, a bottom metal layer 101 is formed on the substrate 100. The bottom metal layer 101 includes sub-metal layers (e.g., at least 4 sub-metal layers) formed by multiple film deposition processes. The thickness of each sub-metal layer ranges from 950 Å to 1050 Å. After each film deposition process is completed, the temperature of the substrate 100 is reduced to a preset value by lowering the temperature of the reaction chamber of the film deposition process before performing the next film deposition process. This is to suppress the growth of metal grains in each sub-metal layer. The preset value ranges from 25°C to 100°C. During the formation of the bottom metal layer 101, the temperature of the substrate 100 needs to be kept below 270°C. To further suppress the growth of metal grains in each of the sub-metal layers, during the formation of the bottom metal layer 101, at least one of the deposition rate, deposition power, and deposition vacuum level of the film formation process is reduced to a preset value. When the deposition rate of the film formation process is reduced, the preset value corresponding to the deposition rate is less than 200 Å / s; when the deposition power of the film formation process is reduced, the preset value corresponding to the deposition power is less than 18 kW; when the deposition vacuum level of the film formation process is reduced, the preset value corresponding to the deposition power is less than 6 mtorr. The material of the bottom metal layer 101 includes aluminum and tantalum.

[0042] In this embodiment, the bottom metal layer 101 includes a sub-metal layer formed by four film-forming processes. However, in other embodiments, the bottom metal layer 101 may also include a sub-metal layer formed by five film-forming processes, but this is not a limitation.

[0043] See Figure 2b In step S203 above, an inhibition layer 102 of 3-5 nm is formed on the bottom metal layer 101 by atomic layer deposition. The inhibition layer 102 has a high density, and its thermal stability and thermomechanical properties are much higher than those of the bottom metal layer 101. The inhibition layer 102 can resist the tendency of the bottom metal layer 101 to expand due to thermal polymerization during subsequent annealing, and can further inhibit the growth of metal grains in the bottom metal layer. The material of the inhibition layer 102 includes alumina and aluminum nitride.

[0044] See Figure 2c In step S204 above, a dielectric layer 103 is formed on the suppression layer 102 by atomic layer deposition, chemical vapor deposition or physical vapor deposition process. Its function is to store charge and isolate the upper and lower metal electrodes to prevent short circuit. The material of the dielectric layer 103 includes alumina, high dielectric constant material, silicon nitride, tin oxide and low dielectric constant material, etc.

[0045] See Figure 2dIn step S205 above, a buffer layer 104 of 3-5 nm is formed on the dielectric layer 103 by atomic layer deposition. This buffer layer serves as a transition layer between the dielectric layer 103 and the subsequent top metal layer, making the interface between the dielectric layer 103 and the subsequent top metal layer smoother and reducing interface stress. The materials of the buffer layer include aluminum oxide and aluminum nitride.

[0046] Continue reading Figure 2d In step S206 above, a top metal layer 105 is formed on the buffer layer 104, the top metal layer 105 including a sub-metal layer formed by two film deposition processes.

[0047] In this embodiment, the top metal layer 105 includes a sub-metal layer formed by two film-forming processes. However, in other embodiments, the top metal layer 105 may also include a sub-metal layer formed by three film-forming processes, but this is not a limitation.

[0048] Continue reading Figure 2d In step S207 above, rapid thermal annealing is performed on the substrate 100. The temperature range of the rapid thermal annealing is 300~500℃ and the time is 100~900ms. Since rapid thermal annealing does not easily coarsen the metal grains in the bottom metal layer 101, the presence of the suppression layer 102 can prevent the further aggregation and increase of the metal grains in the bottom metal layer 101. Therefore, rapid thermal annealing can further eliminate defects such as vacancies in the interface region, making the overall structure more compact and eliminating internal stress.

[0049] In summary, in the method for manufacturing a MIM capacitor provided by the present invention, a bottom metal layer is formed on a substrate. The bottom metal layer includes sub-metal layers formed by multiple film deposition processes. After each film deposition process is completed, the temperature of the substrate is first reduced to a preset value before the next film deposition process is performed to suppress the growth of metal grains in each sub-metal layer. Finally, an inhibition layer is formed on the bottom metal layer.

[0050] In the method for fabricating a MIM capacitor provided by this invention, a bottom metal layer is formed through multiple film deposition processes. The temperature of the substrate is reduced to a preset value between each film deposition process, thereby lowering the average temperature of the substrate during the formation process to below 270°C, thus suppressing the growth of metal grains in the bottom metal layer. Simultaneously, during the formation of the bottom metal layer, at least one of the deposition rate, deposition power, and deposition vacuum degree of the film deposition process is reduced to a preset value, further suppressing the growth of metal grains in the bottom metal layer. Reducing the deposition rate of the film deposition process also increases the controllability and stability of the bottom metal layer deposition process; reducing the deposition vacuum degree of the film deposition process makes the shape of the metal grains in the bottom metal layer more uniform, resulting in a smoother bottom metal layer and improved controllability.

[0051] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that, include: Provide a base; A bottom metal layer is formed on the substrate. The bottom metal layer includes sub-metal layers formed by multiple film deposition processes. After each film deposition process is completed, the temperature of the substrate is first reduced to a preset value before the next film deposition process is performed, so as to suppress the growth of metal grains in each sub-metal layer. An inhibition layer is formed on the bottom metal layer.

2. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The preset value ranges from 25℃ to 100℃.

3. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, During the formation of the bottom metal layer, the temperature of the substrate is less than 270°C.

4. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The process of forming the bottom metal layer also includes: At least one of the deposition rate, deposition power, and deposition vacuum degree of the film formation process is reduced to a preset value.

5. The method for manufacturing a MIM capacitor as described in claim 4, characterized in that, When the deposition rate of the film formation process is reduced, the preset value corresponding to the deposition rate is less than 200 Å / s.

6. The method for manufacturing a MIM capacitor as described in claim 4, characterized in that, When the deposition power of the film formation process is reduced, the preset value corresponding to the deposition power is less than 18KW.

7. The method for manufacturing a MIM capacitor as described in claim 4, characterized in that, When the deposition vacuum of the film formation process is reduced, the preset value corresponding to the deposition power is less than 6 mtorr.

8. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The thickness of each of the sub-metal layers ranges from 950 Å to 1050 Å.

9. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The bottom metal layer is made of aluminum and tantalum.

10. The method for manufacturing a MIM capacitor as described in claim 8, characterized in that, The materials of the inhibition layer include aluminum oxide and aluminum nitride.

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