Semiconductor structure and preparation method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a preparation method of the semiconductor structure. The semiconductor structure comprises a substrate, an epitaxial layer, a trench gate structure, a doping structure, a source electrode structure and a drain electrode structure, wherein the epitaxial layer is located at one side of the substrate; the trench gate structure is located in the epitaxial layer; the doping structure is located in the epitaxial layer, at least part of the doping structure is located between the groove gate structure and the substrate, and the doping concentration of the doping structure is firstly increased and then decreased in the direction that the substrate points to the epitaxial layer; the source structure is located at one side of the epitaxial layer away from the substrate; the drain structure is located on one side of the substrate away from the epitaxial layer. The performance of the semiconductor structure can be improved by arranging the doping structure with the variable doping concentration.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] SiC MOSFETs, with their high voltage resistance and low loss characteristics, have replaced silicon-based IGBTs in high-voltage, high-current applications and are widely used in new energy vehicles and photovoltaics. However, current concentration at the bottom of the trench leads to localized overheating and reliability issues, especially the formation of hot spots at high current densities, which affects device performance.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a semiconductor structure and a method for fabricating the semiconductor structure, so as to solve the problem of how to improve the performance of semiconductor structures in the prior art.

[0005] To achieve the above objectives, according to one aspect of this application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on one side of the substrate; a trench gate structure located within the epitaxial layer; a doped structure located within the epitaxial layer, and at least a portion of the doped structure is located between the trench gate structure and the substrate, wherein the doping concentration of the doped structure first increases and then decreases in the direction from the substrate to the epitaxial layer; a source structure located on the side of the epitaxial layer away from the substrate; and a drain structure located on the side of the substrate away from the epitaxial layer.

[0006] Optionally, the doped structure includes a first doped layer, a second doped layer, and a third doped layer, wherein the first doped layer is located between the trench gate structure and the substrate, the second doped layer is located on the side of the first doped layer away from the substrate, the third doped layer is located on the side of the second doped layer away from the substrate, and in the thickness direction perpendicular to the substrate, the third doped layer is located on both sides of the trench gate structure, the doping concentration of the first doped layer is less than the doping concentration of the second doped layer, and the doping concentration of the first doped layer is greater than the doping concentration of the third doped layer.

[0007] Optionally, the ratio of the thickness of the first doped layer, the thickness of the second doped layer, and the thickness of the third doped layer is in the range of 1:(1.5~2):1~1:2:1.

[0008] Optionally, the ratio of the doping concentration of the first doped layer, the doping concentration of the second doped layer, and the doping concentration of the third doped layer is in the range of (1.5~2):(2~3):1.

[0009] Optionally, the minimum distance between the bottom surface of the trench gate structure and the surface of the third doped layer away from the substrate is a first distance, and the ratio of the first distance to the thickness of the third doped layer is in the range of (1~2):(2~3).

[0010] Optionally, the ratio of the depth of the trench gate structure to the width of the trench gate structure is in the range of (1~5):1.

[0011] Optionally, the semiconductor structure further includes: a first doped region, a second doped region, and a third doped region, wherein the first doped region, the second doped region, and the third doped region are located in the epitaxial layer, the first doped region is located on the side of the second doped region and the third doped region closer to the substrate, and in the direction perpendicular to the substrate, the first doped region is located on the side of the third doped region away from the second doped region, wherein the doping type of the first doped region is the same as the doping type of the second doped region, and the doping type of the first doped region is different from the doping type of the third doped region.

[0012] Optionally, the trench gate structure includes a gate layer, a first dielectric layer, and a gate electrode. The first dielectric layer is located on the side of the gate layer closer to the substrate, and the gate electrode is located on the side of the gate layer away from the substrate. In the thickness direction perpendicular to the substrate, the first dielectric layer is located on both sides of the gate layer.

[0013] Optionally, the semiconductor structure further includes: a second dielectric layer located between adjacent trench gate structures and source structures and on the side of the gate structure away from the substrate; and an ohmic contact layer located between the source structure and the epitaxial layer.

[0014] To achieve the above objectives, according to one aspect of this application, a method for fabricating a semiconductor structure is provided. The method includes: providing a substrate and sequentially forming a first pre-epitaxial layer, a pre-doped structure, and a second pre-epitaxial layer on one side of the substrate; sequentially removing a portion of the second pre-epitaxial layer and a portion of the pre-doped structure to obtain a trench; forming an epitaxial layer with the remaining first pre-epitaxial layer, the remaining pre-doped structure, and the remaining second pre-epitaxial layer; forming a trench gate structure within the trench; wherein, in the direction from the substrate to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases; forming a source structure on the side of the epitaxial layer away from the substrate; and forming a drain structure on the side of the substrate away from the epitaxial layer.

[0015] The present application provides a semiconductor structure including a substrate, an epitaxial layer, a trench gate structure, a doped structure, a source structure, and a drain structure. The epitaxial layer is located on one side of the substrate; the trench gate structure is located within the epitaxial layer; the doped structure is located within the epitaxial layer, and at least part of the doped structure is located between the trench gate structure and the substrate. In the direction from the substrate to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases; the source structure is located on the side of the epitaxial layer away from the substrate; and the drain structure is located on the side of the substrate away from the epitaxial layer. In this scheme, the doped structure located between the trench gate structure and the substrate exhibits a doping concentration that first increases and then decreases in the direction from the substrate to the epitaxial layer. The portion where the doping concentration decreases creates a gradient change, similar to a "linearly variable junction" or "punch-through junction." This gradient doping allows the depletion region to extend upwards more smoothly and broadly into the less concentrated portion of the epitaxial layer, providing excellent interface characteristics. The portion where the doping concentration increases reduces resistivity, providing a lateral current expansion layer for electrons. After electrons are injected from the channel, they diffuse laterally, dispersing the current from the narrow region directly below the channel to a flat plane. Then, the current flows vertically downwards uniformly from this broad plane. This "lateral-then-vertical" current path significantly alleviates the "current congestion" effect in traditional structures, especially under overcurrent (such as short-circuit) conditions, preventing the formation of local hot spots and significantly improving the short-circuit withstand capability of the semiconductor structure. Through the synergistic effect of different doping concentrations in the doped structure, the technical problem of how to improve the performance of semiconductor structures is solved. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic diagram of a semiconductor structure provided according to an embodiment of this application is shown;

[0018] Figure 2 A schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application is shown;

[0019] Figures 3(a) to (i) show schematic diagrams of the specific process of the semiconductor structure fabrication method provided according to the embodiments of this application.

[0020] The above figures include the following reference numerals:

[0021] 10. Substrate; 11. Epitaxial layer; 12. Trench gate structure; 121. Gate layer; 122. First dielectric layer; 123. Gate electrode; 13. Doped structure; 131. First doped layer; 132. Second doped layer; 133. Third doped layer; 14. Source structure; 15. Drain structure; 16. First doped region; 17. Second doped region; 18. Third doped region; 19. Second dielectric layer; 20. Ohmic contact layer; 21. First pre-epitaxial layer; 22. Pre-doped structure; 221. Pre-doped layer; 23. Second pre-epitaxial layer; 24. Pre-doped region; 25. Trench. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0026] As described in the background section, the performance of semiconductor structures in the prior art is not ideal. To solve the above problems, embodiments of this application provide a semiconductor structure and a method for preparing the semiconductor structure.

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0028] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of this application. For example... Figure 1 As shown, it includes:

[0029] Substrate 10;

[0030] The substrate 10 can be made of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc., and the resistivity of the substrate 10 can be 0.02±20%Ωcm.

[0031] Epitaxial layer 11 is located on one side of the substrate 10;

[0032] In practical applications, the epitaxial layer 11 can be a single-layer structure or a multi-layer structure. The epitaxial layer 11 can serve as a drift layer, bearing the main breakdown load. The doping concentration of the epitaxial layer 11 can be 1E+15~1E1+16cm. -3 .

[0033] The trench gate structure 12 is located within the aforementioned epitaxial layer 11;

[0034] The width and depth of the trench gate structure 12 can be set according to actual needs.

[0035] The doped structure 13 is located within the epitaxial layer 11, and at least a portion of the doped structure 13 is located between the trench gate structure 12 and the substrate 10. In the direction from the substrate 10 to the epitaxial layer 11, the doping concentration of the doped structure 13 first increases and then decreases.

[0036] In practical applications, the doped structure 13 can be a single-layer structure or a multi-layer structure, as long as it meets the aforementioned trend of doping concentration variation. In some embodiments, the doped structure 13 can be located on both sides of the trench gate structure 12 and the substrate 10, or on both sides of the trench gate structure 12 in the thickness direction perpendicular to the substrate 10. The doping concentration in the doped structure 13 first increases and then decreases. That is, in the direction from the substrate 10 to the epitaxial layer 11, the portion of the doped structure 13 with the maximum doping concentration has a doping concentration that can have the same or different doping concentrations on both sides, as long as the doping concentration is less than the maximum value.

[0037] The source structure 14 is located on the side of the epitaxial layer 11 away from the substrate 10;

[0038] In practical applications, the source structure 14 can be used as the input terminal of current. The material of the source structure 14 can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0039] The drain structure 15 is located on the side of the substrate 10 away from the epitaxial layer 11.

[0040] In practical applications, the drain structure 15 can be used as the output terminal of current. The material of the drain structure 15 can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0041] This embodiment provides a semiconductor structure including a substrate, an epitaxial layer, a trench gate structure, a doped structure, a source structure, and a drain structure. The epitaxial layer is located on one side of the substrate; the trench gate structure is located within the epitaxial layer; the doped structure is located within the epitaxial layer, and at least a portion of the doped structure is located between the trench gate structure and the substrate. In the direction from the substrate to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases; the source structure is located on the side of the epitaxial layer away from the substrate; and the drain structure is located on the side of the substrate away from the epitaxial layer. In this scheme, the doped structure located between the trench gate structure and the substrate exhibits a doping concentration that first increases and then decreases in the direction from the substrate to the epitaxial layer. The portion where the doping concentration decreases creates a gradient change, similar to a "linearly variable junction" or "punch-through junction." This gradient doping allows the depletion region to extend upwards more smoothly and broadly into the less concentrated portion of the epitaxial layer, providing excellent interface characteristics. The portion where the doping concentration increases reduces resistivity, providing a lateral current expansion layer for electrons. After electrons are injected from the channel, they diffuse laterally, dispersing the current from the narrow region directly below the channel to a flat plane. Then, the current flows vertically downwards uniformly from this broad plane. This "lateral-then-vertical" current path significantly alleviates the "current congestion" effect in traditional structures, especially under overcurrent (such as short-circuit) conditions, preventing the formation of local hot spots and significantly improving the short-circuit withstand capability of the semiconductor structure. Through the synergistic effect of different doping concentrations in the doped structure, the technical problem of how to improve the performance of semiconductor structures is solved.

[0042] In the specific implementation process, such as Figure 1As shown, the doped structure 13 includes a first doped layer 131, a second doped layer 132, and a third doped layer 133. The first doped layer 131 is located between the trench gate structure 12 and the substrate 10. The second doped layer 132 is located on the side of the first doped layer 131 away from the substrate 10. The third doped layer 133 is located on the side of the second doped layer 132 away from the substrate 10. Furthermore, in the thickness direction perpendicular to the substrate 10, the third doped layer 133 is located on both sides of the trench gate structure 12. The doping concentration of the first doped layer 131 is less than the doping concentration of the second doped layer 132, and the doping concentration of the first doped layer 131 is greater than the doping concentration of the third doped layer 133. This structure allows for more precise control of the doping profile, improving the consistency and yield of the breakdown voltage of the semiconductor structure. The moderate doping of the first doped layer 131 can optimize the electric field distribution, the high doping of the second doped layer 132 can provide the main current path, and the low doping of the third doped layer 133 can ensure good interface characteristics with the well region. The above triple doping distribution can achieve more precise carrier control. The synergistic effect of the three layers can optimize the electric field distribution at the bottom of the trench, reduce the current concentration effect at the bottom of the trench, and further improve the reliability of the semiconductor structure.

[0043] In the above implementation process, the presence of the first doped layer 131 forms a doping gradient from top to bottom of "N+ (third doped region 18) — N (first doped layer 131) — N- (epitaxy layer 11 drift region)". This allows the electric field to gradually and linearly increase from a lower value below the N+ layer to the value required for the ideal electric field distribution in the N- drift region. This eliminates the second electric field spike, ensuring that the electric field of the entire device presents a uniform, peak-free trapezoidal distribution from the well region or drift region interface to the drift region or substrate 10 interface. In existing trench structures, electrons need to flow vertically downwards immediately after leaving the channel, resulting in a relatively narrow path. The presence of the second doped layer 132, due to its extremely low resistivity, provides a strong, lateral current spreading layer for electrons. After electrons are injected into the channel, they are rapidly drawn into the second doped layer 132 and diffuse laterally within it. This disperses the current from the narrow region directly below the channel to a broad plane roughly the same area as the second doped layer 132. The current then flows vertically downwards uniformly from this broad plane. This "lateral-then-vertical" current path greatly alleviates the "current congestion" effect in traditional structures, especially under overcurrent (such as short-circuit) conditions, avoiding the generation of local hot spots and significantly improving the device's short-circuit withstand capability. In the device's off state (withstanding high voltage), the first doped region 16 and the underlying epitaxial layer 11 form a PN junction, with the depletion region primarily extending towards the lightly doped side. If the first doped region 16 is directly below the heavily doped epitaxial layer 11, an abrupt junction will be formed. The depletion region of this junction is extremely narrow, and according to the Poisson equation, the electric field strength E = -dV / dx will be very high, resulting in an extremely high peak electric field located precisely at the interface between the first doped region 16 and the heavily doped layer. The presence of the third doped layer 133 is equivalent to inserting a buffer layer between the first doped region 16 and the heavily doped epitaxial layer 11. This creates a gradient change in doping concentration from "P (first doped region 16) — N- (third doped layer 133) — N+ (epitaxy layer 11)", similar to the characteristics of a "linearly gradual junction" or "punch-through junction". This gradient doping allows the depletion region to extend upwards into the well region more smoothly and widely. The decrease in potential (voltage determined by dV = -E × dx) is distributed over a wider distance, thereby significantly reducing the peak electric field at the well / N-type buried layer interface.

[0044] like Figure 1 As shown, in order to further enhance the synergistic effect of the first doped layer 131, the second doped layer 132 and the third doped layer 133 in the doped structure 13, the ratio of the thickness of the first doped layer 131, the thickness of the second doped layer 132 and the thickness of the third doped layer 133 is in the range of 1: (1.5~2): 1~1: 2: 1.

[0045] In the above implementation scheme, the thickness of the first doped layer 131 can be 0.08~0.12μm, the thickness of the second doped layer 132 can be 0.1~0.2μm, and the thickness of the third doped layer 133 can be 0.08~0.12μm. The thickness of the first doped layer 131 can be the same as or different from the thickness of the third doped layer 133.

[0046] In other embodiments, such as Figure 1 As shown, the ratio of the doping concentration of the first doped layer 131, the doping concentration of the second doped layer 132, and the doping concentration of the third doped layer 133 ranges from (1.5~2):(2~3):1. The doping concentration ratio among the first doped layer 131, the second doped layer 132, and the third doped layer 133 is within the above range, which can further enhance the synergistic effect of the first doped layer 131, the second doped layer 132, and the third doped layer 133 in the doped structure 13, thereby further improving the performance of the semiconductor structure.

[0047] In practical applications, the doping concentration of the first doped layer 131 can be 2 × 10⁻⁶. 17 ~4×10 17 cm -3 The doping concentration of the second doped layer 132 can be 3 × 10⁻⁶. 17 ~5×10 17 cm -3 The doping concentration of the third doped layer 133 can be 1×10⁻⁶. 17 ~3×10 17 cm -3 .

[0048] In some embodiments, such as Figure 1 As shown, the minimum distance between the bottom surface of the trench gate structure 12 and the surface of the third doped layer 133 away from the substrate 10 is the first distance, and the ratio of the first distance to the thickness of the third doped layer 133 is in the range of (1~2):(2~3). The above ratio range can further optimize the electric field distribution at the bottom of the trench, reduce the current concentration effect at the bottom of the trench, and improve the reliability of the device.

[0049] In the above implementation scheme, during the fabrication of the trench gate structure 12, when etching to form the trench, the etched portion can stop at a position of 1 / 2 to 2 / 3 of the thickness of the third doped layer 133.

[0050] In this invention, such as Figure 1As shown, the ratio of the depth to the width of the trench gate structure 12 is in the range of (1~5):1. The aspect ratio of the trench gate structure 12 is within the above range, which helps to optimize the electric field distribution and improve the breakdown voltage; at the same time, it can also disperse the current, thereby further reducing the current concentration effect at the bottom of the trench.

[0051] In some embodiments, the depth of the trench gate structure 12 can be 0.3~3μm, and the width of the trench gate structure 12 can be 0.3~0.6μm. That is, the trench gate structure 12 is formed by removing part of the third doped layer 133 to form the trench.

[0052] like Figure 1 As shown, the semiconductor structure further includes a first doped region 16, a second doped region 17, and a third doped region 18. These three regions are located within the epitaxial layer 11. The first doped region 16 is located on the side of the second doped region 17 and the third doped region 18 closest to the substrate 10, and in a direction perpendicular to the substrate 10, the first doped region 16 is located on the side of the third doped region 18 furthest from the second doped region 17. The doping type of the first doped region 16 is the same as that of the second doped region 17, while the doping type of the first doped region 16 is different from that of the third doped region 18. The second doped region 17 can reduce the lateral resistance of the first doped region 16. The third doped region 18 can form an ohmic contact with the source structure 14, thereby reducing the contact resistance.

[0053] In the above implementation, the doping concentration of the second doped region 17 is greater than the doping concentration of the first doped region 16. In the thickness direction perpendicular to the substrate 10, the average thickness of the first doped region 16 can be 0.7~0.8 μm. The doping concentration of the first doped region 16 can be 1E+17±50%cm. -3 In the thickness direction perpendicular to the substrate 10, the average thickness of the second doped region 17 can be 0.2~0.3 μm, and the doping concentration of the second doped region 17 can be 1E+19±50%cm. -3 The doping elements of the first doped region 16 and the second doped region 17 can be B, Al, Ga, etc. In the thickness direction perpendicular to the substrate 10, the average thickness of the third doped region 18 can be 0.2~0.3 μm, and the doping concentration of the third doped region 18 can be 1E+19~1E+20 cm⁻¹. -3 A channel is formed between adjacent third dopants, and the width of the channel is 0.3~0.6μm along a direction perpendicular to the thickness of the substrate 10.

[0054] like Figure 1 As shown, the trench gate structure 12 includes a gate layer 121, a first dielectric layer 122, and a gate electrode 123. The first dielectric layer 122 is located on the side of the gate layer 121 closer to the substrate 10, and the gate electrode 123 is located on the side of the gate layer 121 away from the substrate 10. Furthermore, in the thickness direction perpendicular to the substrate 10, the first dielectric layer 122 is located on both sides of the gate layer 121. The first dielectric layer 122 can be used to improve interface states, thereby further improving carrier mobility.

[0055] The gate layer 121 can be made of polysilicon and its width can be 0.2~1μm. The first dielectric layer 122 can be made of silicon oxide and its thickness can be 300~800 angstroms.

[0056] In other embodiments, such as Figure 1 As shown, the semiconductor structure further includes: a second dielectric layer 19 located between the adjacent trench gate structure 12 and the source structure 14, and on the side of the gate structure 12 away from the substrate 10; and an ohmic contact layer 20 located between the source structure 14 and the epitaxial layer 11. The second dielectric layer 19 provides electrical isolation, preventing short circuits between metal wiring layers of different levels, and also contributes to surface planarization, which is crucial for subsequent metal layer deposition because a flat surface reduces irregularities between metal lines, thereby reducing resistance and capacitance effects in signal transmission. The ohmic contact layer 20 forms a low-resistance, highly conductive contact interface in the semiconductor device, allowing current to flow efficiently between the metal and semiconductor materials, further reducing the contact resistance of the semiconductor device and thus further improving the overall efficiency of the device.

[0057] The second dielectric layer 19 can be used as an interlayer dielectric layer to isolate the gate structure 12 and the source structure 14. The material of the second dielectric layer 19 can be silicon oxide or the like, and its thickness can be 600~1000 nm. The ohmic contact layer 20 can be formed using metal materials such as Ni or Ti.

[0058] This application also provides a method for fabricating a semiconductor structure, which can be used to fabricate any of the aforementioned semiconductor structures. Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 2 As shown, the above method includes:

[0059] Step S301: Provide a substrate, and sequentially form a first pre-epitaxial layer, a pre-doped structure, and a second pre-epitaxial layer on one side of the substrate;

[0060] The substrate material can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, or sapphire, and the resistivity of the substrate can be 0.02 ± 20% Ωcm. The first pre-epiaxial layer, the second pre-epiaxial layer, and the pre-doped structure can be a single-layer structure or a multilayer structure. The first and second pre-epiaxial layers can be used as drift layers, bearing the main breakdown load. The doping concentration of the first and second pre-epiaxial layers can be 1E+15~1E1+16 cm⁻¹. -3 The thicknesses of the first and second pre-epitaxial layers can be set according to the breakdown voltage of the MOS device. The higher the voltage of the MOS device, the greater the thickness of the pre-epitaxial layers.

[0061] Step S302: Sequentially remove part of the second pre-epitaxial layer and part of the pre-doped structure to obtain a trench. The remaining first pre-epitaxial layer, the remaining pre-doped structure and the remaining second pre-epitaxial layer form an epitaxial layer, and a trench gate structure is formed in the trench. In the direction from the substrate to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases.

[0062] The width and depth of the trench gate structure can be set according to actual needs.

[0063] Step S303: A source structure is formed on the side of the epitaxial layer away from the substrate.

[0064] The aforementioned source structure can serve as the input terminal for current. The material of the aforementioned source structure can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0065] Step S304: A drain structure is formed on the side of the substrate away from the epitaxial layer.

[0066] Specifically, the drain structure described above can serve as the output terminal of the current, and the material of the drain structure can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0067] This embodiment provides a method for fabricating a semiconductor structure. First, a substrate is provided, and a first pre-epitaxial layer, a pre-doped structure, and a second pre-epitaxial layer are sequentially formed on one side of the substrate. Then, a portion of the second pre-epitaxial layer and a portion of the pre-doped structure are sequentially removed to obtain a trench. The remaining first pre-epitaxial layer, the remaining pre-doped structure, and the remaining second pre-epitaxial layer form an epitaxial layer, and a trench gate structure is formed in the trench. In the direction from the substrate to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases. Next, a source structure is formed on the side of the epitaxial layer away from the substrate. Finally, a drain structure is formed on the side of the substrate away from the epitaxial layer. In this scheme, the doped structure located between the trench gate structure and the substrate exhibits a doping concentration that first increases and then decreases in the direction from the substrate to the epitaxial layer. The portion where the doping concentration decreases creates a gradient change, similar to a "linearly variable junction" or "punch-through junction." This gradient doping allows the depletion region to extend upwards more smoothly and broadly into the less concentrated portion of the epitaxial layer, providing excellent interface characteristics. The portion where the doping concentration increases reduces resistivity, providing a lateral current expansion layer for electrons. After electrons are injected from the channel, they diffuse laterally, dispersing the current from the narrow region directly below the channel to a flat plane. Then, the current flows vertically downwards uniformly from this broad plane. This "lateral-then-vertical" current path significantly alleviates the "current congestion" effect in traditional structures, especially under overcurrent (such as short-circuit) conditions, preventing the formation of local hot spots and significantly improving the short-circuit withstand capability of the semiconductor structure. Through the synergistic effect of different doping concentrations in the doped structure, the technical problem of how to improve the performance of semiconductor structures is solved.

[0068] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the semiconductor structure fabrication method of this application will be described in detail below with reference to specific embodiments.

[0069] This embodiment relates to a specific method for fabricating a semiconductor structure. The schematic diagrams of the structures obtained in each step of the above fabrication method are shown in Figure 3. The fabrication method includes the following steps:

[0070] Step S1: Provide a substrate 10, and sequentially form a first pre-epipolar layer 21, a pre-doped structure 22, and a second pre-epipolar layer 23 on one side of the substrate 10. The pre-doped structure 22 includes a first doped layer 131, a second doped layer 132, and a pre-doped layer 221, resulting in the structure shown in FIG3(a).

[0071] Step S2: Ion implantation is performed on the second pre-epithetical layer 23 to form a second doped region 17, resulting in the structure shown in Figure 3(b). Ion implantation is performed on the second pre-epithetical layer 23 to form a pre-doped region 24, resulting in the structure shown in Figure 3(c). Ion implantation is performed on the pre-doped region 24 to form a third doped region 18. The remaining pre-doped region 24 forms a first doped region 16. The first doped region 16, the second doped region 17, and the third doped region 18 form the second pre-epithetical layer 23, resulting in the structure shown in Figure 3(d).

[0072] Step S3: Sequentially remove part of the second pre-epipolar layer 23 and part of the pre-doped layer 221 to obtain a groove 25. The remaining first pre-epipolar layer 21, the remaining pre-doped structure 22 and the remaining second pre-epipolar layer 23 form an epitaxial layer 11. The remaining pre-doped layer 221 forms a third doped layer 133. The first doped layer 131, the second doped layer 132 and the third doped layer 133 form a doped structure 13, resulting in the structure shown in FIG3(e).

[0073] Step S4: A first dielectric layer 122 is formed in the above-mentioned groove 25 to obtain the structure shown in FIG3(f), and a gate layer 121 and a gate electrode 123 are further formed in the groove 25 to form a trench gate structure 12. In the direction from the above-mentioned substrate 10 to the above-mentioned epitaxial layer 11, the doping concentration of the above-mentioned doped structure 13 first increases and then decreases to obtain the structure shown in FIG3(f).

[0074] Step S5: A second dielectric layer 19 is formed on the side of the gate electrode 123 away from the substrate 10, and an ohmic contact layer 20 is formed on the side of the epitaxial layer 11 away from the substrate 10, to obtain the structure shown in FIG3(h).

[0075] Step S6: A source structure 14 is formed on the side of the epitaxial layer 11 away from the substrate 10, resulting in the structure shown in FIG3(i);

[0076] Step S7: A drain structure 15 is formed on the side of the substrate 10 away from the epitaxial layer 11, resulting in the following: Figure 1 The structure shown.

[0077] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0078] 1) The semiconductor structure of this application includes a substrate, an epitaxial layer, a trench gate structure, a doped structure, a source structure, and a drain structure. The epitaxial layer is located on one side of the substrate; the trench gate structure is located within the epitaxial layer; the doped structure is located within the epitaxial layer, and at least part of the doped structure is located between the trench gate structure and the substrate. In the direction from the substrate to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases; the source structure is located on the side of the epitaxial layer away from the substrate; and the drain structure is located on the side of the substrate away from the epitaxial layer. In this scheme, the doped structure located between the trench gate structure and the substrate exhibits a doping concentration that first increases and then decreases in the direction from the substrate to the epitaxial layer. The portion where the doping concentration decreases creates a gradient change, similar to a "linearly variable junction" or "punch-through junction." This gradient doping allows the depletion region to extend upwards more smoothly and broadly into the less concentrated portion of the epitaxial layer, providing excellent interface characteristics. The portion where the doping concentration increases reduces resistivity, providing a lateral current expansion layer for electrons. After electrons are injected from the channel, they diffuse laterally, dispersing the current from the narrow region directly below the channel to a flat plane. Then, the current flows vertically downwards uniformly from this broad plane. This "lateral-then-vertical" current path significantly alleviates the "current congestion" effect in traditional structures, especially under overcurrent (such as short-circuit) conditions, preventing the formation of local hot spots and significantly improving the short-circuit withstand capability of the semiconductor structure. Through the synergistic effect of different doping concentrations in the doped structure, the technical problem of how to improve the performance of semiconductor structures is solved.

[0079] 2) The semiconductor structure fabrication method of this application firstly provides a substrate and sequentially forms a first pre-epipolar layer, a pre-doped structure, and a second pre-epipolar layer on one side of the substrate; then, a portion of the second pre-epipolar layer and a portion of the pre-doped structure are sequentially removed to obtain a trench; the remaining first pre-epipolar layer, the remaining pre-doped structure, and the remaining second pre-epipolar layer form an epitaxial layer, and a trench gate structure is formed in the trench; in the direction from the substrate to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases; then, a source structure is formed on the side of the epitaxial layer away from the substrate; finally, a drain structure is formed on the side of the substrate away from the epitaxial layer. In this scheme, the doped structure located between the trench gate structure and the substrate exhibits a doping concentration that first increases and then decreases in the direction from the substrate to the epitaxial layer. The portion where the doping concentration decreases creates a gradient change, similar to a "linearly variable junction" or "punch-through junction." This gradient doping allows the depletion region to extend upwards more smoothly and broadly into the less concentrated portion of the epitaxial layer, providing excellent interface characteristics. The portion where the doping concentration increases reduces resistivity, providing a lateral current expansion layer for electrons. After electrons are injected from the channel, they diffuse laterally, dispersing the current from the narrow region directly below the channel to a flat plane. Then, the current flows vertically downwards uniformly from this broad plane. This "lateral-then-vertical" current path significantly alleviates the "current congestion" effect in traditional structures, especially under overcurrent (such as short-circuit) conditions, preventing the formation of local hot spots and significantly improving the short-circuit withstand capability of the semiconductor structure. Through the synergistic effect of different doping concentrations in the doped structure, the technical problem of how to improve the performance of semiconductor structures is solved.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; an epitaxial layer on one side of the substrate; a trench gate structure in the epitaxial layer; a doped structure in the epitaxial layer, and at least part of the doped structure is between the trench gate structure and the substrate, and the doping concentration of the doped structure first increases and then decreases in the direction of the substrate pointing to the epitaxial layer; a source structure on the side of the epitaxial layer away from the substrate; a drain structure on the side of the substrate away from the epitaxial layer.

2. The semiconductor structure of claim 1, wherein, The doped structure comprises a first doped layer, a second doped layer and a third doped layer, wherein the first doped layer is between the trench gate structure and the substrate, the second doped layer is on the side of the first doped layer away from the substrate, the third doped layer is on the side of the second doped layer away from the substrate, and in the direction perpendicular to the thickness of the substrate, the third doped layer is on both sides of the trench gate structure, the doping concentration of the first doped layer is less than the doping concentration of the second doped layer, and the doping concentration of the first doped layer is greater than the doping concentration of the third doped layer.

3. The semiconductor structure of claim 2, wherein, The ratio of the thickness of the first doped layer, the thickness of the second doped layer and the thickness of the third doped layer ranges from 1:(1.5-2):1-2:1:

1.

4. The semiconductor structure of claim 2, wherein, The ratio of the doping concentration of the first doped layer, the doping concentration of the second doped layer and the doping concentration of the third doped layer ranges from (1.5-2):(2-3):

1.

5. The semiconductor structure of claim 2, wherein, The minimum distance between the bottom surface of the trench gate structure and the surface of the third doped layer away from the substrate is a first distance, and the ratio of the first distance to the thickness of the third doped layer ranges from (1-2):(2-3).

6. The semiconductor structure of claim 1, wherein, The ratio of the depth of the trench gate structure to the width of the trench gate structure ranges from (1-5):

1.

7. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a first doped region, a second doped region and a third doped region, the first doped region, the second doped region and the third doped region are in the epitaxial layer, the first doped region is on the side of the second doped region and the third doped region close to the substrate, and in the direction perpendicular to the substrate, the first doped region is on the side of the third doped region away from the second doped region, wherein the doping type of the first doped region is the same as the doping type of the second doped region, and the doping type of the first doped region is different from the doping type of the third doped region.

8. The semiconductor structure of claim 1, wherein, The trench gate structure comprises a gate layer, a first dielectric layer and a gate electrode, the first dielectric layer is on the side of the gate layer close to the substrate, and the gate electrode is on the side of the gate layer away from the substrate, and in the direction perpendicular to the thickness of the substrate, the first dielectric layer is on both sides of the gate layer.

9. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a second dielectric layer between adjacent trench gate structures and source structures, and on the side of the gate structure away from the substrate; an ohmic contact layer between the source structure and the epitaxial layer.

10. A method of fabricating a semiconductor structure, characterized by, The method is used for preparing the semiconductor structure in any one of claims 1 to 9, and the method comprises the following steps: providing a substrate, and sequentially forming a first preliminary epitaxial layer, a preliminary doped structure and a second preliminary epitaxial layer on one side of the substrate; sequentially removing part of the second preliminary epitaxial layer and part of the preliminary doped structure to obtain a groove, and the remaining first preliminary epitaxial layer, the remaining preliminary doped structure and the remaining second preliminary epitaxial layer form an epitaxial layer, and a trench gate structure is formed in the groove, and in the direction of the substrate pointing to the epitaxial layer, the doping concentration of the doped structure first increases and then decreases; forming a source structure on the side of the epitaxial layer away from the substrate; forming a drain structure on the side of the substrate away from the epitaxial layer.

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