Source / drain epitaxial profile and method for implementing same

Abstract

The invention discloses a source / drain epitaxial profile and a method for implementing the same. A method includes forming a plurality of semiconductor nanostructures, where an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess alongside the plurality of semiconductor nanostructures, and forming a first semiconductor layer from the plurality of semiconductor nanostructures. The first semiconductor layer has a convex shape in a cross-sectional view of the first semiconductor layer. A second semiconductor layer is formed over the first semiconductor layer. A silicide region is formed over and in contact with the second semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to source / drain epitaxial profiles and methods for their implementation. Background Technology

[0002] Technological advancements in integrated circuit (IC) materials and design have resulted in several generations of ICs, each featuring smaller and more complex circuitry than its predecessors. Throughout IC evolution, functional density (e.g., the number of interconnect devices per chip area) has typically increased, while geometric dimensions have decreased. This scaling down process generally provides benefits through increased manufacturing efficiency and reduced associated costs.

[0003] This miniaturization also increases the complexity of processing and manufacturing ICs, and similar advancements in IC processing and manufacturing are needed to achieve these progresses. For example, Gate-All-Around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods for manufacturing GAA transistors are being developed. Summary of the Invention

[0004] According to a first aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures; forming source / drain recesses adjacent to the plurality of semiconductor nanostructures; forming a first semiconductor layer from the plurality of semiconductor nanostructures, wherein the first semiconductor layer has a convex shape in a cross-sectional view of the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; and forming and contacting a silicide region on and therewith the second semiconductor layer.

[0005] According to a second aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a semiconductor stack comprising a plurality of semiconductor nanostructures; and forming source / drain regions, comprising: epitaxially growing a first semiconductor layer, the first semiconductor layer comprising a first portion and a second portion at the same level, wherein the first portion and the second portion are grown toward each other, and wherein the first portion comprises a bottom portion, a top portion and an intermediate portion between the bottom portion and the top portion; annealing the first semiconductor layer, wherein a first thickness of the intermediate portion increases and a second thickness of the top portion and the bottom portion decreases; and epitaxially growing a second semiconductor layer on the first semiconductor layer.

[0006] According to a third aspect of this disclosure, a semiconductor structure is provided, comprising: a semiconductor stack including a plurality of semiconductor nanostructures, wherein the plurality of semiconductor nanostructures include: a first semiconductor nanostructure; and a second semiconductor nanostructure overlapping the first semiconductor nanostructure; a source / drain region adjacent to the semiconductor stack, the source / drain region including: a first semiconductor layer including a first portion and a second portion, wherein the first portion includes an intermediate portion having a maximum thickness of the first portion, and wherein the thickness of the first portion gradually decreases toward corresponding upper and lower portions of the first portion; and a second semiconductor layer between the first portion and the second portion of the first semiconductor layer; a source / drain silicide region on and in contact with the second semiconductor layer, wherein the source / drain silicide region is spaced apart from the first semiconductor layer; and a source / drain contact plug on and in contact with the source / drain silicide region. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B as well as Figures 21 to 23 A view showing an intermediate stage in the formation of a gate-all-around (GAA) transistor according to some embodiments is shown.

[0009] Figures 15 to 20 A view showing the intermediate stages of forming the source / drain regions according to an alternative embodiment is illustrated.

[0010] Figures 24 to 29 A view showing the intermediate stages of forming the source / drain regions according to an alternative embodiment is illustrated.

[0011] Figure 30 A process flow for forming a GAA transistor according to some embodiments is shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and not limiting. For instance, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially related terms (e.g., "below," "below," "lower part," "overlapping," "upper part," etc.) may be used herein to facilitate the description of the relationship between one element or feature shown in the figure and another element(s) or feature(s). The apparatus may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0014] A gate-all-around (GAA) transistor and a method for forming the same are provided. According to some embodiments, forming the source / drain region of the GAA transistor includes: forming a first epitaxial layer with raised sidewalls, and forming a second epitaxial layer over the first epitaxial layer. The first epitaxial layer has a lower dopant concentration (e.g., boron) than the second epitaxial layer and may have a lower percentage of germanium atoms. Therefore, with the first epitaxial layer having a raised profile, the top of the epitaxial layer is narrower, thus creating more space for the second epitaxial layer. The source / drain silicide region and the overlying source / drain contact plug are more likely to be located on the second epitaxial layer than on the first epitaxial layer. Therefore, the source / drain resistance is reduced.

[0015] Although the GAA transistor is used as an example to discuss the concepts of this disclosure, embodiments can be applied to other types of transistors, including but not limited to planar transistors, FinFETs, Complementary Field-Effect Transistors (CFETs), etc. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the contemplated scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] Furthermore, although p-type transistors may be discussed as examples in some sections of the discussion, the concepts of this application are readily applicable to the formation of n-type transistors, wherein the conductivity type of the corresponding feature is the opposite of that in p-type transistors.

[0017] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B as well as Figures 15 to 23 A cross-sectional view of an intermediate stage in the formation of a GAA transistor according to some embodiments of the present disclosure is shown. The corresponding process is also schematically reflected in... Figure 30 The process flow shown is as follows.

[0018] refer to Figure 1 The diagram shows a perspective view of wafer 10. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, etc., but other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, etc. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor substrate.

[0019] According to some embodiments, a multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are described in... Figure 30 The process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material, which is different from the first semiconductor material.

[0020] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or includes the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the first layer 22A (e.g., SiGe) is deposited by epitaxial growth, and the corresponding deposition methods may include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have a first thickness in the range of about 30 Å to about 300 Å. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0021] Once the first layer 22A is deposited on the substrate 20, a second layer 22B is deposited on top of the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, and combinations thereof, and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon-germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0022] According to some embodiments, a second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to have a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to have a thickness different from that of the first layer 22A. According to some embodiments, for example, the second layer 22A has a thickness in the range of about 4 nm to 7 nm, while the second layer 22B has a thickness in the range of about 8 nm to 12 nm.

[0023] Once the second layer 22B is formed on top of the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to in the specification as sacrificial layer 22A. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0024] According to some embodiments, one or more pad oxide layers and one or more hard mask layers (not shown) may be formed on the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0025] refer to Figure 2 In one or more etching processes, a portion of the multilayer stack 22 and the underlying substrate 20 is patterned, thereby forming trenches 23. The corresponding process is... Figure 30 The process flow 200 shown is illustrated as process 204. Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', a portion of substrate 20 is left, and these portions are hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layer 22A and semiconductor layer 22B. hereinafter, semiconductor layer 22A is alternatively referred to as sacrificial layer, and semiconductor layer 22B is alternatively referred to as nanostructure. The portion of multilayer stack 22' and the underlying substrate strip 20' is collectively referred to as semiconductor strip 24.

[0026] In the above embodiments, the GAA transistor structure can be patterned using any suitable method. For example, these structures can be patterned using one or more photolithography processes (including dual-patterning or multi-patterning processes). Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have smaller spacing, for example, than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are then used to pattern the GAA structure.

[0027] Figure 3 The formation of isolation region 26 is shown; isolation region 26 is also referred to as shallow trench isolation (STI) region in the specification. The corresponding process is described in... Figure 30The process flow 200 is shown as process 206. STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, etc. STI region 26 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, etc. A planarization process (e.g., chemical mechanical polishing (CMP) or mechanical grinding) may then be performed to flush the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes STI region 26.

[0028] The STI region 26 is then recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top portion of the substrate strip 20' and the multilayer stack 22'. The recess of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. Plasma can be generated during the etching process. Argon gas may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 26 is performed by a wet etching process. For example, the etching chemicals may include HF.

[0029] refer to Figure 4 A dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is described in... Figure 30 The process flow 200 is shown as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 located on the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, the dummy gate electrode 34 may be formed using polycrystalline silicon or amorphous silicon, and may also use other materials such as amorphous carbon.

[0030] Each dummy gate stack 30 may further include one or more hard mask layers 36 located above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may span a single protruding fin 28 or multiple protruding fins 28 and an STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding fin 28. Forming the dummy gate stack 30 includes: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers by one or more patterning processes.

[0031] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material (e.g., silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.) and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include: depositing one or more dielectric layers, and then performing one or more anisotropic etching processes on the dielectric layers(one or more). The remaining portion of the dielectric layers(one or more) constitutes the gate spacers 38.

[0032] Figure 5A and Figure 5B It shows Figure 4 Cross-sectional view of the structure shown. Figure 5A It shows Figure 4 The reference cross section A1-A1 cuts through the portion of the protruding fin 28 that is not covered by the gate stack 30 and the gate spacer 38, and is perpendicular to the gate length direction. Figure 5B It shows Figure 4 The reference cross section BB is parallel to the length direction of the protruding fin 28.

[0033] refer to Figure 6A and Figure 6B The portion of the protruding fin 28 that is not directly below the dummy gate stack 30 and the gate spacer 38 is recessed using an etching process to form a recess 42. The corresponding process is as follows: Figure 30The process flow 200 is shown as process 210. For example, a dry etching process can be performed using a mixture of C2F6, CF4, SO2, HBr, Cl2 and O2, or a mixture of HBr, Cl2, O2 and CH2F2, etc., to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or may be lower than the bottom of the multilayer semiconductor stack 22' (e.g., ...). Figure 6B (As shown). This etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown. Figure 6B As shown.

[0034] refer to Figure 7A and Figure 7B The sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed relative to the edges of the corresponding upper nanostructure 22B and the corresponding lower nanostructure 22B. The corresponding process is carried out in... Figure 30 The process flow 200 shown is illustrated as process 212.

[0035] The lateral recesses of the sacrificial semiconductor layer 22A can be achieved using a wet etching process that employs an etchant more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon-germanium (SiGe)) than for the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon-germanium and the nanostructure 22B is formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform the wet etching process. The wet etching process can be performed using immersion processes, spraying processes, spin coating processes, etc.

[0036] According to an alternative embodiment, the lateral recess of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of dry etching and wet etching processes.

[0037] refer to Figure 8A and Figure 8B This forms the internal spacer 44. The corresponding process is as follows: Figure 30 The process flow 200 is shown as process 214. According to some embodiments, the formation of the internal spacer 44 includes depositing a conformal dielectric layer that extends into the lateral recess 41. Figure 7B Next, an etching process (also known as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral recess 41, thereby leaving the portion of the spacer layer within the lateral recess 41. The remaining portion of the spacer layer is referred to as the inner spacer 44. The inner spacer may be a single-layer spacer or may include multiple sublayers (e.g., two to three sublayers).

[0038] According to an alternative embodiment, the internal spacer 44 is not formed, and the subsequently formed source / drain regions can contact the high-k dielectric layer in the alternative gate stack.

[0039] refer to Figure 9A and Figure 9B For example, a source / drain region 48 is formed in the recess 42 using an epitaxial process. According to some embodiments, the details of the source / drain region 48 are as follows: Figure 23 or Figure 29 As shown in the image.

[0040] Figures 15 to 20 Details of the formation of the source / drain region 48 according to some embodiments are shown. Figure 15 It shows Figure 8B An enlarged view of region 47, in which the recess 42 and the internal spacer 44 have been formed. In such a way... Figure 15 The example shown illustrates three stacked nanostructures 22B as an example. The number of nanostructures 22B in the stack can be any other number, for example, in the range of 2 to about 5.

[0041] refer to Figure 16 A dielectric layer 49 is formed at the bottom of the recess 42. The corresponding process is as follows: Figure 30 The process flow 200 is shown as process 216. According to some embodiments, the dielectric layer 49 includes a silicon nitride layer. The dielectric layer 49 may have a monolayer structure comprising a single layer, or a multilayer structure comprising multiple dielectric layers formed of different dielectric materials. The material of the dielectric layer 49 may be selected from silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and combinations thereof.

[0042] Figure 17 The epitaxy of semiconductor layer 48A (also referred to as layer-1 or L1) using a selective epitaxial process is shown. The corresponding process is described in... Figure 30 The process flow 200 is shown as process 218. The semiconductor layer 48A shown, grown from opposite sides of the recess 42, is referred to as the first portion and the second portion of semiconductor layer 48A. Semiconductor layer 48A is selectively grown from the exposed sidewall surface of nanostructure 22B. According to some embodiments where the top surface of semiconductor substrate 20 is on a (100) surface plane, the sidewall surface of semiconductor layer 48A may be on a (110) surface plane. On the other hand, no portion (or only a very small portion) of semiconductor layer 48A is grown directly from dielectric features such as gate spacer 38 and hard mask 36 (refer to FIG. 9).

[0043] When the source / drain regions are the p-type regions of a p-type transistor, semiconductor layer 48A may include silicon, SiGe, or Ge, and may also include a p-type dopant (e.g., boron, indium, or a combination thereof). For example, semiconductor layer 48A may include boron-doped SiGe. Semiconductor layer 48A may have a density of approximately 4E2O / cm². 3 And about 7E20 / cm 3 The p-type dopant concentration can range between approximately 0% and approximately 40%.

[0044] According to an alternative embodiment where the source / drain regions are the n-type regions of an n-type transistor, semiconductor layer 48A may include Si, SiC, etc., and may also include an n-type dopant, such as phosphorus, arsenic, antimony, or combinations thereof. For example, semiconductor layer 48A may include SiP. The n-type dopant concentration may also be approximately 4E20 / cm³. 3 And about 7E20 / cm 3 Within the range between.

[0045] According to some embodiments, the formation of semiconductor layer 48A is performed at a relatively low first (wafer) temperature. The first temperature can be in the range of about 400°C to about 600°C. During the epitaxial process, a silicon-containing precursor (e.g., silane (SiH4), disilane (Si2H6), dichlorosilane (DCS, SiH2Cl2), etc., or combinations thereof) can be used as a deposition precursor. An etching gas such as HCl can be added. Flow rate ratio FR E / FR D It can be in the range of approximately 0.2 to approximately 0.4, where the value FR E It is the flow rate of the etching gas, and the value FR D It is the flow rate of the silicon-containing deposition precursor.

[0046] According to some embodiments, multiple discrete semiconductor layers 48A may exist, each epitaxially grown from a nanostructure 22B. The semiconductor layers 48A may have similar (and / or identical) dimensions and shapes. Furthermore, the upper semiconductor layers 48A may have the same dimensions and extend laterally into the recess 42 by the same distance as the corresponding lower semiconductor layer 48A. As the epitaxial process proceeds, portions of the semiconductor layers 48A grown from different nanostructures 22B are merged into an integrated assembly, such as... Figure 17 As shown. The sidewalls of the merged semiconductor layer 48A have an X shape in the cross-sectional view. Due to the lower growth rate in the (111) direction, multiple small facets can be formed.

[0047] Further reference Figure 17 The epitaxial process is stopped, and annealing process 112 is performed to reshape semiconductor layer 48A. The corresponding process is... Figure 30 The process flow 200 is shown as process 220. According to some embodiments, the wafer temperature during annealing process 112 can be in the range of about 700°C to about 850°C. The process gas may include an inert gas and / or a reducing gas to prevent oxidation of semiconductor layer 48A. According to some embodiments, the process gas may include hydrogen (H2), nitrogen (N2), argon, or a combination thereof. The pressure of the process gas can be in the range of about 20 Torr and about 1 atmosphere. The annealing duration can be in the range of about 30 seconds to about 120 seconds.

[0048] The reshaped semiconductor layer 48A in Figure 18 As shown in the diagram. In annealing process 112, semiconductor layer 48A does not melt into a liquid. However, the temperature is high enough, and the annealing duration is long enough, to cause migration of semiconductor layer 48A and result in reshaping. Therefore, the middle portion between the topmost and corresponding bottommost ends of semiconductor layer 48A becomes thicker, and the corresponding upper and lower portions become thinner.

[0049] The transition of thickness at different levels in different portions of semiconductor layer 48A can be continuous. The decrease in thickness from the thickest portion to the corresponding top and bottom ends can be gradual and continuous. Therefore, the sidewall surfaces of semiconductor layer 48A can be continuously curved. The thickest portion of semiconductor layer 48A can be located midway between the corresponding top and bottom ends of semiconductor layer 48A (or near the midway, for example, with a positional change of less than about 10% of the height of semiconductor layer 48A). The resulting semiconductor layer 48A is also referred to hereinafter as a raised semiconductor layer 48A. The sidewalls of semiconductor layer 48A can define an hourglass-shaped space therebetween.

[0050] According to some embodiments, the annealing process 112 ends before the semiconductor layer 48A grown from the opposite side of the recess 42 is merged, such as... Figure 18 As shown. According to some embodiments, when the annealing process 112 stops, the spacing S1 between adjacent semiconductor layers 48A ( Figure 18 It can be in the range of approximately 0 nm to approximately 13 nm.

[0051] According to an alternative embodiment, the annealing process 112 is extended. Therefore, the top and bottom portions of the semiconductor layer 48A become increasingly thinner, and more and more material of the semiconductor layer 48A migrates to the portion at the middle level. The middle portions of the semiconductor layer 48A grown from opposite sides of the recess 42 eventually merge. Therefore, Figure 18 The extended annealing process 112 is shown as a dashed line to indicate that the extended annealing process 112 can cause merging. The resulting structure is as follows: Figure 19 As shown. The sidewalls of the merged semiconductor layer 48A have an X shape in the cross-sectional view. Figure 19The dashed lines also represent the sidewalls of semiconductor layer 48A in embodiments where semiconductor layer 48A is not merged. According to some embodiments, the spacing S2 of the merged semiconductor layers 48A can range from about 5 nm to about 18 nm, wherein the spacing S2 is measured at the mid-level of the topmost nanostructure 22B. The overlap height OLH of the merged semiconductor layers 48A can range from about 0 nm to about 20 nm.

[0052] According to some embodiments, the formation of the raised semiconductor layer 48A includes a single deposition and annealing cycle, which includes one or more deposition processes and a single annealing process 112 for reshaping. According to an alternative embodiment, the formation of the raised semiconductor layer 48A includes multiple deposition and annealing cycles, wherein each deposition and annealing cycle includes a deposition process followed by an annealing process for reshaping. The first annealing process 112 is performed after all semiconductor layers 48A grown from the same side of the recess have been consolidated. Otherwise, the migrating material would not be able to migrate to the intermediate level of the respective semiconductor layer 48A. Multiple deposition and annealing cycles can improve the reshaping profile and make the shape of the semiconductor layer 48A more raised, but at the cost of higher manufacturing costs and lower throughput.

[0053] Figure 20 The epitaxial growth of semiconductor layer 48B (also referred to as semiconductor layer-2 or L2) is shown. The corresponding process is described in... Figure 30 The process flow 200 is shown as process 222. The resulting semiconductor layer 48B is grown from and differs from semiconductor layer 48A. Semiconductor layer 48B can have a higher p-type dopant concentration than semiconductor layer 48A. For example, when the corresponding transistor is a p-type transistor, the boron concentration in semiconductor layer 48B can be approximately 5E20 / cm³. 3 3E21 / cm 3 Within the range between. When the corresponding transistor is an n-type transistor, the dopant is an n-type dopant, and the n-type dopant in semiconductor layer 48B can also have a higher dopant concentration than the dopant concentration in semiconductor layer 48A.

[0054] It should be understood that although semiconductor layer 48A can be merged, semiconductor layer 48B can be filled into the space below the merging point because it can enter the space below the merging point from a cross section different from the cross section shown.

[0055] According to some embodiments, the formation of semiconductor layer 48B is performed at a second (wafer) temperature, which may be in the same or similar temperature range as that used to form semiconductor layer 48A. For example, the second temperature may be in the range between about 400°C and about 600°C.

[0056] Semiconductor layer 48B may include SiGe with a higher percentage of germanium atoms than semiconductor layer 48A. For example, the percentage of germanium atoms in semiconductor layer 48B may be in the range of about 40% to about 90%. The top surface of semiconductor layer 48B is higher than the topmost surface of semiconductor layer 48A and the topmost surface of topmost nanostructure 22B.

[0057] Figure 21 The formation of a semiconductor layer (cap layer) 48C, for example by a selective epitaxial process, according to some embodiments is also shown. The corresponding process is... Figure 30 The process flow 200 is shown as process 224. According to some embodiments, the cap layer 48C comprises silicon and is germanium-free. The cap layer 48C may also comprise SiGe with a germanium atomic percentage lower than that in semiconductor layers 48A and 48B. The boron concentration in the cap layer 48C may also be lower than or equal to the boron concentration in semiconductor layer 48B. According to alternative embodiments, the cap layer 48C is not formed. Throughout the description, semiconductor layers 48A, 48B, and 48C are collectively referred to as source / drain regions 48.

[0058] Return to reference Figure 10A and Figure 10B This forms a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is as follows: Figure 30 The process flow 200 is shown as process 226. The corresponding structure is also shown in... Figure 21 As shown in the diagram. CESL 50 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 52 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 can be formed from an oxygen-containing dielectric material, which can be silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0059] The CESL 50 and ILD 52 are planarized using a planarization process (e.g., CMP or mechanical polishing). According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, such as... Figure 10A As shown. According to an alternative embodiment, the planarization process may expose the hard mask 36 and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within the process variation.

[0060] Next, the dummy gate electrode 34 and dummy gate dielectric 32 (and hard mask 36, if remaining) are removed in one or more etching processes to form a recess, as shown. Figure 11A and Figure 11B As shown. The corresponding process is in Figure 30 The process flow 200 shown is illustrated as process 228.

[0061] The sacrificial layer 22A is then removed to allow the recess 58 to extend between the nanostructures 22B. The corresponding process is as follows: Figure 30 The process flow 200 shown is illustrated as process 230. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective for the material of the sacrificial layer 22A, while the nanostructure 22B, the substrate 20, and the STI region 26 remain relatively unetched compared to the sacrificial layer 22A.

[0062] The corresponding process is Figure 30 The process flow 200 is shown as process 232. The corresponding process is... Figure 30 The process flow 200 is shown as process 232. The corresponding structure is also shown in... Figure 22 As shown in the figure. According to some embodiments, each gate dielectric 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed of or comprise silicon oxide. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the high-k dielectric layer may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0063] A gate electrode 68 is also formed. In the formation process, a conductive layer is first formed on a high-k dielectric layer, and the remaining portion of the recess 58 is filled. The gate electrode 68 may include a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof.

[0064] exist Figure 13A and Figure 13B In the process shown, the gate stack 70 is recessed such that a recess is formed directly above the gate stack 70 and between the opposite portion of the gate spacer 38. A gate mask 74 comprising one or more dielectric material layers (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each recess, followed by a planarization process to remove excess dielectric material extending above the ILD 52.

[0065] like Figure 13A and Figure 13BAs further shown, ILD 76 is deposited over ILD 52 and gate mask 74. An etch stop layer (not shown) may or may not be deposited prior to the formation of ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0066] exist Figure 14A and Figure 14B In this process, ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surfaces of the source / drain regions 48 and / or gate stack 70. These recesses can be formed by etching using anisotropic etching processes (e.g., RIE, NBE, etc.). Although Figure 14B The diagram shows contact plugs 80A and 80B in the same cross-section, but in various embodiments, contact plugs 80A and 80B may be formed in different cross-sections, thereby reducing the risk of short-circuiting each other.

[0067] After forming the recess, a silicide region 78 is formed above the epitaxial source / drain region 48. The corresponding process is as follows: Figure 30 The process flow 200 is shown as process 234. A contact plug 80B is then formed over the silicide region 78. Furthermore, a contact 80A (also referred to as a gate contact plug) is formed in the recess and is located above and in contact with the gate electrode 68. The corresponding structure is also... Figure 23 As shown in the figure. This forms transistor 82.

[0068] Figure 23 A portion of transistor 82 is shown, which is also... Figure 14A and Figure 14B As shown in the diagram. It should be understood that if the forming process of semiconductor layer 48A is not performed, some portions of the silicide region 78 and the (source / drain) contact plug 80B (also referred to as contact structure 80B) may be located on semiconductor layer 48A instead of semiconductor layer 48B. Semiconductor layer 48B may have a higher boron doping concentration and / or a higher percentage of germanium atoms than semiconductor layer 48A. Therefore, by reshaping semiconductor layer 48A and making the top portion of semiconductor layer 48A smaller, silicide region 78 is more likely to be located on semiconductor layer 48B instead of semiconductor layer 48A. Therefore, the source / drain resistance is reduced.

[0069] Figures 24 to 29The formation of a GAA transistor 82 according to an alternative embodiment is shown. These embodiments are substantially the same as the foregoing embodiments, except that the reshaping of semiconductor layer 48A is performed concurrently with (rather than after) the deposition of semiconductor layer 48A. Unless otherwise stated, the materials, structures, and formation processes of the components in these embodiments are substantially the same as those of the same components indicated by the same reference numerals in the foregoing embodiments. Where applicable, the details regarding materials, structures, and formation processes provided in each embodiment throughout the specification can be applied to any other embodiment.

[0070] The initial steps of these embodiments are basically the same as Figures 1 to 8A / Figure 8B The initial steps shown are the same. Next, refer to... Figure 24 The semiconductor layer 48A is deposited via epitaxy. According to some embodiments, the semiconductor layer 48A is deposited with a raised shape, wherein the middle portion is thicker than the corresponding upper and lower portions.

[0071] According to some embodiments, the formation of semiconductor layer 48A is performed at a relatively high temperature that can cause migration of semiconductor layer 48A, and therefore semiconductor layer 48A is formed to have a bump shape. The bump shape also grows as the formation process proceeds. This temperature is also higher than that used for forming such... Figure 17 The temperature of the semiconductor layer 48A shown. According to some embodiments, the temperature used to form the semiconductor layer 48A can be in the range of about 700°C and about 850°C.

[0072] During the epitaxial process, silicon-containing precursors (such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), or combinations thereof) can be used as deposition precursors. Etching gases such as HCl can be added. To form the bumped semiconductor layer 48A, the flow rate ratio FR can also be increased. E / FR D And this flow rate ratio can be greater than, for example Figure 17 The flow rate ratio FR in the deposition process shown E / FR D .For example, Figure 24 The flow rate ratio FR in the process shown E / FR D It can be in the range of approximately 0.4 to approximately 0.9.

[0073] Other process parameters that can affect the profile of semiconductor layer 48A include chamber pressure, deposition rate, etc., which can also influence the profile of semiconductor layer 48A. By employing an appropriate combination of the process parameters discussed above, a raised profile of semiconductor layer 48A can be achieved.

[0074] As the epitaxial process progresses, semiconductor layer 48A grows thicker and larger, such as Figure 25 As shown. During the epitaxial process, semiconductor layer 48A maintains a raised shape. According to some embodiments, semiconductor layer 48A can be grown until opposing portions of semiconductor layer 48A merge with each other, and the resulting structure... Figure 26 As shown in the figure. According to an alternative embodiment, the formation of semiconductor layer 48A is stopped before merging, as... Figure 25 As shown. Figure 26 The dashed lines are shown to represent the sidewalls of semiconductor layer 48A when the sidewalls of semiconductor layer 48A are not merged during the formation of semiconductor layer 48B.

[0075] According to some embodiments, such as Figure 25 and Figure 26 As further shown, annealing process 112 may (or may not) be further performed (when growth of semiconductor layer 48A stops) to reshape semiconductor layer 48A, making the top portion of semiconductor layer 48A thinner. A single deposition and annealing cycle may exist: this cycle is used to grow semiconductor layer 48A, and then annealing process 112 is performed without introducing a precursor for growth. Alternatively, multiple deposition and annealing cycles may exist, wherein each deposition and annealing cycle includes a deposition process and a subsequent annealing process.

[0076] Annealing process 112 can begin before or after the merging of semiconductor layer 48A. Furthermore, if semiconductor layer 48A is not merged at the start of subsequent annealing process 112, annealing process 112 may or may not involve merging, such as... Figure 25 and Figure 26 As shown. According to an alternative embodiment, annealing process 112 is not performed.

[0077] Figure 27 The formation of semiconductor layers 48B and 48C according to some embodiments is shown. Then CESL 50 and ILD 52 are performed. These processes are essentially the same as those in the reference [reference]. Figures 20 to 22 The processes discussed are the same, and will not be repeated in this article.

[0078] Figure 28 The formation of the replacement gate stack 70 is shown. Figure 29 The formation of the silicide region 78 and the source / drain contact plug 80B is shown. (Referenced) Figure 23 These processes have been discussed and will not be repeated here.

[0079] The embodiments of this disclosure have several advantageous features. By forming a first semiconductor layer in the source / drain region with a raised cross-sectional shape, the top of the first semiconductor layer is narrower. The space created by the narrow top is occupied by a second semiconductor layer, which has a lower resistivity than the first semiconductor layer. Therefore, the source / drain silicide region is more likely to be located on the second semiconductor layer. Consequently, the resistance of the conductive path, including the source / drain, the silicide region, and the source / drain contact plug, is reduced, and the drive current of the transistor is increased. These embodiments have even more significant results when a dielectric layer is formed below the source / drain region. Due to the dielectric layer that can be formed at the bottom of the source / drain region, less strain can be applied to the channel region, and the need to increase the drive current by reducing resistance can be achieved through the embodiments of this disclosure.

[0080] According to some embodiments of the present disclosure, a method includes: forming a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures; forming source / drain recesses next to the plurality of semiconductor nanostructures; forming a first semiconductor layer from the plurality of semiconductor nanostructures, wherein the first semiconductor layer has a convex shape in a cross-sectional view of the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; and forming and contacting a silicide region on and therewith the second semiconductor layer.

[0081] In one embodiment, forming the first semiconductor layer includes: depositing the first semiconductor layer; and performing an annealing process to thicken the middle portion of the first semiconductor layer. In another embodiment, after depositing the first semiconductor layer, the first semiconductor layer includes: a plurality of first portions grown from a plurality of semiconductor nanostructures; and a plurality of second portions between the plurality of first portions, wherein the plurality of second portions are thinner than the plurality of first portions.

[0082] In one embodiment, the first semiconductor layer is deposited at a first wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature equal to or higher than the first wafer temperature. In another embodiment, the first semiconductor layer includes a first portion and a second portion growing toward each other, wherein the first portion and the second portion are merged upon completion of the annealing process.

[0083] In one embodiment, the first semiconductor layer includes a first portion and a second portion growing toward each other, wherein the first portion and the second portion are physically separated upon completion of the annealing process. In another embodiment, when the first semiconductor layer is deposited, the middle portion of the first semiconductor layer is thicker than the corresponding upper and lower portions of the first semiconductor layer.

[0084] In one embodiment, the first semiconductor layer is deposited at a first wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature lower than the first wafer temperature. In another embodiment, the method further includes forming a dielectric layer at the bottom of the source / drain recess before forming the first semiconductor layer. In another embodiment, the first semiconductor layer is spaced from the dielectric layer by the second semiconductor layer. In another embodiment, the second semiconductor layer has a higher boron concentration than the first semiconductor layer.

[0085] According to some embodiments of the present disclosure, a method includes: forming a semiconductor stack comprising a plurality of semiconductor nanostructures; and forming source / drain regions, including: epitaxially growing a first semiconductor layer, the first semiconductor layer including a first portion and a second portion at the same level, wherein the first portion and the second portion are grown toward each other, and wherein the first portion includes a bottom portion, a top portion, and an intermediate portion between the bottom portion and the top portion; annealing the first semiconductor layer, wherein a first thickness of the intermediate portion increases, and a second thickness of the top portion and the bottom portion decreases; and epitaxially growing a second semiconductor layer on the first semiconductor layer.

[0086] In one embodiment, after the first semiconductor layer is annealed, the first portion and the second portion are spaced apart. In another embodiment, before the first semiconductor layer is annealed, the first portion has a non-protruding profile, and after the first semiconductor layers are merged, the first semiconductor layer has X-shaped sidewalls. In another embodiment, both the first portion and the second portion of the first semiconductor layer have protruding profiles at a first time before the first semiconductor layer is annealed and at a second time after the first semiconductor layer is annealed. In another embodiment, the first semiconductor layer is deposited at a first temperature, and the second semiconductor layer is deposited at a second temperature, which is lower than the first temperature.

[0087] According to some embodiments of this disclosure, a structure includes a semiconductor stack comprising a plurality of semiconductor nanostructures, wherein the plurality of semiconductor nanostructures include: a first semiconductor nanostructure; and a second semiconductor nanostructure overlapping the first semiconductor nanostructure; a source / drain region adjacent to the semiconductor stack, the source / drain region comprising: a first semiconductor layer including a first portion and a second portion, wherein the first portion includes an intermediate portion having a maximum thickness of the first portion, and wherein the thickness of the first portion gradually decreases toward corresponding upper and lower portions of the first portion; and a second semiconductor layer between the first portion and the second portion of the first semiconductor layer; a source / drain silicide region on and in contact with the second semiconductor layer, wherein the source / drain silicide region is spaced apart from the first semiconductor layer; and a source / drain contact plug on and in contact with the source / drain silicide region.

[0088] In one embodiment, the first portion is joined to the second portion, and wherein, in a cross-sectional view of the structure, a first sidewall of the first portion is joined to a second sidewall of the second portion to form an X-shape. In another embodiment, the first portion and the second portion are spaced apart, and in a cross-sectional view of the structure, the portion of the second semiconductor layer between the first and second portions has an hourglass shape. In yet another embodiment, the structure further includes a dielectric layer beneath the first and second semiconductor layers, wherein the first semiconductor layer is spaced apart from the dielectric layer by a bottom portion of the second semiconductor layer.

[0089] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein.

[0090] Example Example 1. A method for forming a semiconductor structure, comprising: forming a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures; forming source / drain recesses adjacent to the plurality of semiconductor nanostructures; forming a first semiconductor layer from the plurality of semiconductor nanostructures, wherein the first semiconductor layer has a convex shape in a cross-sectional view of the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; and forming and contacting a silicide region on and therewith the second semiconductor layer.

[0091] Example 2. The method according to Example 1, wherein forming the first semiconductor layer comprises: depositing the first semiconductor layer; and performing an annealing process to make the middle portion of the first semiconductor layer thicker.

[0092] Example 3. According to the method of Example 2, wherein, after the deposition of the first semiconductor layer, the first semiconductor layer comprises: a plurality of first portions grown from the plurality of semiconductor nanostructures; and a plurality of second portions between the plurality of first portions, wherein the plurality of second portions are thinner than the plurality of first portions.

[0093] Example 4. The method according to Example 2, wherein the first semiconductor layer is deposited at a first wafer temperature and the second semiconductor layer is deposited at a second wafer temperature equal to or higher than the first wafer temperature.

[0094] Example 5. The method according to Example 2, wherein the first semiconductor layer includes a first portion and a second portion growing toward each other, and wherein, upon completion of the annealing process, the first portion and the second portion are merged.

[0095] Example 6. The method according to Example 2, wherein the first semiconductor layer includes a first portion and a second portion growing toward each other, and wherein, upon completion of the annealing process, the first portion and the second portion are physically separated.

[0096] Example 7. The method according to Example 1, wherein, when the first semiconductor layer is deposited, the middle portion of the first semiconductor layer is thicker than the corresponding upper and lower portions of the first semiconductor layer.

[0097] Example 8. The method according to Example 7, wherein the first semiconductor layer is deposited at a first wafer temperature and the second semiconductor layer is deposited at a second wafer temperature lower than the first wafer temperature.

[0098] Example 9. The method according to Example 1 further includes: forming a dielectric layer at the bottom of the source / drain recess before forming the first semiconductor layer.

[0099] Example 10. The method according to Example 9, wherein the first semiconductor layer is spaced apart from the dielectric layer by the second semiconductor layer.

[0100] Example 11. The method according to Example 1, wherein the second semiconductor layer has a higher boron concentration than the first semiconductor layer.

[0101] Example 12. A method for forming a semiconductor structure, comprising: forming a semiconductor stack comprising a plurality of semiconductor nanostructures; and forming source / drain regions, comprising: epitaxially growing a first semiconductor layer, the first semiconductor layer comprising a first portion and a second portion at the same level, wherein the first portion and the second portion are grown toward each other, and wherein the first portion comprises a bottom portion, a top portion and an intermediate portion between the bottom portion and the top portion; annealing the first semiconductor layer, wherein a first thickness of the intermediate portion is increased and a second thickness of the top portion and the bottom portion is decreased; and epitaxially growing a second semiconductor layer on the first semiconductor layer.

[0102] Example 13. The method according to Example 12, wherein, after the first semiconductor layer is annealed, the first portion is spaced apart from the second portion.

[0103] Example 14. The method according to Example 12, wherein the first portion has a non-protruding profile before the first semiconductor layer is annealed, and the first semiconductor layer has X-shaped sidewalls after the first semiconductor layer is merged.

[0104] Example 15. The method according to Example 12, wherein the first portion and the second portion of the first semiconductor layer both have raised profiles at a first time before the first semiconductor layer is annealed and at a second time after the first semiconductor layer is annealed.

[0105] Example 16. The method according to Example 12, wherein the first semiconductor layer is deposited at a first temperature and the second semiconductor layer is deposited at a second temperature, which is lower than the first temperature.

[0106] Example 17. A semiconductor structure comprising: a semiconductor stack including a plurality of semiconductor nanostructures, wherein the plurality of semiconductor nanostructures include: a first semiconductor nanostructure; and a second semiconductor nanostructure overlapping the first semiconductor nanostructure; a source / drain region adjacent to the semiconductor stack, the source / drain region including: a first semiconductor layer including a first portion and a second portion, wherein the first portion includes an intermediate portion having a maximum thickness of the first portion, and wherein the thickness of the first portion gradually decreases toward corresponding upper and lower portions of the first portion; and a second semiconductor layer between the first portion and the second portion of the first semiconductor layer; a source / drain silicide region on and in contact with the second semiconductor layer, wherein the source / drain silicide region is spaced apart from the first semiconductor layer; and a source / drain contact plug on and in contact with the source / drain silicide region.

[0107] Example 18. The structure according to Example 17, wherein the first portion is joined to the second portion, and wherein, in a cross-sectional view of the structure, a first sidewall of the first portion is joined to a second sidewall of the second portion to form an X shape.

[0108] Example 19. The structure according to Example 17, wherein the first portion is spaced apart from the second portion, and the portion of the second semiconductor layer between the first portion and the second portion has an hourglass shape in a cross-sectional view of the structure.

[0109] Example 20. The structure according to Example 17 further includes: a dielectric layer beneath the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer is spaced apart from the dielectric layer by a bottom portion of the second semiconductor layer.

Claims

1. A method for forming a semiconductor structure, comprising: Multiple semiconductor nanostructures are formed, wherein the upper semiconductor nanostructure of the multiple semiconductor nanostructures overlaps with the corresponding lower semiconductor nanostructure of the multiple semiconductor nanostructures; Source / drain recesses are formed next to the plurality of semiconductor nanostructures; A first semiconductor layer is formed from the plurality of semiconductor nanostructures, wherein the first semiconductor layer has a convex shape in a cross-sectional view of the first semiconductor layer; A second semiconductor layer is formed on top of the first semiconductor layer; and A silicide region is formed on and in contact with the second semiconductor layer.

2. The method according to claim 1, wherein, The formation of the first semiconductor layer includes: Depositing the first semiconductor layer; and An annealing process is performed to make the middle portion of the first semiconductor layer thicker.

3. The method according to claim 2, wherein, The time following the deposition of the first semiconductor layer, the first semiconductor layer comprises: Multiple first parts are grown from the multiple semiconductor nanostructures; and A plurality of second portions are located between the plurality of first portions, wherein the plurality of second portions are thinner than the plurality of first portions.

4. The method according to claim 2, wherein, The first semiconductor layer is deposited at a first wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature equal to or higher than the first wafer temperature.

5. The method according to claim 2, wherein, The first semiconductor layer includes a first portion and a second portion growing toward each other, wherein the first portion and the second portion are merged upon completion of the annealing process.

6. The method according to claim 2, wherein, The first semiconductor layer includes a first portion and a second portion growing toward each other, wherein the first portion and the second portion are physically separated upon completion of the annealing process.

7. The method according to claim 1, wherein, When the first semiconductor layer is deposited, the middle portion of the first semiconductor layer is thicker than the corresponding upper and lower portions of the first semiconductor layer.

8. The method according to claim 7, wherein, The first semiconductor layer is deposited at a first wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature lower than the first wafer temperature.

9. A method for forming a semiconductor structure, comprising: Forming a semiconductor stack comprising multiple semiconductor nanostructures; as well as Forming the source / drain regions, including: Epitaxial growth of a first semiconductor layer, the first semiconductor layer comprising a first portion and a second portion at the same level, wherein the first portion and the second portion are grown toward each other, and wherein the first portion comprises a bottom portion, a top portion and an intermediate portion between the bottom portion and the top portion; The first semiconductor layer is annealed, wherein the first thickness of the middle portion is increased, and the second thickness of the top and bottom portions is decreased; and A second semiconductor layer is epitaxially grown on top of the first semiconductor layer.

10. A semiconductor structure comprising: A semiconductor stack comprising multiple semiconductor nanostructures, wherein the multiple semiconductor nanostructures include: First semiconductor nanostructure; and The second semiconductor nanostructure overlaps with the first semiconductor nanostructure. Source / drain regions, adjacent to the semiconductor stack, include: A first semiconductor layer includes a first portion and a second portion, wherein the first portion includes an intermediate portion having a maximum thickness, and wherein the thickness of the first portion gradually decreases toward corresponding upper and lower portions of the first portion; and A second semiconductor layer is located between the first portion and the second portion of the first semiconductor layer; Source / drain silicide regions, situated on and in contact with the second semiconductor layer, wherein the source / drain silicide regions are spaced apart from the first semiconductor layer; and Source / drain contact plugs are placed on and in contact with the source / drain silicide regions.

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