Efficient binary multiplier with reduced area and power consumption

Abstract

A signed or unsigned multiplier for multiplication of binary numbers, comprising a combination of logical cells consisting of standard cells or circuits in any multiplication architecture, said logical cells being modified such that, in any architecture of the signed or unsigned multiplier, the standard cells or circuits in any architecture of the signed or unsigned multiplier are connected to the standard cells or circuits. The modified logic unit partially replaces the CMOS circuit as a hybrid matching implementation or completely replaces the CMOS circuit as a direct embedding implementation.

Description

[0001] References

[0002] U.S. Patent Documents

[0003] US4638449 Multiplier architecture

[0004] US5150322 Mixed-radix serial / parallel multipliers

[0005] US5262976 Plural-bit recoding multiplier

[0006] US4752905 High-speed multiplier having carry-save adder circuit

[0007] US5008850 Circuitry for multiplying binary numbers

[0008] US5337268 Partial multiplier selector for multiplication circuit

[0009] US6446104B1 Double precision floating point multiplier having a 32-bit booth-encoded array multiplier

[0010] US5343417 Fast multiplier

[0011] US5586071 Enhanced fast multiplier

[0012] US5181185 Parallel multiplier using skip array and modified Wallacetree

[0013] US5504915 Modified Wallace tree adder for high speed binarymultiplier, structure and method

[0014] US4901270 Four-to-Two adder cell for parallel multiplication

[0015] US5347482 Multiplier tree using nine-to-three adders

[0016] US5265043 Wallace tree multiplier array having an improved layouttopology

[0017] US6029187 Fast regular multiplier architecture

[0018] Other publications

[0019] A Signed Binary Multiplication Technique, Booth, Andrew Donald, TheQuarterly Journal of Mechanics and Applied Mathematics. vol. IV (2): pp 236–240 (1951).

[0020] A Parallel Algorithm for the Efficient Solution of a General Class ofRecurrence Equations. Kogge, Peter and Stone, Harold. IEEE Transactions on Computers. C-22 (8): 786–793 (1973). Technical Field

[0021] This invention relates to the field of static logic digital circuits. More particularly, this invention relates to power- and area-efficient binary multipliers achieved by introducing novel circuit designs that utilize drop-in or mix-and-match methods as CMOS binary multipliers. Background Technology

[0022] Multipliers are fundamental blocks in many processors. A multiplication circuit or multiplier mainly consists of three parts: (1) a partial product generator implemented by multiple AND or NAND gates, each operating on a bit of the multiplicand and a bit of the multiplier (here, we are referring to the numbers being multiplied, not the circuit); (2) a multiplier array (also called an adder array) consisting of columns of adders that reduce the partial product by summing the sum word and the carry-out word; and (3) a multi-bit final adder that adds the sum word and the carry-out word to produce a single output word, the product. When two binary numbers, an M-bit multiplicand and an N-bit multiplier, are multiplied, M x N partial products are typically generated. The resulting product is typically M + N - 1 bits long. In most multiplication circuits, both the multiplicand and the multiplier have the same bit length N, and the resulting product is therefore 2N-1 bits long. Any integer, binary multiplier involves multiple sums of multi-digit numbers in a manner similar to decimal integer multiplication.

[0023] Multiplication circuits are often built with accumulators to form multiply-accumulate (MAC) processing elements or fused multiply-add (FMA) processing elements. These processing elements act as building blocks in circuits that implement vector dot products, matrix-vector multiplication, and matrix-matrix multiplication. High-speed processing is required; for example, for artificial intelligence (AI), machine learning (ML), high-performance computing (HPC), etc., which rely on intensive multiplication and addition. Power dissipation is a key performance indicator for multipliers. Other important factors are area and layout regularity. Regular architectures of multipliers are easier to route, while irregular architectures increase wire congestion and area. The choice of multiplier architecture involves trade-offs between power, area, and delay.

[0024] Multipliers are classified by their operating mode: serial, parallel, or shift-add, and by their architecture: array or tree architecture. They are also classified as unsigned or signed, depending on whether they multiply only positive numbers (i.e., unsigned numbers) or signed numbers (i.e., positive and negative numbers). Array architectures of multipliers are common due to their relatively simple and regular structure. However, array multipliers have higher latency compared to other multiplier architectures. Array architectures have a latency of O(N) (where N is the word length of the operands in bits). They also have relatively high switching activity. High switching activity is a major source of power dissipation in binary multipliers.

[0025] Tree architectures have irregular structures that result in propagation delays of O(log₂ N). Tree multipliers are faster than array multipliers, but require more complex wiring and have a larger area.

[0026] Input recoding is one of the most common methods for implementing compact multipliers.

[0027] Andrew Donald Booth described an input recoding method for reducing the number of partial products in “A Signed Binary Multiplication Technique” in The Quarterly Journal of Mechanics and Applied Mathematics Vol. IV (2), pp 236–240 (1951). It reduces the number of partial products by multiplying two signed binary numbers using their two's complement representations and a (modified) higher radix. Booth encoding is commonly used for long operands (16 bits or more) to reduce the number of partial products. However, Booth multipliers trade circuit complexity for speed (i.e., adding additional circuitry to recode the inputs in the Booth encoding scheme and generate the partial products).

[0028] U.S. Patent 4,638,449 presents an array architecture relying on a radix-4 booth encoder for reducing multiplier depth and increasing its speed. In patent US5,150,322, Smith et al. presented a hybrid radix-2 and 4 encoder array multiplier for area savings and speed improvements. U.S. Patent 5,262,976 also describes recoding two or more input bits to reduce the number of partial products. U.S. Patent 4,752,905 describes a multiplier array structure with a reduced number of summing stages and uses a combination of full adders and carry-saving adders to reduce carry propagation time. U.S. Patent US5,008,850 describes a multiplier including dedicated circuitry for classifying the multiplicand and the multiplied number into consecutive ones and zeros. Above the shared multiple AND gates that generate partial products, the multiplier includes additional circuitry such as multiplexers and networks of multi-input AND and OR gates, increasing its area and layout complexity. U.S. Patent 5,337,268 uses a Booth algorithm multiplier with an internal register for storing and sequentially fetching encoded inputs to reduce multiplier latency. U.S. Patent 6,446,104B1 describes a double-precision floating-point multiplier using a 32-bit Booth-encoded array multiplier with a partial accumulator, which includes a carry-preserving adder, a sum register, a carry-output counter, and an extender.

[0029] For tree architectures, U.S. Patents 5,343,417 and 5,586,071 describe a Wallace tree architecture in which full adders and half adders are used in the multipliers to reduce partial products by successively adding the sum word and carry output word, such that the specific inputs to be added at each adder stage are designed to increase the operating speed of the multipliers. U.S. Patents 5,181,185 by Han et al. and 5,504,915 by Rarick disclose modified Wallace tree adders for summing partial products, aimed at improving speed. U.S. Patent 4,901,270 by Galbi et al. presents the use of four-to-two compressor adders in the tree multiplier to further improve its speed. In U.S. Patent 5,347,482, Williams discloses the use of nine-to-three adders in the Wallace tree, which simplifies the layout and wiring of the multipliers by using larger basic building blocks in the tree architecture, although there is no speed improvement compared to three-to-two compressor adders. U.S. Patent 5,265,043 to Naini et al. discloses a Wallace tree multiplier architecture based on a carry-save adder (CSA) arranged in an L-folded planar diagram, designed to improve layout regularity and save area. U.S. Patent 6,029,187 describes a multiplier architecture that provides increased operating speed while maintaining regularity in its structure to achieve a smaller planar diagram. The multiplier is modified by replacing the full adder circuitry with compressor circuitry in a manner that maintains a balance in signal propagation delay.

[0030] As can be seen, most patents seek to improve the power, area, and performance of multipliers by modifying their architecture (e.g., tree architecture, high cardinality, etc.) and rarely by introducing, replacing, or modifying the standard cells of the multiplier (standard cells are pre-designed and pre-characterized building blocks used to implement different functions in microprocessor designs, i.e., adders, XOR / XNOR gates, etc.).

[0031] One object of the present invention is to provide a power- and area-efficient implementation of a binary multiplier by replacing the standard cells of the multiplier with more efficient cells.

[0032] Another object of the present invention is to provide a power- and area-efficient implementation of a binary multiplier suitable for any type of multiplier architecture.

[0033] Another object of the present invention is to provide an implementation of a power- and area-efficient binary multiplier that performs unsigned or signed multiplication with or without input encoding, with or without bit precision.

[0034] As the description proceeds, other objects and advantages of the invention will become apparent. Summary of the Invention

[0035] This invention relates to static CMOS logic and describes a novel circuit for multiplication of binary numbers.

[0036] A signed or unsigned multiplier for multiplying binary numbers includes a combination of logic units consisting of standard cells or circuits in any multiplication architecture, the logic units being modified such that, in any architecture of the signed or unsigned multiplier, the modified logic units partially replace CMOS circuitry as a mixed-match implementation, or completely replace CMOS circuitry as a direct-embedded implementation.

[0037] The final adder of a signed or unsigned multiplier is implemented as a hybrid match or direct embedding of a modified standard cell or circuit in any adder architecture.

[0038] Multiply significant numbers (in the case of floating-point format) using an array architecture, tree architecture, or any other architecture of multipliers implemented by a combination of modified logic units.

[0039] A multi-bit adder, implemented using a combination of modified logic units, is used to add exponents (in the case of floating-point format).

[0040] The modified standard units and circuits can be selected from the following groups:

[0041] - XOR NOT;

[0042] - XOR;

[0043] - Selectable logic function gates;

[0044] - One-bit half-adder;

[0045] - One-bit full adder;

[0046] - Pre-positioned size adder;

[0047] - A tall fan enters through the door;

[0048] - High fan entrance or door.

[0049] A one-bit half-adder can be directly embedded (i.e., replacing a known CMOS standard cell) or mixed-matched (i.e., combined with a known CMOS standard cell or circuitry) into an array multiplier, and this one-bit half-adder is implemented in the following way:

[0050] a) Connect two one-bit inputs to multiple transistors that compute binary addition;

[0051] b) The first block of the half-adder is generated by a single-bit half-adder, the first block consisting of the first set of transistors;

[0052] c) The carry output is generated by the second block of a one-bit half-adder, which consists of a second set of transistors.

[0053] A one-bit half-adder can be directly embedded or mixed into a tree multiplier. This one-bit half-adder is implemented in the following way:

[0054] a) Connect two one-bit inputs to multiple transistors that compute binary addition;

[0055] b) The first block of the half-adder is generated by a single-bit half-adder, the first block consisting of the first set of transistors;

[0056] c) The carry output is generated by the second block of a one-bit half-adder, which consists of a second set of transistors.

[0057] A one-bit half-adder and / or a one-bit full-adder or a combination thereof is directly embedded or mixed into an N-bit adder of any architecture, where N is an arbitrary word length. The one-bit half-adder is implemented as follows:

[0058] a) Connect two one-bit inputs to multiple transistors that compute binary addition;

[0059] b) The first block of the half-adder is generated by a single-bit half-adder, the first block consisting of the first set of transistors;

[0060] c) The carry output is generated by the second block of a one-bit half-adder, which consists of a second set of transistors.

[0061] A one-bit half-adder and / or a one-bit full-adder, or a combination thereof, can be directly embedded or mixed-matched into an NxM multiplier of any architecture, where N and M are arbitrary bit lengths. The one-bit half-adder can be implemented as follows:

[0062] a) Connect two one-bit inputs to multiple transistors that compute binary addition;

[0063] b) The first block of the half-adder is generated by a single-bit half-adder, the first block consisting of the first set of transistors;

[0064] c) The carry output is generated by the second block of a one-bit half-adder, which consists of a second set of transistors.

[0065] A single-level high-fan-in AND gate can be used to quickly check if the 8-bit exponent in IEEE-754 floating-point 32-bit format or any other integer or floating-point binary format is all-ones for infinity checks and NaN checks. This single-level high-fan-in AND gate is implemented as follows:

[0066] a) A stack of n-type transistor pull-up blocks, which acts as an AND gate, the output of which is fed to a recovery buffer for the output result, or...

[0067] b) A double-stacked pull-down n-type transistor network in CMOS topology, connected to a stack of inverters or buffers, for compensation of circuit delay.

[0068] A multi-bit adder is implemented using modified logic units to add exponents.

[0069] A single-level high-fan-in NOR gate is implemented in the following way:

[0070] a) A single-stage leakage-tolerant NOR gate, implemented in conjunction with another leakage-tolerant NOR gate or a standard CMOS NOR gate, for zero-checking, comprising a pull-up stack of p-type transistors, the output of which is fed into a recovery buffer whose output is the gate's output; and optionally:

[0071] b) Any number of inputs can be implemented as a pull-up stack of leak-tolerant NOR gates, wherein the stack is divided into multiple sub-stacks of lower numbers of inputs that are concatenated.

[0072] In one aspect, a single-stage high-fan-in logic NOR gate is implemented via a double-stacked network of pull-up p-type transistors in a CMOS topology, which is connected to a stack of inverters or buffers for compensation against circuit delay.

[0073] It can implement NOR gates of different bit lengths for zero checking of floating-point or integer binary numbers of arbitrary bit length.

[0074] An n+1 input AND gate is used in a carry-skip adder to implement a carry-skip adder wider than 4 bits. This n+1 input AND gate may comprise a stack of n-type transistors acting as an AND logic gate, the output of which is fed to a recovery buffer for the output result. Alternatively, the n+1 input AND gate may comprise a CMOS topology double-stacked network of pull-down n-type transistors connected to a stack of inverters or buffers to compensate for circuit delays.

[0075] Any combination of modified half-adders and full-adders can be mixed-matched with or directly embedded with known CMOS full-adders and half-adders.

[0076] A selectable logic gate that performs a pre-selected logical function includes:

[0077] a) A first inverter, the output of which is connected to the output of a selectable logic gate;

[0078] b) A pair of complementary transistors connected in parallel, having shared source and drain ports and separate gating inputs, the shared drain and source ports being the outputs of selectable logic gates; and

[0079] c) Configure selectable logic gates to perform multiple inputs for a specific logic function.

[0080] Selectable logic gates can be configured for pre-selected logic functions.

[0081] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. While similar or equivalent methods and materials may be used in the practice or testing of embodiments of the invention, exemplary methods and / or materials are described below. In the event of conflict, the patent specification, including its definitions, shall prevail. Furthermore, materials, methods, and examples are illustrative only and are not intended to be necessarily limiting. Attached Figure Description

[0082] The above and other features and advantages of the invention will be better understood by referring to the accompanying drawings and the following illustrative and non-limiting detailed description of preferred embodiments of the invention, in which:

[0083] Figure 1a The invention describes a full-voltage swing two-input XOR gate implementation comprising a pair of parallel complementary transistors having a common source and drain port and separate gated inputs, the common drain and source port being connected to an output inverter and two transistor pull-up (p-type) and pull-down (n-type) transistors.

[0084] Figure 1b Another full-voltage swing two-input XOR gate implementation of the present invention is described;

[0085] Figure 2 The present invention describes a full-voltage swing two-input selectable logic gate that executes a pre-selected logic function.

[0086] Figure 3 This is a circuit diagram of the one-bit half-adder of the present invention;

[0087] Figure 4a (Prior art) is a circuit diagram of a one-bit full adder;

[0088] Figure 4b(Prior art) is a circuit diagram of a one-bit full adder with inverting output;

[0089] Figure 5a The present invention is a leakage-tolerant single-stage high-fan-in logic (10-input AND) gate, which includes a pull-up stack of n-type transistors acting as an AND logic gate, the output of which is fed to a recovery buffer of the output result;

[0090] Figure 5b This invention provides a single-stage implementation of a high-fan-in logic (10-input AND) gate, comprising a CMOS topology and a double-stacked pull-down n-type transistor network connected to a stack of inverters or buffers to compensate for circuit delays.

[0091] Figure 6a The leakage-tolerant single-stage 8-input NOR gate of the present invention comprises a stack of multiple p-type transistor pull-up blocks, the output of which is fed into a recovery buffer, the output of which is the output of the gate.

[0092] Figure 6b This invention provides a single-level implementation of a high-fan-in logic (8-input NOR) gate, comprising a CMOS topology and a double-stacked pull-up p-type transistor network connected to a stack of inverters or buffers to output a result.

[0093] Figure 7a This is an existing technology circuit diagram of a radix-4 (also known as a modified Booth decoder). Booth's decoder circuit (left) and Booth's encoder circuit (right);

[0094] Figure 7b This is a circuit diagram of the base-4 Booth decoder of the present invention;

[0095] Figure 8 This is a block diagram of an n-bit carry-skip adder in the public domain;

[0096] Figure 9 This is a block diagram of a public domain 4-bit carry ripple (also known as ripple carry) adder;

[0097] Figure 10 This is a block diagram of a public domain 4-bit carry-store adder;

[0098] Figure 11 This is a block diagram of the public domain implementation of a 4x4 unsigned binary array multiplier of A and B, where some products are... .

[0099] Figure 12 This is a block diagram of the public-domain implementation of a 4x4 unsigned A and B binary (Wallace) tree multiplier, where some products are... .

[0100] Figure 13 This is a block diagram of a prior art implementation of an 8-bit Kogge-Stone parallel prefix adder for binary numbers A and B, in which... and It is dissemination ( ) and generation ( The signal is represented by a black square, which indicates a black cell in the Kogge-Stone group that generates the propagation and generation of the signal. and ;and

[0101] Figure 14 This is a simplified block diagram of a public domain (IEEE-754) floating-point binary multiplier architecture, in which zero-checking, infinity-checking, and NaN-checking circuits have been omitted for clarity. Detailed Implementation

[0102] This invention relates to achieving power- and area-efficient binary multipliers by introducing novel circuit designs. The disclosed embodiments propose novel static logic circuits that can be used as direct embedded implementations in CMOS binary multipliers (where CMOS circuitry or standard cells are completely replaced by modified logic cells with high power- and area efficiency) or as hybrid-matched implementations in CMOS binary multipliers (where CMOS circuitry or standard cells are partially replaced by modified logic cells with high power- and area efficiency).

[0103] The methods and circuits described in this invention replace standard cells of multipliers (i.e., as direct embeddings or hybrid matching) with more efficient cells. These methods are applicable to any type of multiplier architecture, including but not limited to parallel and sequential multipliers, pipelined and systolic arrays of processing elements including multipliers, circuits for computing fundamental functions, etc. The multiplier methods cited above are applicable to any bit precision, unsigned or signed multiplication, with or without input encoding.

[0104] Figure 1a A full-voltage swing two-input XOR gate circuit according to an embodiment of the present invention is presented. The two-input XOR gate circuit includes a transmission gate comprising a pair of parallel complementary transistors having common source and drain ports and separate gated inputs, and a pMOS-nMOS transistor stack to save power and area and improve performance compared to known CMOS XOR gate circuits.

[0105] Input A is fed to an inverter, and input B is fed to another inverter. The inverted input B is fed to the transmission gate at position 1 and pMOS-nMOS stack pins 5 and 6. The inverted input A and input B are fed to the control pins 3 and 2 of the transmission gate, respectively. Output pin 8 generates an XOR operation. .

[0106] Alternatively, one of the inputs is inverted by the same circuit (i.e., by discarding one of the input inverters, the input is...). or Implement a two-input XOR NOT gate. For example, for... Figure 1a Invert the input B (to) This results in an XOR gate that is more power-efficient than known CMOS gates. In embodiments of the invention, Different combinations of these circuits enable XOR or XOR NOT circuits that are more efficient than known CMOS power. Furthermore, in another embodiment of the invention, the circuit output is fed to an inverter, a buffer, or a chain of inverters, or to a stack of inverters or a combination thereof, to enable XOR or XOR NOT circuits with different drive currents.

[0107] Figure 1b Another embodiment of the invention, a full-voltage swing two-input XOR gate, is presented for power saving. The XOR operation is performed at output pin 9. .

[0108] Alternatively, one of the inputs is inverted by the same circuit (i.e., by discarding one of the input inverters, the input is...). or This implements a two-input XOR gate. For example, it inverts input B (to...). This results in an XOR gate that is more power-efficient than known CMOS gates. In embodiments of the invention, Different combinations of these circuits enable XOR or XOR gates that are more power-efficient than known CMOS gates. Furthermore, in another embodiment of the invention, the circuit output is fed to an inverter, a buffer, a chain of inverters, or a stack of inverters or buffers, or a combination thereof, to implement XOR or XOR gates with different drive currents.

[0109] Figure 2 This paper presents an embodiment of the standard cell for a full-voltage swing, two-input, selectable logic gate of the present invention. The circuit produces different logic functions at output Z depending on the X1…X6 configuration of the inputs. Inputs A and B, or their complementary signals, are fed to different… Pins are used to implement pre-selected logic functions.

[0110] Table I describes several two-input configurations that implement different logic functions (e.g., XOR, AND, NOR, OR, NAND).

[0111] Table I

[0112] Figure 3 A circuit diagram of an embodiment of the one-and-a-half adder of the present invention is presented. Two single-digit numbers A and B are fed into terminals 10 and 11, respectively. It is generated at terminal 12 and carries over to the output. It is generated at terminal 13. In embodiments of the invention, this one-bit half-adder is used for column reduction in a tree multiplier via a known Wallace or Dadda reduction scheme or any other reduction scheme.

[0113] In another embodiment, the half-adder is placed within a multi-bit carry-skip adder, a carry-ripple adder, or a carry-save adder, or within a multi-bit adder of any bit length and architecture. In yet another embodiment of the invention, the half-adder is used to sum partial products or elements in any multiplier of any bit length and architecture.

[0114] In another embodiment, a modified one-bit half-adder is implemented by connecting two one-bit inputs to multiple gates of a single-type transistor that computes binary addition and generating a sum via a first block of a one-bit half-adder consisting of a first set of transistors. The carry output is then generated via a second block of a one-bit half-adder consisting of a second set of transistors. Finally, the modified one-bit half-adder is directly embedded or mixed-matched into an array multiplier or a tree multiplier.

[0115] In another embodiment, a modified one-bit half-adder or a modified one-bit full-adder is implemented by connecting two one-bit inputs to multiple gates of a single-type transistor for computing binary addition and generating a sum via a first block of a one-bit half-adder consisting of a first set of transistors. Then, a carry output is generated via a second block of a one-bit half-adder consisting of a second set of transistors. Finally, the modified one-bit half-adder and / or the modified one-bit full-adder, or a combination thereof, is directly embedded or mixed-matched into an N-bit adder of any architecture, or into an NxM multiplier of any architecture, where N and M are arbitrary.

[0116] Figure 4a (Prior art) is a circuit diagram of a known CMOS one-bit full adder, which includes 28 transistors. Two single-bit numbers A (14) and B (15) are fed in together with the carry input (16). It is generated at position 17, and a carry is output. It was generated at 18 locations.

[0117] Figure 4b (Prior technology) has an inverted output. Figure 4aThe circuit diagram of a one-bit full adder is shown below. That is, this adder generates an inverted sum (…). ,19) and the inverted carry output ( (20). In an implementation of the invention, the inverting property of a one-bit full adder is implemented in a multiplier via an inverted output one-bit full adder using any two-input XOR gate of the invention, thereby implementing a selectable logic function gate. The selectable logic function gate is configured as a two-input XOR, or a half adder of the invention, or a combination thereof, to save power and area.

[0118] In one embodiment of the invention, any XOR / XOR NOT gate of the invention is used to replace a known CMOS XOR / XOR NOT gate in a known CMOS full adder to save power and area of ​​the multiplier. Furthermore, in another embodiment of the invention, the two XOR or XOR NOT gates of the invention are used as replacements for the XOR gates of a known CMOS full adder to save power and area.

[0119] Furthermore, in another embodiment of the invention, a modified known CMOS one-bit full adder according to the invention is directly embedded or hybrid-matched into a multi-bit adder to save power and area. In another embodiment of the invention, a modified known CMOS one-bit full adder (which is implemented using any XOR or XOR gate of the invention) is directly embedded or hybrid-matched into a multiplier to save power and area.

[0120] Figure 5a The present invention relates to a single-stage leakage-tolerant high-fan-in AND gate, comprising a pull-up stack of n-type transistors acting as AND gates, the output of which is fed to a recovery buffer for output results. In one embodiment of the invention, ten data inputs A1 to A10 are fed to a stack 21 of n-type transistors acting as AND gates, the output of which is fed to a recovery buffer 22, which outputs the result to 23. Inverting the output of the gate results in a single-stage high-fan-in NAND gate. In one embodiment of the invention, such a high-fan-in gate is implemented as an alternative to known CMOS tree-of-gates to improve power consumption and save power.

[0121] The IEEE-754 32-bit floating-point format conditions for zero, infinity, and NaN numbers are given in Table II below.

[0122] Table II

[0123] Zero, infinity, and Not-a-N (NaN) checks are performed before any multiplication operation. In one embodiment of the invention, an 8-input single-stage leak-tolerant AND gate is used to quickly check that all 8 bits of the 32-bit floating-point format (FP32) are one, for both infinity and NaN checks. In another embodiment of the leak-tolerant AND gate of the invention, optimal leak-tolerant operation is achieved by placing the gate in circuits where logic "1" outputs are relatively rare (e.g., infinity or NaN values). Therefore, with (In the case of uniformly distributed inputs, where N is the number of inputs, e.g., N = 8, 10, or higher) The scaled-down time-averaged or statistically averaged power consumption (of the inputs fed into the gate) results in significant power savings compared to known CMOS equivalent implementations of the gate, and faster operation (up to 200 times faster) than by software checking. In another embodiment of the gate, the 11-input single-stage leakage-tolerant AND gate of the present invention is implemented for infinity and NaN checking in IEEE-754 64-bit format (double precision). Furthermore, in other embodiments, the high fan-in single-stage leakage-tolerant AND gate implements infinity and NaN checking in multipliers of other formats such as BFLOAT-16 format (8-bit exponent), NVIDIA's 16-bit TensorFloat format (8-bit exponent) or 32-bit TensorFloat format (8-bit exponent), AMD's fp24 format (7-bit exponent), etc.

[0124] refer to Figure 5b The invention describes a static CMOS high-fan-in logic AND gate (i.e., 10 inputs) comprising a double-stacked pull-down network (PDN, 24) to overcome parasitic resistance and capacitance, and an inverter stack 25 at the output for compensating for RC delays in the PDN stack. In one embodiment of the invention, this high-fan-in gate is implemented as an alternative to known CMOS gate trees to improve power consumption and save power. In another embodiment of the invention, the high-fan-in gate is used to implement infinity and NaN checks as described above. In yet another embodiment of the invention, multiple PDN stacks in different combinations (series, parallel, and series-parallel) are implemented to compensate for RC delays. Furthermore, in yet another embodiment of the invention, other stack combinations (series, parallel, and series-parallel) of inverters or buffers are used at output 25 to compensate for RC delays or control the drive current of the gate.

[0125] refer to Figure 6a The implementation of a single-stage leakage-tolerant 8-input NOR gate includes a stack of p-type transistors whose output is fed to a recovery buffer whose output is the output of a gate that overcomes the 4-input limitation of known CMOS standard cells and is implemented as an OR gate tree to save power and area.

[0126] Data inputs A1 through A8 are fed to a stack 26 of p-type transistors that act as NOR gates. The output of the stack is fed to a recovery buffer 27, whose output 28 is a gate output. Inverting output 28 results in an OR gate.

[0127] In one embodiment of the leakage-tolerant NOR gate, a 23-input NOR gate comprising a stack of twenty-three p-type transistors is implemented in conjunction with an 8-bit NOR gate to achieve zero-checking for a 32-bit floating-point format according to IEEE-754, saving power and area. Inverting the gate's output results in an OR gate. In another embodiment of the invention, any number of inputs are implemented as a p-type transistor stack leakage-tolerant OR or NOR gate, wherein the stack is divided into multiple sub-stacks of connected lower-number inputs. In another embodiment of the gate, OR or NOR gates of varying bit lengths are implemented for zero-checking in floating-point or integer binary formats of arbitrary bit lengths. The use of high-fan-in leakage-tolerant NOR gates is limited in some applications, such as sparse matrix multiplication.

[0128] Figure 6b A static CMOS circuit for a high-fan-in NOR gate of the present invention is presented, which overcomes the 4-input limitation of known CMOS to save power and area. A dual-stacked pull-up network (PUN, 29) is implemented to reduce RC delay, and an inverter output stack 30 is used to improve speed and control the gate's drive current. The inverted output results in a high-fan-in NOR gate. In one embodiment of the invention, the gate is used in the same manner as described for the high-fan-in leakage-tolerant NOR gate of the present invention.

[0129] The dual-stacked coil topology 29-30 is used to reduce the stacked RC delay and facilitate a large number of inputs (i.e., more than 4 inputs in known CMOS) to provide a single-stage 8-input NOR gate, instead of the tree topology used to implement such a high fan-entry gate in known CMOS.

[0130] Figure 7a This is prior art with modified (radix-4) Booth encoder and decoder circuitry. A radix-4 encoder circuit 31 is depicted, whose output signals Neg, X1, Z, and X2 are used to encode the multiplier (in radix-4 representation). The encoded multiplier and multiplicand are fed into a decoder 32 to generate a partial product (…). In one embodiment of the invention, the XOR and XOR gates of the encoder are replaced with any XOR and XOR gates of the present invention. In another embodiment of the invention, any XOR gates of the modified Booth decoder are replaced with XOR gates of the present invention.

[0131] Figure 7b This is a circuit diagram of the modified Booth decoder implementation 33 of the present invention for saving power and area. The encoded multiplier and multiplicand are fed to the decoder to generate a partial product (…). In another embodiment of the invention, the XOR gate of the decoder is replaced by any XOR gate of the invention.

[0132] Figure 8 (Prior art) A block diagram of an n-bit carry-skip (CSkA) adder is shown. Two n-bit numbers An and Bn, along with a carry input 34, are added. The result is a list of numbers S0 (LSB, 35) to Sn (MSB, 36) and a carry output 38 at the output of an OR gate. The square designated as FA is a one-bit full adder unit. The carry-skip subcircuit includes n+1 input AND gates 39, which are composed of n+1 partial integrators. feed.

[0133] In one embodiment of the invention, a known CMOS one-bit full adder in CSKA is replaced by one or more modified one-bit full adders according to the invention, thereby saving power and area as previously described. In another embodiment of the invention, the n+1 input high-fan-in AND gate of the invention is used in carry-skip adder 39 instead of a known CMOS AND gate. Furthermore, in yet another embodiment of the invention, a single-stage high-fan-in AND gate with nine inputs exceeding the inputs of a known CMOS (any single-stage CMOS standard cell is limited to four inputs) is directly embedded to implement an 8-bit (exceeding the 4-bit wide carry-skip adder of a known CMOS) single-block carry-skip adder, thereby improving performance, power, and area. Furthermore, in yet another embodiment, any high-fan-in AND gate of the invention is used to implement a single-block carry-skip adder of arbitrary bit length. In another embodiment, any hybrid matching combination of a known CMOS full adder implemented with the XOR or XOR NOT gates of the invention is implemented to improve power consumption, save area, and increase the speed of any multi-bit adder.

[0134] Figure 9 A prior art 4-bit carry-ripple adder (CRA) is presented. Two 4-bit numbers A and B, along with a carry input 40, are added. The FA unit specifies a single-bit full adder unit. Output 41 is the carry output of the summation. A list of sums S0 (LSB) to S3 (MSB) represents the result of the addition.

[0135] In embodiments of the invention, modified one-bit full adders implemented using the XOR or XOR NOT gates of the invention, or combinations thereof, are directly inserted into the CRA to replace one or more known CMOS one-bit full adders, or mixed-matched with known CMOS one-bit full adders, to save power and area. In embodiments where the least significant bits are implemented by half adders (i.e., without carry input), the half adders of the invention are directly embedded as replacements for known CMOS one-bit half adders to save area and power. In another embodiment, any mixed-matching combination of prior art full adders is implemented using the XOR or XOR NOT gates and / or half adders of the invention to improve power consumption, save area, and increase the speed of CRAs of any bit length.

[0136] refer to Figure 10 This paper presents a prior art technique for a multi-bit adder carry-store adder (CSA) for adding two 4-bit binary numbers A and B with a carry input (42). A list of numbers S0 (LSB) to S3 (MSB) and a carry output 43 provide the result.

[0137] In embodiments of the invention, any combination of the half-adder of the invention and a full adder having modifications of the XOR or XOR NOT gates of the invention is directly embedded into known CMOS full adders and half-adders in carry-store adders of any bit length, or mixed-matched with known CMOS full adders and half-adders in carry-store adders of any bit length to save power and area. Furthermore, in another embodiment, the XOR implementation of the invention is directly embedded to replace the known CMOS XOR gate 44 to save power and area.

[0138] Figure 11 The existing technical architecture of an unsigned array multiplier is presented to illustrate the multiplication of two 4-bit numbers A × B. Partial product... Generated through a two-input AND or two-input NAND gate, and fed into a rectangular array of adding elements (full adders and half adders), where the output product contains 2N-1 (i.e., Figure 11 The bits F0 to F6 and the carry are output F7. Partial product , 45, etc. HA, 46, represent half adders, FA, 47, represent full adders. The multiplier produces a list of numbers F0 (LSB) to F6 (MSB).

[0139] In embodiments of the invention, any combination of the half-adder of the invention and a full adder having modifications of the XOR or XOR NOT gates of the invention can be directly embedded into or mixed with any known CMOS adder to implement any array multiplier to save power and area.

[0140] refer to Figure 12This paper presents a prior art implementation of a (Wallace) tree multiplier for multiplying two 4-digit numbers A × B. (Partial product) The partial product is fed into a tree array of adding elements (full adders and half adders), where the output product contains 2N-1 bits and a carry-out bit. , 48, etc. HA, 49, are half adders, and FA, 50, are full adders. The multiplier generates a list of numbers F0 (LSB) to F6 (MSB). Output F7 is a carry output.

[0141] Tree multipliers are faster than array multipliers and are commonly used; they are also used in conjunction with more sophisticated partial product generation schemes (i.e., Booth encoding), which reduce the number of partial products to less than [a certain value]. As described in U.S. Patents 4,638,449, 5,150,322, and 5,262,976, etc. According to the present invention, the combination of the half-adder of the present invention and a modified full adder implemented using the XOR or XOR NOT gates of the present invention is directly embedded or mixed-matched with known CMOS adders to implement any tree multiplier to save power and area.

[0142] Figure 13 Based on the Kogge-Stone algorithm, this method is used to separate two n-digit numbers A and B ( Figure 13 Existing technology examples of parallel prefix adders that add 8-bit numbers. Terminology and These are carry generation and carry propagation, respectively. Black cells are used to output the generalized generation and propagation terms. and In one embodiment of the present invention, the XOR gate of the present invention is used to implement... And as In the target Direct embedding.

[0143] Figure 14 A simplified public domain block diagram of one implementation of a multiplier for two 32-bit floating-point numbers is given. Each of the input numbers A and B is separated into a sign bit 51, an exponent bit 52, and a significant bit bit 53. If one of the numbers is negative, multiplying the two numbers results in a negative signed number. An XOR gate (51) is used to determine the sign bit of the product. For the addition of exponents; an unsigned adder is used. For the multiplication of significant bits; an unsigned multiplier with or without input encoding is used.

[0144] In one embodiment of the invention, the XOR circuit of the invention is used for sign computation to save power and area. Furthermore, in another embodiment of the invention, any connection of an 8-bit or single-type adder according to the invention (e.g., a 3-bit adder connected to a 5-bit adder) or any combination of adders of different bit lengths and types is implemented for exponential addition using the previously described method. In another embodiment, adders of any bit length are implemented using the already described direct embedding or hybrid matching method for exponential addition. Without limiting the scope of the invention, other prior art architectures of multi-bit adders (such as carry-ahead, Kogge-Stone, Brent-Kung, Ladner-Fischer, Han-Carlson, Beaumont-Smith, Jackson, Ling, Krapchenko, Sklansky, Knowles, etc.) can be implemented in any multiplier architecture using the direct embedding and hybrid matching methods of the invention.

[0145] In another embodiment of the invention, the direct embedding and hybrid matching method according to the invention is used, as described for multipliers, to multiply the significant digits (mantissas) of floating-point numbers using an array or tree of multipliers or any other architecture.

[0146] Furthermore, in yet another embodiment of the invention, whenever the final portion of a signed or unsigned multiplier includes a final adder for generating the final product, the direct embedding and hybrid matching method of the invention described for multi-bit adders can be implemented for any multi-bit adder and for any connection of multiple single-type or different-type adders (e.g., a k-bit long carry-skip adder connected to an m-bit carry-hold adder connected to a l-bit carry-ripple adder, etc.) to create adders of any bit length and placement order, as well as any combination of any sub-adders.

[0147] The methods and circuits described in this invention are applicable to any bit width and any type of multiplier architecture, including but not limited to parallel and sequential multipliers, pipelines and systolic arrays of processing elements including multipliers, circuits for computing basic functions, etc.

[0148] It should be understood that, for clarity, certain features of the invention described in the context of individual embodiments may also be provided in combination in a single embodiment. Conversely, for brevity, various features of the invention described in the context of a single embodiment may also be provided individually or in any suitable sub-combination or in a manner suitable for any other described embodiment of the invention. Certain features described in the context of various embodiments should not be considered essential features of those embodiments unless the embodiment is inoperable without these elements.

[0149] Although the invention has been described in conjunction with specific embodiments thereof, it will be apparent to those skilled in the art that many alternatives, modifications, and variations will be apparent. Therefore, it is intended to cover all such alternatives, modifications, and variations falling within the spirit and broad scope of the appended claims.

Claims

1. A signed or unsigned multiplier for multiplication of binary numbers comprising: a combination of logic cells consisting of standard cells or circuits in any multiplier architecture, the logic cells are modified such that in any architecture of the signed or unsigned multiplier, the modified logic cells partially replace CMOS circuits as a hybrid match implementation or completely replace CMOS circuits as a direct embedded implementation.

2. The multiplier of claim 1, wherein, The final adder of the signed or unsigned multiplier is implemented as a hybrid match or direct embedded of modified standard cells or circuits in any adder architecture.

3. The multiplier for floating-point numbers as defined in claim 1, wherein, Multiplication of significant numbers is performed using an array architecture, tree architecture or any other architecture of multipliers implemented by the combination of modified logic cells.

4. A multiplier for floating point numbers, wherein, Addition of exponents is performed using a multi-bit adder implemented by the combination of modified logic cells.

5. The multiplier of claims 1-4, wherein, The standard cells and circuits are selected from the group of: - XNOR NOT; - XOR; - Selectable logic function gate; - One-bit half adder; - One-bit full adder; - Pre-determined bit size adder; - High fan-in AND gate; - High fan-in OR gate.

6. The multiplier of claim 2, wherein, The one-bit half adder is directly embedded or hybrid matched into an array multiplier, the one-bit half adder is implemented by: a) connecting two one-bit inputs to multiple gates of single type transistors that compute binary addition; b) generating sum through a first block of the one-bit half adder, the first block consists of a first set of transistors; c) generating carry out through a second block of the one-bit half adder, the second block consists of a second set of transistors.

7. The multiplier of claim 2, wherein, The one-bit half adder is directly embedded or hybrid matched into a tree multiplier, the one-bit half adder is implemented by: d) connecting two one-bit inputs to multiple gates of single type transistors that compute binary addition; e) generating sum through a first block of the one-bit half adder, the first block consists of a first set of transistors; f) generating carry out through a second block of the one-bit half adder, the second block consists of a second set of transistors.

8. The multiplier of claim 2, wherein, The modified one-bit half adder and / or the modified one-bit full adder or their combination is directly embedded or hybrid matched into an N-bit adder of any architecture, where N is arbitrary, the modified one-bit half adder is implemented by: a) connecting two one-bit inputs to multiple gates of single type transistors that compute binary addition; b) generating sum through a first block of the one-bit half adder, the first block consists of a first set of transistors; c) generating carry out through a second block of the one-bit half adder, the second block consists of a second set of transistors.

9. The signed or unsigned multiplier of claim 2, wherein, The modified one-bit half adder and / or the modified one-bit full adder or their combination is directly embedded or hybrid matched into an NxM multiplier of any architecture, where N and M are arbitrary, the modified one-bit half adder is implemented by: a) connecting two one-bit inputs to multiple gates of single type transistors that compute binary addition; b) generating sum through a first block of the one-bit half adder, the first block consists of a first set of transistors; c) generating carry out through a second block of the one-bit half adder, the second block consists of a second set of transistors. c) generating a carry output by a second block of the one-bit half-adder, the second block consisting of a second set of transistors.

10. The multiplier of claim 3, wherein, A single stage high fan-in logical AND gate is used for fast checking of 8-bit exponent all ones for infinity check and NaN check for floating point 32-bit format or any other integer or floating point binary number format, the single stage high fan-in logical AND gate is implemented by: a) a stack of n-type transistors, the stack of n-type transistors acting as an AND logic gate, the output of the AND logic gate being fed to a restoration buffer of the output result, or, b) a CMOS topology double stack of pull-down n-type transistor network for compensation for output delay.

11. The multiplier of claim 3, wherein, A multi-bit adder is implemented using modified logic cells for adding exponents.

12. The multiplier of claim 3, wherein, A single stage leakage tolerant NOR gate is implemented in conjunction with another leakage tolerant NOR gate or a double stack of pull-up p-type transistor network of CMOS topology or a standard CMOS NOR gate stacked with an inverter or buffer for zero check, the single stage leakage tolerant NOR gate comprising a stack of p-type transistors, the output of the stack of p-type transistors being fed into a restoration buffer, the output of the restoration buffer being the gate output.

13. The multiplier of claim 5, wherein, Any number of inputs are implemented as a stack of p-type transistors of a leakage tolerant NOR gate, wherein the stack is divided into multiple sub-stacks of a lower number of inputs that are concatenated, or, a CMOS topology NOR gate comprising a double stack of pull-up p-type transistor network stacked with an inverter or buffer for compensation for circuit delay.

14. The multiplier of claim 12, wherein, NOR gates of different bit lengths are implemented for zero check of arbitrary bit length floating point or integer binary number formats.

15. The multiplier of claim 2, wherein, An n+1 input high fan-in AND gate is used in a carry-skip adder, thereby implementing a carry-skip adder wider than 4 bits, wherein the n+1 input high fan-in AND gate comprises a stack of n-type transistors, the stack of n-type transistors acting as an AND logic gate, the output of the AND logic gate being fed to a restoration buffer of the output result, or, the n+1 input high fan-in AND gate comprises a double stack of pull-down network, the pull-down network being used to overcome parasitic effects for compensation for output delay.

16. The multiplier of claims 1-4, wherein, Any combination of modified half-adders and full-adders are mixed and matched with known CMOS full-adders and half-adders or directly embedded.

17. A selectable logic gate that performs a logic function, comprising: a) a first inverter, an output of the first inverter connected to an output of the selectable logic gate; b) a pair of complementary transistors connected in parallel, having a common drain and source port and separate gate inputs, the common drain and source port being the output of the selectable logic gate; and c) a plurality of inputs that configure the selectable logic gate to perform a particular logic function.

18. The selectable logic gate of claim 16, configured as an exclusive OR gate.

19. The selectable logic gate of claim 16, used for sign checking. ​

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