GaN device dynamic on-resistance measurement error suppression method and system

Abstract

The invention relates to the technical field of semiconductor device testing, in particular to a GaN device dynamic on-resistance measurement error suppression method and system. The method comprises the following steps: acquiring a break-over voltage waveform, a gate voltage waveform and a drain current waveform of a switching period of the GaN device based on a predetermined test loop; respectively calculating a grid feed-through theoretical error waveform and a parasitic parameter theoretical error waveform based on the grid voltage waveform and the drain current waveform; subtracting the grid feed-through theoretical error waveform and the parasitic parameter theoretical error waveform from the conduction voltage waveform to obtain a preliminary compensation waveform; constructing a voltage waveform hybrid compensation model, and calculating a compensated voltage waveform by using the voltage waveform hybrid compensation model based on the preliminary compensation waveform, the gate voltage waveform, the drain current waveform and the break-over voltage waveform; and calculating on resistance according to the compensated voltage waveform and the drain current waveform. The problem that in the prior art, dynamic on-resistance measurement of a GaN device is not accurate enough is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, specifically a method and system for suppressing errors in the dynamic on-resistance measurement of GaN devices. Background Technology

[0002] Gallium nitride (GaN), as a core device of third-generation wide-bandgap semiconductors, has become a key support for new energy vehicles, 5G communications, and data center power supplies due to its excellent characteristics such as high frequency, high efficiency, and high power density. Dynamic on-resistance is a core parameter for evaluating the conduction loss and reliability of GaN devices, and its measurement accuracy directly determines the accuracy of system efficiency optimization and lifetime assessment. Particular attention must be paid to the dynamic degradation problem caused by charge trapping effects.

[0003] However, measuring the dynamic on-resistance of GaN devices faces several technical bottlenecks: First, the drain-source voltage range during switching is extremely wide (hundreds to kilovolts), while the on-state voltage is only a few volts or even lower, leading to resolution conflicts and overload risks in oscilloscope measurements. Second, the dynamic rate of change of voltage and current under high-frequency switching amplifies the interference of parasitic parameters of the probe, causing signal distortion. Third, although traditional hardware clamping circuits can eliminate high-voltage components, they introduce additional parasitic parameters and voltage offsets, further deteriorating measurement accuracy. All of these factors increase measurement uncertainty.

[0004] Existing measurement methods either rely on complex hardware designs or lack comprehensive suppression of multi-source errors, making it difficult to balance measurement accuracy and practicality. Therefore, a more accurate method for measuring the dynamic on-resistance of GaN devices is urgently needed. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method and system for suppressing measurement errors in the dynamic on-resistance of GaN devices, solving the problem of insufficient accuracy in the measurement of dynamic on-resistance of GaN devices in existing technologies.

[0006] To achieve the above objectives, one aspect of the present invention provides a method for suppressing measurement errors in the dynamic on-resistance of a GaN device. The method includes: acquiring the on-state voltage waveform, gate voltage waveform, and drain current waveform of a GaN device for one switching cycle based on a predetermined test circuit; calculating the theoretical gate feedthrough error waveform and the theoretical parasitic parameter error waveform based on the gate voltage waveform and the drain current waveform, respectively; obtaining a preliminary compensation waveform by subtracting the theoretical gate feedthrough error waveform and the theoretical parasitic parameter error waveform from the on-state voltage waveform; constructing a voltage waveform hybrid compensation model; calculating the compensated voltage waveform based on the preliminary compensation waveform, the gate voltage waveform, the drain current waveform, and the on-state voltage waveform using the voltage waveform hybrid compensation model; and calculating the on-resistance based on the compensated voltage waveform and the drain current waveform.

[0007] This invention obtains the on-state voltage, gate voltage, and drain current waveforms of a GaN device during its switching cycle based on a predetermined test circuit. First, it calculates and performs preliminary compensation for the theoretical error waveforms of gate feedthrough and parasitic parameters. Then, it uses a voltage waveform hybrid compensation model to fuse multiple waveforms to achieve secondary accurate correction. Finally, it combines the compensated voltage waveform with the drain current waveform to calculate the on-state resistance. This effectively suppresses measurement errors caused by gate feedthrough, parasitic parameters, and residual dynamic interference, and improves the measurement accuracy of the dynamic on-state resistance of GaN devices.

[0008] Optionally, the step of calculating the gate feedthrough theoretical error waveform and the parasitic parameter theoretical error waveform based on the gate voltage waveform and the drain current waveform includes: smoothing the gate voltage waveform and the drain current waveform to obtain an optimized gate voltage waveform and an optimized drain current waveform; calculating the gate feedthrough theoretical error waveform using the optimized gate voltage waveform; and calculating the parasitic parameter theoretical error waveform using the optimized drain current waveform.

[0009] This invention first smooths the gate voltage waveform and drain current waveform to obtain optimized gate voltage waveform and optimized drain current waveform, and then calculates the gate feedthrough theoretical error waveform and parasitic parameter theoretical error waveform based on the two types of optimized waveforms. This effectively suppresses noise interference in the original waveform and improves the accuracy of calculating the gate feedthrough theoretical error waveform and parasitic parameter theoretical error waveform.

[0010] Optionally, the step of calculating the gate feedthrough theoretical error waveform using the optimized gate voltage waveform includes: performing numerical differentiation on the optimized gate voltage waveform to obtain a gate voltage change rate waveform; setting the GaN device to the off state and applying a ramp voltage with a predetermined change rate to the gate of the GaN device to obtain a drain-source voltage change waveform of the GaN device; extracting the change amplitude from the drain-source voltage change waveform; calculating the ratio of the change amplitude to the predetermined change rate to obtain a feedthrough coefficient; and multiplying the feedthrough coefficient by the gate voltage change rate waveform to obtain the gate feedthrough theoretical error waveform.

[0011] This invention obtains the gate voltage change rate waveform by numerically differentiating the optimized gate voltage waveform. After turning off the GaN device, a predetermined rate-of-change ramp voltage is applied to the gate to obtain the drain-source voltage change waveform and extract its amplitude. The ratio of this amplitude to the predetermined rate of change is calculated to obtain the feedthrough coefficient. Finally, the feedthrough coefficient is multiplied by the gate voltage change rate waveform to obtain the gate feedthrough theoretical error waveform. This invention accurately quantifies the error caused by gate feedthrough interference and improves the pertinence and accuracy of the gate feedthrough theoretical error waveform calculation.

[0012] Optionally, the step of calculating the theoretical error waveform of parasitic parameters using the optimized drain current waveform includes: configuring the test circuit to an unloaded state; performing resonance testing and DC short-circuit testing on the test circuit based on the unloaded state to obtain the parasitic inductance, parasitic capacitance, and parasitic resistance values ​​of the test circuit; calculating the error component waveform using the parasitic inductance, parasitic capacitance, and parasitic resistance values ​​based on the optimized drain current waveform; and superimposing the error component waveforms to obtain the theoretical error waveform of parasitic parameters.

[0013] This invention configures the test circuit to an unloaded state and combines resonance testing and DC short-circuit testing to accurately obtain the parasitic inductance, parasitic capacitance, and parasitic resistance values ​​of the circuit. Then, based on the optimized drain current waveform, it uses these parasitic parameters to calculate the error component waveform and superimposes it to obtain the theoretical error waveform of the parasitic parameters. This achieves accurate quantification of the interference of parasitic parameters in the test circuit and improves the accuracy and pertinence of the calculation of the theoretical error waveform of parasitic parameters.

[0014] Optionally, the error component waveforms include inductance error component waveforms, resistance error component waveforms, and capacitance error component waveforms. The calculation of the error component waveforms based on the optimized drain current waveform using the parasitic inductance, parasitic capacitance, and parasitic resistance values ​​includes: numerically differentiating the optimized drain current waveform to obtain a current rate of change waveform; numerically integrating the optimized drain current waveform to obtain a current integral waveform; obtaining the inductance error component waveform based on the current rate of change waveform and the parasitic inductance value; obtaining the resistance error component waveform based on the optimized drain current waveform and the parasitic resistance value; and obtaining the capacitance error component waveform based on the current integral waveform and the parasitic capacitance value.

[0015] This invention obtains the current rate of change waveform and the current integral waveform by numerically differentiating and integrating the optimized drain current waveform. Then, by combining the parasitic inductance, parasitic resistance, and parasitic capacitance values ​​of the test circuit, the three error component waveforms of inductance, resistance, and capacitance are accurately calculated. This invention achieves the classification, quantification, and precise decomposition of errors caused by different parasitic parameters, thereby improving the accuracy of error component waveform calculation.

[0016] Optionally, the construction of the voltage waveform hybrid compensation model includes: obtaining training sample data by performing low-frequency quasi-static tests and high-frequency dynamic tests on the GaN device; and training the voltage waveform hybrid compensation model based on the training sample data using a neural network.

[0017] This invention obtains training sample data covering multiple operating conditions by conducting low-frequency quasi-static tests and high-frequency dynamic tests on GaN devices. It then uses a neural network to train the sample data to construct a voltage waveform hybrid compensation model, which fully learns the error correlation law of waveforms under different operating conditions. This effectively adapts to nonlinear residual errors that are difficult to eliminate through theoretical modeling, thereby improving the predictive performance of the voltage waveform hybrid compensation model.

[0018] Optionally, the step of training the voltage waveform hybrid compensation model based on the neural network using the training sample data includes: setting a loss function using mean square error; setting constraint terms and adding the constraint terms to the loss function to obtain an optimized loss function; and training the voltage waveform hybrid compensation model based on the neural network using the training sample data with the goal of minimizing the optimized loss function.

[0019] This invention utilizes mean square error to set a loss function, and constructs an optimized loss function by combining adjacent step consistency and energy constraint terms. With the goal of minimizing this optimized loss function, a voltage waveform hybrid compensation model is trained based on a neural network. This ensures both the numerical fit between the predicted waveform and the real waveform, and constrains the rationality of time series changes and energy conservation characteristics. It avoids prediction bias caused by a single loss function, and further improves the generalization ability and prediction accuracy of the voltage waveform hybrid compensation model.

[0020] Optionally, calculating the on-resistance based on the compensated voltage waveform and the drain current waveform includes: identifying a stable conduction phase based on the drain current waveform; calculating the average current value of the stable conduction phase using the drain current waveform; calculating the average voltage value of the stable conduction phase using the compensated voltage waveform; and calculating the on-resistance based on the average current value and the average voltage value.

[0021] This invention accurately identifies the stable conduction stage based on the drain current waveform, calculates the average current and the average voltage after compensation for this stage, and then calculates the on-resistance by the ratio of the two based on Ohm's law. This eliminates the influence of switching transient interference and waveform noise, and improves the calculation accuracy of the dynamic on-resistance of GaN devices.

[0022] Optionally, the step of calculating the on-resistance based on the compensated voltage waveform and the drain current waveform further includes: constructing the instantaneous power consumption waveform of the GaN device during the switching cycle based on the compensated voltage waveform and the drain current waveform; integrating the instantaneous power consumption waveform during the stable conduction phase to obtain an energy loss value; calculating the theoretical energy loss value of the stable conduction phase based on the on-resistance and the average current value; comparing the energy loss value with the theoretical energy loss value, and evaluating the on-resistance based on the comparison result.

[0023] This invention constructs an instantaneous power consumption waveform based on the compensated voltage waveform and drain current waveform, integrates the instantaneous power consumption waveform during the stable conduction phase to obtain the energy loss value, and calculates the theoretical energy loss value by combining the on-resistance and the average current value and compares and evaluates it. This realizes closed-loop verification of the on-resistance measurement results and improves the reliability of the dynamic on-resistance measurement results of GaN devices.

[0024] Another aspect of the present invention provides a GaN device dynamic on-resistance measurement error suppression system, comprising: a processor, an input device, an output device, and a memory, wherein the processor, the input device, the output device, and the memory are interconnected, wherein the memory is used to store a computer program, the computer program including program instructions, and the processor is configured to call the program instructions to execute the GaN device dynamic on-resistance measurement error suppression method according to any one of the preceding aspects of the present invention.

[0025] The present invention provides a GaN device dynamic on-resistance measurement error suppression system, which is compact, stable, highly integrated, and simple in construction. It can stably execute the GaN device dynamic on-resistance measurement error suppression method provided in the preceding aspect of the present invention, further improving the overall applicability and practical application capability of the present invention. Attached Figure Description

[0026] Figure 1 This is a flowchart of a method for suppressing measurement errors of dynamic on-resistance of a GaN device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a GaN device dynamic on-resistance measurement error suppression system according to an embodiment of the present invention. Detailed Implementation

[0027] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, software, or methods have not been specifically described to avoid obscuring the invention.

[0028] Throughout this specification, references to "an embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0029] Please see Figure 1 In order to solve the problems in the existing technology, such as Figure 1 The method for suppressing measurement error of dynamic on-resistance of GaN devices, as shown, includes the following steps: Step S1: Based on the predetermined test circuit, acquire the on-state voltage waveform, gate voltage waveform, and drain current waveform of the GaN device for one switching cycle.

[0030] In this embodiment, the predetermined test circuit is a standard dual-pulse test circuit, which includes a DC power supply, bus capacitor, GaN device under test, load inductor, resistor, and gate drive circuit. Based on the pre-built dual-pulse test circuit, a high-speed oscilloscope with a sampling rate of greater than or equal to 1GS / s is used, along with a high-bandwidth differential voltage probe with a bandwidth of greater than or equal to 500MHz and a Rogowski coil / coaxial shunt type current probe. The gate drive signal is used as the trigger signal to ensure the capture of the complete switching process. The drain-source voltage waveform (i.e., on-state voltage waveform), gate-source voltage waveform (i.e., gate voltage waveform), and drain current waveform of the GaN device are acquired synchronously within one switching cycle. Before acquisition, the probe needs to be pre-calibrated and time-matched. When measuring the drain-source voltage, a true differential probe must be used to suppress common-mode noise. The probe grounding should be as short as possible to avoid forming a grounding loop. It is also recommended to average the data after multiple acquisitions to reduce random noise interference and ensure that the acquired discrete timing waveform data is accurate and reliable.

[0031] Pre-calibration and delay matching of the probes include: using a standard signal source to output a sine wave or fast-edge square wave of known amplitude and frequency, connecting it to the differential voltage probe for gain and offset calibration to ensure that the voltage amplitude measured by the probe deviates from the standard signal amplitude within ±1%. Simultaneously, the current probe is calibrated by placing it on a current-carrying conductor driven by a standard current source, or by using it with a precision shunt resistor, to verify the linear correspondence between the probe output signal and the actual current. During delay matching, a synchronization pulse signal with a rising edge of less than or equal to 1 ns is generated using a function generator and connected to the measurement terminals of both the voltage and current probes. The output signals of two probes are simultaneously acquired using an oscilloscope. The time difference between the two signals is calculated using the cross-correlation algorithm built into the oscilloscope. By adjusting the probe cable length, the oscilloscope channel delay compensation parameters, or fine-tuning the physical installation position of the probes, the rising / falling edges of the two signals are precisely aligned, and the delay error is controlled within the sub-nanosecond level. During the calibration process, it is necessary to ensure that the probe grounding is short and reliable (the grounding lead length is less than or equal to 3mm) to avoid forming a grounding loop, and to keep the test environment temperature and humidity stable. Each calibration step is repeated 3-5 times and the average value is taken to ensure the reliability of the calibration and delay matching results.

[0032] Step S2: Calculate the gate feedthrough theoretical error waveform and the parasitic parameter theoretical error waveform based on the gate voltage waveform and the drain current waveform, respectively.

[0033] The calculation of the gate feedthrough theoretical error waveform and the parasitic parameter theoretical error waveform based on the gate voltage waveform and the drain current waveform specifically includes the following sub-steps: Step S201: Smooth the gate voltage waveform and the drain current waveform to obtain the optimized gate voltage waveform and the optimized drain current waveform.

[0034] In this embodiment, the Savitzky-Golay filtering algorithm is used to smooth the acquired gate voltage waveform (discrete time-series data) and drain current waveform (discrete time-series data) to obtain optimized gate voltage waveform and optimized drain current waveform. For typical switching frequencies (e.g., 100kHz) and sampling rates (1GS / s, corresponding to sampling interval Δt=1ns), a sliding window with a window length of 51~101 points (corresponding to a time span of 51~101ns) is selected when implementing the filtering. A third-order polynomial is used to perform convolution operations on the waveform data. Noise interference is suppressed by fitting the data points within the polynomial within the window.

[0035] Step S202: Calculate the gate feedthrough theoretical error waveform using the optimized gate voltage waveform.

[0036] The calculation of the gate feedthrough theoretical error waveform using the optimized gate voltage waveform specifically includes the following sub-steps: Step S20201: Perform numerical differentiation on the optimized gate voltage waveform to obtain the gate voltage change rate waveform.

[0037] In this embodiment, for the regular time points in the middle of the optimized gate voltage waveform, a center-difference method is used. Two adjacent optimized gate voltage data points before and after this time point are selected, and the difference between them is calculated and divided by twice the sampling interval to obtain the gate voltage change rate at that point. For the starting point of the waveform, a forward-difference method is used. The starting point and the next immediately adjacent data point are selected, and the difference between them is calculated and divided by the sampling interval. For the ending point of the waveform, a backward-difference method is used. The ending point and the previous immediately adjacent data point are selected, and the difference between them is calculated and divided by the sampling interval. Considering that the numerical differentiation process amplifies noise, a slight secondary smoothing process (such as using Savitzky-Golay filtering with a window length of 11-21 points) is required on the initially obtained gate voltage change rate waveform. In the switching edge region where the gate voltage changes drastically, a higher-order difference method is switched to improve the calculation accuracy. Throughout the process, it is ensured that the time axis of the final obtained gate voltage change rate waveform is strictly consistent with the original optimized gate voltage waveform, without any phase shift.

[0038] Step S20202: Set the GaN device to the off state and apply a ramp voltage with a predetermined rate of change to the gate of the GaN device to obtain the waveform of the drain-source voltage change of the GaN device.

[0039] In this embodiment, the GaN device is first configured to be completely off, ensuring that its gate-source voltage is lower than the device threshold voltage and the drain-source voltage is zero, so as to avoid the channel current interfering with subsequent measurements. Then, an arbitrary waveform generator is used to apply a linear ramp voltage to the gate of the GaN device. The predetermined rate of change is calculated from the gate voltage waveform obtained in step S1. Specifically, the voltage change rate of the gate voltage waveform switching edge (10% to 90% voltage range) is extracted, and 1.2 to 1.5 times the predetermined rate of change is used as the setting range of the predetermined rate of change to ensure that the actual dynamic process is covered. While the voltage is applied, a high-speed oscilloscope and a high-bandwidth differential voltage probe that have been calibrated and time-matched are used to simultaneously measure the voltage change at the drain and source ends of the GaN device caused by the gate ramp voltage, and then the waveform of the drain-source voltage change is recorded.

[0040] Step S20203: Extract the amplitude of the change in the drain-source voltage change waveform.

[0041] In this embodiment, for the acquired drain-source voltage change waveform, an overall trend analysis is first performed to eliminate interference, with a focus on removing initial spike signals caused by overshoot or ringing of the measurement system itself (these spikes do not reflect the true voltage change of the gate-drain coupling of the GaN device). Then, the state after the waveform jumps is observed. If the waveform tends to be stable after the jump, the voltage value of the stable segment is directly selected as the change amplitude. If there is a damped oscillation after the waveform jumps, the average voltage after the oscillation tends to be stable is calculated as the change amplitude. To further improve the accuracy of amplitude extraction, the above measurement and extraction process can be repeated under multiple ramp voltage excitations with different rates of change, and finally the average value of the extracted change amplitudes is taken.

[0042] Step S20204: Calculate the ratio of the magnitude of the change to the predetermined rate of change to obtain the feedthrough coefficient.

[0043] In this embodiment, the feedthrough coefficient is a key parameter for quantifying the gate-drain coupling effect of GaN devices. Its core significance lies in establishing the correspondence between the gate voltage change rate and the parasitic voltage interference at the drain and source terminals, enabling the quantification of the feedthrough error caused by dynamic changes in the gate voltage on the drain-source voltage measurement into a calculable theoretical waveform. When calculating the feedthrough coefficient, the amplitude of the change corresponding to each predetermined rate of change is used as the numerator, and the predetermined rate of change is used as the denominator. A division operation is performed to obtain the preliminary feedthrough coefficient corresponding to a single set of data. To improve the robustness of the results, the waveform acquisition and amplitude extraction of the drain-source voltage change are repeated under multiple different predetermined rates of change to obtain multiple sets of paired data of the amplitude of change and the corresponding predetermined rate of change. These paired data are then fitted by linear regression to obtain the final feedthrough coefficient (which is time-dimensional).

[0044] Step S20205: Multiply the feedthrough coefficient by the gate voltage change rate waveform to obtain the gate feedthrough theoretical error waveform.

[0045] In this embodiment, a point-by-point multiplication method is first used to multiply the feedthrough coefficient with the value of each corresponding time point in the gate voltage change rate waveform. During the operation, attention should be paid to the consistency of the sign. If the gate voltage change rate corresponding to the rising edge of the gate voltage is positive, the sign of the product result is positive. If the gate voltage change rate corresponding to the falling edge of the gate voltage is negative, the sign of the product result is negative. This is to truly reflect the polarity characteristics of the gate feedthrough interference. Finally, through point-by-point operation of the full-time data, a gate feedthrough theoretical error waveform that can quantify the gate feedthrough interference is generated. This waveform maintains the same time span and sampling interval as the original gate voltage change rate waveform.

[0046] Step S203: Calculate the theoretical error waveform of parasitic parameters using the optimized drain current waveform.

[0047] The theoretical error waveform for calculating parasitic parameters using the optimized drain current waveform includes: Step S20301: Configure the test circuit to an unloaded state.

[0048] In this embodiment, when configuring the test circuit to an unloaded state, the GaN device must first be completely removed from the test PCB board, or the device pin connection must be disconnected to make it an open circuit. This ensures that the power circuit becomes a pure parasitic network without core device connections. At the same time, it is necessary to strictly ensure that the PCB trace layout, probe contact position, cable connection method, etc. in the unloaded state are completely consistent with the configuration when the GaN device is actually tested. This avoids distortion of the extracted parasitic parameters due to differences in hardware connections, and ensures that the parasitic inductance, parasitic capacitance, and parasitic resistance values ​​obtained subsequently can truly reflect the parasitic characteristics of the actual test circuit.

[0049] Step S20302: Based on the no-load state, perform resonance test and DC short-circuit test on the test circuit to obtain the parasitic inductance value, parasitic capacitance value and parasitic resistance value of the test circuit.

[0050] In this embodiment, a resonance test is first performed. A vector network analyzer is used to sweep the impedance of the unloaded circuit within the range of 1MHz to 500MHz. By analyzing the measurement results, the series resonant frequency and quality factor of the circuit are obtained, and then the parasitic inductance and parasitic capacitance values ​​of the test circuit are calculated. During the test, the excitation power of the vector network analyzer needs to be controlled to avoid nonlinear effects. Considering the characteristics of parasitic parameters changing with frequency, data can be extracted at multiple frequency points or a simple RLC network model can be fitted to improve accuracy. Next, a DC short-circuit test is performed. A precision DC source meter is used to measure the DC resistance of the unloaded circuit using a four-wire Kelvin connection method. During the measurement, the influence of probe contact resistance needs to be deducted. Finally, the parasitic inductance, parasitic capacitance, and parasitic resistance values ​​of the test circuit are obtained through the combined results of the above two tests.

[0051] Step S20303: Based on the optimized drain current waveform, calculate the error component waveform using the parasitic inductance value, the parasitic capacitance value, and the parasitic resistance value.

[0052] The error component waveforms include inductance error component waveforms, resistance error component waveforms, and capacitance error component waveforms.

[0053] The calculation of the error component waveform based on the optimized drain current waveform using the parasitic inductance, parasitic capacitance, and parasitic resistance specifically includes the following sub-steps: Step S2030301: Perform numerical differentiation on the optimized drain current waveform to obtain the current change rate waveform.

[0054] In this embodiment, for the conventional time points in the middle of the optimized drain current waveform, a center-difference method is used. Two adjacent optimized drain current data points before and after this time point are selected, and the difference between them is calculated and divided by twice the sampling interval to obtain the current change rate at that point. For the starting point of the optimized drain current waveform, a forward-difference method is used. The starting point and the next immediately adjacent data point are selected, and the difference between them is calculated and divided by the sampling interval. For the ending point of the optimized drain current waveform, a backward-difference method is used. The ending point and the previous immediately adjacent data point are selected, and the difference between them is calculated and divided by the sampling interval. Considering that current measurement noise is usually significant, a moderate secondary smoothing process can be performed on the optimized drain current waveform before differentiation to suppress noise interference. In regions where the drain current changes drastically, a higher-order difference method is switched to improve calculation accuracy. Throughout the process, it is ensured that the final current change rate waveform is strictly aligned with the time axis of the original optimized drain current waveform, without any phase shift.

[0055] Step S2030302: Perform numerical integration on the optimized drain current waveform to obtain the current integral waveform.

[0056] In this embodiment, the optimized drain current waveform after Savitzky-Golay filtering is processed using a trapezoidal numerical integration method to obtain the current integral waveform. Before integration, the waveform is checked for DC bias; if present, the DC component is removed to prevent linear drift in the integration result. If the current ripple is large, the optimized drain current waveform can be lightly smoothed to suppress noise interference. The initial integration value is set to zero, and then integration is performed point by point: for each time point, the average value of the optimized drain current data at that point and the previous time point is taken, and then multiplied by a fixed sampling interval to obtain the integration increment within that time period. This increment is added to the integration result at the previous time point to obtain the integration value at the current time point. Throughout the process, it is necessary to ensure that the integration process is strictly aligned with the time axis of the original optimized drain current waveform. The final current integral waveform is consistent with the original waveform in terms of time span and sampling interval, accurately reflecting the changing trend of conducted charge.

[0057] Step S2030303: Based on the current change rate waveform and the parasitic inductance value, the inductance error component waveform is obtained.

[0058] In this embodiment, the inductance error component originates from the induced voltage generated by the parasitic inductance in the test circuit when the current changes. To accurately extract this component, it is first ensured that the current rate of change waveform is strictly time-synchronized with the original current signal. Subsequently, the extracted parasitic inductance value of the circuit is multiplied one by one with the value at each time point in the current rate of change waveform to obtain the inductance error voltage value at each moment, forming the inductance error component waveform. This operation physically realizes point-by-point quantization of the transient voltage drop caused by parasitic inductance, which can accurately reflect the voltage distortion introduced by inductive parasitic effects during rapid current changes. The final generated inductance error component waveform is completely aligned with the original waveform in terms of time axis and sampling interval. Essentially, by directly combining parasitic inductance and dynamic current rate of change, it achieves accurate modeling and waveform representation of inductive interference in high-frequency switching processes, significantly improving the extraction accuracy of inductance-type errors and laying a reliable foundation for subsequent targeted voltage compensation.

[0059] Step S2030304: Based on the optimized drain current waveform and the parasitic resistance value, the resistance error component waveform is obtained.

[0060] In this embodiment, the resistance error component originates from the ohmic voltage drop generated by the parasitic resistance in the test circuit when current flows through it. First, it is ensured that the optimized drain current waveform has been noise-filtered and timing integrity maintained. Then, the measured parasitic resistance value is multiplied point-by-point by the current value at each moment in the current waveform to obtain the resistance error voltage at each time point, forming the resistance error component waveform. This calculation essentially treats the parasitic resistance distributed at various locations as a lumped parameter, thereby reproducing the additional voltage drop caused by the current across the parasitic resistance in the circuit at the waveform level. During execution, attention must be paid to the correspondence between the current direction and the voltage drop polarity to ensure that the sign of the error component conforms to the actual physical process. Essentially, by combining a clear resistance model with a real-time current waveform, the resistive parasitic effect in the test circuit is directly quantified. Especially under high-current operating conditions, the contribution of the resistive voltage drop to the overall error can be clearly separated, enhancing the completeness of the error analysis and the targeted nature of the compensation.

[0061] Step S2030305: Obtain the capacitance error component waveform based on the current integral waveform and the parasitic capacitance value.

[0062] In this embodiment, the capacitance error component corresponds to the voltage shift caused by charge accumulation and release in the parasitic capacitance of the test circuit. To calculate this component, the optimized drain current waveform is first numerically integrated to obtain the charge accumulation waveform over time. Then, the reciprocal of the parasitic capacitance value is taken and multiplied by the value at each time point in the charge waveform to obtain the capacitance error voltage at each moment, forming the capacitance error component waveform. This method, based on the fundamental relationship between charge and voltage, directly reflects the voltage error introduced by charge storage in the parasitic capacitance during dynamic processes, especially significant during current commutation or switching. During implementation, it is necessary to eliminate DC offset during the integration process to avoid non-physical drift in the waveform. Essentially, by combining current integration and capacitance parameters, the time-domain waveform reconstruction of capacitive parasitic effects is achieved, accurately capturing the voltage error caused by charge redistribution during switching transients. This compensates for the shortcomings of traditional methods in capacitive interference modeling, making the parasitic error model more comprehensive.

[0063] Step S20304: The error component waveforms are superimposed to obtain the parasitic parameter theoretical error waveform.

[0064] In this embodiment, the error component waveforms include inductance error component waveforms, resistance error component waveforms, and capacitance error component waveforms. To comprehensively reflect the combined influence of parasitic parameters in the test circuit, these waveforms need to be synthesized. Specifically, a point-by-point algebraic addition is used. At each identical time point, the corresponding inductance error voltage values, resistance error voltage values, and capacitance error voltage values ​​in the inductance, resistance, and capacitance error component waveforms are summed to obtain the total parasitic error voltage at that moment. During the superposition process, the physical polarity of each error component must be strictly followed: the inductance error is related to the direction of current change, the resistance error is consistent with the instantaneous direction of current, and the capacitance error corresponds to the polarity of accumulated charge. The resulting theoretical error waveform of parasitic parameters fully characterizes the systematic interference caused by the parasitic effects of the test circuit on the measured voltage during dynamic testing, providing an accurate and comprehensive error benchmark for subsequent waveform compensation. Essentially, by classifying, extracting, and linearly superimposing, a complete and analytical synthetic waveform of parasitic errors is constructed. This not only preserves the independent physical characteristics of various parasitic effects but also enables an overall assessment of their combined impact, significantly improving the integrity of the error model and the systematic nature of the compensation process, thus providing a solid theoretical basis for high-precision dynamic measurement.

[0065] Step S3: Subtract the gate feedthrough theoretical error waveform and the parasitic parameter theoretical error waveform from the conduction voltage waveform to obtain the preliminary compensation waveform.

[0066] In this embodiment, to isolate the main systematic interference from the measured turn-on voltage, preliminary error compensation is first performed based on the physical premise that the gate feedthrough error and the parasitic parameter error of the test circuit are independent and can be linearly superimposed. Since the gate feedthrough effect mainly originates from the coupling of the gate-drain capacitance inside the device, while the parasitic parameter error comes from the distributed inductance, resistance, and capacitance in the external test circuit, the two are completely different in their generation mechanism and source, and therefore can be linearly separated and subtracted. During operation, at each sampling time point, the theoretical gate feedthrough error waveform value and the theoretical parasitic parameter error waveform value of the same period are subtracted from the original turn-on voltage waveform value at that time, thus obtaining the preliminary compensation voltage value at that time point. This calculation is performed point by point throughout the entire switching cycle, ultimately forming a preliminary compensation voltage waveform.

[0067] The preliminary compensation waveform is a purified voltage signal after minimizing the two main types of dynamic interference (internal gate feed-through voltage and external circuit parasitic voltage drop) while retaining the device's own on-state voltage drop. Therefore, the preliminary compensation waveform can be regarded as an approximation of the theoretical on-state voltage generated solely by the combined effect of the device channel resistance and instantaneous current under an ideal non-destructive testing environment. This provides an important intermediate signal basis for further extraction of the true dynamic on-state resistance. This is done because the directly measured on-state voltage during high-speed switching is mixed with various dynamic errors. If these systematic and modelable interferences are not subtracted first, the true conduction characteristics of the device cannot be accurately observed. This invention achieves the first round of noise reduction and correction of the measured signal through error separation guided by theory, significantly improving the waveform quality.

[0068] Although the initial compensation has removed the main errors based on the physical model, some residual errors will still exist in the compensated waveform due to model simplification, non-ideal parameter extraction, and uncovered dynamic effects (such as device nonlinearity and residual frequency response errors of the probe). Therefore, the initial compensated waveform is not the final result, but rather provides a cleaner and more realistic input signal for the subsequent introduction of a data-driven hybrid compensation model. This forms a two-stage error suppression system of theoretical compensation and intelligent correction, ensuring the accuracy and reliability of the final result.

[0069] Step S4: Construct a voltage waveform hybrid compensation model. Calculate the compensated voltage waveform based on the preliminary compensation waveform, the gate voltage waveform, the drain current waveform, and the conduction voltage waveform using the voltage waveform hybrid compensation model.

[0070] The construction of the voltage waveform hybrid compensation model specifically includes the following sub-steps: Step S401: Obtain training sample data by performing low-frequency quasi-static tests and high-frequency dynamic tests on the GaN device.

[0071] In this embodiment, a sample set for training a voltage waveform hybrid compensation model is constructed by performing paired tests on the same GaN device under different operating conditions. First, the core parameters of the low-frequency quasi-static test (low switching frequency 1kHz, slow gate edge 500ns, small duty cycle 0.1%) are kept constant to ensure that each low-frequency test yields a "quasi-true" low-frequency voltage waveform (referred to as the historical low-frequency voltage waveform) and low-frequency current waveform (referred to as the historical low-frequency current waveform) with minimal error. This is because, under low-frequency, slow-switching conditions, the dynamic error caused by gate feedthrough and circuit parasitic parameters is negligible. The measured conduction voltage waveform can then be approximated as the device's true conduction voltage waveform. To eliminate the influence of trap effects and self-heating effects on the difference in intrinsic conduction resistance between low-frequency and high-frequency tests, a pre-processing pulse sequence is applied before pairing tests to stabilize the device's trap charge state. Test conditions are controlled so that both tests are performed at approximately the junction temperature. Then, under the same thermal stability and DC bias conditions as the low-frequency test, the actual operating frequency and normal switching speed are switched to perform high-frequency dynamic testing, simultaneously acquiring high-frequency voltage waveforms, high-frequency gate voltage waveforms, and high-frequency current waveforms (referred to as the historical high-frequency voltage waveform, historical low-frequency current ... Historical high-frequency gate voltage waveform and historical high-frequency current waveform were used. After each round of high and low frequency testing, the consistency between the low-frequency on-resistance and the on-resistance during high-frequency operation was verified (correcting for trap effects and self-heating differences). Then, the historical preliminary compensation waveform, historical gate feedthrough theoretical error waveform, and historical parasitic parameter theoretical error waveform were calculated according to the methods in steps S2 and S3. The historical preliminary compensation waveform, historical gate feedthrough theoretical error waveform, and historical parasitic parameter theoretical error waveform of the current round were used as input features, and the corresponding historical low-frequency voltage waveform was used as output features to form a set of sample data. Subsequently, the test conditions were systematically adjusted, including different bus voltages (e.g., 50V, 100V, 200V), different load currents (e.g., 1A, 5A, 10A), different junction temperatures (set to 25℃, 50℃, 85℃ using a temperature control station), and different gate resistances (e.g., 1Ω, 5Ω, 10Ω), etc., and multiple rounds of testing were conducted. Finally, multiple sets of training sample data covering the expected operating scenarios of GaN devices were constructed to ensure that the voltage waveform hybrid compensation model trained subsequently has strong generalization ability.

[0072] Step S402: Based on the neural network, a voltage waveform hybrid compensation model is trained using the training sample data.

[0073] The voltage waveform hybrid compensation model trained using the training sample data based on a neural network specifically includes the following sub-steps: Step S40201: Set the loss function using mean square error.

[0074] The loss function satisfies the following formula: in, For loss function, The number of training samples. For the first The total number of time steps for each sample For the first Each sample at time step The predicted compensated voltage waveform value, For the first Each sample at time step Historical low-frequency voltage waveform values.

[0075] The above formula measures the overall deviation between the voltage waveform hybrid compensation model's prediction result and the "near-truth" reference waveform. First, for each training sample, the sum of the squares of the differences between the predicted compensated voltage waveform value and the historical low-frequency voltage waveform value used as the true reference within the entire time step is calculated. This sum is then divided by the total number of time steps for that sample to obtain the mean square deviation between the predicted and true waveforms for a single sample. Finally, the mean square deviation of this deviation is averaged for all training samples to obtain the final result. The value represents the average deviation between the predicted compensated voltage waveform and the actual low-frequency voltage waveform across the entire sample and time dimension.

[0076] Step S40202: Set constraint terms and add the constraint terms to the loss function to obtain the optimized loss function.

[0077] In this embodiment, the constraints include adjacent stride consistency constraints and energy constraints.

[0078] The adjacent stride consistency constraint term satisfies the following formula: in, For adjacent stride consistency constraints, The number of training samples. For the first The total number of time steps for each sample For the first Each sample at time step Historical low-frequency voltage waveform values, For the first Each sample at time step Historical low-frequency voltage waveform values, For the first Each sample at time step The predicted compensated voltage waveform value, For the first Each sample at time step The predicted voltage waveform value after compensation.

[0079] The above formula constrains the voltage waveform. The compensated voltage waveform predicted by the hybrid compensation model is consistent with the real historical low-frequency voltage waveform in terms of the rhythm of temporal dynamic changes. First, for each training sample, adjacent time steps ( and The step change amplitude (absolute value of the difference between adjacent voltage values) of the real low-frequency voltage waveform and the step change amplitude (absolute value of the difference between adjacent voltage values) of the predicted compensated voltage waveform are calculated separately. The difference between these two amplitudes is then squared to measure the deviation between the change rhythm of the predicted waveform at adjacent steps and the real waveform. Finally, the average of all time steps for a single sample is taken, and then the average is taken over the entire training sample set to obtain the result. The core function of this constraint is to prevent the model from merely satisfying the fact that the predicted value is close to the actual value, but the voltage change amplitude of adjacent time steps is disordered (for example, the actual waveform changes smoothly and gradually but the predicted waveform changes abruptly). It ensures that the predicted compensated voltage waveform not only matches the actual device voltage characteristics in terms of value, but also that its dynamic change rhythm in time sequence conforms to physical laws, thereby improving the temporal rationality of the predicted waveform and its consistency with actual physics.

[0080] The energy constraint term satisfies the following formula: in, For energy constraint terms, The number of training samples. For the first The total number of time steps for each sample For the first Each sample at time step The predicted compensated voltage waveform value, For the first Each sample at time step Historical low-frequency voltage waveform values, For the first Each sample at time step The low-frequency current waveform value.

[0081] The above formula ensures that the compensated voltage waveform predicted by the hybrid voltage waveform compensation model is consistent with the actual device characteristics in terms of energy loss corresponding to voltage and current. In the formula, the numerator is the sum of the products of the predicted compensated voltage waveform and the actual low-frequency current waveform over the entire time step (corresponding to the device energy loss under the predicted voltage), and the denominator is the sum of the products of the actual low-frequency voltage waveform and the actual low-frequency current waveform over the entire time step (corresponding to the actual energy loss of the device). The ratio of the two reflects the energy deviation between the predicted voltage and the actual voltage. By constraining the sample average of the square of the difference between this ratio and 1 to be as small as possible, the energy loss corresponding to the predicted compensated voltage waveform can be highly consistent with the energy loss corresponding to the actual voltage waveform. Its core function is to avoid the situation where the model only satisfies the fit of voltage values ​​and time-series changes, but a small overall voltage deviation leads to a large deviation of the energy loss from the actual value. It ensures that the predicted waveform is not only reasonable in waveform shape, but also conforms to the actual operating characteristics of the device in terms of the physical quantity of "energy loss jointly determined by voltage and current", further improving the physical reliability of the model prediction. Among them, the low-frequency current waveform value is a key reference value obtained when the sample data is used for low-frequency quasi-static testing.

[0082] The optimized loss function satisfies the following formula: in, To optimize the loss function, For loss function, For adjacent stride consistency constraints, This is an energy constraint term.

[0083] Step S40203: Based on the neural network, a voltage waveform hybrid compensation model is obtained by training the training sample data with the goal of minimizing the optimized loss function.

[0084] In this embodiment, a temporal convolutional network (TCN) is first constructed as the core network structure. Its input layer receives a tensor that is spliced ​​and standardized along the time dimension by the historical preliminary compensation waveform, the historical gate feedthrough theoretical error waveform, and the historical parasitic parameter theoretical error waveform. The main body of the network contains 4 to 8 residual blocks with causal dilated convolutions to extract the temporal features of the waveform. The output layer is mapped through a fully connected layer to output the predicted compensated voltage waveform sequence. The input features are defined as historical preliminary compensation waveforms, historical gate feedthrough theoretical error waveforms, and historical parasitic parameter theoretical error waveforms. The output is the predicted compensated voltage waveform. Subsequently, the input features of all training sample data are standardized and preprocessed. The mean and standard deviation are calculated based on the training set data and these parameters are fixed to ensure consistent data distribution and stabilize the training process. During training, the Adam optimizer is used, with the goal of minimizing the optimization loss function, which includes the mean square error loss term, the adjacent step consistency constraint term, and the energy constraint term. Model training is carried out on the divided training set, validation set, and test set. During training, a cosine annealing learning rate scheduling strategy is used to dynamically adjust the learning rate. At the same time, an early stopping strategy is enabled. Training is stopped when the optimization loss function value on the validation set no longer decreases for several consecutive rounds to prevent overfitting. Finally, a hybrid voltage waveform compensation model with strong generalization ability and high compensation accuracy is obtained.

[0085] The voltage waveform after compensation is calculated using the voltage waveform hybrid compensation model based on the preliminary compensation waveform, the gate voltage waveform, the drain current waveform, and the conduction voltage waveform. According to the preprocessing standards set during the training phase of the voltage waveform hybrid compensation model, the discrete time-series data of four types of waveforms—preliminary compensation waveform, gate voltage waveform, drain current waveform, and on-state voltage waveform—are standardized. The standardized waveforms are then combined into multi-dimensional input features according to preset dimensions (the preliminary compensation waveform has had major systematic errors deducted, the gate voltage and drain current waveforms reflect the dynamic operating state of the device, and the on-state voltage waveform retains the original measurement information; these four features complement each other to form complete error correlation information). These multi-dimensional input features are then input into the trained voltage waveform hybrid compensation model. Through deep convolution and time-series modeling capabilities, the model extracts the residual error patterns hidden in the four types of features, including incompletely deducted gate feedthrough residual errors, parasitic parameter modeling deviations, and dynamic errors caused by device nonlinearity. Based on the input features learned during training and the low-frequency quasi-true voltage mapping relationship, the model outputs a predicted compensated voltage waveform. Finally, the waveform output by the voltage waveform hybrid compensation model is post-processed to restore the standardized predicted values ​​to the actual voltage amplitude, ensuring that its time axis is strictly aligned with the original input waveform, thus obtaining the final compensated voltage waveform.

[0086] It should be noted that the core reason why the voltage waveform hybrid compensation model can accurately predict the compensated voltage waveform is as follows: First, during the training phase, a "quasi-true" low-frequency voltage waveform with minimal error was obtained through low-frequency quasi-static testing as a label. Combined with high-frequency dynamic test data under multiple operating conditions, this allowed the model to fully learn the mapping relationship between the initial compensation waveform, the device operating state waveform (gate voltage, drain current), the original conduction voltage waveform, and the true voltage waveform under different operating conditions. In particular, it mastered the error patterns of residual nonlinear errors and dynamic interference after initial compensation, which are difficult to deduct through theoretical modeling. Second, the four types of input waveforms cover the device operating state... The system consists of four parts: first, the state (gate voltage, drain current), the original measurement information (conduction voltage), and the preliminary error correction results (preliminary compensation waveform), forming a complete information chain that provides sufficient basis for the model to capture residual errors; second, the core structure of the temporal convolutional network is adapted to discrete temporal waveform data, which can effectively mine the temporal correlation of the waveform and avoid prediction deviations caused by the loss of temporal information; and third, the optimized loss function used during training (including mean square error, adjacent step consistency constraints, and energy constraints) ensures that the waveform predicted by the model is not only close to the true value in terms of numerical value, but also conforms to physical laws in terms of temporal change trends and energy conservation, further improving the reliability of the prediction.

[0087] Step S5: Calculate the on-resistance based on the compensated voltage waveform and the drain current waveform.

[0088] The calculation of the on-resistance based on the compensated voltage waveform and the drain current waveform specifically includes the following sub-steps: Step S501: Identify the stable conduction stage based on the drain current waveform.

[0089] In this embodiment, the drain current waveform is first smoothed by low-pass filtering to suppress current oscillations caused by switching transients and avoid multiple crossover interferences in subsequent threshold judgment. Then, the current threshold is set to 90% of the maximum drain current value. The current waveform is traversed throughout the entire switching cycle. The moment when the current first rises and stabilizes above the threshold is recorded as the turn-on start point ton, and the moment when the current falls and stabilizes below the threshold is recorded as the turn-off start point tooff. If there are brief fluctuations in the waveform that cause the threshold to cross repeatedly, the first moment when three consecutive sampling points meet the threshold condition is taken as the valid start / end point. At the same time, the gate-source voltage waveform is used for auxiliary verification. Only the interval where the gate-source voltage waveform exceeds the device threshold voltage and remains at a high level is retained, and invalid intervals caused by noise or false triggering are eliminated. Finally, the time interval between ton and tooff is determined as the stable conduction stage, ensuring that the switching transient process is completely excluded from this interval and is strictly aligned with the time axis of subsequent voltage and current average value calculations.

[0090] Step S502: Calculate the average current during the stable conduction phase using the drain current waveform.

[0091] In this embodiment, the stable conduction phase time interval [ton, toff] identified by the drain current waveform is first defined to ensure that the switching transient process is completely excluded from this interval. Then, the drain current waveform in this interval is preprocessed. First, the current ripple is suppressed by low-pass filtering, and then abnormal sampling points (such as extreme pulses) that exceed the normal fluctuation range are removed to avoid interference with the average value calculation. Next, the total number of discrete time-series data steps in this interval (i.e., the number of sampling points between toff and ton) is counted. All preprocessed drain current sampling values ​​are summed. Finally, the total current value is divided by the total number of sampling points in this interval to obtain the average current value of the stable conduction phase (if normalization in the physical time dimension is required, the total current value can be multiplied by the sampling interval to obtain the total charge, and then divided by the time length of [ton, toff]). This ensures that the calculation result strictly corresponds to the stable conduction phase and is completely synchronized with the calculation interval of the subsequent average voltage value.

[0092] Step S503: Calculate the average voltage during the stable conduction phase using the compensated voltage waveform.

[0093] In this embodiment, the compensated voltage waveform within the conduction phase time interval [ton, toff] is first preprocessed. Residual noise and minor oscillations are suppressed by low-pass filtering, while abnormal sampling points (such as pulse interference) that exceed the normal fluctuation range are removed to avoid affecting the accuracy of the average value. Next, the total number of discrete sampling points of the compensated voltage waveform within the [ton, toff] interval is counted, and all preprocessed voltage sampling values ​​are summed. Finally, the average value is calculated based on the characteristics of discrete time-series data. By normalizing to physical time, the total voltage value is multiplied by the sampling interval to obtain the total voltage-time integral value, which is then divided by the time length of [ton, toff] to finally obtain the average voltage value during the stable conduction phase. This ensures that the result is completely matched with the calculation logic and range of the corresponding average current value.

[0094] Step S504: Calculate the on-resistance based on the average current and the average voltage.

[0095] In this embodiment, the dynamic on-resistance is obtained by calculating the ratio of the average voltage to the average current according to the core formula of Ohm's law. This ratio represents the dynamic on-resistance value of the GaN device measured under the current switching cycle and specific test conditions.

[0096] Step S505: Based on the compensated voltage waveform and the drain current waveform, construct the instantaneous power consumption waveform of the GaN device during the switching cycle.

[0097] In this embodiment, a point-by-point multiplication method is adopted. At each corresponding time step, the compensated voltage value and the drain current value at that moment are multiplied to obtain the instantaneous power consumption value at that time step. By traversing all time steps of the entire switching cycle, all instantaneous power consumption values ​​are arranged in chronological order to construct a complete instantaneous power consumption waveform within the switching cycle. In this waveform, the power consumption during the stable conduction phase is mainly the conduction loss, and the power consumption during the switching transient phase is mainly the switching loss. Throughout the process, it is necessary to ensure that there is no time misalignment between the two sets of waveforms, and the multiplication operation strictly corresponds to the data at the same time point to ensure that the instantaneous power consumption waveform can truly reflect the power consumption changes of the device in different operating stages.

[0098] Step S506: Integrate the instantaneous power consumption waveform during the stable conduction phase to obtain the energy loss value.

[0099] In this embodiment, the trapezoidal numerical integration method is used for calculation. The initial value of the integral is set to zero. All sampling points in the interval [ton, toff] are traversed. For each time step, the average value of the power consumption at the current time and the power consumption at the previous time is taken, and then multiplied by a fixed sampling interval to obtain the integral increment of that time step. All integral increments are accumulated in sequence, and the final accumulated result is the energy loss value of the stable conduction stage.

[0100] Step S507: Calculate the theoretical energy loss value of the stable conduction stage based on the on-resistance and the average current value.

[0101] In this embodiment, the ripple coefficient of the drain current waveform within the conduction phase time interval [ton, toff] is first calculated (ripple coefficient = peak drain current during stable conduction phase / average current × 100%). If the ripple coefficient is less than or equal to 5%, it is determined that the current ripple is small. It can be assumed that the current is constant, and the theoretical energy loss value is obtained by multiplying the conduction resistance by the square of the average current value and then by the time length of the stable conduction phase. If the ripple coefficient is greater than 5%, it is determined that the current ripple is large. The effective value of the current is obtained by first calculating the root mean square of the drain current sampling value during this phase, and then by multiplying the conduction resistance by the square of the effective current value and combining it with the time length of the stable conduction phase.

[0102] Step S508: Compare the energy loss value with the theoretical energy loss value, and evaluate the on-resistance based on the comparison result.

[0103] In this embodiment, the actual energy loss value and the theoretical energy loss value during the stable conduction phase strictly correspond to the same stable conduction phase [ton, toff] in the same switching cycle. First, it is verified that the theoretical energy loss value is not zero and is within a reasonable range to avoid the comparison result from abnormal theoretical values. Then, the relative error between the energy loss value and the theoretical energy loss value is calculated. The relative error in percentage form is obtained by dividing the absolute difference between the actual energy loss value and the theoretical energy loss value by the theoretical energy loss value and then multiplying by 100%. This indicator can intuitively reflect the degree of deviation between the actual loss and the theoretical loss of the pure resistance model. Referring to the standard accuracy requirements for dynamic measurements of GaN devices, a preset relative error threshold of 5% is used (this can be flexibly adjusted according to the accuracy requirements of specific application scenarios; it can be reduced to 3% for high-precision scenarios and relaxed to 8% for general scenarios). If the calculated relative error is less than or equal to this threshold, it indicates that the initial voltage waveform compensation is effective, the average voltage and current values ​​during the stable conduction phase are accurately calculated, and the final measured on-resistance is highly reliable, truly reflecting the dynamic conduction characteristics of the device. If the relative error is greater than the preset threshold, the reliability of the on-resistance measurement result is deemed insufficient, and potential causes need to be analyzed, including the testing system. Insufficient calibration (e.g., probe delay offset, inaccurate parasitic parameter extraction), abnormal device status (e.g., severe trap effect, self-thermal runaway), improper current ripple handling (e.g., failure to use RMS values ​​to calculate theoretical losses when ripple is large), or identification deviation in the stable conduction phase, etc., necessitate pausing the measurement. The test system should be recalibrated for the possible causes, the device operating status checked, the ripple handling method optimized, or the conduction phase identification logic corrected. After troubleshooting, data acquisition and calculation should be performed again to ensure the rigor of the conduction resistance evaluation results. Finally, the calculated conduction resistance value is output as the measurement result. It should be noted that this comparison is an auxiliary consistency check; the final judgment should be based on a comprehensive assessment of factors such as the quality of the previous waveform, the completeness of data preprocessing, and the stability of the test conditions to avoid misjudgment due to a single error indicator.

[0104] It should be noted that the GaN device dynamic on-resistance measurement error suppression method provided by this invention systematically solves the measurement error problems caused by gate feedthrough, parasitic parameters of the test circuit, and nonlinear dynamic interference by combining hardware testing, theoretical modeling, and intelligent compensation. This method not only achieves a closed-loop process from waveform acquisition, error separation, preliminary compensation to intelligent secondary correction, but also introduces a result verification mechanism based on energy consistency. Therefore, it significantly improves the measurement accuracy and reliability of dynamic on-resistance without relying on complex external hardware, making it particularly suitable for the accurate characterization and performance evaluation of GaN devices in high-frequency and high-voltage applications.

[0105] like Figure 2As shown, in another aspect, the present invention also provides a GaN device dynamic on-resistance measurement error suppression system, comprising: a processor, an input device, an output device, and a memory, wherein the processor, the input device, the output device, and the memory are interconnected, wherein the memory is used to store a computer program, the computer program including program instructions, and the processor is configured to call the program instructions to execute the relevant steps of the relevant embodiments of the GaN device dynamic on-resistance measurement error suppression method of the present invention.

[0106] This invention provides a dynamic on-resistance measurement error suppression system for GaN devices. The functional components can be integrated into a single processing unit, or each component can exist independently, or two or more components can be integrated into one unit. The integrated components can be implemented in hardware or software.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A method for suppressing measurement errors in the dynamic on-resistance of GaN devices, characterized in that, The method includes: Based on a predetermined test circuit, the on-state voltage waveform, gate voltage waveform, and drain current waveform of the GaN device for one switching cycle are obtained. The theoretical error waveform of gate feedthrough and the theoretical error waveform of parasitic parameters are calculated based on the gate voltage waveform and the drain current waveform, respectively. A preliminary compensation waveform is obtained by subtracting the gate feedthrough theoretical error waveform and the parasitic parameter theoretical error waveform from the conduction voltage waveform; A voltage waveform hybrid compensation model is constructed, and the compensated voltage waveform is calculated using the voltage waveform hybrid compensation model based on the preliminary compensation waveform, the gate voltage waveform, the drain current waveform, and the conduction voltage waveform. The on-resistance is calculated based on the compensated voltage waveform and the drain current waveform.

2. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 1, characterized in that, The calculation of the gate feedthrough theoretical error waveform and the parasitic parameter theoretical error waveform based on the gate voltage waveform and the drain current waveform respectively includes: The gate voltage waveform and the drain current waveform are smoothed to obtain optimized gate voltage waveform and optimized drain current waveform, respectively. The optimized gate voltage waveform is used to calculate the theoretical gate feedthrough error waveform; The theoretical error waveform of parasitic parameters is calculated using the optimized drain current waveform.

3. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 2, characterized in that, The calculation of the gate feedthrough theoretical error waveform using the optimized gate voltage waveform includes: The optimized gate voltage waveform is numerically differentiated to obtain the gate voltage change rate waveform; The GaN device is set to the off state, and a ramp voltage with a predetermined rate of change is applied to the gate of the GaN device to obtain the waveform of the drain-source voltage change of the GaN device. Extract the amplitude of the change in the drain-source voltage waveform; The feedthrough coefficient is obtained by calculating the ratio of the magnitude of the change to the predetermined rate of change; The theoretical gate feedthrough error waveform is obtained by multiplying the feedthrough coefficient by the gate voltage change rate waveform.

4. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 2, characterized in that, The theoretical error waveform for calculating parasitic parameters using the optimized drain current waveform includes: Configure the test circuit to an unloaded state; Based on the no-load state, the parasitic inductance, parasitic capacitance, and parasitic resistance values ​​of the test circuit are obtained by performing resonance testing and DC short-circuit testing on the test circuit. Based on the optimized drain current waveform, the error component waveform is calculated using the parasitic inductance value, the parasitic capacitance value, and the parasitic resistance value; The parasitic parameter theoretical error waveform is obtained by superimposing the error component waveforms.

5. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 4, characterized in that, The error component waveform includes inductance error component waveform, resistance error component waveform, and capacitance error component waveform. The calculation of the error component waveform based on the optimized drain current waveform using the parasitic inductance value, the parasitic capacitance value, and the parasitic resistance value includes: The current change rate waveform is obtained by numerically differentiating the optimized drain current waveform. The optimized drain current waveform is numerically integrated to obtain the current integral waveform; The inductance error component waveform is obtained based on the current change rate waveform and the parasitic inductance value; The resistance error component waveform is obtained based on the optimized drain current waveform and the parasitic resistance value; The capacitance error component waveform is obtained based on the current integral waveform and the parasitic capacitance value.

6. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 1, characterized in that, The constructed voltage waveform hybrid compensation model includes: Training sample data was obtained by performing low-frequency quasi-static tests and high-frequency dynamic tests on GaN devices. A voltage waveform hybrid compensation model is obtained by training the training sample data using a neural network.

7. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 6, characterized in that, The voltage waveform hybrid compensation model trained using the training sample data based on a neural network includes: Use the mean squared error to set the loss function; Set constraints and add them to the loss function to obtain the optimized loss function; A voltage waveform hybrid compensation model is obtained by training the training sample data using a neural network with the goal of minimizing the optimized loss function.

8. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 1, characterized in that, The calculation of the on-resistance based on the compensated voltage waveform and the drain current waveform includes: The stable conduction phase is identified based on the drain current waveform. The average current during the stable conduction phase is calculated using the drain current waveform. The average voltage during the stable conduction phase is calculated using the compensated voltage waveform. The on-resistance is calculated based on the average current and the average voltage.

9. The method for suppressing measurement error of dynamic on-resistance of GaN device according to claim 8, characterized in that, The step of calculating the on-resistance based on the compensated voltage waveform and the drain current waveform further includes: Based on the compensated voltage waveform and the drain current waveform, the instantaneous power consumption waveform of the GaN device during the switching cycle is constructed. The instantaneous power consumption waveform is integrated during the stable conduction phase to obtain the energy loss value; Calculate the theoretical energy loss value during the stable conduction phase based on the on-resistance and the average current. The energy loss value is compared with the theoretical energy loss value, and the on-resistance is evaluated based on the comparison result.

10. A system for suppressing measurement errors in the dynamic on-resistance of GaN devices, characterized in that, include: The device includes a processor, an input device, an output device, and a memory, which are interconnected. The memory stores a computer program, which includes program instructions. The processor is configured to invoke the program instructions to execute a method for suppressing dynamic on-resistance measurement errors of a GaN device as described in any one of claims 1 to 9.

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