Data transmission devices, data transmission methods, and electronic devices

Abstract

This disclosure provides a data transmission apparatus, a data transmission method, and an electronic device. The data transmission apparatus includes a clock generation module, a phase selection module, and a data transmission module. The clock generation module is configured to sequentially generate N sampling result clock signals with uniformly distributed phases. The phase selection module is configured to determine a target sampling result clock signal based on the phase relationship between the N uniformly distributed sampling result clock signals and a second low-speed clock. The data transmission module is configured to sample source data based on the target sampling result clock signal to generate intermediate transmission data, and then sample the intermediate transmission data based on the second low-speed clock to obtain the target data. This data transmission apparatus enables efficient data transmission across clock domains, simplifies the data transmission path, has lower data transmission latency, significantly reduces chip area and power consumption, and improves data transmission reliability.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuits, and more specifically to a data transmission device, a data transmission method, and an electronic device. Background Technology

[0002] As the integration density of System-on-Chip (SoC) increases, the coexistence of multiple asynchronous clock domains leads to metastability risks in cross-clock domain (CDC) data transmission. For example, the asynchronous First-In-First-Out (FIFO) scheme uses dual-port random access memory (RAM), Gray code pointers, and synchronizers to achieve data buffering, but it still struggles to meet high real-time requirements, incurs high hardware resource and power consumption overhead, and suffers from clock phase alignment issues. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a data transmission device, comprising: a clock generation module, a phase selection module, and a data transmission module. The clock generation module is configured to sample a first low-speed clock based on a first high-speed clock, sequentially generating N sampled result clock signals with uniformly distributed phases. The phase selection module is configured to determine a target sampled result clock signal based on the phase relationship between the N uniformly distributed sampled result clock signals and a second low-speed clock, wherein the frequency of the first high-speed clock is higher than the frequencies of the first low-speed clock and the second low-speed clock, and N is an integer greater than 2. The data transmission module is configured to sample source data based on the target sampled result clock signal to generate intermediate transmission data, and sample the intermediate transmission data based on the second low-speed clock to obtain target data.

[0004] For example, in at least one embodiment of the data transmission apparatus provided in this disclosure, the clock generation module further includes: an N-stage flip-flop. The N-stage flip-flops are connected in series, the data input terminal of the first-stage flip-flop is configured to receive the first low-speed clock, the data input terminal of the i-th stage flip-flop is coupled to the output terminal of the (i-1)-th stage flip-flop, the clock input terminal corresponding to the N-stage flip-flop is configured to receive the first high-speed clock, and the N outputs of the N-stage flip-flops are respectively N sampling result clock signals, where i is an integer greater than 1 and less than or equal to N.

[0005] For example, in a data transmission apparatus provided in at least one embodiment of this disclosure, the first low-speed clock belongs to a first clock domain, the second low-speed clock belongs to a second clock domain, the source data is data in the first clock domain to be transmitted to the second clock domain, and the target data is data received in the second clock domain.

[0006] For example, in a data transmission apparatus provided in at least one embodiment of this disclosure, the phase selection module further includes: a multiplexing unit, a sampling unit, and a logic unit. The multiplexing unit is configured to sequentially select and output a selected phase clock from the N sampled result clock signals based on a selection control signal; the sampling unit is configured to sample the selected phase clock based on a second low-speed clock to generate a comparison sampling result; the logic unit is configured to detect the voltage transition state of the comparison sampling result, determine a target selection control signal based on the voltage transition state, and wherein the target selection control signal is used to control the multiplexing unit to determine the target sampled result clock signal.

[0007] For example, in a data transmission apparatus provided in at least one embodiment of this disclosure, the logic unit is further configured to traverse the selected phase clock and, in response to detecting a voltage transition time between 1 and 0 in the comparison sampling result, determine the target selection control signal from the N sampling result clock signals.

[0008] For example, in the data transmission apparatus provided in at least one embodiment of this disclosure, the multiplexing unit is a multiplexer, the N input terminals of the multiplexing unit respectively receive the N sampling result clock signals, the selection control terminal of the multiplexing unit is configured to receive the selection control signal and the target selection control signal, and the output terminal of the multiplexing unit is configured to output the target sampling result clock signal based on the target selection control signal.

[0009] In at least one embodiment of the data transmission apparatus provided in this disclosure, the data transmission module further includes: a pre-alignment unit and a synchronization unit. The pre-alignment unit is configured to sample the source data based on the target sampling result clock signal to generate the intermediate transmission data; the synchronization unit is configured to sample the intermediate transmission data based on the second low-speed clock to obtain the target data.

[0010] For example, in a data transmission apparatus provided in at least one embodiment of this disclosure, the clock input terminal of the pre-alignment unit is coupled to the multiplexing unit to receive the target sampling result clock signal.

[0011] For example, at least one embodiment of this disclosure provides a data transmission method, the data transmission method comprising: sampling a first low-speed clock based on a first high-speed clock to sequentially generate N sampling result clock signals with uniformly distributed phases; determining a target sampling result clock signal based on the phase relationship between the N uniformly distributed sampling result clock signals and a second low-speed clock, wherein the frequency of the first high-speed clock is higher than the frequency of the first low-speed clock and the frequency of the second low-speed clock, and N is an integer greater than 2; and sampling source data based on the target sampling result clock signal to generate intermediate transmission data, and sampling the intermediate transmission data based on the second low-speed clock to obtain target data.

[0012] At least one embodiment of this disclosure provides an electronic device, which includes a data transmission device provided in any embodiment of this disclosure.

[0013] At least one embodiment of this disclosure provides an electronic device, the electronic device including: at least one processor and at least one memory, wherein the at least one memory stores at least one computer program, and when the at least one computer program is executed by the at least one processor, it implements the data transmission method provided in any embodiment of this disclosure.

[0014] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium for storing computer-readable instructions non-transitory. When the computer-readable instructions are executed by a computer, the data transmission method provided in any embodiment of this disclosure is implemented.

[0015] In at least one embodiment of this disclosure, efficient data transfer across clock domains can be achieved, simplifying the data transmission path, resulting in lower data transmission latency, significantly reducing chip area and power consumption, and improving data transmission reliability. For example, at least one embodiment of this disclosure can be applied to high-speed intra-chip interface communication scenarios that are latency-sensitive and require maintaining the phase relationship between data and clock, providing an efficient, simple, and reliable cross-clock domain data transmission solution for the design of high-performance heterogeneous integrated chips. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0017] Figure 1 A schematic block diagram of a data transmission device is shown.

[0018] Figure 2A schematic block diagram of a data transmission apparatus provided in at least one embodiment of the present disclosure is shown.

[0019] Figure 3 A schematic block diagram of another data transmission apparatus provided in at least one embodiment of the present disclosure is shown.

[0020] Figure 4 A data transmission timing diagram is shown, which is provided by at least one embodiment of the present disclosure.

[0021] Figure 5 A schematic diagram of another data transmission timing provided by at least one embodiment of the present disclosure is shown.

[0022] Figure 6 A schematic flowchart of a data transmission method provided in at least one embodiment of the present disclosure is shown.

[0023] Figure 7 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0024] Figure 8 A schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure is shown.

[0025] Figure 9 A schematic block diagram of a non-transitory computer-readable storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0027] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0028] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0029] With the continuous advancement of semiconductor technology and the increasing integration of systems, System-on-Chip (SoC) has become the core of modern electronic devices. SoC integrates multiple processing modules with different functions and operating frequencies, such as a Central Processing Unit (CPU), Graphics Processing Unit (GPU), General-Purpose Graphics Processing Unit (GPGPU), Artificial Intelligence (AI) accelerator, various high-speed interface controllers, various signal processors, and memory controllers. To achieve a balance between performance, power consumption, and chip area, these modules with different functions can be designed to operate at their own independent clock frequencies, thus forming a heterogeneous architecture with multiple asynchronous clock domains coexisting within the chip. Therefore, achieving reliable and efficient data transmission between different clock domains—i.e., Clock Domain Crossing (CDC) design—has become a critical technical problem that needs to be solved in chip design.

[0030] For example, cross-clock domain data transmission suffers from metastability. Metastability refers to the situation where, when the data signal changes near the effective clock edge of a flip-flop in the target clock domain, violating the required setup time and hold time of the flip-flop, the flip-flop's output may remain at a non-zero, non-one intermediate level or oscillate for a considerable period. This can lead to unpredictable functional errors or data loss, severely impacting the system's reliability.

[0031] To address the above issues, a solution based on an asynchronous first-in-first-out (FIFO) queue could be employed, for example.

[0032] Figure 1 A schematic block diagram of a data transmission device is shown.

[0033] This data transmission device is used, for example, to transmit data between different clock domains within a chip. Figure 1 As shown, the data transmission device includes an asynchronous FIFO module, a write control terminal, a read control terminal, and two clock synchronization modules.

[0034] The write control terminal can be configured to receive write data, a write enable signal, and a write clock, used to control data writing operations in the write clock domain (first clock domain); the read control terminal can be configured to receive a read enable signal and a read clock, used to perform data reading in the read clock domain (second clock domain). The FIFO storage unit can act as a data buffer, connecting the write control terminal and the read control terminal to achieve temporary data storage across clock domains. To ensure secure transmission of control signals between clock domains of different frequencies or phases, the data transmission device also includes a "clock synchronization" module on both the write control terminal and the read control terminal, used for multi-level synchronization processing of status signals such as full and empty.

[0035] The write and read pointers are incremented in the write clock domain and read clock domain respectively, and immediately converted to Gray code. Gray code, due to its characteristic that only one bit changes between adjacent codewords, is used for pointer synchronization across clock domains. For example, after synchronization through two or more stages of flip-flops, the pointer is passed to the other clock domain to generate a flag indicating whether the FIFO is empty or full. Through this combination of "buffered isolation" and "Gray code pointer synchronization," the asynchronous FIFO can control the probability of metastability, ensuring the correct sequential transmission of data between asynchronous clock domains.

[0036] However, the inventors of this disclosure note that the above-described asynchronous FIFO queue solution still has at least one of the following technical problems.

[0037] For example, asynchronous FIFO queue solutions inherently have significant latency. From the time data is written to when it becomes readable, it needs to go through a series of serial processes, such as write pointer updates, Gray code conversion, pointer cross-domain synchronization (requiring more than two clock cycles to reduce the risk of metastability propagation), and empty / full flag checks. This results in a significant increase in latency in the data transmission path, making it difficult to meet the needs of applications with extremely high real-time requirements.

[0038] For example, asynchronous FIFO queue solutions have higher hardware resource and power consumption overhead. These solutions include dual-port memory and relatively complex read / write pointer management, Gray code conversion, and synchronization logic, increasing chip area and dynamic power consumption, resulting in higher costs for area- and power-sensitive designs.

[0039] For example, asynchronous FIFO queue solutions cannot address clock phase alignment requirements. While asynchronous FIFOs are designed for secure data buffering and sequential delivery, the relative phase relationship between the data signal and the receiver's clock signal can still lead to clock phase alignment errors. However, in many high-speed interface standards (such as source-synchronous interfaces), the receiver needs a clock with a defined phase relationship to the data edges to accurately sample the data. The pure buffering mechanism of asynchronous FIFOs cannot actively establish or maintain this precise clock phase alignment.

[0040] Therefore, there is an urgent need for a cross-clock domain data transmission scheme that can overcome at least some of the above-mentioned technical problems. For example, a reliable data transmission scheme that can achieve lower latency, lower hardware overhead, and take into account clock phase relationships between clock domains with the same frequency or a fixed frequency ratio.

[0041] To address at least one of the aforementioned problems, at least one embodiment of this disclosure provides a data transmission apparatus, a data transmission method, an electronic device, and a storage medium. The data transmission apparatus includes a clock generation module, a phase selection module, and a data transmission module. The clock generation module is configured to sample a first low-speed clock based on a first high-speed clock, sequentially generating N sampled result clock signals with uniformly distributed phases. The phase selection module is configured to determine a target sampled result clock signal based on the phase relationship between the N uniformly distributed sampled result clock signals and a second low-speed clock, wherein the frequency of the first high-speed clock is higher than the frequency of the first low-speed clock and the frequency of the second low-speed clock, and N is an integer greater than 2. The data transmission module is configured to sample source data based on the target sampled result clock signal to generate intermediate transmission data, and sample the intermediate transmission data based on the second low-speed clock to obtain the target data. This data transmission apparatus can achieve efficient data transmission across clock domains, simplify the data transmission path, has lower (even extremely low) data transmission latency, significantly reduces chip area and power consumption, and improves the reliability of data transmission.

[0042] Figure 2 A schematic block diagram of a data transmission apparatus provided in at least one embodiment of the present disclosure is shown.

[0043] like Figure 2 As shown, the data transmission device 2000 includes a clock generation module 210, a phase selection module 220, and a data transmission module 230.

[0044] The clock generation module 210 is configured to sample the first low-speed clock (Block 0 Low speed clk) based on the first high-speed clock (Block 0 High speed clk) and sequentially generate N sampled clock signals with uniform phase distribution.

[0045] The phase selection module 220 is configured to determine the target sampling result clock signal based on the phase relationship between the N sampling result clock signals with uniformly distributed phases and the second low-speed clock (Block 1 Low speed clk).

[0046] The data transmission module 230 is configured to sample the source data (Block 0 data) based on the target sampling result clock signal (Block 0 Low speed clk select output) to generate intermediate transmission data (Sampleddata), and sample the intermediate transmission data based on the second low speed clock to obtain the target data (Block 1 data).

[0047] For example, the frequency of the first high-speed clock is higher than the frequency of the first low-speed clock, and N is an integer greater than 2.

[0048] For example, the input of the clock generation module 210 can be configured to receive a first high-speed clock and a first low-speed clock.

[0049] For example, the clock generation module 210 can be configured to perform multi-level delay sampling of the low-frequency clock using a high-frequency clock.

[0050] For example, the frequency of the first high-speed clock (f_high) can be N times the frequency of the first low-speed clock (f_low), that is, f_high = N * f_low.

[0051] For example, the clock generation module 210 can be configured to periodically sample and delay a first low-speed clock based on a first high-speed clock, thereby sequentially generating N sampled clock signals. For example, these sampled clock signals originate from the sampled values ​​of the same original low-speed clock signal at different times, so the phase delay between adjacent signals is fixed and uniform.

[0052] For example, the N sampled clock signals include the original first low-speed clock itself without delay, and the N sampled clock signals with sequentially delayed phases generated by sampling and delaying the original clock.

[0053] For example, the phase difference between adjacent signals in the N sampled clock signals is uniform, and the value of the phase difference is equal to one first high-speed clock cycle (1 / F_high).

[0054] For example, the clock generation module 210 can shift and sample a low-speed clock under the drive of a high-speed clock by using cascaded storage units (e.g., flip-flops).

[0055] For example, the value of N can be flexibly selected according to the design requirements for phase resolution and hardware cost, such as 4, 8, 16, etc. The embodiments of this disclosure do not limit the specific value of N. For example, the larger the value of N, the higher the phase resolution and the higher the accuracy of finding the alignment point, but the time required for traversal search also increases accordingly.

[0056] For example, the phase selection module 220 can be configured to receive N sampled clock signals (e.g., clk_ph1~clk_phN) from the clock generation module 210 and a second low-speed clock from the target clock domain (e.g., the second clock domain Block 1 Domain).

[0057] For example, the second low-speed clock has the same frequency as the first low-speed clock.

[0058] For example, the phase selection module 220 can be configured to sequentially evaluate the timing (phase) relationship between each of the N sampled clock signals and the second low-speed clock.

[0059] For example, the phase selection module 220 can be configured to detect the logic level state of each sampled clock signal at the effective edge (e.g., rising edge) of the second low-speed clock. By traversing N sampled clock signals, the relative position of the effective edge of the second low-speed clock within the entire first low-speed clock cycle can be completely mapped. Based on this phase relationship mapping, a sampled clock signal is determined and locked as the output; this selected sampled clock signal is the target sampled clock signal.

[0060] For example, the phase selection module 220 can be configured to sequentially compare N sampled result clock signals with a second low-speed clock. Specifically, by sampling each phase clock at the effective edge of the second low-speed clock and comparing the logic level changes of adjacent phase clock sampling results (e.g., sample_result_ph[k] and sample_result_ph[k+1]), it determines between which two adjacent phase clock edges the effective edge of the second low-speed clock lies. Based on this, it identifies the specific sampled result clock signal from the N candidate phases that has the closest alignment (i.e., the closest in time) to the rising edge of the second low-speed clock and selects it as the target sampled result clock signal for subsequent data transmission. k is an integer greater than 1 and less than or equal to N.

[0061] For example, the data transmission module 230 can be configured to transmit data from the source clock domain (e.g., the first clock domain Block 0 Domain) to the target clock domain (e.g., the second clock domain Block 1 Domain) based on a clock signal with a determined phase relationship (i.e., the target sampling result clock signal).

[0062] For example, the data transmission module 230 can be configured to receive source data (Block 0 data, for example, belonging to the first clock domain), the target sampling result clock signal, and the second low-speed clock (Block 1 Low speed clock, for example, belonging to the second clock domain).

[0063] For example, the data transmission module 230 can be configured to sample the input source data using the target sampling result clock signal and generate intermediate transmitted data (Sampled data). Since the rising edge of the target sampling result clock signal has been determined to be aligned or approximately aligned with the rising edge of the second low-speed clock, the intermediate transmitted data (Sampled data) satisfies the setup and hold time requirements before the effective edge of the second low-speed clock arrives. Subsequently, the data transmission module 230 samples the intermediate transmitted data using the second low-speed clock and outputs the target data (Block 1 data), thereby completing the cross-clock domain data transmission.

[0064] In at least one embodiment of this disclosure, the clock generation module 210, phase selection module 220, and data transmission module 230 are coupled through signal lines and work together, thereby achieving efficient data transmission across clock domains, simplifying the data transmission path, resulting in lower data transmission latency, significantly reducing chip area and power consumption, and improving data transmission reliability. At least one embodiment of this disclosure can be applied to high-speed intra-chip interface communication scenarios that are latency-sensitive and require maintaining the phase relationship between data and clock, providing an efficient, simple, and reliable cross-clock domain data transmission solution for the design of high-performance heterogeneous integrated chips.

[0065] Figure 3 A schematic block diagram of another data transmission apparatus provided in at least one embodiment of the present disclosure is shown.

[0066] In some embodiments of this disclosure, the clock generation module 210 further includes an N-stage flip-flop.

[0067] like Figure 3 As shown, N flip-flops are connected in series. The data input of the first-stage flip-flop (DFF1) is configured to receive a first low-speed clock. The data input of the i-th stage flip-flop (DFFi) is coupled to the output of the (i-1)-th stage flip-flop (DFFi-1). Therefore, the data input of the i-th stage flip-flop (DFFi) is the output of the (i-1)-th stage flip-flop (DFFi-1). The clock input of the N-stage flip-flops is configured to receive a first high-speed clock. Thus, the N outputs of the N-stage flip-flops are N sampling result clock signals, where i is an integer greater than 1 and less than or equal to N.

[0068] For example, the trigger may include an edge-triggered D-type trigger (D Flip-Flop), a trigger with an asynchronous reset terminal, or a trigger with a scan input terminal, etc., and the embodiments disclosed herein are not limited thereto.

[0069] For example, N-level flip-flops (e.g., level 1 flip-flop DFF1, level 2 flip-flop DFF2, ..., level N flip-flop DFFN) can be connected in series.

[0070] For example, the data input D terminal of the i-th stage flip-flop DFFi can be connected to the data output Q terminal of its preceding stage flip-flop DFFi-1, where i is an integer greater than 1 and less than or equal to N.

[0071] For example, the data input D terminal of the first stage flip-flop DFF1 can be configured to receive the first low-speed clock (Block 0 Low speed clk).

[0072] For example, all N-stage flip-flops can be configured to share the same clock signal. The clock input (CLK) of each stage flip-flop can be configured to receive a first high-speed clock (Block 0 High speed clk), allowing all flip-flops to operate synchronously at the same high-frequency beat.

[0073] For example, the data output Q of each stage of the flip-flop is the output point of a sampled result clock signal. For example, the Q of the first stage flip-flop DFF1 outputs the first sampled result clock signal (e.g., denoted as clk_ph1), the Q of the second stage flip-flop DFF2 outputs the second sampled result clock signal (e.g., denoted as clk_ph2), and so on, with the Q of the Nth stage flip-flop DFFN outputting the Nth sampled result clock signal (e.g., denoted as clk_phN), which is the N sampled result clock signals after delay among the N sampled result clock signals.

[0074] For example, at the rising edge (or effective activation edge) of each first high-speed clock, each flip-flop can sample the data at its D input and, after a brief clock-to-output delay (CLK-to-Q delay), present the data at its Q output, maintaining it for one high-speed clock cycle. Due to the cascaded structure, the original first low-speed clock signal is sampled at the D input of DFF1 by the first high-speed clock. The sampled value (i.e., clk_ph1) is then sampled again as the input of DFF2 in the next high-speed clock cycle, generating clk_ph2. This process is repeated sequentially.

[0075] For example, since each stage of the flip-flop sampling occurs at a new edge of the first high-speed clock, and each stage of the flip-flop has similar delay characteristics, the delay of clk_ph1 relative to the original first low-speed clock is approximately one high-speed clock cycle (T_high = 1 / F_high), clk_ph2 is delayed by approximately one T_high relative to clk_ph1, and so on. Therefore, the phase difference between the N output signals clk_ph1 to clk_phN is basically uniform and is approximately one T_high. Thus, the edges of signals clk_ph1 to clk_phN are arranged sequentially at equal intervals on the time axis, and the phase uniformly covers a complete low-speed clock cycle.

[0076] In at least one embodiment of this disclosure, a highly efficient and reliable multiphase clock generation scheme is provided by employing a circuit structure including N-stage series D flip-flops. The generated phase relationship is highly deterministic and predictable, and its accuracy is directly determined by the frequency stability of the high-speed clock and the clock offset control capability between the flip-flops. Furthermore, this structural design is easy to integrate into various digital chips, which can significantly reduce the complexity and risk of the overall system design.

[0077] In some embodiments of this disclosure, a first low-speed clock belongs to a first clock domain, a second low-speed clock belongs to a second clock domain, source data is data in the first clock domain to be transmitted to the second clock domain, and target data is data received in the second clock domain.

[0078] For example, the first clock domain (Block 0 Domain) may include a separate and complete synchronous sequential logic subsystem.

[0079] For example, all sequential logic units (such as registers and state machines) within the first clock domain can be synchronously driven by the same set of clock signals with a fixed phase relationship.

[0080] For example, in some embodiments of this disclosure, the first low-speed clock (Block 0 Low speed clk) can be a clock signal of the first clock domain, and the first low-speed clock can be used to define the basic clock cycle for data transmission and processing within the first clock domain.

[0081] For example, the second clock domain (Block 1 Domain) may include another independent and complete synchronous timing logic subsystem, which may be physically located on the same chip as the first clock domain, but asynchronous in timing.

[0082] For example, the timing within the second clock domain can be synchronously driven by the second low-speed clock (Block 1 Low speed clk).

[0083] For example, in some embodiments of this disclosure, there is no common, phase-defined root clock source between the first clock domain and the second clock domain. Therefore, the relative relationship between their clock edges on the time axis is not fixed and unpredictable, which is one of the reasons for cross-clock domain timing problems.

[0084] For example, in some embodiments of this disclosure, the nominal frequencies of the first low-speed clock and the second low-speed clock can be equal (i.e., the same frequency), and the consistency of the frequencies can provide a physical basis for achieving stable transmission through phase scanning and alignment.

[0085] For example, the data signal corresponding to the source data (Block 0 data) can be generated or processed by logic or functional circuits within the first clock domain, and its validity is determined by the timing rules within that first clock domain (relative to a first low-speed clock or its derived clocks). For example, the source data can be an information carrier that needs to be securely and reliably transmitted to the second clock domain.

[0086] For example, the data signal corresponding to the target data (Block 1 data) may include data that is ultimately received and used by the logic circuit or functional circuit in the second clock domain.

[0087] In at least one embodiment of this disclosure, by determining the attribution relationship between a first clock domain, a second clock domain, source data, and target data, a point-to-point data channel with lower latency, higher reliability, and lower overhead can be provided between two independent digital system modules operating at the same frequency but with uncertain phases, without introducing large-scale buffering or relying on complex synchronization protocols. At least one embodiment of this disclosure can be applied to inter-module communication within a chip that is extremely sensitive to transmission latency and requires matching clock frequencies, such as the exchange of control signals and data between a processor core and a coprocessor, or between functional units under different power management domains.

[0088] In some embodiments of this disclosure, the phase selection module 220 may further include a multiplexing unit 221, a sampling unit 222, and a logic unit 223.

[0089] The multiplexing unit 221 can be configured to select a selected phase clock from N sampled clock signals in sequence based on a selection control signal.

[0090] The sampling unit 222 can be configured to sample a selected phase clock based on a second low-speed clock to generate a comparison result.

[0091] Logic unit 223 can be configured to detect voltage transition states of the comparison sampling results and determine the target selection control signal based on the voltage transition states.

[0092] For example, the target selection control signal can be used to control the multiplexing unit 221 (MUX) to determine the target sampling result clock signal.

[0093] For example, the multiplexing unit 221 can be implemented as an N-to-1 multiplexer (MUX) to select one of multiple input signals and route it to a single output.

[0094] For example, the multiplexing unit 221 may include N data input terminals, one data output terminal, and one selection control terminal.

[0095] For example, the multiplexing unit 221 includes N data input terminals that can respectively receive N sampling result clock signals (clk_ph1 to clk_phN) from the clock generation module 210.

[0096] For example, the selection control terminal included in the multiplexing unit 221 can receive a selection control signal from the logic unit 223.

[0097] For example, the data output terminal of the multiplexing unit 221 can provide a selected phase clock, which can be provided to the sampling unit 222.

[0098] For example, the value of the select control signal can be used to determine which input clock signal to connect to the output. For example, during phase alignment, logic unit 223 causes the value of the select control signal to change periodically, thereby driving multiplexing unit 221 to sequentially traverse all its inputs, so that each of clk_ph1 to clk_phN can be output as the selected phase clock for subsequent comparison.

[0099] For example, sampling unit 222 (DFF_A) may include a synchronous sampler.

[0100] For example, sampling unit 222 can be implemented by an edge-triggered flip-flop.

[0101] For example, the data input terminal (D) of the sampling unit 222 can be connected to the output terminal of the multiplexing unit 221 to receive the selected phase clock.

[0102] For example, the clock input (CLK) of the sampling unit 222 can be configured to receive a second low-speed clock from the second clock domain.

[0103] For example, the data output terminal of sampling unit 222 can be configured to provide a comparison sampling result signal, which is sent to logic unit 223.

[0104] For example, at each effective edge (e.g., rising edge) of the second low-speed clock, sampling unit 222 can be configured to sample the level of the selected phase clock at the current moment. Since the two clock frequencies are the same, if the edge of the selected phase clock is not very close to the sampling edge, the output will be a stable logic "1" or "0". This comparison sampling result can intuitively reflect the logic state of the currently selected source clock domain phase clock within the target clock domain. For example, when traversing all phases, the changing sequence of this comparison sampling result encodes the relative position information between the two clock edges.

[0105] For example, logic unit 223 may include a digital controller and decision unit.

[0106] For example, logic unit 223 may be implemented by a combination of finite state machines, counters and comparison logic, etc., and the embodiments of this disclosure are not limited thereto.

[0107] For example, the input of logic unit 223 can be configured to monitor the comparison sampling result output by sampling unit 222.

[0108] For example, the output of logic unit 223 can be configured to generate and output a selection control signal. For example, after making a decision, logic unit 223 can also be configured to output (or internally latch) the final target selection control signal.

[0109] For example, during phase alignment, logic unit 223 can be configured to control the selection control signal to increment sequentially, driving multiplexer unit 221 to traverse all its inputs, thereby sequentially outputting each phase clock to sampling unit 222. For example, logic unit 223 can be configured to read the comparison sampling result output by sampling unit 222 at each effective edge of the second low-speed clock and compare it with the comparison sampling result (or recorded state) corresponding to the previous phase. During the traversal, because the phases of each phase clock are sequentially delayed, the logic value of the comparison sampling result will change depending on the selected phase.

[0110] Specifically, when logic unit 223 controls multiplexing unit 221 to select phases sequentially, sampling unit 222 samples them on the effective edge of the second low-speed clock. Logic unit 223 detects changes in logic values ​​by comparing the sampling results of adjacent numbers (such as k and k+1). For example, when it is found that the sampling result corresponding to phase k is logic "1", while the sampling result corresponding to phase k+1 becomes logic "0", it can be determined that the rising edge of the second low-speed clock is located between the clock edges of phase k and phase k+1. This change from "1" to "0" in adjacent sampling results identifies the phase boundary.

[0111] For example, once a change in logic value between adjacent sampling results that meet the above conditions is detected, logic unit 223 can latch the current (or changed) selection control signal value and determine it as the target selection control signal. Subsequently, logic unit 223 can fix the output to the target selection control signal and control multiplexing unit 221 to stop scanning and stably output the corresponding target sampling result clock signal.

[0112] In at least one embodiment of this disclosure, the abstract “phase relationship determination” can be transformed into an executable digital logic operation, which greatly improves the reliability and ease of use of the cross-clock domain interface while maintaining low latency and low power consumption.

[0113] In some embodiments of this disclosure, logic unit 223 may be further configured to traverse selected phase clocks and, in response to detecting a voltage transition time between "1" and "0" in the comparison sampling result, determine a target selection control signal from N sampling result clock signals.

[0114] For example, logic unit 223 can be configured to generate a series of ordered selection control signal values, enabling multiplexing unit 221 to sequentially and non-repeatingly select each clock signal from clk_ph1 to clk_phN as the selected phase clock output.

[0115] For example, logic unit 223 can be implemented using an internal counter or state machine, whereby the selection control signal increments once every one or more second low-speed clock cycles until all N options are covered.

[0116] For example, the "voltage transition time" here refers to the comparison sampling results obtained by logic unit 223 in the process of sequentially traversing each phase clock, comparing two adjacent samples (corresponding to phase k and phase k+1) at the effective edge of the second low-speed clock. When it is detected that the comparison sampling result corresponding to phase k is logic "1" and the comparison sampling result corresponding to phase k+1 becomes logic "0", it is determined that a voltage transition from "1" to "0" has occurred.

[0117] For example, when the effective high-level interval of the selected phase clock output by the multiplexing unit 221 covers the sampling time of the second low-speed clock, the comparison sampling result is a stable "1". Conversely, when the low-level interval of the selected phase clock covers the sampling time, the result is "0". During the traversal, when the above-mentioned adjacent phase sampling result is detected to jump from "1" to "0", it can be indicated that the sampling point (e.g., rising edge) of the second low-speed clock is exactly located between the edges of these two adjacent phase clocks. Therefore, the phase switching point corresponding to this jump (i.e., from phase k to phase k+1) directly indicates that the rising edge of the second low-speed clock is located on the time axis between the edges of two adjacent sampling result clock signals (e.g., clk_ph[k] and clk_ph[k+1]) with a phase difference of one high-speed clock cycle, where k is an integer greater than 1 and less than or equal to N.

[0118] For example, to maximize the setup time margin for subsequent data sampling, the phase clock corresponding to the transition (e.g., clk_ph[k+1]) can be selected as the target phase clock. Therefore, after detecting a falling edge transition, logic unit 223 can determine the selection control signal corresponding to clk_ph[k+1] (i.e., the next value of the current selection control signal, or the current value latched after detection, depending on the specific design, which is not limited in the embodiments of this disclosure) as the target selection control signal.

[0119] In at least one embodiment of this disclosure, by detecting the voltage transition between adjacent phase sampling results during phase traversal, the subtle relative positional relationship between two asynchronous clock edges can be automatically and accurately located, phase alignment can be transformed into practically integrable hardware logic, and high-performance cross-clock domain data transmission can be achieved.

[0120] In some embodiments of this disclosure, the multiplexing unit 221 may include a multiplexer. The N inputs of the multiplexing unit 221 respectively receive N sampling result clock signals. The selection control terminal of the multiplexing unit 221 can be configured to receive a selection control signal and a target selection control signal. The output of the multiplexing unit 221 can be configured to output a target sampling result clock signal based on the target selection control signal.

[0121] For example, the multiplexing unit 221 can be implemented as an N-to-1 multiplexer and can be configured to physically select from a number of candidate clock signals.

[0122] For example, the data input terminals of the multiplexing unit 221 may include N data input channels. For example, these N input terminals may respectively receive N sampled clock signals (e.g., clk_ph1 to clk_phN) from the clock generation module 210.

[0123] For example, the selection control terminal of the multiplexing unit 221 can be configured to receive a selection control signal. For example, the value of this selection control signal can change sequentially, such that the multiplexing unit 221 selects and outputs only one of the N sampled clock signals at any given time. For example, clk_ph1 can be selected for evaluation first, then clk_ph2, then clk_ph3, and so on, until the evaluation of all phases is completed.

[0124] For example, the bit width of the selection control signal can be at least ceil(log2(N)) to encode the selection of any one of the N inputs.

[0125] For example, the data output of the multiplexing unit 221 can be configured to provide a selected phase clock signal, which can logically be equal to the clock signal of the input specified by the selected control signal encoding.

[0126] For example, the selection control signal generated by logic unit 223 can change dynamically in a predetermined order (e.g., incrementing from 0 to N). For example, multiplexing unit 221 can receive the selection control signal and switch its output sequentially to each of clk_ph1 to clk_phN, thereby presenting each candidate phase clock to the subsequent sampling unit 222 for comparison.

[0127] For example, after logic unit 223 completes the comparison and determines the corresponding phase, logic unit 223 can generate a fixed target selection control signal. At this time, the selection control signal can be updated or directly replaced with the target value. For example, after receiving this signal, the output of multiplexer unit 221 is fixedly connected to the specific input clock specified by the target selection control signal.

[0128] For example, the output of the multiplexing unit 221 can then be the target sampling result clock signal, which will remain stable unless the system is reset or the alignment process is retried.

[0129] In at least one embodiment of this disclosure, a multiplexer is used as a specific implementation of the multiplexing unit, providing an efficient, reliable and low-latency hardware path for phase selection.

[0130] In some embodiments of this disclosure, the data transmission module 230 further includes a pre-alignment unit 231 (DFF_B) and a synchronization unit 232 (DFF_C).

[0131] The pre-alignment unit 231 (DFF_B) can be configured to sample the source data based on the target sampling result clock signal and generate intermediate transmission data (Sampled data) from the sampling result.

[0132] Synchronization unit 232 (DFF_C) can be configured to sample intermediate transmission data based on a second low-speed clock to obtain target data.

[0133] In some embodiments of this disclosure, the clock input of the pre-alignment unit 231 is coupled to the multiplexing unit 221 to receive the target sampling result clock signal.

[0134] For example, the clock input of the pre-alignment unit 231 can be connected to the output of the multiplexing unit 221, so that the target sampling result clock signal output by the phase selection module 220 can directly drive the clock input of the pre-alignment unit 231.

[0135] For example, the output of the multiplexing unit 221 can be directly connected to the clock input of the pre-alignment unit 231 via dedicated metal wiring, and the embodiments of this disclosure do not limit this.

[0136] For example, the pre-alignment unit 231 can be configured to sample raw data from the first clock domain based on the target sampling result clock signal determined and output by the phase selection module 220.

[0137] For example, the data input of the pre-alignment unit 231 can be configured to receive source data (Block 0 data) from the first clock domain. For example, the clock input (CLK) of the pre-alignment unit 231 can be configured to receive the target sampling result clock signal (Block 0 low speed clk select output) from the phase selection module 220. For example, the data output (Q) of the pre-alignment unit 231 can be configured to provide intermediate transmission data (Sampled data).

[0138] For example, at each valid edge (such as the rising edge) of the target sampling result clock signal, the pre-alignment unit 231 samples the source data at its data input. The transition moments of the intermediate transmission data generated thereby can be aligned with the edge of the aforementioned selected clock, thereby establishing and maintaining a stable time close to a complete low-speed clock cycle in advance relative to the sampling point of the subsequent second low-speed clock.

[0139] For example, synchronization unit 232 (DFF_C) can be configured to formally synchronize pre-aligned data to the timing specification of the second clock domain.

[0140] For example, the data input terminal (D) of the synchronization unit 232 can be configured to be connected to the output terminal of the pre-alignment unit 231 to receive intermediate transmission data.

[0141] For example, the clock input (CLK) of the synchronization unit 232 can be configured to receive a second low-speed clock (Block 1 low speed clk) from the second clock domain.

[0142] For example, the data output terminal (Q) of the synchronization unit 232 can be configured to output target data (Block 1 data).

[0143] For example, this target data can be directly used by any logic circuit within the second clock domain.

[0144] In at least one embodiment of this disclosure, a simple, efficient and extremely reliable physical implementation path for cross-clock domain data transmission is provided through pre-alignment units and synchronization units.

[0145] Figure 4 A data transmission timing diagram is shown, which is provided by at least one embodiment of the present disclosure.

[0146] like Figure 4 The diagram illustrates an embodiment of determining the phase clock closest to the rising edge of a target clock using multi-phase sampling. In this embodiment, the source clock domain samples the original low-speed clock using a high-speed clock with a frequency N times that of the low-speed clock (e.g., N=8), generating eight clock signals with uniformly distributed phases (e.g., Clk_ph1 to Clk_ph8), which are separated by a fixed phase angle. The target clock domain samples each of these eight phase clocks using a second low-speed clock, obtaining the corresponding sampling results (Sample_result_ph1 to Sample_result_ph8).

[0147] like Figure 4 As shown, at the sampling time of the rising edge of the second low-speed clock, the sampling results of different phase clocks constitute a set of logic values. By comparing the sampling results of adjacent phases, the changes in logic values ​​can be observed. For example, Sample_result_ph2 is low (0), while Sample_result_ph3 becomes high (1), which marks a boundary from low to high; Sample_result_ph6 is high (1), while Sample_result_ph7 becomes low (0), which marks a boundary from high to low. By identifying the change point between these two adjacent sampling results, the position interval of the rising edge of the second low-speed clock in the phase sequence can be accurately located, thereby determining the phase clock closest to it (e.g., selecting the phase clock after the change point to obtain the maximum setup time margin). This can improve data transmission efficiency and significantly reduce latency, making it suitable for complex communication scenarios in high-performance chip design.

[0148] Figure 5 A schematic diagram of another data transmission timing provided by at least one embodiment of the present disclosure is shown.

[0149] like Figure 5 As shown, the source data (e.g., including D0, D1, D2, etc.) is driven by a first low-speed clock, which is effectively sampled and updated on its rising edge. Simultaneously, a first high-speed clock, serving as an auxiliary clock with a frequency N times that of the first low-speed clock (e.g., N=8), is used to accurately sample the first low-speed clock, thereby generating eight uniformly distributed phase clock signals (e.g., Clk_ph1 to Clk_ph8). These phase clocks have a fixed phase difference from each other, covering the entire first low-speed clock cycle, forming a phase sampling set.

[0150] Then, the eight phase clocks can be sampled based on the second low-speed clock (e.g., the clock in the target clock domain) to obtain the corresponding sampling results. By analyzing the changes in these sampling results, it is possible to detect which phase clock is closest to the rising edge of the second low-speed clock.

[0151] For example, such as Figure 5 As shown, when the rising edge of the second low-speed clock arrives, comparing the sampling results of adjacent phases reveals that the sampling result of Clk_ph6 is 1, while the sampling result of Clk_ph7 is 0. Based on this change from "1" to "0", Clk_ph7 can be selected as the closest synchronization phase.

[0152] Subsequently, the source data can be presampled using the selected closest phase clock (e.g., Clk_ph7) to generate "intermediate transmission data." This intermediate data is sampled and synchronized within the source clock domain using the closest phase clock, and its timing is highly aligned with the rising edge of the target clock domain. Finally, the target clock domain uses a second low-speed clock to perform final sampling of the intermediate transmission data, obtaining the "target data," thus completing the cross-clock domain data transmission.

[0153] In at least one embodiment of this disclosure, not only is precise data alignment achieved, but transmission latency is also significantly reduced, improving the overall performance and stability of the system, making it applicable to complex communication scenarios in high-performance chip design.

[0154] Figure 6 A schematic flowchart of a data transmission method provided in at least one embodiment of the present disclosure is shown.

[0155] like Figure 6 As shown, the data transmission method includes steps S400-S420. This data transmission method can be applied, for example, to the data transmission apparatus provided in any embodiment of this disclosure.

[0156] Step S400: Sample the first low-speed clock based on the first high-speed clock, and sequentially generate N sampling result clock signals with uniform phase distribution.

[0157] Step S410: Determine the target sampling result clock signal based on the phase relationship between the N uniformly distributed sampling result clock signals and the second low-speed clock.

[0158] For example, the frequency of the first high-speed clock is higher than the frequency of the first low-speed clock and the frequency of the second low-speed clock, where N is an integer greater than 2.

[0159] Step S420: Based on the target sampling result clock signal, sample the source data to generate intermediate transmission data, and sample the intermediate transmission data based on the second low-speed clock to obtain the target data.

[0160] In some embodiments of this disclosure, for example, step S400 may further include steps S401-S402.

[0161] Step S401: Receive the first low-speed clock through the data input terminal of the first stage flip-flop.

[0162] Step S402: Receive the first high-speed clock through the clock input terminal corresponding to the N-level flip-flop.

[0163] In some embodiments of this disclosure, step S410 may further include steps S411-S413.

[0164] Step S411: Based on the selection control signal, the selected phase clock is selected from the N sampled clock signals in sequence through the multiplexing unit.

[0165] Step S412: Based on the second low-speed clock, sample the selected phase clock through the sampling unit to generate a comparison sampling result.

[0166] Step S413: Detect the voltage transition state of the sampling results through the logic unit, and determine the target selection control signal based on the voltage transition state.

[0167] In some embodiments of this disclosure, step S413 may further include step S4131.

[0168] Step S4131: By traversing the selected phase clock through the logic unit, in response to the detection of a voltage transition time between 1 and 0 in the comparison sampling result, the target selection control signal is determined from the N sampling result clock signals.

[0169] In some embodiments of this disclosure, step S420 may further include steps S421-S422.

[0170] Step S421: Sample the source data based on the target sampling result clock signal and generate intermediate transmission data through the pre-alignment unit.

[0171] Step S422: The intermediate transmission data is sampled by the synchronization unit based on the second low-speed clock to obtain the target data.

[0172] It should be noted that the specific functions of each step and the beneficial effects that can be achieved in the data transmission method provided in any embodiment of this disclosure can be referred to the relevant descriptions of the data transmission device embodiments above, and will not be repeated here.

[0173] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0174] For example, such as Figure 7 As shown, the electronic device 700 includes at least one processor 701 and at least one memory 702. The at least one memory 702 includes one or more computer program modules. These computer program modules are stored in the memory 702 and configured to be executed by the at least one processor 701. The computer program modules include instructions for performing data transmissions using the aforementioned data transmission device, and when executed by the at least one processor 701, they can perform corresponding computational tasks. The memory 702 and the processor 701 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0175] For example, processor 701 may be a central processing unit (CPU), digital signal processor (DSP), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), artificial intelligence (AI) accelerator, or other processing unit with data processing capabilities and / or program execution capabilities, such as a field-programmable gate array (FPGA), etc. It may include, for example, a data transmission device comprising at least one embodiment of this disclosure to realize data transmission between different clock domains; for example, the central processing unit (CPU) may be an x86, ARM, RISC-V architecture, etc. Processor 701 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 700 to perform desired functions.

[0176] For example, memory 702 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0177] Figure 8 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0178] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0179] The electronic device includes at least one processor and a memory. The processor may be referred to as processing device 801 as described below, and the memory may include at least one of ROM 802, RAM 803, and storage device 808 as described below. The memory is used to store programs for performing the methods described in the various method embodiments above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other forms of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0180] like Figure 8As shown, the electronic device 800 may include a processing device 801 (e.g., a central processing unit (CPU), digital signal processor (DSP), image processor (GPU), general-purpose graphics processor (GPGPU), or other forms of processing unit with data processing capabilities and / or program execution capabilities), including a data transmission device according to any embodiment of this disclosure, which can perform various appropriate actions and processes according to a program stored in ROM 802 or a program loaded from storage device 808 into RAM 803. RAM 803 also stores various programs and data required for the operation of the electronic device 800. The processing device 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interfaces are also connected to bus 804.

[0181] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, displays, speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 8 An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0182] In particular, according to at least one embodiment of this disclosure, the process described above with reference to the flowchart can be implemented as a computer software program.

[0183] For example, at least one embodiment of this disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by a processing device 801, it performs the functions defined in the methods of at least one embodiment of this disclosure.

[0184] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0185] In at least one embodiment of this disclosure, a computer-readable storage medium can be any tangible medium that includes or stores a program that can be used or combined with an instruction execution system, apparatus, or device. In at least one embodiment of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or combined with an instruction execution system, apparatus, or device. The program code included on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0186] The aforementioned computer-readable medium may be included in the aforementioned electronic device 800; or it may exist independently and not assembled into the electronic device 800.

[0187] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0188] For example, such as Figure 9 As shown, a non-transitory computer-readable storage medium 900 stores computer-readable instructions 901, which, when executed by at least one processor, perform one or more steps of the data transmission method described above.

[0189] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard drive for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be... Figure 7 The memory 702 in the memory is described in the foregoing content and will not be repeated here.

[0190] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the inventive concept of the present disclosure are within the scope of protection claimed by the present disclosure.

[0191] The following points should be noted regarding this disclosure:

[0192] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0193] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0194] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0195] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A data transmission device, characterized in that, The data transmission device includes: The clock generation module is configured to sample a first low-speed clock based on a first high-speed clock, and sequentially generate N sampled clock signals with uniform phase distribution, wherein the phase difference between adjacent signals in the N sampled clock signals is equal to one cycle of the first high-speed clock. The phase selection module is configured to determine a target sampling result clock signal based on the phase relationship between the N sampling result clock signals and the second low-speed clock, wherein the frequency of the first high-speed clock is higher than the frequency of the first low-speed clock and the frequency of the second low-speed clock, and N is an integer greater than 2; and The data transmission module is configured to sample the source data based on the target sampling result clock signal to generate intermediate transmission data, and to sample the intermediate transmission data based on the second low-speed clock to obtain the target data.

2. The data transmission device according to claim 1, characterized in that, The clock generation module further includes: An N-stage flip-flop is configured such that the N flip-flops are connected in series, the data input of the first-stage flip-flop is configured to receive the first low-speed clock, and the data input of the i-th stage flip-flop is coupled to the output of the (i-1)-th stage flip-flop. The clock input terminal corresponding to the N-level flip-flop is configured to receive the first high-speed clock, and the N outputs of the N-level flip-flop are respectively N sampling result clock signals, where i is an integer greater than 1 and less than or equal to N.

3. The data transmission device according to claim 1, characterized in that, The first low-speed clock belongs to the first clock domain, and the second low-speed clock belongs to the second clock domain. The source data is the data in the first clock domain to be transmitted to the second clock domain. The target data is the data received in the second clock domain.

4. The data transmission apparatus according to any one of claims 1-3, characterized in that, The phase selection module further includes: The multiplexing unit is configured to select and output a selected phase clock from the N sampled clock signals sequentially based on a selection control signal; The sampling unit is configured to sample the selected phase clock based on the second low-speed clock, and generate a comparison sampling result; and A logic unit is configured to detect voltage transition states of the comparison sampling result and determine a target selection control signal based on the voltage transition states. The target selection control signal is used to control the multiplexing unit to determine the target sampling result clock signal.

5. The data transmission device according to claim 4, characterized in that, The logic unit is further configured to traverse the selected phase clock and, in response to detecting a voltage transition time between 1 and 0 in the comparison sampling result, determine the target selection control signal from the N sampling result clock signals.

6. The data transmission device according to claim 4, characterized in that, The multiplexing unit is a multiplexer. The N input terminals of the multiplexing unit respectively receive the N sampling result clock signals. The selection control terminal of the multiplexing unit is configured to receive the selection control signal and the target selection control signal. The output of the multiplexing unit is configured to output the target sampling result clock signal based on the target selection control signal.

7. The data transmission device according to claim 4, characterized in that, The data transmission module further includes: A pre-alignment unit is configured to sample the source data based on the target sampling result clock signal to generate the intermediate transmission data; and The synchronization unit is configured to sample the intermediate transmission data based on the second low-speed clock to obtain the target data.

8. The data transmission device according to claim 7, characterized in that, The clock input terminal of the pre-alignment unit is coupled to the multiplexing unit to receive the target sampling result clock signal.

9. A data transmission method, characterized in that, The data transmission method includes: Based on the first high-speed clock, the first low-speed clock is sampled to generate N sampling result clock signals with uniform phase distribution in sequence, wherein the phase difference between adjacent signals in the N sampling result clock signals is equal to one cycle of the first high-speed clock. Based on the phase relationship between the N sampled result clock signals and the second low-speed clock, the target sampled result clock signal is determined, wherein the frequency of the first high-speed clock is higher than the frequency of the first low-speed clock and the frequency of the second low-speed clock, and N is an integer greater than 2; and Based on the target sampling result clock signal, the source data is sampled to generate intermediate transmission data, and the intermediate transmission data is sampled based on the second low-speed clock to obtain the target data.

10. An electronic device, characterized in that, The electronic device includes a data transmission device as described in any one of claims 1-8.

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