Transistor device and method for preparing gate of transistor device

Abstract

Transistor devices and methods of fabricating gates of transistor devices are disclosed. In an embodiment, a transistor device includes a semiconductor substrate having a main surface, a cell field including a plurality of transistor cells, and an edge termination region laterally surrounding the cell field. The cell field includes a gate trench in a main surface of the semiconductor substrate, a gate dielectric backing the gate trench, a metal gate electrode disposed in the gate trench on the gate dielectric, and an electrically insulating cap disposed on the metal gate electrode and within the gate trench.

Description

[0001] This is a divisional application. The parent application is entitled "Transistor Device and Method for Preparing Gate of Transistor Device", filed on February 5, 2021, with application number 202110158204.8. Background Technology

[0002] Common transistor devices used in power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated-gate bipolar transistors (IGBTs). US 9,680,004 B2 discloses a power MOSFET that includes a metal gate electrode in a gate trench having a strip shape. The power MOSFET also includes a field plate in a field plate trench having a columnar or needle-like shape. The field plate provides charge compensation and provides opportunities to reduce the area-specific on-resistance of the MOSFET device.

[0003] It would be desirable to allow for simpler manufacturing methods for transistor devices that include metal gate electrodes and transistor devices that include metal gate electrodes with even better performance. Summary of the Invention

[0004] According to the present invention, a transistor device includes: a semiconductor substrate having a main surface; a cell field including a plurality of transistor cells; and an edge termination region surrounding the cell field in the lateral direction. The cell field includes: a gate trench in the main surface of the semiconductor substrate; a gate dielectric padding the gate trench; a metal gate electrode disposed in the gate trench on the gate dielectric; and an electrically insulating cap disposed on the metal gate electrode and within the gate trench.

[0005] In some embodiments, the metal gate electrode has an upper surface located within a gate trench.

[0006] In some embodiments, the gate dielectric is a deposited layer having a uniform thickness on the sidewalls of the trench.

[0007] In some embodiments, the transistor device further includes a first electrically insulating layer disposed on the main surface of the semiconductor substrate that is laterally adjacent to the gate trench.

[0008] In some embodiments, the first electrical insulating layer extends onto the gate dielectric.

[0009] In some embodiments, an electrically insulating cap forms part of a second electrically insulating layer, which extends over the first electrically insulating layer and over a metal gate electrode located within a gate trench. The second electrically insulating layer is in direct contact with the upper surface of the metal gate electrode.

[0010] In some embodiments, the gate dielectric further includes a lower dielectric layer disposed at the bottom of the gate trench, and the gate dielectric pads the sidewalls of the gate trench and is located on the upper surface of the lower dielectric layer. In some embodiments, the lower dielectric layer is formed using an HDP (high-density plasma) deposition process.

[0011] In some embodiments, the electrically insulating cap includes an upper dielectric layer having an upper surface substantially coplanar with the main surface of the semiconductor substrate.

[0012] In some embodiments, the transistor device further includes a second electrically insulating layer extending on the main surface of the semiconductor substrate and on the upper dielectric layer located in the gate trench. The second electrically insulating layer may include a TEOS layer, i.e., deposited using TEOS (tetraethyl orthosilicate).

[0013] In some embodiments, the upper dielectric layer includes a TEOS layer, i.e., deposited using TEOS (tetraethyl orthosilicate) treatment.

[0014] In some embodiments, the metal gate electrode includes a pad layer disposed on the gate dielectric and a filler material. The pad layer may include two or more sublayers.

[0015] In some embodiments, the liner layer comprises Ti and / or TiN. In some embodiments, the filler material comprises tungsten. In some embodiments, the liner layer comprises TiN, and the filler material is formed of tungsten.

[0016] In some embodiments, the transistor device further includes a charge compensation structure. The charge compensation structure may include, for example, one or more conductive field plates or superjunction structures.

[0017] In some embodiments, the charge compensation structure includes an elongated field plate in an elongated field plate trench extending into the main surface and substantially parallel to the gate trench. Each transistor cell may include the elongated field plate, such that the charge compensation structure includes a plurality of elongated field plate trenches, each elongated field plate trench including the elongated field plate.

[0018] In some embodiments, the charge compensation structure includes a columnar field plate extending into the main surface and positioned laterally adjacent to a gate trench in a columnar field plate trench. Each transistor cell may include a columnar field plate, such that the charge compensation structure includes a plurality of columnar field plate trenches, each columnar field plate trench including a columnar field plate.

[0019] In some embodiments, the field plate comprises polycrystalline silicon. The field plate may be electrically isolated from the semiconductor substrate by an electrically insulating layer or field oxide that pads the bottom and sidewalls of the field plate trench. The field oxide may include silicon oxide.

[0020] Transistor devices can be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), or superjunction devices.

[0021] A method for fabricating a gate for a transistor device is also provided. The transistor device includes: a semiconductor substrate having a main surface; a cell field including a plurality of transistor cells; and an edge termination region surrounding the cell field in a lateral direction. The method includes: forming a gate trench in the main surface of the semiconductor substrate in the cell field; padding the gate trench with a gate dielectric; forming a metal gate electrode on the gate dielectric; and forming an electrically insulating capping on the metal gate electrode and within the gate trench.

[0022] In some embodiments, the gate dielectric is deposited on the bottom and sidewalls of the gate trench.

[0023] In some embodiments, the method further includes removing an upper portion of the metal gate electrode such that the upper surface of the metal gate electrode is recessed within a gate trench.

[0024] In some embodiments, the method further includes selectively forming a first electrically insulating layer on the main surface of the semiconductor substrate that is laterally adjacent to the gate trench.

[0025] In some embodiments, the method further includes forming a second electrically insulating layer on the first electrically insulating layer and on the metal gate electrode in the gate trench to form an electrically insulating cap.

[0026] In some embodiments, the method further includes forming a lower dielectric layer disposed at the bottom of a gate trench, and forming a gate dielectric on the sidewalls of the gate trench and on the upper surface of the lower dielectric layer.

[0027] In some embodiments, the method further includes: forming an upper dielectric layer on a metal gate electrode to form an electrically insulating cap, the upper dielectric layer having an upper surface substantially coplanar with the main surface of the semiconductor substrate; and forming a second electrically insulating layer on the upper dielectric layer and on the main surface of the semiconductor substrate.

[0028] In some embodiments, the method further includes, after forming an electrically insulating cap, implanting the body region and the source region into the main surface of the semiconductor substrate.

[0029] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0030] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings and described in detail in the following description.

[0031] Figure 1 The figure shows a cross-sectional view of a transistor device including a gate trench according to an embodiment.

[0032] Figure 2 includes Figures 2A to 2C The figure shows a view of a transistor device according to an embodiment, wherein... Figure 2A The figure shows a top view of a transistor device according to an embodiment.

[0033] Figure 2B Illustration Figure 2A A cross-sectional view of a transistor device.

[0034] Figure 2C The figure shows a cross-sectional view of a transistor device according to an embodiment.

[0035] Figure 3 The figure shows a cross-sectional view of a transistor device including a gate trench according to an embodiment.

[0036] Figure 4 includes Figures 4A to 4I The diagram illustrates a method for fabricating the gate of a transistor device.

[0037] Figure 5 includes Figures 5A to 5I The illustration shows a method for fabricating the gate of a transistor device according to an embodiment.

[0038] Figure 6 includes Figure 6A and Figure 6B The illustration shows a method for fabricating a transistor device including one of the embodiments described herein with a gate trench.

[0039] Figure 7 The diagram illustrates a flowchart for fabricating the gate of a transistor device. Detailed Implementation

[0040] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and which illustrate specific embodiments in which the invention may be practiced by way of illustration. In this regard, directional terms such as “top,” “bottom,” “front,” “back,” “front end,” “end,” etc., are used to indicate orientation with reference to the described figures(s). Because the components of the embodiments may be positioned in many different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention is not taken in a limiting sense, and the scope of the invention is defined by the appended claims.

[0041] Many exemplary embodiments will be explained below. In this context, the same structural features are identified by the same or similar reference numerals in the various figures. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or extension generally parallel to the lateral extension of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0042] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or there may be intermediate elements present. In contrast, when an element is referred to as "directly on" or "directly extending onto" another element, no intermediate elements are present.

[0043] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0044] As used herein, various device types and / or doped semiconductor regions may be identified as n-type or p-type, but this is merely for ease of description and is not intended to be limiting, and such identification may be replaced by a more general description of “first conductivity type” or “opposite second conductivity type”, wherein the first type may be n-type or p-type and thus the second type is p-type or n-type.

[0045] Each figure indicates the relative doping concentration by indicating "-" or "+" next to the doping type "n" or "p". For example, "n"- "" means a doping concentration lower than the doping concentration of the "n" doped region, while "n" + "The doped region has a higher doping concentration than the 'n' doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different 'n' doped regions can have the same or different absolute doping concentrations."

[0046] For modern trench power MOSFETs, the continuous reduction in size to achieve better area-specific on-resistance has resulted in very small gate dimensions. Polysilicon is typically used as the gate material. For small sizes, polysilicon has relatively high sheet resistance and specific resistivity, which can lead to an increase in the distributed gate resistance on the chip. This increased gate resistance can cause uneven switching on the chip and a decrease in switching speed. Therefore, it limits the possibilities for further reducing switching losses and adversely affects device robustness.

[0047] One approach to mitigate these effects is based on metal fingers that enable contact between the polysilicon gates of individual transistor cells. However, this requires silicon area that cannot be used for switching.

[0048] Another approach is to use metal instead of polysilicon as the gate material. The significantly higher conductivity of metal compared to doped polysilicon eliminates the need for gate fingers to provide uniform switching across the chip and allows for reduced trench widths. By using a metal gate (e.g., a TiN / W gate), a reduction in the specific resistivity of the gate compared to a polysilicon gate can be achieved. Metal gates offer the advantages of reducing gate size and thus enabling smaller device dimensions and increased switching speeds, as well as allowing for uniform switching across the entire chip area. However, fabricating silicon devices with metal gates is not straightforward, as it would require integrating the metal into the front end of the fabrication line process.

[0049] The embodiments described herein provide a gate trench structure filled with a metallic gate electrode material, which is encapsulated by an electrically insulating capping layer (e.g., an oxide capping layer). In some embodiments, charge compensation is performed using a field plate in a field plate trench or a needle-shaped or columnar field plate in a needle-shaped or columnar field plate trench.

[0050] The encapsulation of the metal gate electrode according to the embodiments described herein allows for the use of standard wet chemical cleaning in subsequent processing steps during device fabrication. Therefore, this structure provides a method to overcome many constraints inherent in the fabrication of metal gate devices. Furthermore, the top of the gate electrode is not exposed to an increased electric field, which is useful for increasing device lifetime.

[0051] Figure 1 The figure shows a cross-sectional view of a transistor device 10 according to an embodiment. The transistor device 10 includes a semiconductor substrate 11 having a main surface 12, a cell field 13 including a plurality of transistor cells 14, and an edge termination region 15 surrounding the cell field 13 in the lateral direction. The plurality of transistor cells 14 in the cell field 13 may all have substantially the same structure.

[0052] Cell field 13 includes: a gate trench 16 in the main surface 12 of semiconductor substrate 11; a gate dielectric 17 lining the gate trench 16; and a metal gate electrode 18 disposed in the gate trench and on the gate dielectric 17. An electrically insulating cap 19 is disposed on the metal gate electrode 18 and within the gate trench 16.

[0053] Each transistor cell 14 in the cell field may include the same arrangement of gate trench 16, gate dielectric 17, metal gate electrode 18, and electrically insulating cap 19. The cell field 13 contributes to the switching of the transistor device 10, while the edge termination region 15 is used to provide electrical isolation between the active device region (i.e., cell field 13) and the edge region of the device.

[0054] The gate dielectric 17 can be formed by depositing a dielectric layer onto the sidewalls 22 and bottom 23 of the gate trench 16. For example, the TEOS method can be used. If a deposition process is used instead of thermal oxidation of the semiconductor material forming the bottom 23 and sidewalls 22 of the gate trench 16, the thickness of the gate dielectric 17 can be more uniform.

[0055] The metal gate electrode 18 may comprise a metal such as tungsten. In some embodiments, the metal gate electrode 18 comprises two or more sublayers. In some embodiments, the metal gate electrode 18 comprises one or more pad layers located on and lining the gate dielectric 17, and a filler material located on the pad material and filling the remainder of the trench (i.e., the void surrounded by the pad layers) to form the metal gate electrode 18. The pad layers may be TiN and the filler material may be tungsten.

[0056] The metal gate electrode 18 includes an upper surface 20 located within the gate trench 16 and thus within the semiconductor substrate 11 at a depth extending from the main surface 12. An electrically insulating layer 19 extends between its lateral sides and is defined on its lateral sides by the gate dielectric 17 of the sidewalls 22 of the pad gate trench 16. In some embodiments, the electrically insulating cap 19 has an upper surface 21 substantially coplanar with the main surface or primary surface 12 of the semiconductor substrate 11. The electrically insulating cap 19 may be positioned directly on and completely cover the upper surface 20 of the metal gate electrode 18 located in the region of the transistor device 10 within the cell field 13.

[0057] The electrically insulating cap 19 is used to electrically insulate the metal gate electrode 18 from the conductive layer on the gate trench 16 located in the cell field 13 and from subsequent processing steps—such as the fabrication and implantation of the body region and source region of the transistor device and subsequent wet chemical cleaning and / or etching processes.

[0058] The use of the electrically insulating cap 19 also creates a flat surface on which a metallized structure with its interlayer dielectric can be constructed. However, due to the presence of the intermediate electrically insulating cap 19 located in the gate trench 16 on top of the metal gate electrode 18, the interlayer dielectric layer, typically formed of undoped silicon glass (USG) and / or BPSG (borophosphosilicate glass), does not directly contact the metal gate electrode 18 in the cell field 13.

[0059] Electrical contact with the metal gate electrode 18 can be achieved using one or more conductive vias extending through the electrically insulating cap 19. However, these one or more conductive vias are positioned laterally outside the cell field 13 and within the edge termination region 15. In some embodiments, the electrically insulating cap 19 may have a lateral extension such that it does not extend at least into the region of the edge termination region 15 in which the conductive vias are disposed.

[0060] At a location within the cell field 13 of the transistor device 10, the metal gate electrode 18 is completely encapsulated by the dielectric material of the gate dielectric 17 and the electrically insulating cap 19. At least one opening is formed in the electrically insulating cap 19 (in... Figure 1 (Not visible in the image) to allow for the formation of a contact with the metal gate electrode 18. The opening may be located in the edge termination region 15.

[0061] The semiconductor substrate 11 may be formed from a single-crystal semiconductor substrate, such as a single-crystal silicon wafer. In some embodiments, the semiconductor substrate may be formed from an epitaxial semiconductor layer (e.g., an epitaxial silicon layer).

[0062] The gate trench 16 may have an elongated strip-like structure, wherein its length extends into the plane of the figure. The gate trenches 16 of the plurality of transistor cells 14 may extend substantially parallel to each other.

[0063] In some embodiments, the gate trench formation comprises a portion of a grid structure consisting of segments extending in different lateral directions and intersecting each other. For example, a grid of longitudinal and lateral trenches can be provided. This arrangement can be used in transistor devices comprising a columnar field plate located in a columnar field plate trench, wherein the columnar trench is surrounded laterally by two longitudinal and two lateral segments, providing a continuous, typically square, ring.

[0064] The gate trench 16 having a gate dielectric 17, a metal gate electrode 18, and an electrically insulating cap 19 can be fabricated before the body region and source region of the transistor device are injected and after any field plate trench is formed in the main surface 12.

[0065] Transistor device 10 may be a vertical transistor device having a drain region located on a second main surface 24 opposite to the main surface 12. Figure 1 (Not shown in the image). The semiconductor substrate 11 can form the drift region of the transistor device 10 and is doped with a first conductivity type (e.g., n-type). The drain region can be highly doped with a first conductivity type (e.g., n-type). The body region ( Figure 1 (Not shown) is located on the drift region and includes a dopant of a second conductivity type (e.g., p-type) opposite to the first conductivity type. Source region ( Figure 1 (Not shown) Located on or in the body region and includes a dopant of the first conductivity type.

[0066] A metal layer may be located on the drain region to form a drain contact for the transistor device 10 on the back surface. A conductive layer may be located on the main surface 12 of the semiconductor substrate 11 on a cell field 13 electrically coupled to the source region and a field plate (if present), forming a source contact for the transistor device 10. A metal gate electrode 18 may be coupled to a gate contact for the transistor device 10, which is laterally positioned adjacent to the source contact on the main surface 12.

[0067] Figure 2A The figure shows a top view of the transistor device 30 according to an embodiment and Figure 2B The figure shows a cross-sectional view of a transistor device 30 including a gate trench 16.

[0068] The transistor device 30 includes a semiconductor substrate 11 having: a main surface 12; a cell field 13 including a plurality of transistor cells 14; and edge termination regions 15 surrounding the cell field 13 laterally on all sides. The cell field 13 includes: a gate trench 16 in the main surface 12 of the semiconductor substrate 11; a gate dielectric 17 padding the gate trench 16; a metal gate electrode 18 disposed on the gate dielectric 17 in the gate trench 16; and an electrically insulating cap 19 disposed on the metal dielectric 18 and located within the gate trench 16.

[0069] As in Figure 2A As can be seen in the top view, in the transistor device 30, the gate trench 16 has a grid shape, the grid including longitudinal segments 16a that extend substantially parallel to each other in the y direction and lateral segments 16b that extend substantially parallel to each other in the x direction.

[0070] Gate trench 16 extends to gate channel 31 located on the main surface 11 adjacent to cell field 13 in the lateral direction. Gate channel 31 extends between gate trenches 16a and 16b and substantially perpendicular to the length of gate trench 16. Gate electrodes 18 located within gate trench 16 also have an elongated shape and each is electrically connected to gate channel 31.

[0071] The transistor device 30 further includes a charge compensation structure. In some embodiments, such as the one illustrated in FIG2, the charge compensation structure includes a field plate 33 located in a field plate trench 32 extending into the main surface 12 of the semiconductor substrate 11 and positioned laterally adjacent to the gate trench 16. The field plate 33 is conductive and may be formed, for example, from polysilicon. The field plate 33 may be electrically isolated from the semiconductor substrate 11, wherein the field plate trench 32 is lined with an electrically insulating layer typically known as a field oxide. The field oxide typically has a thickness greater than that of the gate dielectric 17.

[0072] In some embodiments, such as the one illustrated in FIG2, the charge compensation structure includes columnar field plates 33 located in columnar field trenches 32. The cell field 13 includes a plurality of field plate trenches 32 arranged in a regular array and extending from the main surface 12 into the semiconductor substrate 11. Each field plate trench 32 includes a columnar or needle-shaped field plate 33 electrically insulated from the semiconductor substrate 11 by an electrically insulating layer 38 or a field plate oxide, the electrically insulating layer 38 or field plate oxide lining the bottom and sidewalls of the field plate trench 32. Each transistor cell can be considered to include a portion of a gate trench 16 and a columnar field plate trench 32.

[0073] Each columnar field plate 33 is located at the center of the area defined by two longitudinal trench segments 16a and two transverse trench segments 16b of a square grid structure formed on the main surface 12.

[0074] Reference Figure 2B In a cross-sectional view, the transistor device 30 further includes a first electrically insulating layer 34 disposed on the main surface 12 of the semiconductor substrate 11 and laterally adjacent to the gate trench 16, leaving the gate trench 16 and the gate electrode 18 uncovered. The first electrically insulating layer 34 can be used as a scattering oxide for subsequent body and source implantation.

[0075] The gate trench 16 includes an electrically insulating cap 19 disposed on the metal gate electrode 18 and located within the gate trench 16. In some embodiments, such as in Figure 2BIn the embodiment illustrated, the electrically insulating cap 19 includes an upper dielectric layer 39 located on top of the gate electrode 18 within the gate trench 16. The upper dielectric layer 39 may have an upper surface 40 substantially coplanar with the upper surface 12 of the semiconductor substrate 11. The upper surface 20 of the gate electrode 18 is recessed within the trench 16 such that it is located at a distance from the main surface 12. This recess at the top of the gate trench 16 is filled using the upper dielectric layer 39.

[0076] The second insulating layer 35 extends continuously over the first insulating layer 34 and is located on the main surface 12 of the semiconductor substrate 11 that is laterally adjacent to the gate trench 16 and on the upper dielectric layer 39 disposed in the gate trench 16.

[0077] The electrical insulating cap 19 is believed to include two layers: an upper dielectric layer 39 located within the gate trench 16 and in direct contact with the metal gate electrode 18; and a second insulating layer 35 located on the upper dielectric layer 39.

[0078] The sidewalls and bottom of the gate trench 16 are covered with an insulating layer in the form of a gate dielectric 17, which is typically thinner than the upper dielectric layer 39.

[0079] The transistor device 30 is a vertical transistor device, specifically a MOSFET in this embodiment, having a drain region 41 heavily doped with a first conductivity type at a second main surface 24 opposite to the main surface 12. The semiconductor substrate 11 may form the drift region 42 of the transistor device 30 and is lightly doped with, for example, an n-type first conductivity type. A body region 43 is located on the drift region 42 and includes a dopant of a second conductivity type, for example, a p-type, opposite to the first conductivity type. A source region 44 is located on or within the body region 43 and includes a dopant of the first conductivity type.

[0080] A metal layer 45 is located on the drain region 41 to form a drain contact on the back surface for the transistor device 30. A conductive layer 46 is located on the main surface 12 of the semiconductor substrate 11 on the cell field 13. The conductive layer 46 is electrically coupled to the source region 44 and the field plate 33, and forms a source contact for the transistor device 30. One or more insulating layers 47 are located between the conductive layer 46 and the second dielectric layer 35. A metal gate electrode 18 may be coupled to the gate contact for the transistor device 30.

[0081] Although the columnar field plate groove 32 and columnar field plate 33 are illustrated as circular in the plan view, the columnar field plate groove 32 and field plate 33 are not limited to this shape and can have other shapes, such as hexagonal or square.

[0082] In other embodiments not shown, the field plate 33 and the field plate trench 32 are elongated and have a strip-like shape, and the gate trench has an elongated strip-like shape. The lengths of the field plate trench 32 and the field plate 33 extend substantially parallel to the lengths of the elongated gate trench 16 and the elongated metal gate electrode 18.

[0083] The electrically insulating cover 19 may have other structures. In some embodiments, such as in Figure 2C In the embodiment illustrated, the electrically insulating cap 19 is formed by a portion of the second insulating layer 35 extending from the first insulating layer 34 and from the metal gate electrode 18 located within the gate trench 16. In this embodiment, the gate electrode 18 is recessed within the gate trench 16, such that its upper surface 20 is spaced apart from the main surface 12 and located within the gate trench 16. The second insulating layer 35 extends into the upper portion of the gate trench 16 and is in direct contact with the upper surface 20 of the metal gate electrode 18 located within the gate trench 16.

[0084] exist Figure 2C In the embodiment illustrated, the electrically insulating cap 19 is formed only from a portion of the second electrically insulating layer 35. The sidewalls and bottom of the gate trench 16 are covered with an insulating layer in the form of a gate dielectric 17. The formation of the gate dielectric 17 and the electrically insulating layer 35 partially forms the cap 19 for encapsulating the metal gate electrode.

[0085] Reference Figure 3 In some embodiments, the transistor device 30' includes a gate trench 16', wherein the gate dielectric 17 further includes a lower dielectric layer 36 located at the bottom 23 of the gate trench 16. The gate dielectric 17 pads the sidewalls 22 of the gate trench 16 and may also be located on the upper surface 37 of the lower dielectric layer 36. Therefore, the gate dielectric 17 has a larger width at the bottom 23 of the trench compared to the sidewalls 22 of the trench 16.

[0086] In some embodiments, such as in Figure 3 In the embodiment illustrated, the electrically insulating cap 19 includes an upper dielectric layer 39 having an upper surface 40 substantially coplanar with the upper surface 12 of the semiconductor substrate 11. In this arrangement, the transistor device 30 may include a first insulating layer 34 and a second dielectric layer 35. The first insulating layer 34 is formed on the main surface 12 of the semiconductor substrate 11, which is laterally adjacent to the gate trench 16 and leaves the upper dielectric layer 39 uncovered. The second dielectric layer 35 is located on the first electrically insulating layer 34 and extends on the main surface 12 of the substrate 11 and on the upper dielectric layer 39 located within the gate trench 16.

[0087] With Figure 2CIn comparison to the embodiments illustrated in the figure, the electrically insulating cap 19 is considered to include two layers: an upper dielectric layer 39 located within the gate trench 16; and a second insulating layer 35 located on the upper dielectric layer 39.

[0088] In some embodiments, the gate dielectric layer 17 of the pad sidewall 22 and the bottom 23 of the trench 16 or the upper surface 37 of the additional lower dielectric layer 36 is a deposited layer, rather than formed by thermal oxidation of the material of the semiconductor substrate. In some embodiments, the gate dielectric 17 is a deposited silicon oxide layer.

[0089] The difference between the gate dielectric 17 formed by deposition and the gate dielectric 17 formed by thermal oxidation lies in the increased uniformity of the gate dielectric thickness on the sidewalls of the trench. The gate dielectric 17 may be formed using a TEOS deposition process. In some embodiments, further densification of the deposited gate dielectric is performed, for example, by using a subsequent annealing step.

[0090] The combination of the metal gate electrode 18 and the deposited gate dielectric 17 was found to enable fast switching and result in lower losses, which is believed to be a result of reduced gate charge and gate resistance.

[0091] In embodiments that include a lower dielectric layer 36, the lower dielectric layer 36 may be deposited using a high-density plasma (HDP) process.

[0092] In embodiments that include an upper dielectric layer 39, the upper dielectric layer 39 may include a TEOS deposition layer.

[0093] In some embodiments, the pad layer of the metal gate electrode 18 is a deposited layer. The pad layer may include titanium (Ti) and / or titanium nitride (TiN), and the filler material may include tungsten (W).

[0094] In this embodiment, the gate dielectric is a TEOS layer, the pad layer is formed of titanium nitride (TiN), and the filler material is formed of tungsten (W).

[0095] The method for fabricating the gate of a transistor device will now be described with reference to Figure 4, which includes... Figures 4A to 4G .

[0096] The following describes and illustrates the processing sequence for a silicon power MOSFET using charge compensation via a field plate in a columnar field plate trench, where the columnar field plate trench is illustrated as separate circular needle-shaped trenches. However, this sequence is not limited to needle-shaped trenches; for example, strip-shaped field plate trenches can be used.

[0097] The process is compatible with very high aspect ratios (i.e., 3 and higher) for trenches. Aspect ratio is defined as depth / width. Aspect ratios are even higher after gate oxide modules, reaching 10 in our case; however, the techniques described herein can be used for even higher aspect ratios.

[0098] Reference Figure 4A Top view and Figure 4B The cross-sectional view begins at the semiconductor substrate 50 with a main surface 51, into which a deep field plate trench 64 with a field plate 65 has been formed. However, the body and source regions of the transistor structure have not yet been formed. The semiconductor substrate 50 can be formed, for example, from monocrystalline silicon or an epitaxial silicon layer. The columnar field plate trench is illustrated as circular in the plan view. However, the columnar field plate trench can have other shapes in the plan view, such as square or hexagonal. The later gate trench is located in... Figure 4B The dotted lines are used to indicate this.

[0099] exist Figures 4C to 4I In the diagram, only the region of the semiconductor substrate 50 including the gate trench is shown.

[0100] Reference Figure 4C Gate trenches are formed in the region of the main surface 51 located between the two rows of field plate trenches.

[0101] A gate trench 52 is formed in the main surface 51, which includes a bottom 53 and sidewalls 54 extending substantially perpendicular to the main surface 51. The gate trench 52 may have an elongated strip-like structure, wherein its length extends into the plane of the figure.

[0102] Reference Figure 4D A gate dielectric 55 is formed on the main surface 51 of the semiconductor substrate 50 and on the sidewalls 54 and bottom 53 of the trench 52. The gate dielectric 55 may be a silicon oxide layer, which may be formed by depositing a silicon oxide layer on the main surface 51 of the semiconductor substrate 50 and on the bottom 53 and sidewalls 54 of the gate trench 52. The gate dielectric 55 may be deposited using TEOS processing and subsequently subjected to a densification process, such as annealing.

[0103] Reference Figure 4E and Figure 4F Then, a metal gate electrode 59 is formed on the gate dielectric 55. The metal gate electrode 59 is formed by forming one or more pad layers 56 on the gate dielectric 55 and by forming a filler material 57 on the pad layers 56.

[0104] The padding layer 56 may include titanium, such as titanium nitride, and some embodiments may include two or more sublayers, such as titanium and titanium nitride. The filler material 57 may be formed of tungsten and may completely fill the voids in the gate trench 52 that are padded by the padding layer 56 and the gate dielectric 55, which also extend laterally on the main surface 51 of the semiconductor substrate 50 adjacent to the gate trench 52.

[0105] The backing layer 56 may be formed by pulsed chemical vapor deposition (pCVD) or atomic layer deposition (ALD). The filler material 57 may be formed by a process that enables conformal deposition, such as metal-organic chemical vapor deposition (MOCVD), and may undergo subsequent annealing.

[0106] Reference Figure 4G A planarization process can be performed to produce a planarized surface 58 formed by a gate dielectric layer 55 located on the main surface 51 of the semiconductor substrate 50 and a filler material 57 located in the gate trench 52. A portion of the pad layer 56 disposed adjacent to the gate trench 52 on the main surface 51 is removed.

[0107] Reference Figure 4H A portion of the filler material 57 and the pad layer 56 are removed from the upper portion of the gate trench 52, such that the metal gate electrode 59 has an upper surface 60 recessed within the trench 52 and located at a distance from the main surface 51 of the substrate 50. In this embodiment, the upper surface 60 of the metal gate electrode 59 may be approximately coplanar with the main surface 51 or recessed within the gate trench 52 at a small distance.

[0108] Reference Figure 4I A first electrically insulating layer 61 is formed on the main surface 51 of the semiconductor substrate 50. The first electrically insulating layer 61 may be selectively formed on the semiconductor substrate 50. In some embodiments, the first electrically insulating layer may extend onto the gate dielectric 55 of the pad gate trench 52. The metal gate electrode 59 remains uncovered by the first electrically insulating layer 61. The first electrically insulating layer 61 may be used as a scattering layer during subsequent implantation of the body and source regions.

[0109] Then, a second insulating layer 62 is formed on the first electrically insulating layer 61 and extends on the upper surface 60 of the metal gate electrode 59. The portion of the second insulating layer 62 directly on the metal gate electrode 59 forms an electrically insulating cap 63 for the metal gate electrode 59. At a location within the active region of the transistor device, the metal gate electrode 59 is completely encapsulated by the dielectric material of the gate dielectric 55 and the electrically insulating cap 63.

[0110] At this stage of the method, the metal gate electrode 59 is completely encapsulated by the dielectric material of the gate dielectric and the electrically insulating cap 63 throughout all areas of the transistor device. In a later stage, at least one opening is formed in the encapsulation to allow the formation of a contact to the metal gate electrode. The opening may be located in an edge termination region.

[0111] Figure 5 includes Figures 5A to 5I The illustration shows a method for fabricating the gate of a transistor device according to an embodiment.

[0112] Reference Figure 5A A semiconductor substrate 50 is provided having a main surface 51 and a gate trench 52 formed in the main surface 51. The gate trench 52 includes a bottom 53 and sidewalls 54 extending substantially perpendicular to the main surface 51. The gate trench 52 has an elongated shape having a length extending into the plane of the figures. As in the embodiment described with reference to FIG4, the semiconductor substrate 50 may also include a charge compensation structure comprising a field plate 65 located in a field plate trench 64, which is not visible in the portion of the semiconductor substrate shown in FIG5. The field plate 65 and the field plate trench 64 may be elongated or columnar.

[0113] Reference Figure 5B A lower dielectric layer 70 is formed on the bottom 53 of the gate trench 52. This dielectric layer 70 also has a portion 70' formed laterally adjacent to the trench 52 on the main surface 51 of the substrate 50. The lower dielectric layer 70 and the portion 70' can be deposited, for example, using HDP to achieve a greater thickness on the lateral or horizontal surface compared to a vertical surface (such as the sidewall 54 of the gate trench 52). In subsequent processing, the portion deposited on the vertical surface can be removed, for example, by using a wet or dry chemical etching process.

[0114] Reference Figure 5C A gate dielectric layer 55 is then formed, extending over the dielectric layer 70', the sidewalls 54 of the trench 52, and the lower dielectric layer 70 disposed at the bottom 53 of the gate trench 52. The gate dielectric layer 55 may be deposited, for example, using TEOS. In this embodiment, a thicker gate dielectric is provided at the bottom 53 of the gate trench 52 by the combination of the lower dielectric layer 70 and the deposited gate dielectric layer 55. This increased thickness at the bottom 53 of the gate trench 52 can be used to further reduce gate charge and gate-drain charge.

[0115] Reference Figure 5DThen, a metal gate electrode 59 is formed in the gate trench 52 by forming a pad layer 56 on the gate dielectric layer 55 and on the main surface 51, sidewalls 54, and bottom 53 of the trench 52 of the semiconductor substrate 50. A filler material 57 is then deposited to fill the voids formed in the gate trench 52 by the pad layer 56 and the gate dielectric 55. The filler material 57 is also located on the main surface 51 of the semiconductor substrate 50 in a laterally adjacent region to the gate trench 52. The filler material 57 may be conformally deposited and have a thickness such that any depressions in the gate trench 52 caused by the conformal deposition of the filler material 57 lie above the plane of the pad layer 56 disposed on the main surface 51.

[0116] The backing layer 56 may be formed by pulsed chemical vapor deposition (pCVD) or atomic layer deposition (ALD). The filler material 57 may be formed by a process that enables conformal deposition (e.g., metal-organic chemical vapor deposition (MOCVD)) and may be subjected to subsequent annealing.

[0117] Reference Figure 5E A planarization process is performed to remove the filler material 57 and the pad layer 56 located on the main surface 51 and laterally adjacent to the gate trench 52, to provide a planarized surface 58 forming a region on the dielectric layer 70' and the filler material 57 that includes the dielectric layer 55.

[0118] Then, the filler material 57 and the pad layer 56 are removed from the gate trench 52, thereby forming a metal gate electrode 59 having an upper surface 60 located at a certain depth from the main surface 51 of the semiconductor substrate 50 and within the gate trench 52, as shown in Figure 5F As can be seen in the diagram, the metal material of the gate electrode 59 is selectively removed, such that the gate dielectric layer 55 remains on the dielectric layer 70' and the sidewall 54 of the gate trench 52. Compared to the embodiment described with reference to FIG4, the upper surface 60 of the gate electrode 59 is at a greater depth from the main surface.

[0119] Reference Figure 5F In this embodiment, a further electrically insulating layer 71 is formed, which fills the upper portion of the gate trench 52 and extends over the gate dielectric 55 positioned adjacent to the gate trench 52. The further electrically insulating layer 71 may be deposited using TEOS or a plasma-based technique such as HDP.

[0120] Reference Figure 5GFurther planarization is performed to remove dielectric material 71, gate dielectric 55, and dielectric material 70', and to form a planarized surface 72. The planarized surface 72 is formed from the material of the semiconductor substrate 50 and the remaining portion of the electrically insulating layer 71 located in the upper portion of the gate trench 52 on the metal gate electrode 59. The remaining portion of the electrically insulating layer 71 forms an upper dielectric layer 73 located on the upper surface 60 of the gate electrode 59 and within the gate trench 52. The upper dielectric layer 73 extends laterally within the gate trench 52 between the gate dielectric 55 located on the sidewalls 54.

[0121] Reference Figure 5H A first electrically insulating layer 61 is then formed on the main surface 51 of the semiconductor substrate 50. The first electrically insulating layer 61 can be selectively formed on the main surface 51 by selectively oxidizing the semiconductor material of the substrate 50. In some embodiments, the first electrically insulating layer 61 also extends over the gate dielectric layer 55 of the pad gate trench 52, but leaves the upper dielectric layer 73 uncovered. A second electrically insulating layer 62 is then formed as a single continuous layer over the first electrically insulating layer 61 and the upper dielectric layer 73 in the gate trench 52. The second electrically insulating layer 62 may be formed by a TEOS process. In some embodiments, the first electrically insulating layer 61 is omitted and only the second electrically insulating layer 62 is applied.

[0122] Therefore, the metal gate electrode 59 is electrically insulated on its top surface by the combination of the upper dielectric layer 73 and the second insulating layer 62 forming the electrically insulating cap 74, electrically insulated on its bottom surface by the lower dielectric layer 70 and the gate dielectric 55, and electrically insulated on its side surface by the gate dielectric 55 located on the sidewall 54 of the gate trench 52.

[0123] The electrically insulating cap 74 also creates a flat surface 72 on which subsequent metallization structures (with their interlayer dielectrics) can be built. However, due to the presence of the intermediate electrically insulating cap 74 located on top of the metal gate electrode 59 in the gate trench 52, the interlayer dielectric layer, typically formed of undoped silicon glass (USG) and / or BPSG (borophosphosilicate glass), does not directly contact the metal gate electrode 59 located in the gate trench 52 in the cell field.

[0124] Figure 6A and Figure 6B The illustration shows a cross-sectional view of a transistor device that may include a gate structure according to any of the embodiments described herein. Figure 6A and Figure 6BThe illustration shows a charge compensation structure in the form of a field plate trench 80, which includes a field plate 81 electrically insulated from a semiconductor substrate 52 by an electrically insulating layer 82. The electrically insulating layer 82 is typically known as a field plate oxide and paves the sidewalls 83 and bottom 84 of the field plate trench 80. In some embodiments, the field plate trench 80 may have an elongated strip-like structure having a length substantially parallel to the length of the gate trench 52. In other embodiments, the field plate trench 80 may have a columnar shape and provide a plurality of columnar field plate trenches arranged in a regular array of rows and columns. Elongated gate trenches may be located between two rows of columnar field plate trenches.

[0125] exist Figure 6A In the embodiment illustrated, the gate trench 52 includes a lower dielectric layer 70 located at its bottom 53, and a gate dielectric 55 located on the lower dielectric layer 70 and the sidewalls 54 of the gate trench 52. A metal gate electrode 59 located within the trench is electrically isolated at its top side by a second dielectric layer 62, which extends on the main surface 51 of the semiconductor substrate 50 and into the gate trench 52, where it directly contacts the upper surface 60 of the metal gate electrode 59.

[0126] In the embodiment illustrated in FIG6, the metal gate electrode 59 is encapsulated on its lower side by a lower dielectric layer 70 and a gate dielectric 55, on its side by a gate dielectric 55, and on its upper side by a second dielectric layer 62.

[0127] In other embodiments, the gate trench 52 may be arranged such that the metal gate electrode 59 is encapsulated only by the gate dielectric 55 on its lower side and on its side surface, and only by the second dielectric layer 62 on its upper side.

[0128] In other embodiments, the metal gate electrode 59 is encapsulated on its lower side by a lower dielectric layer 70 and a gate dielectric 55, on its side by a gate dielectric 55, and on its upper side by an additional upper dielectric layer located within a gate trench 52 and a second dielectric layer 62 located on the additional upper dielectric layer.

[0129] A first dielectric layer 61 is also provided, which extends on the main surface 51 of the semiconductor substrate 50, such that a second dielectric layer 62 is located on the first dielectric layer 61 in a region laterally adjacent to the metal gate electrode 59.

[0130] Field trenches and field plates 81 can be formed in the main surface 51 before the gate electrode 59 is fabricated.

[0131] An electrically insulating cap provided by a second insulating layer 62 located on the metal gate electrode 59 and, if present, an additional upper dielectric layer 73, is used to protect the underlying metal gate electrode 59 during subsequent processing.

[0132] Reference Figure 6B After the gate electrode 59 is fabricated in the gate trench 52, the following steps are performed: a dopant of a second conductivity type is implanted into the main surface 51 to form a body region 85, and a dopant of a first conductivity type is implanted to form a source region 86 on the body region 85.

[0133] A metallization structure can then be formed on the main surface 51 to provide electrical connections to the source region 86 and field plate 83 located within the cell field 13, and to the metal gate electrode 59 located outside the cell field 13.

[0134] Figure 7 The diagram illustrates a flowchart 100 for fabricating the gate of a transistor device. The transistor device includes a semiconductor substrate having a main surface, a cell field comprising multiple transistor cells, and an edge termination region surrounding the cell field in the lateral direction.

[0135] In block 101, a gate trench is formed in the main surface of the semiconductor substrate in the cell field. In block 102, the gate trench is substrated using a gate dielectric. In block 103, a metal gate electrode is formed on the gate dielectric and within the gate trench. In block 104, an electrically insulating cap is formed on the metal gate electrode and within the gate trench.

[0136] A gate structure is provided in which a metal gate electrode is encapsulated by a gate dielectric on all sides of the region of the metal gate electrode located in the active region of the device, i.e., in the cell field. Therefore, the fabrication of transistor devices including metal gate electrodes is simplified because standard wet chemical cleaning techniques can be used in subsequent processing steps during device fabrication. Thus, this structure provides a method to overcome many constraints inherent in the fabrication of metal gate devices. Furthermore, the top of the gate electrode is not exposed to the increased electric field, which can lead to increased device lifetime.

[0137] For ease of description, spatially relative terms such as "below," "below," "lower part," "above," and "upper part" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, areas, sections, etc., without any intention of limitation. Throughout the description, the same terms refer to the same elements.

[0138] As used herein, the terms “having,” “comprising,” “including,” and “including” are open-ended terms that indicate the presence of a stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “an,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is to be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0139] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various substitutions and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A transistor device, comprising: A semiconductor substrate having a main surface, and a cell field including multiple transistor cells of power transistors; The unit field further includes: Body region of the second conductivity type; In the source region of the first conductivity type on or in the body region, the first conductivity type is opposite to the second conductivity type; Gate trenches in the main surface of a semiconductor substrate; Gate dielectric of the pad gate trench; A metal gate electrode is disposed in a gate trench on a gate dielectric; and An electrically insulating cap is disposed on the metal gate electrode. The electrically insulating cap has an upper surface that is substantially coplanar with the main surface of the semiconductor substrate.

2. The transistor device according to claim 1, wherein, The metal gate electrode comprises at least two different metals.

3. The transistor device according to claim 1, wherein, The gate dielectric comprises at least two distinct layers.

4. The transistor device according to claim 1, wherein, The electrical insulation cap is confined to the gate trench.

5. The transistor device according to claim 4, wherein, The gate dielectric includes a lower dielectric layer disposed at the bottom of the gate trench, and the gate dielectric pads the sidewalls of the gate trench and is located on the upper surface of the lower dielectric layer.

6. The transistor device of claim 1, further comprising an electrically insulating layer extending on the main surface of the semiconductor substrate and on the upper surface of the electrically insulating cap.

7. The transistor device according to claim 1, further comprising a charge compensation structure, wherein, The charge compensation structure includes a columnar field plate extending into the main surface and positioned laterally adjacent to the gate trench in a columnar field plate trench.

8. The transistor device according to claim 1, wherein, The metal gate electrode comprises titanium nitride, and the filler material comprises tungsten.

9. A method for fabricating a gate of a transistor device, the transistor device comprising a semiconductor substrate having a main surface and a cell field comprising a plurality of transistor cells including power transistors, the method comprising: A gate trench is formed in the main surface of the semiconductor substrate in the unit field; Gate trenches utilizing gate dielectric pads; A metal gate electrode is formed on the gate dielectric; Remove the upper portion of the metal gate electrode, so that the upper surface of the metal gate electrode is recessed into the gate trench. as well as An electrically insulating cap is formed on the recessed upper surface of the metal gate electrode, such that the electrically insulating cap includes an upper surface that is substantially coplanar with the main surface of the semiconductor substrate.

10. The method according to claim 9, wherein, The electrical insulation cap is confined to the gate trench.

11. The method of claim 9, further comprising: An electrically insulating layer is formed on the main surface of a semiconductor substrate and extends on the upper surface of an electrically insulating cap.

12. The method of claim 9, further comprising: The bulk region and source region are implanted into the main surface of the semiconductor substrate.

13. The method according to claim 9, wherein, Forming a metal gate electrode includes: A pad layer is formed on the gate dielectric; and Deposit filler material on the liner layer.

14. The method according to claim 13, wherein, The liner layer comprises titanium nitride, and the filler material comprises tungsten.

15. The method of claim 9, further comprising: Before forming the gate dielectric, a lower dielectric layer is formed in the gate trench. Forming the gate dielectric includes forming the gate dielectric on the lower dielectric layer.

16. The method of claim 9, further comprising: At least one charge compensation structure is formed within the semiconductor substrate. The at least one charge compensation structure includes a columnar field plate extending into the main surface and positioned laterally adjacent to the gate trench in a columnar field plate trench.

17. A method for fabricating a gate of a transistor device, the transistor device comprising a semiconductor substrate having a main surface and a cell field comprising a plurality of transistor cells including power transistors, the method comprising: A gate trench is formed in the main surface of the semiconductor substrate in the unit field; A gate dielectric layer is formed on the main surface of the semiconductor substrate and within the gate trench; Metal gate electrodes are formed on the main surface of the semiconductor substrate and on the gate dielectric layer within the gate trench; Remove the metal gate electrode from the main surface of the semiconductor and a portion of the gate trench, such that the remaining portion of the metal gate electrode within the gate trench includes an upper surface that is substantially coplanar with the upper surface of the gate dielectric layer formed on the main surface. Remove the upper portion of the remaining metal gate electrode from the gate trench, such that the upper surface of the metal gate electrode is recessed within the gate trench. An insulating layer is formed on the recessed upper surface of the metal gate electrode and on the main surface of the semiconductor substrate; as well as The insulating layer and gate dielectric layer on the main surface and part of the ground gate trench are removed, such that the remaining portion of the insulating layer forms an electrically insulating cap, the electrically insulating cap including an upper surface that is substantially coplanar with the main surface of the semiconductor substrate.

18. The method of claim 17, further comprising: After the insulating layer and gate dielectric layer are removed from the main surface, a second insulating layer is formed extending on the main surface of the semiconductor substrate and the upper surface of the electrically insulating cap.

19. The method of claim 17, further comprising: At least one charge compensation structure is formed within a semiconductor substrate, wherein the at least one charge compensation structure includes a columnar field plate extending into the main surface and positioned laterally adjacent to a gate trench in a columnar field plate trench.

20. The method of claim 17, wherein, Forming a metal gate electrode includes: A pad layer is formed on the main surface of the semiconductor substrate and on the gate dielectric layer within the gate trench; and Filler material is deposited on the main surface of the semiconductor substrate and on the pad layer within the gate trench.

21. The method according to claim 20, wherein, The liner layer comprises titanium nitride, and the filler material comprises tungsten.

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