Integrated circuit device including stacked transistors and method of manufacturing same

Abstract

Integrated circuit devices and methods of forming the same are provided. The integrated circuit device may include: a substrate; an insulator on an upper surface of the substrate; a transistor between the substrate and the insulator, the transistor including: channel layers spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; and a gate structure on the channel layers and the insulator, wherein a width of the insulator in a second direction parallel to the upper surface of the substrate is equal to or substantially equal to a width of an uppermost one of the channel layers in the second direction.

Description

Technical Field

[0001] This disclosure relates generally to the field of integrated circuit devices, and more specifically to integrated circuit devices comprising stacked transistors. Background Technology

[0002] Various structures and methods for forming integrated circuit devices have been proposed to improve integration density. For example, stacked transistor structures, which include multiple transistors stacked vertically, have been proposed. Summary of the Invention

[0003] According to some embodiments, an integrated circuit device may include: a substrate; an insulator on an upper surface of the substrate; a transistor between the substrate and the insulator, the transistor including: channel layers spaced apart from each other in a first direction perpendicular to the upper surface of the substrate; and a gate structure on the channel layers and the insulator, wherein the width of the insulator in a second direction parallel to the upper surface of the substrate is equal to or substantially equal to the width of the uppermost channel layer in the second direction.

[0004] According to some embodiments, an integrated circuit device may include: a first transistor on a substrate; a second transistor on the first transistor; and an inter-gate insulator between the first transistor and the second transistor, wherein the first transistor includes: a first channel layer spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; and a first gate structure on the first channel layer and the inter-gate insulator, wherein the second transistor includes: a second channel layer spaced apart from each other in a vertical direction; and a second gate structure on the second channel layer and the inter-gate insulator, wherein the first gate structure is in contact with the second gate structure, and wherein the side surfaces of the inter-gate insulator are respectively aligned with the corresponding side surfaces of the uppermost first channel layer in the first channel layer.

[0005] According to some embodiments, a method of forming an integrated circuit device may include: forming a first stack on a substrate, wherein the first stack includes alternating stacked first channel layers and first sacrificial layers; forming an inter-gate sacrificial layer on the first stack; forming a second stack on the inter-gate sacrificial layer, wherein the second stack includes alternating stacked second channel layers and second sacrificial layers; and replacing the inter-gate sacrificial layer with an inter-gate insulator, wherein the width of the inter-gate insulator in a horizontal direction parallel to the upper surface of the substrate is equal to or substantially equal to the width in the horizontal direction of the uppermost first channel layer in the first channel layers. Attached Figure Description

[0006] Figure 1 It is a cross-sectional view of an integrated circuit device according to some implementation methods.

[0007] Figure 2This is a flowchart of a method for forming an integrated circuit device according to some implementation methods.

[0008] Figures 3 to 7 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments.

[0009] Figure 8 It is a cross-sectional view of an integrated circuit device according to some implementation methods.

[0010] Figures 9 to 13 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments.

[0011] Figure 14 It is a cross-sectional view of an integrated circuit device according to some implementation methods.

[0012] Figure 15 It is a cross-sectional view of an integrated circuit device according to some implementation methods.

[0013] Figure 16 It is a cross-sectional view of an integrated circuit device according to some implementation methods.

[0014] Figure 17 This is a flowchart of a method for forming an integrated circuit device according to some implementation methods.

[0015] Figures 18 to 22 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments.

[0016] Figure 23 It is a cross-sectional view of an integrated circuit device according to some implementation methods.

[0017] Figures 24 to 28 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments. Detailed Implementation

[0018] According to the embodiments described herein, an integrated circuit device may include a stacked transistor structure comprising a first transistor (e.g., a lower transistor) and a second transistor (e.g., an upper transistor) vertically stacked on a substrate. The first transistor may include a first channel layer (e.g., a lower channel layer) spaced apart from each other in a vertical direction. The first transistor may further include a first gate insulator (e.g., a lower gate insulator), a first work function layer (e.g., a lower work function layer) on the first gate insulator, and a first gate electrode (e.g., a lower gate electrode) on the first work function layer. The second transistor may include a second channel layer (e.g., an upper channel layer) spaced apart from each other in a vertical direction. The second transistor may further include a second gate insulator (e.g., an upper gate insulator), a second work function layer (e.g., an upper work function layer) on the second gate insulator, and a second gate electrode (e.g., an upper gate electrode) on the second work function layer. In some embodiments, each first channel layer and each second channel layer may be a nanosheet or a nanowire. The integrated circuit device may include a first insulator (also referred to as an inter-gate insulator or intermediate dielectric isolation) between the first transistor and the second transistor in a vertical direction. The width of the first insulator in the horizontal direction may be equal to or substantially equal to the width of the uppermost first channel layer in the horizontal direction. The integrated circuit device may further include a second insulator (also called an upper insulator) on the second transistor. The first and second insulators may be vertically opposite each other such that the second transistor is located therebetween. The width of the second insulator in the horizontal direction may be equal to or substantially equal to the width of the uppermost second channel layer in the horizontal direction. The width of the first insulator in the horizontal direction may be greater than the width of the lowermost second channel layer in the horizontal direction. The width of each first channel layer in the horizontal direction (first width) may be equal or substantially equal. The width of each second channel layer in the horizontal direction (second width) may be equal or substantially equal. The first width may be greater than the second width. Here, "substantially" may mean a deviation of no more than 10%. For example, when element X has a width of 10 nm and the width of element Y is substantially equal to the width of element X, the width of element Y may be no less than 9 nm or no more than 11 nm.

[0019] Example implementations will be described in more detail with reference to the accompanying drawings.

[0020] Figure 1 This is a cross-sectional view of an integrated circuit device 10 according to some embodiments. (Refer to...) Figure 1The integrated circuit device 10 may include a first transistor 140 (e.g., a lower transistor 140) and a second transistor 160 (e.g., an upper transistor 160) formed on a substrate 100. The first transistor 140 may be located between the substrate 100 and the second transistor 160 in a vertical direction perpendicular to the upper and / or lower surfaces of the substrate 100. In some embodiments, the centers of the first transistor 140 and the second transistor 160 may be misaligned with each other in the vertical direction. The first transistor 140 and the second transistor 160 may have different or the same conductivity type. In some embodiments, the first transistor 140 may be an N-type transistor including an N-type source / drain region (not shown), and the second transistor 160 may be a P-type transistor including a P-type source / drain region (not shown). However, the inventive concept of the types of the first transistor 140 and the second transistor 160 is not limited to the embodiments described above. For example, the first transistor 140 may be a P-type transistor including a P-type source / drain region (not shown), and the second transistor 160 may be an N-type transistor including an N-type source / drain region (not shown).

[0021] Substrate 100 may include semiconductor materials such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP, and / or may include insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, and / or low-k materials. In some embodiments, substrate 100 may be a bulk substrate (e.g., a silicon wafer), a semiconductor-on-insulator (SOI) substrate, or an insulating layer (e.g., a monolithic insulating layer). Low-k materials may have a lower dielectric constant than silicon oxide (e.g., SiO). Low-k materials may include, for example, fluorine-doped silicon oxide, organosilicon glass, carbon-doped oxide, porous disilicide, porous organosilicon glass, spin-coated organic polymer dielectrics, and / or spin-coated silicon-based polymer dielectrics.

[0022] The first transistor 140 may include a first channel layer 102 (e.g., a lower channel layer 102), a first gate insulator 104 on the first channel layer 102 (e.g., a lower gate insulator 104), a first work function layer 106 on the first gate insulator 104 (e.g., a lower work function layer 106), and a first gate electrode 108 on the first work function layer 106 (e.g., a lower gate electrode 108). The first gate insulator 104, the first work function layer 106, and the first gate electrode 108 may be collectively referred to as a first gate structure (e.g., a lower gate structure).

[0023] The first channel layers 102 may be spaced apart from each other in the vertical direction. In some embodiments, the first channel layers 102 may be spaced apart from each other at equal or substantially equal distances in the vertical direction. In some embodiments, each first channel layer 102 may have equal or substantially equal widths in a horizontal direction parallel to the upper and / or lower surfaces of the substrate 100. For example, each first channel layer 102 may have a first width W1 in the horizontal direction.

[0024] In the cross-sectional view, the first gate insulator 104 may extend around the first channel layer 102 (e.g., at least partially around the first channel layer 102). The first work function layer 106 may extend around the first gate insulator 104 (e.g., at least partially around the first gate insulator 104). The first gate electrode 108 may extend around the first work function layer 106 (e.g., at least partially around the first work function layer 106).

[0025] In some embodiments, the first channel layer 102 may include a semiconductor material, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the first gate insulator 104 may include an insulator, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, and / or a low-k material having a dielectric constant lower than that of silicon oxide. In some embodiments, the first work function layer 106 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer. In some embodiments, the first gate electrode 108 may include, for example, tungsten (W), aluminum (Al), and / or copper (Cu). However, the materials in the first channel layer 102, the first gate insulator 104, the first work function layer 106, and the first gate electrode 108 are not limited to the embodiments described above.

[0026] The first gate electrode 108 may include a first inner gate electrode 108_I and a first outer gate electrode 108_O. The first inner gate electrode 108_I may be located between adjacent first channel layers 102 in the vertical direction. The first outer gate electrode 108_O may be located on the upper surface of the uppermost first channel layer 102 and / or on the lower surface of the lowermost first channel layer 102 in the first channel layer 102. For example, the first outer gate electrode 108_O may be located between the uppermost first channel layer 102 and the first insulator 110 (described in detail later) in the vertical direction. The first outer gate electrode 108_O may be located between the lowermost first channel layer 102 and the substrate 100 in the vertical direction. In some embodiments, the first inner gate electrode 108_I and the first outer gate electrode 108_O may be integrally formed (joined) to constitute the first gate electrode 108.

[0027] In some embodiments, the thickness in the vertical direction of the first gate structure between adjacent first channel layers 102 in the first channel layer 102 and the thickness in the vertical direction of the first gate structure between the uppermost first channel layer 102 and the first insulator 110 (described in detail below) in the first channel layer 102 may be equal or substantially equal. In some embodiments, the thickness in the vertical direction of the first gate structure between adjacent first channel layers 102 in the first channel layer 102 and the thickness in the vertical direction of the first gate structure between the lowermost first channel layer 102 and the substrate 100 in the first channel layer 102 may be equal or substantially equal. For example, the thickness in the vertical direction of the first inner gate electrode 108_I may be equal to or substantially equal to the thickness in the vertical direction of the first outer gate electrode 108_O.

[0028] Since the width of the first insulator 110 in the horizontal direction is formed to be equal to or substantially equal to the width of the uppermost first channel layer 102 in the horizontal direction, and the thickness of the first inner gate electrode 108_I in the vertical direction is equal to or substantially equal to the thickness of the first outer gate electrode 108_O in the vertical direction, the performance of the integrated circuit device 10 (e.g., the first transistor 140) can be improved. For example, when the thickness of the first inner gate electrode 108_I in the vertical direction is equal to or substantially equal to the thickness of the first outer gate electrode 108_O in the vertical direction, the subthreshold swing and / or peak in the IV curve of the integrated circuit device 10 (e.g., the first transistor 140) can be improved (e.g., reduced).

[0029] The second transistor 160 may include a second channel layer 112 (e.g., upper channel layer 112), a second gate insulator 114 on the second channel layer 112 (e.g., upper gate insulator 114), a second work function layer 116 on the second gate insulator 114 (e.g., upper work function layer 116), and a second gate electrode 118 on the second work function layer 116 (e.g., upper gate electrode 118). The second gate insulator 114, the second work function layer 116, and the second gate electrode 118 may be collectively referred to as the second gate structure (e.g., the upper gate structure).

[0030] The second channel layers 112 may be spaced apart from each other in the vertical direction. In some embodiments, the second channel layers 112 may be spaced apart from each other at equal or substantially equal distances in the vertical direction. In some embodiments, each second channel layer 112 may have equal or substantially equal widths in the horizontal direction. The width of at least one first channel layer 102 in the horizontal direction may be greater than the width of at least one second channel layer 112 in the horizontal direction. In some embodiments, each second channel layer 112 may have a second width W2 in the horizontal direction. For example, the first width W1 of each first channel layer 102 may be greater than the second width W2 of each second channel layer 112.

[0031] In the cross-sectional view, the second gate insulator 114 may extend around the second channel layer 112 (e.g., at least partially surrounding the second channel layer 112). The second work function layer 116 may extend around the second gate insulator 114 (e.g., at least partially surrounding the second gate insulator 114). The second gate electrode 118 may extend around the second work function layer 116 (e.g., at least partially surrounding the second work function layer 116). In some embodiments, the first gate structure may contact the second gate structure. For example, the second gate electrode 118 may contact the first gate electrode 108. The first gate electrode 108 and the second gate electrode 118 may comprise the same material. In some embodiments, the first gate electrode 108 and the second gate electrode 118 may be integrally formed (joined) to constitute the gate electrode of the integrated circuit device 10.

[0032] In some embodiments, the second channel layer 112 may include a semiconductor material, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the second gate insulator 114 may include an insulator, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, and / or a low-k material having a dielectric constant lower than that of silicon oxide. In some embodiments, the second work function layer 116 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer. In some embodiments, the second gate electrode 118 may include, for example, tungsten (W), aluminum (Al), and / or copper (Cu). However, the materials in the second channel layer 112, the second gate insulator 114, the second work function layer 116, and the second gate electrode 118 are not limited to the embodiments described above.

[0033] The second gate electrode 118 may include a second inner gate electrode 118_I and a second outer gate electrode 118_O. The second inner gate electrode 118_I may be located between adjacent second channel layers 112 in the vertical direction. The second outer gate electrode 118_O may be located on the upper surface of the uppermost second channel layer 112 and / or on the lower surface of the lowermost second channel layer 112 in the second channel layer 112. The second outer gate electrode 118_O may be located between the lowermost second channel layer 112 and the first insulator 110 in the vertical direction. In some embodiments, the second inner gate electrode 118_I and the second outer gate electrode 118_O may be integrally formed (joined) to constitute the second gate electrode 118.

[0034] In some embodiments, the thickness of the second gate structure between adjacent second channel layers in the second channel layer 112 in the vertical direction may be equal to or substantially equal to the thickness of the second gate structure between the bottommost second channel layer 112 and the first insulator 110 (described in detail later) in the vertical direction. For example, the thickness of the second inner gate electrode 118_I in the vertical direction may be equal to or substantially equal to the thickness of the second outer gate electrode 118_O in the vertical direction between the bottommost second channel layer 112 and the first insulator 110 in the second channel layer 112.

[0035] In some embodiments, each of the first channel layer 102 and the second channel layer 112 may be a nanosheet (which may have a thickness in the vertical direction ranging from about 1 nm to about 100 nm) or a nanowire (which may have a circular cross-section with a diameter in the vertical direction ranging from about 1 nm to about 100 nm). In some embodiments, each first channel layer 102 and each second channel layer 112 may have equal thickness in the vertical direction.

[0036] The integrated circuit device 10 may include a first insulator 110 (e.g., an inter-gate insulator 110 or an intermediate dielectric isolation 110) between a first transistor 140 and a second transistor 160 in the vertical direction. The width of the first insulator 110 in the horizontal direction may be equal to or substantially equal to the width of the uppermost first channel layer 102 in the horizontal direction. In some embodiments, the side surfaces of the first insulator 110 may be aligned with corresponding side surfaces of the uppermost first channel layer 102 in the first channel layers 102. For example, the first insulator 110 may have a first width W1 in the horizontal direction. In some embodiments, the width of the first insulator 110 in the horizontal direction may be equal to or substantially equal to the width of each first channel layer 102 in the horizontal direction. The first insulator 110 may have multiple (e.g., non-uniform) thicknesses in the vertical direction. For example, the first insulator 110 may have a first portion with a first thickness in the vertical direction and a second portion with a second thickness in the vertical direction, the second thickness being greater than the first thickness. In some embodiments, a portion of the first insulator 110 may be recessed to have a thickness (e.g., a first thickness) in the vertical direction that is less than the thickness (e.g., a second thickness) of another portion of the first insulator 110. The recess in the first insulator 110 may be oriented towards the uppermost first channel layer 102 in the first channel layer 102. For example, in a cross-sectional view, the first insulator 110 may have an asymmetrical stepped shape in the horizontal direction. The stepped shape of the first insulator 110 may include a sloping curve. However, the shape of the first insulator 110 is not limited thereto. The first insulator 110 may include an insulator, such as a silicon nitride (e.g., SiN). However, the material of the first insulator 110 is not limited thereto.

[0037] Although Figure 1 The diagram shows a first transistor 140 comprising three first channel layers 102, but in some embodiments, the first transistor 140 may include one, two, or more than three first channel layers 102. Although Figure 1 The second transistor 160 is shown to include three second channel layers 112, but in some embodiments, the second transistor 160 may include one, two or more than three second channel layers 112.

[0038] Although not in Figure 1 As shown, the integrated circuit device 10 may also include a mid-process (MOL) structure and a back-end process (BEOL) structure. Each of the MOL and BEOL structures may include an interlayer insulating layer in which conductive lines (e.g., metal lines) and conductive path plugs (e.g., metal path plugs) are provided. Various elements of the first transistor 140 and the second transistor 160 may be (electrically) connected to one of the conductive lines of the MOL and BEOL structures.

[0039] Furthermore, in some embodiments, a back-side power distribution network structure (BSPDNS) may be provided below or within substrate 100. In some embodiments, some components of the BSPDNS may be provided within substrate 100. The BSPDNS may include a back-side insulating layer therein providing conductive back-side lines (e.g., metal power rails) and conductive back-side contacts (e.g., back-side metal contacts). Various components of the first transistor 140 and the second transistor 160 may be (electrically) connected to one of the conductive back-side lines.

[0040] Figure 2 This is a flowchart illustrating a method for forming an integrated circuit device according to some implementation methods. For example, Figure 2 It is formed according to some implementation methods Figure 1 The flowchart shows the method of the integrated circuit device 10.

[0041] Figures 3 to 7 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments. For example, Figures 3 to 7 This illustrates the formation according to some embodiments. Figure 1 A cross-sectional view of the method of the integrated circuit device 10 shown.

[0042] Reference Figure 1 , Figure 2 and Figure 3 The method may include forming a first stack 342 (e.g., a lower stack 342) on a substrate 100 (box 202). The first stack 342 may include a first channel layer 102 and a first sacrificial layer 320 (e.g., a lower sacrificial layer 320). In some embodiments, the first channel layer 102 and the first sacrificial layer 320 may be stacked alternately in the vertical direction. In some embodiments, the first sacrificial layer 320 may include a material that has etch selectivity relative to the first channel layer 102. For example, the first sacrificial layer 320 may include SiGe.

[0043] Reference Figure 1 , Figure 2 and Figure 3An inter-gate sacrificial layer 322 (also referred to as an intermediate sacrificial layer 322) (box 204) can be formed on the first stack 342. The first stack 342 can be located between the inter-gate sacrificial layer 322 and the substrate 100 in the vertical direction.

[0044] Reference Figure 1 , Figure 2 and Figure 3 A second stack 362 (e.g., upper stack 362) can be formed on the inter-gate sacrificial layer 322 (box 206). The inter-gate sacrificial layer 322 can be located between the first stack 342 and the second stack 362 in the vertical direction. The second stack 362 may include a second channel layer 112 and a second sacrificial layer 324 (e.g., upper sacrificial layer 324). In some embodiments, the second channel layer 112 and the second sacrificial layer 324 may be stacked alternately in the vertical direction. In some embodiments, the second sacrificial layer 324 may include a material that has etch selectivity relative to the second channel layer 112. For example, the second sacrificial layer 324 may include SiGe.

[0045] In some embodiments, the inter-gate sacrificial layer 322 may comprise a material having etch selectivity relative to the first channel layer 102, the first sacrificial layer 320, the second channel layer 112, and the second sacrificial layer 324. For example, the inter-gate sacrificial layer 322 may comprise SiGe having a different Ge concentration than the SiGe of the first sacrificial layer 320 and the second sacrificial layer 324. However, the materials of the first sacrificial layer 320, the second sacrificial layer 324, and the inter-gate sacrificial layer 322 are not limited to the embodiments described above.

[0046] Reference Figure 1 , Figure 2 and Figure 4 A portion of the second stack 362 can be removed (e.g., etched) to expose a portion of the inter-gate sacrificial layer 322 (box 208). In some embodiments, a portion of the inter-gate sacrificial layer 322 can be removed together with a portion of the second stack 362. In some embodiments, after removing this portion of the inter-gate sacrificial layer 322, the inter-gate sacrificial layer 322 can have multiple thicknesses in the vertical direction. For example, a portion of the inter-gate sacrificial layer 322 can be recessed (e.g., etched or damaged) to have a thickness (e.g., a first thickness) in the vertical direction that is less than the thickness (e.g., a second thickness) of another portion of the inter-gate sacrificial layer 322. For example, in a cross-sectional view, the inter-gate sacrificial layer 322 can have a stepped shape that is asymmetrical in the horizontal direction. The stepped shape of the inter-gate sacrificial layer 322 can include a sloping curve. However, the shape of the inter-gate sacrificial layer 322 is not limited to this.

[0047] Reference Figure 1 , Figure 2 , Figure 5 and Figure 6 The inter-gate sacrificial layer 322 can be removed, and a first insulator 110 (e.g., inter-gate insulator 110 or intermediate dielectric isolation 110) can be formed in the space where the inter-gate sacrificial layer 322 has been removed. In some embodiments, the inter-gate sacrificial layer 322 can be replaced by the first insulator 110 (box 210). For example, since the inter-gate sacrificial layer 322 can be etched selectively relative to the first channel layer 102, the first sacrificial layer 320, the second channel layer 112, and the second sacrificial layer 324, the inter-gate sacrificial layer 322 can be selectively etched without etching the first stack 342 and the second stack 362. The first insulator 110 can then be formed in the space where the inter-gate sacrificial layer 322 has been etched. The shape of the first insulator 110 can be the same as or substantially the same as the shape of the inter-gate sacrificial layer 322.

[0048] Reference Figure 1 , Figure 2 and Figure 7 The first sacrificial layer 320 and the second sacrificial layer 324 (box 212) can be removed.

[0049] Reference Figure 1 and Figure 2 A gate structure (frame 214) can be formed on the first channel layer 102 and the second channel layer 112. In some embodiments, the gate structure can be formed on the first insulator 110. In some embodiments, the gate structure can include a first gate structure and a second gate structure. The first gate structure includes a first gate insulator 104, a first work function layer 106, and a first gate electrode 108 formed on the first channel layer 102. The second gate structure includes a second gate insulator 114, a second work function layer 116, and a second gate electrode 118 formed on the second channel layer 112.

[0050] Figure 8 This is a cross-sectional view of an integrated circuit device 20 according to some embodiments. Figures 9 to 13 This illustrates the formation according to some embodiments. Figure 8 A cross-sectional view of the method using integrated circuit device 20. Since integrated circuit device 20 can be used with… Figure 1The integrated circuit device 10 in the text is similarly formed and configured, so detailed descriptions of the common configuration and manufacturing methods with integrated circuit device 10 can be omitted, and the differences from integrated circuit device 10 will be described in detail. Substrate 800, first channel layer 802, first gate insulator 804, first work function layer 806, first gate electrode 808, first inner gate electrode 808_I, first outer gate electrode 808_O, first insulator 810, second channel layer 812, second gate insulator 814, second work function layer 816, second gate electrode 818, second inner gate electrode 818_I, second outer gate electrode 818_O, first sacrificial layer 920, inter-gate sacrificial layer 922, second sacrificial layer 924, first transistor 840, second transistor 860, first stack 942 and second stack 962 can be respectively Corresponding to substrate 100, first channel layer 102, first gate insulator 104, first work function layer 106, first gate electrode 108, first inner gate electrode 108_I, first outer gate electrode 108_O, first insulator 110, second channel layer 112, second gate insulator 114, second work function layer 116, second gate electrode 118, second inner gate electrode 118_I, second outer gate electrode 118_O, first sacrificial layer 320, inter-gate sacrificial layer 322, second sacrificial layer 324, first transistor 140, second transistor 160, first stack 342 and second stack 362. Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 The descriptions can correspond to respectively Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 .

[0051] according to Figure 8 ,and Figure 1 Unlike other insulators, the first insulator 810 can have a symmetrical shape in the horizontal direction. In some embodiments, in a cross-sectional view, the first insulator 810 can have two stepped shapes that are mirror images of each other in the horizontal direction. For example, the first insulator 810 can be mirrored with respect to an imaginary vertical line V at the center of the first insulator 810. This symmetrical shape of the first insulator 810 can be achieved by symmetrically removing... Figure 10 The result of a portion of the intergate sacrificial layer 922 shown in the figure.

[0052] according to Figure 8 Integrated circuit device 20 in, and Figure 1Unlike the integrated circuit device 10, the centers of the first transistor 840 and the second transistor 860 can be aligned or substantially aligned with each other in the vertical direction.

[0053] Figure 14 This is a cross-sectional view of an integrated circuit device 30 according to some embodiments. Since the integrated circuit device 30 can be coupled with... Figure 1 The integrated circuit device 10 is similarly configured, so detailed descriptions of the configuration common to integrated circuit device 10 can be omitted, and detailed descriptions of the differences from integrated circuit device 10 are provided. Substrate 1400, first channel layer 1402, first gate insulator 1404, first work function layer 1406, first gate electrode 1408, first insulator 1410, second channel layer 1412, second gate insulator 1414, second work function layer 1416, second gate electrode 1418, first transistor 1440 and second transistor 1460 can respectively correspond to substrate 100, first channel layer 102, first gate insulator 104, first work function layer 106, first gate electrode 108, first insulator 110, second channel layer 112, second gate insulator 114, second work function layer 116, second gate electrode 118, first transistor 140 and second transistor 160.

[0054] according to Figure 14 Integrated circuit device 30 in the middle, and Figure 1 Unlike the integrated circuit device 10, the first insulator 1410 may have a uniform or substantially uniform thickness in the vertical direction.

[0055] Figure 15 This is a cross-sectional view of an integrated circuit device 40 according to some embodiments. Since the integrated circuit device 40 can be coupled with... Figure 8 The integrated circuit device 20 is similarly configured, so a detailed description of the configuration common to integrated circuit device 20 can be omitted, and the differences from integrated circuit device 20 will be described in detail. Substrate 1500, first channel layer 1502, first gate insulator 1504, first work function layer 1506, first gate electrode 1508, first insulator 1510, second channel layer 1512, second gate insulator 1514, second work function layer 1516, second gate electrode 1518, first transistor 1540 and second transistor 1560 can respectively correspond to substrate 800, first channel layer 802, first gate insulator 804, first work function layer 806, first gate electrode 808, first insulator 810, second channel layer 812, second gate insulator 814, second work function layer 816, second gate electrode 818, first transistor 840 and second transistor 860.

[0056] according to Figure 15Integrated circuit device 40 in the middle, and Figure 8 Unlike the integrated circuit device 20, the first insulator 1510 may have a uniform or substantially uniform thickness in the vertical direction.

[0057] Figure 16 This is a cross-sectional view of an integrated circuit device 50 according to some embodiments. Because integrated circuit device 50 and... Figure 1 The integrated circuit device 10 is similarly configured, so detailed descriptions of the common configuration with integrated circuit device 10 can be omitted. Instead, detailed descriptions of the differences from integrated circuit device 10 will be provided. Substrate 1600, first channel layer 1602, first gate insulator 1604, first work function layer 1606, first gate electrode 1608, first inner gate electrode 1608_I, first outer gate electrode 1608_O, first insulator 1610, second channel layer 1612, second gate insulator 1614, second work function layer 1616, second gate electrode 1618, second inner gate electrode 1618_I, second outer gate electrode 1618_O, first transistor 1640, and second transistor. 1660 can correspond to substrate 100, first channel layer 102, first gate insulator 104, first work function layer 106, first gate electrode 108, first inner gate electrode 108_I, first outer gate electrode 108_O, first insulator 110, second channel layer 112, second gate insulator 114, second work function layer 116, second gate electrode 118, second inner gate electrode 118_I, second outer gate electrode 118_O, first transistor 140 and second transistor 160, respectively.

[0058] The integrated circuit device 50 may further include a second insulator 1626 (also referred to as an upper insulator 1626) on the second transistor 1660. For example, the second insulator 1626 may be on the second channel layer 1612. The second transistor 1660 may be positioned vertically between the first insulator 1610 and the second insulator 1626.

[0059] In some embodiments, the second gate electrode 1618 may include a second inner gate electrode 1618_I and a second outer gate electrode 1618_O. The second inner gate electrode 1618_I may be located between adjacent second channel layers 1612 in the vertical direction. The second outer gate electrode 1618_O may be located between the uppermost second channel layer 1612 and the second insulator 1626 in the vertical direction and / or between the lowermost second channel layer 1612 and the first insulator 1610 in the vertical direction.

[0060] In some embodiments, the thickness of the second gate structure between adjacent second channel layers 1612 in the vertical direction and the thickness of the second gate structure between the uppermost second channel layer 1612 and the second insulator 1626 in the vertical direction may be equal or substantially equal. In some embodiments, the thickness of the second gate structure between adjacent second channel layers 1612 in the vertical direction and the thickness of the second gate structure between the lowermost second channel layer 1612 and the first insulator 1610 in the vertical direction may be equal or substantially equal. For example, the thickness of the second inner gate electrode 1618_I in the vertical direction may be equal to or substantially equal to the thickness of the second outer gate electrode 1618_O in the vertical direction.

[0061] The width of the second insulator 1626 in the horizontal direction may be equal to or substantially equal to the width of the uppermost second channel layer 1612 in the horizontal direction. In some embodiments, the side surfaces of the second insulator 1626 may be aligned with the corresponding side surfaces of the uppermost second channel layer 1612 in the second channel layers 1612. For example, the second insulator 1626 may have a second width W2 in the horizontal direction. In some embodiments, the width of the second insulator 1626 in the horizontal direction may be equal to or substantially equal to the width of each second channel layer 1612 in the horizontal direction. The second insulator 1626 may have a uniform or substantially uniform thickness in the vertical direction. However, the shape of the second insulator 1626 is not limited thereto. The second insulator 1626 may include an insulator, such as a silicon nitride (e.g., SiN). However, the material of the second insulator 1626 is not limited thereto.

[0062] Since the width of the second insulator 1626 in the horizontal direction is formed to be equal to or substantially equal to the width of the uppermost second channel layer 1612 in the horizontal direction, and the thickness of the second inner gate electrode 1618_I in the vertical direction is equal to or substantially equal to the thickness of the second outer gate electrode 1618_O in the vertical direction, the performance of the integrated circuit device 50 (e.g., the second transistor 1660) can be improved. For example, when the thickness of the second inner gate electrode 1618_I in the vertical direction is equal to or substantially equal to the thickness of the second outer gate electrode 1618_O in the vertical direction, the subthreshold swing and / or peak in the IV curve of the integrated circuit device 50 (e.g., the second transistor 1660) can be improved (e.g., reduced).

[0063] Figure 17 This is a flowchart illustrating a method for forming an integrated circuit device according to some implementation methods. For example, Figure 17It is formed according to some implementation methods Figure 16 The flowchart of the method of the integrated circuit device 50 shown in the figure.

[0064] Figures 18 to 22 This is a cross-sectional view illustrating a method for forming an integrated circuit device according to some embodiments. For example, Figures 18 to 22 This illustrates the formation according to some embodiments. Figure 16 A cross-sectional view of the method of the integrated circuit device 50 shown in the figure.

[0065] Reference Figure 16 , Figure 17 and Figure 18 The method may include forming a first stack 1842 (e.g., a lower stack 1842) (box 1702) on a substrate 1600. The first stack 1842 may include a first channel layer 1602 (e.g., a lower channel layer 1602) and a first sacrificial layer 1820 (e.g., a lower sacrificial layer 1820). In some embodiments, the first channel layer 1602 and the first sacrificial layer 1820 may be stacked alternately in the vertical direction. In some embodiments, the first sacrificial layer 1820 may include a material with etch selectivity relative to the first channel layer 1602. For example, the first sacrificial layer 1820 may include SiGe.

[0066] Reference Figure 16 , Figure 17 and Figure 18 An inter-gate sacrificial layer 1822 (also known as an intermediate sacrificial layer 1822) (box 1704) can be formed on the first stack 1842. The first stack 1842 can be located between the inter-gate sacrificial layer 1822 and the substrate 1600 in the vertical direction.

[0067] Reference Figure 16 , Figure 17 and Figure 18 A second stack 1862 (e.g., upper stack 1862) can be formed on the inter-gate sacrificial layer 1822 (box 1706). The inter-gate sacrificial layer 1822 can be located between the first stack 1842 and the second stack 1862 in the vertical direction. The second stack 1862 may include a second channel layer 1612 and a second sacrificial layer 1824 (e.g., upper sacrificial layer 1824). In some embodiments, the second channel layer 1612 and the second sacrificial layer 1824 may be stacked alternately in the vertical direction. In some embodiments, the second sacrificial layer 1824 may include a material that has etch selectivity relative to the second channel layer 1612. For example, the second sacrificial layer 1824 may include SiGe.

[0068] Reference Figure 16 , Figure 17 and Figure 18An upper sacrificial layer 1828 (box 1708) can be formed on the second stack 1862. The second stack 1862 can be located between the inter-gate sacrificial layer 1822 and the upper sacrificial layer 1828 in a vertical direction. In some embodiments, each of the inter-gate sacrificial layer 1822 and the upper sacrificial layer 1828 may include a material having etch selectivity relative to the first channel layer 1602, the first sacrificial layer 1820, the second channel layer 1612, and the second sacrificial layer 1824. For example, each of the inter-gate sacrificial layer 1822 and the upper sacrificial layer 1828 may include SiGe having a different Ge concentration than the SiGe of the first sacrificial layer 1820 and the second sacrificial layer 1824. However, the materials of the first sacrificial layer 1820, the second sacrificial layer 1824, the inter-gate sacrificial layer 1822, and the upper sacrificial layer 1828 are not limited to the embodiments described above.

[0069] Reference Figure 16 , Figure 17 and Figure 19 A portion of the second stack 1862 and a portion of the upper sacrificial layer 1828 can be removed (e.g., etched) to expose a portion of the inter-gate sacrificial layer 1822 (box 1710). In some embodiments, a portion of the inter-gate sacrificial layer 1822 can be removed together with that portion of the second stack 1862 and that portion of the upper sacrificial layer 1828. In some embodiments, after removing that portion of the inter-gate sacrificial layer 1822, the inter-gate sacrificial layer 1822 can have multiple thicknesses in the vertical direction. For example, a portion of the inter-gate sacrificial layer 1822 can be recessed (e.g., etched or damaged) to have a thickness (e.g., a first thickness) in the vertical direction that is less than the thickness (e.g., a second thickness) of another portion of the inter-gate sacrificial layer 1822. For example, in a cross-sectional view, the inter-gate sacrificial layer 1822 can have a stepped shape that is asymmetrical in the horizontal direction. The stepped shape of the inter-gate sacrificial layer 1822 can include a sloping curve. However, the shape of the inter-gate sacrificial layer 1822 is not limited to this. In some embodiments, after removing this portion of the upper sacrificial layer 1828, the remaining portion of the upper sacrificial layer 1828 may have a uniform or substantially uniform thickness in the vertical direction.

[0070] Reference Figure 16 , Figure 17 , Figure 20 and Figure 21The inter-gate sacrificial layer 1822 and the upper sacrificial layer 1828 can be removed, and a first insulator 1610 (e.g., inter-gate insulator 1610 or intermediate dielectric isolation 1610) and a second insulator 1626 (e.g., upper insulator 1626) can be formed in the spaces where the inter-gate sacrificial layer 1822 and the upper sacrificial layer 1828 have been removed. In some embodiments, the inter-gate sacrificial layer 1822 can be replaced by the first insulator 1610, and the upper sacrificial layer 1828 can be replaced by the second insulator 1626 (box 1712). For example, since the inter-gate sacrificial layer 1822 can be etched selectively relative to the first channel layer 1602, the first sacrificial layer 1820, the second channel layer 1612, and the second sacrificial layer 1824, the inter-gate sacrificial layer 1822 can be selectively etched without etching the first stack 1842 and the second stack 1862. Then, the first insulator 1610 can be formed in the spaces where the inter-gate sacrificial layer 1822 has been etched. The shape of the first insulator 1610 may be the same as or substantially the same as the shape of the intergate sacrificial layer 1822.

[0071] Reference Figure 16 , Figure 17 and Figure 22 The first sacrificial layer 1820 and the second sacrificial layer 1824 (box 1714) can be removed.

[0072] Reference Figure 16 and Figure 17 A gate structure (frame 1716) may be formed on the first channel layer 1602 and / or the second channel layer 1612. In some embodiments, the gate structure may be further formed on the first insulator 1610 and the second insulator 1626. In some embodiments, the gate structure may include a first gate structure and a second gate structure, the first gate structure including a first gate insulator 1604, a first work function layer 1606 and a first gate electrode 1608 formed on the first channel layer 1602, and the second gate structure including a second gate insulator 1614, a second work function layer 1616 and a second gate electrode 1618 formed on the second channel layer 1612.

[0073] Figure 23 This is a cross-sectional view of an integrated circuit device 60 according to some embodiments. Figures 24 to 28 This illustrates the formation according to some embodiments. Figure 23 A cross-sectional view of the method using integrated circuit device 60. Because integrated circuit device 60 can be used with… Figure 16The integrated circuit device 50 in the text is similarly formed and configured, so detailed descriptions of the common configuration and manufacturing methods with integrated circuit device 50 can be omitted, and the differences from integrated circuit device 50 will be described in detail. Substrate 2300, first channel layer 2302, first gate insulator 2304, first work function layer 2306, first gate electrode 2308, first inner gate electrode 2308_I, first outer gate electrode 2308_O, first insulator 2310, second channel layer 2312, second gate insulator 2314, second work function layer 2316, second gate electrode 2318, second inner gate electrode 2318_I, second outer gate electrode 2318_O, second insulator 2326, first sacrificial layer 2420, inter-gate sacrificial layer 2422, second sacrificial layer 2424, upper sacrificial layer 2428, first transistor 23 40. The second transistor 2360, the first stack 2442, and the second stack 2462 can respectively correspond to the substrate 1600, the first channel layer 1602, the first gate insulator 1604, the first work function layer 1606, the first gate electrode 1608, the first inner gate electrode 1608_I, the first outer gate electrode 1608_O, the first insulator 1610, the second channel layer 1612, the second gate insulator 1614, the second work function layer 1616, the second gate electrode 1618, the second inner gate electrode 1618_I, the second outer gate electrode 1618_O, the second insulator 1626, the first sacrificial layer 1820, the inter-gate sacrificial layer 1822, the second sacrificial layer 1824, the upper sacrificial layer 1828, the first transistor 1640, the second transistor 1660, the first stack 1842, and the second stack 1862. Figure 16 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 The descriptions can correspond to respectively Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 and Figure 28 .

[0074] according to Figure 23 ,and Figure 16 Unlike other insulators, the first insulator 2310 can have a symmetrical shape in the horizontal direction. For example, in a cross-sectional view, the first insulator 2310 can have two stepped shapes that are mirror images of each other in the horizontal direction. This symmetrical shape of the first insulator 2310 can be achieved by symmetrically removing... Figure 25 The results of a portion of the intergate sacrificial layer 2422 shown in the figure.

[0075] according to Figure 23 Integrated circuit device 60 in the middle, and Figure 16Unlike the integrated circuit device 50, the centers of the first transistor 2340 and the second transistor 2360 can be aligned or substantially aligned with each other in the vertical direction.

[0076] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of this disclosure, and therefore this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the inventive concept to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Unless explicitly stated otherwise, the same reference numerals may always refer to the same elements.

[0077] The exemplary embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of idealized embodiments and intermediate structures of the exemplary embodiments. Accordingly, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments herein should not be construed as limited to the specific shapes shown herein, but may include, for example, shape deviations caused by manufacturing processes.

[0078] It should also be noted that in some alternative embodiments, the functions / actions indicated in the flowchart boxes herein may not occur in the order shown in the flowchart. For example, depending on the functions / actions involved, two boxes shown consecutively may actually be executed substantially simultaneously, or these boxes may sometimes be executed in reverse order. Furthermore, the function of a given box in the flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes in the flowchart and / or block diagram may be at least partially merged. Finally, without departing from the scope of the inventive concept, other boxes may be added / inserted between the shown boxes, and / or boxes / operations may be omitted.

[0079] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” “including,” and / or “containing” specify the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0081] It will be understood that when a component is referred to as being “connected” to, “attached” to, or “in response to” or “on” another component, it can be directly connected to, directly connected to, or directly responded to or directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being “directly connected” to, “directly connected” to, or “directly responded to” or “on” another component, there are no intermediate components. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Furthermore, the symbol “ / ” (e.g., when used in the term “source / drain”) will be understood to be equivalent to the term “and / or”.

[0082] As used here, “element A overlaps with element B in direction X” (or similar language) means that there exists at least one line extending in direction X that intersects both elements A and B.

[0083] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the presented embodiments, a first element may be referred to as a second element.

[0084] As used here, "lower surface" refers to the surface facing the substrate (e.g., Figure 1 In the context of substrate 100, "upper surface" refers to the surface opposite to the lower surface. Furthermore, as used herein, "lower portion" refers to the portion closer to the substrate than "upper portion".

[0085] In conjunction with the foregoing description and accompanying drawings, numerous different embodiments have been disclosed herein. It will be understood that a literal description and illustration of each combination and sub-combination of these embodiments would be excessively repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be construed as a complete written description of all combinations and sub-combinations constituting the embodiments described herein, as well as the ways and processes of making and using them, and should support the claims for any such combinations or sub-combinations.

[0086] The foregoing disclosure is intended to be illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the scope of the inventive concept. Therefore, to the fullest extent permitted by law, the scope will be determined by the widest permissible interpretation of the appended claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

Claims

1. An integrated circuit device, comprising: Substrate; An insulator on the upper surface of the substrate; A transistor located between the substrate and the insulator, the transistor comprising: The channel layers are spaced apart from each other in a first direction perpendicular to the upper surface of the substrate; and The gate structure on the channel layer and the insulator, Wherein, the width of the insulator in a second direction parallel to the upper surface of the substrate is equal to the width of the uppermost channel layer in the channel layer in the second direction.

2. The integrated circuit device according to claim 1, wherein, The distance between the insulator and the uppermost channel layer in the channel layer in the first direction is equal to the distance between adjacent channel layers in the first direction.

3. The integrated circuit device according to claim 2, wherein, The first portion of the gate structure between the insulator and the uppermost channel layer in the channel layer and the second portion of the gate structure between the adjacent channel layers in the channel layer have equal thickness in the first direction.

4. The integrated circuit device according to claim 1, wherein, Each of the channel layers has an equal width in the second direction.

5. The integrated circuit device according to claim 1, wherein, The insulator has a first portion having a first thickness in the first direction and a second portion having a second thickness in the first direction, and The second thickness is different from the first thickness.

6. The integrated circuit device according to claim 5, wherein, The insulator has an asymmetrical shape in the cross-sectional view.

7. The integrated circuit device according to claim 5, wherein, The insulator has a symmetrical shape in the cross-sectional view.

8. The integrated circuit device according to claim 1, wherein, The transistor is a first transistor, the channel layer is a first channel layer, and the insulator is an inter-gate insulator. The integrated circuit device further includes a second transistor, the second transistor including a second channel layer spaced apart from each other on the gate insulator in the first direction. Wherein, the gate-to-gate insulator is located between the first transistor and the second transistor in the first direction, and Wherein, the width of the lowermost second channel layer in the second channel layer in the second direction is smaller than the width of the gate insulator in the second direction.

9. The integrated circuit device according to claim 8, wherein, The integrated circuit device further includes an upper insulator on the second transistor. Wherein, the second transistor is located between the gate insulator and the upper insulator in the first direction, and Wherein, the width of the uppermost second channel layer in the second channel layer in the second direction is equal to the width of the upper insulator in the second direction.

10. The integrated circuit device according to claim 9, wherein, Each of the second channel layers has an equal width in the second direction.

11. An integrated circuit device, comprising: The first transistor on the substrate; The second transistor on the first transistor; as well as Gate insulator, located between the first transistor and the second transistor. The first transistor includes: The first channel layers are spaced apart from each other in a direction perpendicular to the upper surface of the substrate; and The first gate structure is located on the first channel layer and the gate inter-insulator. The second transistor includes: The second channel layers are spaced apart from each other in the vertical direction; and The second gate structure is located on the second channel layer and the gate inter-insulator. Wherein, the first gate structure is in contact with the second gate structure, and The side surfaces of the gate insulator are aligned with the corresponding side surfaces of the uppermost first channel layer in the first channel layer.

12. The integrated circuit device according to claim 11, wherein, The first transistor has a first conductivity type, and The second transistor has a second conductivity type that is different from the first conductivity type.

13. The integrated circuit device according to claim 11, wherein, Each of the first channel layers has a first width in a horizontal direction parallel to the upper surface of the substrate. Each of the second channel layers has a second width in the horizontal direction, and Wherein, the first width is greater than the second width.

14. The integrated circuit device according to claim 13, wherein, The gate insulator has the first width in the horizontal direction.

15. The integrated circuit device according to claim 14, wherein, The integrated circuit device further includes an upper insulator on the second channel layer, and The upper insulator has the second width in the horizontal direction.

16. The integrated circuit device according to claim 11, wherein, The gate insulator includes a recess toward the uppermost first channel layer in the first channel layer.

17. A method for forming an integrated circuit device, the method comprising: A first stack is formed on a substrate, wherein the first stack includes alternating stacked first channel layers and first sacrificial layers; An inter-gate sacrificial layer is formed on the first stack; A second stack is formed on the inter-gate sacrificial layer, wherein the second stack includes alternately stacked second channel layers and second sacrificial layers; as well as Replace the inter-gate sacrificial layer with an inter-gate insulator. Wherein, the width of the gate insulator in the horizontal direction parallel to the upper surface of the substrate is equal to the width of the uppermost first channel layer in the first channel layer in the horizontal direction.

18. The method of claim 17, further comprising: Before replacing the inter-gate sacrificial layer with the inter-gate insulator, a portion of the second stack is removed to partially expose the inter-gate sacrificial layer; Remove the first sacrificial layer and the second sacrificial layer; A first gate structure is formed on the first channel layer and the gate inter-insulator; as well as A second gate structure is formed on the second channel layer and the gate inter-insulator. The first gate structure is in contact with the second gate structure.

19. The method of claim 18, further comprising: Before removing the portion of the second stack, an upper sacrificial layer is formed on the second stack; Remove a portion of the upper sacrificial layer; as well as Before removing the first and second sacrificial layers, the upper sacrificial layer is replaced with an upper insulator.

20. The method according to claim 19, wherein, The width of the upper insulator in the horizontal direction is equal to the width of the uppermost second channel layer in the horizontal direction.

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