Closed-loop control method for zero-voltage switching converter

Abstract

Disclosed herein is a controller for an auxiliary resonant commutated pole (ARCP) converter, the controller comprising: a sensor portion comprising: a ZVD sensor configured to measure a voltage across a switch of the converter, and to detect a time when the voltage across the switch equals zero; a dv / dt sensor configured to measure changes in voltage across the switch over time, and to detect voltage transitions across the switch; and a gate sensor configured to measure a gate-source voltage of the switch and detect a time during which the gate-source voltage is sufficient to transition the switch between OFF and ON; and a control section configured to: receive measurement values from the ZVD sensor, the dv / dt sensor, and the gate sensor; and generate a control signal for the switch based at least in part on measurements received from the ZVD sensor, the dv / dt sensor, and the gate sensor.

Description

Cross-references to related applications

[0001] This application claims priority to application No. 63 / 524,976, filed July 5, 2023. For the purposes of the United States, this application claims the benefit of application No. 63 / 524,976, filed July 5, 2023, entitled “Closed-Loop Control Method for Zero-Voltage Switching Converters,” pursuant to 35 U.S.C. § 119 (35 U.S.C. § 119), which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to systems and methods for controlling zero-voltage switching converters. More specifically, this disclosure relates to systems and methods for closed-loop control of zero-voltage switching converters. Background Technology

[0003] Power converters play a vital role in various industries such as transportation, entertainment, energy, and the food chain, as well as in applications such as electric drive, electric vehicles (EVs), renewable energy harvesting, and power regulation. In recent years, their penetration rate in power systems has been steadily increasing due to growing focus on carbon emission reduction and renewable energy harvesting.

[0004] Due to the non-ideal nature of converter switches, the losses they generate can be divided into two parts: conduction losses and switching losses. These losses manifest as heat on the switches. This heat reduces switch lifespan, as well as the converter's efficiency and reliability. In addition to generating heat, switching losses also limit the maximum switching frequency that the converter can operate at. This limited switching frequency also hinders the converter's ability to achieve better output power quality, higher power density, and lower cost. Increasing the switching frequency can lead to better power quality and a smaller number of passive components, making the converter more compact and cost-effective.

[0005] One way to achieve higher switching frequencies is to reduce switching losses, thereby lowering the junction temperature of the switching devices. Lower losses also help save energy and reduce carbon emissions, making the power system more environmentally friendly. Therefore, reducing losses is of great importance. Furthermore, considering the increasing number of sensitive loads in the power grid (such as data processing systems), the electromagnetic compatibility (EMC) of power converters is also an important issue that needs attention.

[0006] Switching losses in power semiconductor devices are caused by the overlap of the rising and falling edges of the voltage across the device with the falling and rising edges of the current flowing through the device, respectively.

[0007] One way to reduce switching losses is to shorten the overlap time by increasing the rise and fall rates of current and voltage. Wide bandgap devices have been introduced to the market for this purpose. Although wide bandgap devices have lower losses compared to silicon-based devices, their use involves challenges such as electromagnetic interference (EMI) and issues related to rapid voltage changes over time (known as "dv / dt"), which can damage loads such as motors.

[0008] Another way to reduce switching losses is to use a zero-voltage switching scheme based on a resonant circuit. The resonant circuit adjusts the voltage across the switching device to zero before a switching event occurs and eliminates the overlap between voltage and current transition edges, thus achieving zero switching losses. This can be referred to as "soft switching".

[0009] Several soft-switching methods have been proposed to reduce switching losses in DC / DC, AC / DC, and DC / AC converters. However, many of these methods (which may be referred to as "open-loop control") use the nominal values ​​of components and known operating points when calculating the appropriate switching time to provide zero-voltage switching. But components not only have tolerances in their values, but their values ​​also depend on their operating conditions, such as temperature and voltage. Furthermore, actual components have parasitic parameters such as the switch's output capacitance and parasitic inductance, which are also inherently dependent on operating conditions. In addition, the operating point can deviate due to temperature variations, the characteristics of the load powered by the converter, and changes in power supply conditions. Therefore, such open-loop control can lead to inaccurate switching times due to these deviations, resulting in partial hard switching and losses.

[0010] An improved zero-voltage switching method is needed. Furthermore, an improved zero-voltage switching method is needed that can at least partially compensate for errors introduced by non-ideals, component tolerances, dynamic behavior, etc. Summary of the Invention

[0011] According to one part of this disclosure, a closed-loop zero-voltage switching (ZVS) control system is provided, applicable to converters with a building block having two complementary switches. One embodiment may be a converter based on an auxiliary resonant commutated pole (ARCP). The ARCP proposed by R. DeDoncker et al. in U.S. Patent No. 5,047,913 reduces switching losses of two-level converter poles. Many open-loop control methods have been proposed to control such a construction. However, despite their mathematical complexity, they suffer from partial hard switching and / or over-switching time, which limits their application [1-3].

[0012] The converter employing the proposed control method can have any number of phases. Each phase of the converter includes a main section, an auxiliary section, a sensor section, and a control section. The main switch synthesizes a reference voltage at the phase output using the DC link voltage. The auxiliary circuitry facilitates zero-voltage switching of the main switch. The sensor section provides the necessary data to the control section to achieve near-guaranteed optimized zero-voltage switching. The control section provides gate signals for the main and auxiliary switches based on feedback signals from the sensor section to control the main and auxiliary circuitry, ensuring zero-voltage switching of the main switch and zero-current switching of the auxiliary switch while providing the desired voltage at the output point. These tasks are accomplished by adjusting the on and off time intervals of the switches and the overlap interval of the on states of the auxiliary and main switches based on the feedback signals. This method uses three sensors—a gate sensor, a dv / dt sensor, and a zero-voltage detection sensor—to find the optimal point for near-guaranteed zero-voltage switching.

[0013] According to one part of this disclosure, a power conversion device is provided, comprising: (a) a power section, which is an auxiliary resonant commutator (ARCP) based converter; and (ii) a control section, which uses information provided by a sensor network about system state and previous switching conditions to provide an appropriate gate pulse to the power section to synthesize a reference output signal, thereby ensuring zero-voltage switching of the main switch and zero-current switching of the auxiliary switch.

[0014] This device includes any number of phases for AC / DC, DC / AC, or DC / DC conversion. The control unit uses feedback signals dv / dt, gate, and ZVD, or any number of these sensors, to control the ZVS converter. The control unit synthesizes a reference signal at the converter output using the feedback signals gate and ZVD, ensuring zero-voltage switching under any conditions and operating point. The algorithm is used to dynamically find the optimal conversion time.

[0015] An exemplary embodiment of the present invention provides a controller for an assisted resonant commutator (ARCP) converter, the controller comprising: a sensor section including: a ZVD sensor configured to measure the voltage across a switch of the converter and detect the time when the voltage across the switch is equal to zero; a dv / dt sensor configured to measure the change in voltage across the switch over time and detect the voltage transition across the switch; and a gate sensor configured to measure the gate-source voltage of the switch and detect the time when the gate-source voltage is sufficient to cause the switch to transition between off and on; and a control section configured to: receive measurements from the ZVD sensor, the dv / dt sensor, and the gate sensor; and generate a control signal for the switch based at least in part on the measurements received from the ZVD sensor, the dv / dt sensor, and the gate sensor.

[0016] In some embodiments of the invention, the control section is further configured to receive load current, a first DC link voltage VC1, and a second DC link voltage VC2, wherein one or both of VC1 and VC2 can be measured directly or indirectly, and a control signal for switching is generated at least in part based on one or more of the load currents VC1 and VC2.

[0017] In some embodiments of the invention, the controller is configured to determine one of VC1 and VC2 based on the DC voltage.

[0018] In some embodiments of the present invention, the switch is the main switch of the converter.

[0019] In some embodiments of the present invention, the switch is an auxiliary switch of the converter.

[0020] In some embodiments of the invention, the control section is further configured to: determine the resonant time of the converter; and generate a control signal based at least in part on the resonant time.

[0021] In some embodiments of the present invention, the control portion further includes a feedforward portion, and the control portion is further configured to: determine an ideal switching signal for the switch using the feedforward portion; and generate a control signal based at least in part on the ideal switching signal.

[0022] In some embodiments of the invention, the sensor portion further includes a DC link voltage sensor and a load current sensor, and determining the ideal switching signal for the switch includes determining the ideal switching signal based at least in part on the DC link voltage measured by the DC link voltage sensor and the load current measured by the load current sensor.

[0023] In some embodiments of the invention, determining the ideal switching signal includes determining the ideal switching signal based at least in part on one or more nominal values ​​of one or more electrical components of the converter.

[0024] In some embodiments of the invention, generating a control signal for a switch includes determining a charging time for the switch, and generating the control signal includes generating the control signal at least in part based on the charging time.

[0025] In some embodiments of the invention, generating a control signal for a switch includes determining a dead time of the switch, and generating the control signal includes generating the control signal at least in part based on the dead time.

[0026] An exemplary embodiment of the present invention provides a controller for an assisted resonant commutator (ARCP) converter, the controller comprising: a sensor section including: a first ZVD sensor configured to measure the voltage across a first switch of the converter and detect the time when the voltage across the first switch is equal to zero; a first dv / dt sensor configured to measure the change in voltage across the first switch over time and detect the voltage transition across the first switch; a first gate sensor configured to measure the gate-source voltage of the first switch and detect the time when the gate-source voltage is sufficient to cause the first switch to transition between off and on; a second ZVD sensor configured to measure the voltage across a second switch of the converter and detect the time when the voltage across the second switch is equal to zero; a second dv / dt sensor configured to measure the change in voltage across the second switch over time and detect the voltage transition across the second switch; and a sensor configured to measure the voltage across the second switch... The system includes a gate-source voltage and a second gate sensor that detects the time during which the gate-source voltage is sufficient to switch the second switch between off and on; and a control section configured to: receive measurements from a first ZVD sensor, a second ZVD sensor, a first dv / dt sensor, a second dv / dt sensor, a first gate sensor, and a second gate sensor; generate a first control signal for the first switch based at least in part on the measurements received from one or more of the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor; and generate a second control signal for the second switch based at least in part on the measurements received from one or more of the first control signal, the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor.

[0027] In some embodiments of the present invention, the first switch is one of the first main switch of the converter and the first auxiliary switch of the converter.

[0028] In some embodiments of the present invention, the second switch is one of the second main switch of the converter and the second auxiliary switch of the converter.

[0029] An exemplary embodiment of the present invention provides a method for controlling an assisted resonant commutator (ARCP) converter, the method comprising: receiving a ZVD sensor signal from a ZVD sensor, wherein the ZVD sensor signal represents the voltage across a switch of the ARCP converter; receiving a dv / dt sensor signal from a dv / dt sensor, wherein the dv / dt sensor signal represents the voltage across the switch over time; receiving a gate sensor signal from a gate sensor, wherein the gate sensor signal represents the gate-source voltage of the switch; and generating a control signal for the switch based at least in part on the ZVD sensor signal, the dv / dt sensor signal, and the gate sensor signal.

[0030] In some embodiments of the present invention, the ZVD sensor signal indicates the time when the voltage across the switch is equal to zero.

[0031] In some embodiments of the present invention, the dv / dt sensor signal indicates the time when the voltage transition occurs across the switch.

[0032] In some embodiments of the invention, the gate sensor signal indicates a voltage sufficient to cause the switch to switch between off and on for a period of time.

[0033] In some embodiments of the present invention, the switch is the main switch of the converter.

[0034] In some embodiments of the present invention, the switch is an auxiliary switch of the converter. Attached Figure Description

[0035] To better understand the one or more embodiments described herein and to more clearly illustrate how one or more embodiments are implemented, reference is made below to the accompanying drawings, which are for illustrative purposes only, wherein: Figure 1A This is a schematic diagram of the phase of an auxiliary resonant commutator (ARCP) converter according to an exemplary embodiment of the present invention; Figure 1B This is for use according to an exemplary embodiment of the present invention. Figure 1A A block diagram of the control system of the ARCP converter is depicted in the figure. Figure 2 This is a flowchart of a control method for an ARCP converter according to an exemplary embodiment of the present invention; Figure 3 This is according to an exemplary embodiment of the present invention. Figure 2 The flowchart of the feedforward portion of the control method depicted in the diagram; Figure 4This is a flowchart of a method for determining dynamic half-resonance time according to an exemplary embodiment of the present invention; Figure 5 This is a schematic diagram of a zero-voltage sensor according to an embodiment of the present disclosure.

[0036] Figure 6 This is a schematic diagram of a dv / dt sensor according to an embodiment of the present disclosure.

[0037] Figure 7 This is a schematic diagram of a gate sensor according to an exemplary embodiment of the present invention.

[0038] Figure 7 This is a schematic diagram of a gate sensor according to an exemplary embodiment of the present invention. Detailed Implementation

[0039] For simplicity and clarity, reference numerals may be repeated in the drawings to indicate corresponding or similar elements where deemed appropriate. Furthermore, numerous specific details are set forth to provide a thorough understanding of one or more embodiments described herein. However, those skilled in the art will understand that the embodiments described herein can be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the embodiments described herein. It should first be understood that although exemplary embodiments are shown in the drawings and described below, the principles of this disclosure can be implemented using any number of techniques, whether or not such techniques are currently known. This disclosure should not be limited in any way to the exemplary embodiments and techniques shown in the drawings and described below.

[0040] Unless the context otherwise indicates, the various terms used throughout this specification may be interpreted and understood as follows: “or” as used throughout is open-ended, as in writing “and / or”; singular articles and pronouns as used throughout include their plural forms and vice versa; similarly, gender pronouns include their corresponding pronouns, and therefore the pronouns should not be construed as limiting anything described herein to use, implementation, performance, etc., of a single gender; “exemplary” should be understood as “illustrative” or “example”, and not necessarily “preferred” with respect to other embodiments. Further definitions of terms may be set forth herein; these further definitions may apply to instances preceding and following those terms, as should be understood by reading this specification. It should also be noted that unless otherwise expressly stated or unless it is understood that it is obvious that it is interpreted as “an”, the use of the terms “a” or “an” will in all instances be understood to mean “at least one”.

[0041] Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of this disclosure. For example, components of the systems and apparatuses may be integrated or separate. Furthermore, the operation of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components, and the described methods may include more, fewer, or other steps. Moreover, the steps may be performed in any suitable order. As used herein, "each" may mean each member of a set or each member of a subset of a set.

[0042] This paper discloses a control circuit and method for a zero-voltage switching converter. The control method uses one or more feedback sensors, which may include one or more main switch gate sensors, a zero-voltage sensor, and one or more main switch dv / dt sensors. These feedback sensors are utilized in conjunction with a closed-loop algorithm and a feedforward loop (which uses load current, converter parameters, and nominal values ​​of components, as well as other algorithms described herein) to calculate the next gate timing to achieve near-guaranteed ZVS. A similar method is proposed by Hamond et al. in U.S. Patent No. 10,367,413. However, the method described in that patent has limitations in providing near-guaranteed ZVS due to the lack of sensors (dv / dt sensors in the case of ARCP); furthermore, because the method does not include a feedforward loop, hard switching may occur in some cases under sudden load changes. Furthermore, U.S. Patent No. 10,367,413 does not consider all possible causes of soft-switching failure and does not take into account the true nature of the components, therefore the timing is not optimal. To address these issues, this disclosure provides a complete circuit and method for achieving near-guaranteed zero-voltage switching (ZVS) for a converter with a building block having two complementary switches. This control method nearly guarantees ZVS under virtually all operating and environmental conditions and manufacturing tolerances, including systems with high dynamic variations in load or DC link voltage, environments with wide temperature variations, and component values ​​with large tolerances (e.g., 30%). ZVS reduces stress on the switches and further reduces converter losses and EMI. Furthermore, the disclosed circuit and method can reduce the manufacturing complexity of converters employing synchronous rectifiers, etc. For example, three circuits 101 can be connected in parallel on the DC side to form a three-phase inverter, a converter well-known and used in industry. The power converter 101 also includes auxiliary circuitry 110 to facilitate zero-voltage switching. The method described herein is beneficial for all converters using similar building blocks with two complementary switches.

[0043] In the unipolar configuration, two semiconductor switches are connected in series between the positive and negative rails of DC link 120, with the midpoint being the phase output point. These two switches always operate in complementary mode and synthesize an analog reference waveform by modulating the DC link voltage. Auxiliary circuit 110 is connected to the midpoint of DC link 140 and the phase output point 130. Resonant capacitors 111 and 112 (collectively referred to as "Cr") are connected in parallel with the converter's main switches 121 and 122, respectively. Figure 1A As shown, the auxiliary circuit 110 also includes an inductor 115 and two switches 113 and 114 connected in series. With the help of the auxiliary circuit 110, the main power semiconductors or switches 121 and 122 of the converter switch at zero voltage (soft switching), which significantly reduces the switching losses and switching-related EMI of the converter.

[0044] exist Figure 1A In the configuration shown, to ensure that the main switches 121 and 122 of the converter switch at zero voltage, the resonant inductor (“Lr”) 115 must be charged to the calculated current level before the main switches 121 and 122 begin switching state transitions, and sufficient switching time should be provided. Several control methods proposed for this converter use an open-loop approach and calculate the time required to charge the resonant inductor and the switching time based on the nominal values ​​of the components and the load current; see references [A], [B], and [C] below. The values ​​of any given passive component are subject to tolerance, and the drain-source capacitance values ​​of some active components (such as MOSFETs) are variable. These variations lead to calculation errors, which in turn lead to errors in the calculated time, resulting in one or more of the following: partial hard switching, additional conduction and switching losses, stress on components, and high dv / dt. For example, positive manufacturing tolerances for inductor values ​​can result in the inductance value of any given passive component, and the drain-source capacitance values ​​of some active components (such as MOSFETs) are variable. These variations lead to calculation errors, which in turn cause errors in the calculated time, resulting in one or more of the following: partial hard switching, additional conduction and switching losses, stress on components, and high dv / dt. For example, a positive manufacturing tolerance in the inductance value compared to the actual required current may cause the inductor to be undercharged. Partial hard switching, accompanied by a high dv / dt, occurs because the energy stored in the inductor is insufficient to achieve soft switching.

[0045] In a unipolar converter, the switches operate in complementary modes, meaning that only one switch is on at any given time. During the transition from one switch to another, a time interval called the dead time is inserted, during which neither main switch is on. The proposed control method adjusts the timing of switching the main switches 121 and 122 based on the previous and / or historical switching conditions and the predicted switching time for the next step to achieve near-guaranteed zero-voltage switching. The described method significantly reduces switching and conduction losses, voltage stress on the switches, EMI, dv / dt filtering requirements, and thermal management requirements, and makes the converter more compact and efficient compared to soft-switching converters controlled by open-loop methods.

[0046] Figure 1B A block diagram of the disclosed system is shown. For example... Figure 1B As shown, the system comprises three parts, referred to as the power section 101, the control section 102, and the sensor section 103. Figure 1A An embodiment of the poles of the power section 101 is shown. For example... Figure 1A As shown, this pole comprises two parts, referred to as the main part 120 and the auxiliary part 110. The main part includes two switches T1 121 and T2 122, two associated anti-parallel diodes 125 and 126, and two DC link capacitors C1 123 and C2 124, which can be shared with other poles in the converter structure. The auxiliary part 110 includes two resonant capacitors 111 and 112, shown as Cr1 and Cr2 (connected in parallel with the main switches 121 and 122, shown as T1 and T2, respectively), two auxiliary switches 113 and 114, shown as Ta1 and Ta2, two auxiliary diodes 116 and 117, shown as Da1 and Da2, and a resonant inductor 115, shown as Lr. Main switches 121 and 122 are connected in series between the positive rail 150 of the DC link and the negative rail 160 of the DC link 140, such that the drain of the upper switch 121 is connected to the positive rail 150, similar to how a capacitor is connected in series between the positive rail 150 and the negative rail 160 of the DC link 140. These capacitors divide the DC link voltage into two voltages, VC1 171 and VC2 172, each of which should nominally be VDC / 2.

[0047] An auxiliary branch is formed by auxiliary switches and auxiliary diodes in conjunction with a resonant inductor, connecting the midpoint (midpoint) of DC link 140 to the output point 130 of the converter. In this branch, auxiliary diodes (116, 117) are connected in parallel with each auxiliary switch (113, 114), respectively. The auxiliary switches are used to charge inductor 115 to a predetermined desired current level to fully discharge and charge the resonant capacitor as needed. This current is referred to as the auxiliary branch current (Ix). To calculate this current, the load current (“IL”) flowing through branch 130 is sensed and fed back to the control algorithm. The charging time can then be calculated based on the midpoint voltage, and the conversion time can also be calculated based on Ix and the resonant time of the LC resonant circuit formed by resonant inductor 115 and capacitors 111, 112.

[0048] The sensor section 103 determines various electrical measurement values ​​of the power section 110 and provides these electrical measurement values ​​to the control section 102 for controlling the power section 101. The electrical measurement values ​​may include: V DS-T1 —The voltage across diode D1 (125) is also the voltage between the source and drain of switch T1 (121); V GS-T1 —The voltage between the source of switch T1 (121) and ground; V DS-T2 —The voltage across diode D2 (126) is also the voltage between the source and drain of switch T2 (122); V GS-T2 —The voltage between the source and ground of switch T2 (122); Signals from one or more ZVD sensors, which measure the voltage on the main switch of the converter and detect the time when the voltage on the switch reaches zero; The signal comes from one or more dv / dt sensors, which uses the measured voltage across the main switch of the converter and quantizes the voltage transition time across the switch. Signals from one or more ZVD sensors, which measure the voltage on the main switch of the converter and detect the time when the voltage on the switch reaches zero; Signals from one or more dv / dt sensors, which use the measured voltage across the main switch of the converter and quantize the voltage transition time across the switch, and Signals from one or more gate sensors that measure the gate-source voltage of the main switch of the converter and detect the on and off times of the switch, optionally taking into account the Miller effect.

[0049] The control section 102 uses the signals provided by the sensor section 103 in conjunction with a control algorithm to control the main section and the auxiliary section. Figure 2 An example embodiment of the control algorithm is shown. After the VC1 and VC2 voltages and the load current IL are obtained from the sensors 103 associated with 171, 172, and 173 in 201 respectively, the feed-forward section 202 provides the timing of the charging time and the dead time (CT and DT respectively) for the next switching event based on the load current, the VC1 and VC2 voltages, and the nominal values of the components. However, in reality, the components have non-idealities and tolerances in terms of their nominal values, which results in errors in the calculated times, leading to ZVS failure. Therefore, the closed-loop section or closed-loop block 203 is designed to compensate for this error. Since there is a closed-loop section to compensate for the error, the formula in the feed-forward section can be simplified compared to known open-loop methods. There is no need to consider the impact of circuit losses on timing, nor is it necessary to perform precise calculations of the timing.

[0050] In some embodiments, the control section can be used to maintain the balance of the DC capacitor voltage; for example, the midpoint balance control block 204, such as but not limited to the control system described in U.S. Patent US 63 / 451,758, the content of which is incorporated herein by reference.

[0051] After calculating the final charging time and dead time (CT’ and DT’ respectively), the gate pulses are generated by block 207 based on the reference voltage.

[0052] Figure 3 The feed-forward section of the control algorithm is shown. In some embodiments, the charging time CT can be calculated by the general formula and the transition time DT (dead time between the main switches - that is, the time when both switches 121 and 122 are in the off state) is equal to half of the resonant time Clearly, half of the resonant time depends on the values ​​of the resonant elements Lr and Cr. In some embodiments, after obtaining VC1 and VC2 and the load current IL value from the sensors (block 301), the control algorithm determines whether the load current will contribute to the switching (block 302). If IL contributes to the switching, the feedforward control sets CT to zero and DT to half of the resonant time (block 303). In another embodiment, CT can take a negative value, and CT and DT will be calculated by block 306 instead of block 303. If IL does not contribute to the switching, CT is calculated using the formula mentioned in block 304. This section or block 305 outputs approximate DT and CT values, which will be fed to... Figure 2 The closed loop portion or closed loop block 203.

[0053] The algorithm also uses measurements to find the actual resonant time of the resonant circuit. This value serves as a reference for the algorithm to keep the transition time nearly constant and avoid high dv / dt. This detection can be accomplished using a dv / dt sensor and a gate sensor in conjunction with load current measurement, or using a zvd sensor and a gate sensor in conjunction with load current measurement.

[0054] Using these sensors, the closed-loop algorithm determines that a perfect ZVS failure is due to one or more of the following reasons: too short / too long transition time, too short / too long charging time, or too short / too long discharging time. For example, if the gate sensor detects that the main switch is turned on before the drain-source voltage of the switch drops to zero, there are two possibilities: insufficient charging time or a transition time shorter than required. Using other sensor information, the algorithm can detect the exact cause and take compensatory measures.

[0055] Since it is difficult to know or measure the values ​​of the resonant elements (Lr and Cr), especially when large-scale production is involved, it is best to use feedback sensors to detect or estimate the half-resonance time value. Therefore, in some embodiments, the half-resonance time (“HR”) is dynamically found during the inverter switching process to account for the effects of component manufacturing tolerances, main and auxiliary switch response delays, and other non-ideals on the HR. Figure 4An algorithm for dynamically finding the HR is illustrated. The HR is equal to (401) dv / dt (405) only if zero voltage (POL=1) is detected before reaching the gate threshold (402), and IL is greater than the minimum (403) (or a negative value less than the minimum), and CT is greater than zero and less than the maximum allowable value (404). If this embodiment includes dynamically finding the HR (400), the value found for the HR will replace the half-resonance time value found for DT in 306. Algorithm 400 can also be operated individually for each phase in the case of a multiphase inverter, thereby optimizing each phase for its own Lr and Cr, as well as switching delays and other non-ideals.

[0056] Closed-loop block 203 uses information provided by sensors to analyze the impact of circuit non-idealities and tolerances on ZVS quality, and then adjusts the timing provided by the feedforward section in an attempt to obtain near-guaranteed optimal ZVS.

[0057] In some embodiments, the feedforward portion 202 may be omitted, and only the closed-loop portion 203 is used to implement ZVS. In these embodiments, the initial dead time is set to the maximum expected dead time and the charging time is set to zero, and then the control system uses feedback values ​​from the sensors to initiate closed-loop control.

[0058] By application Figure 2 The trigger pulse generated by block 207 compensates for the effects of non-ideals, thus nearly guaranteeing optimal ZVS. Therefore, compared to an open-loop ZVS converter, this embodiment exhibits lower component stress and a longer converter lifespan. Furthermore, conduction losses, switching losses, and EMI are reduced.

[0059] The closed-loop section uses information provided by the sensor section to ensure zero-voltage switching. To determine accurate switching behavior, three types of sensors are required: (1) a ZVD sensor, which measures the voltage on the main switch and detects the time when the voltage on the switch reaches zero; (2) a dv / dt sensor, which uses the measured voltage on the main switch and quantifies the voltage transition time on the switch; and (3) a gate sensor, which measures the gate-source voltage of the main switch and detects the turn-on and turn-off times of the switch, taking into account the Miller effect.

[0060] Figure 5An embodiment of a ZVD sensor is shown. The sensor includes a comparator that compares the drain voltage of a transistor with a reference voltage and outputs a logic "1" when the drain voltage is greater than the reference voltage. To ensure the safety of the electronic circuitry and keep it within permissible voltage ranges, R1, D3, and D4 are used to reflect high drain voltages in capacitor C1. Whenever the drain voltage is greater than approximately 5V, diode D3 stops conducting, clamping the voltage across capacitor C1 to almost 5V. When the drain voltage is less than 5V, D3 turns on, and the voltage across C1 follows the drain voltage variation. Therefore, the zero drain voltage of interest described herein can be sensed by sensing the voltage across C1.

[0061] Figure 6 An embodiment of a dv / dt sensor is shown. This dv / dt sensor includes a comparator and a high-pass filter. The illustrated dv / dt sensor detects only the falling edge, which is of interest to the closed-loop algorithm. When the drain voltage changes, the high-pass filter draws current from resistor R2 and capacitor C3, causing the voltage across C3 to drop below the comparator's reference voltage. Therefore, in this case, the comparator outputs logic "1". When the drain voltage stabilizes, no current flows through C1 (i.e., when the voltage across C1 is constant, no current flows through C1), and the voltage across C3 stabilizes at 5V, which is higher than the comparator's reference voltage; therefore, the comparator outputs logic "0". The use of this sensor is crucial for the correct operation of this embodiment and ZVS, as it can distinguish and compensate for non-ideal ZVS conditions.

[0062] Figure 7 A gate signal sensor is shown. This sensor consists of a comparator, a voltage divider, and a low-pass filter. The voltage divider regulates the gate signal to an acceptable range. The comparator outputs a logic "1" when the gate voltage level is greater than a reference voltage regulated to the end of the Miller plateau. Hysteresis is set in the comparator through resistor R5. This hysteresis keeps the comparator's falling edge threshold at a lower level of the Miller plateau. Therefore, if the gate voltage is less than the lower limit of the Miller plateau, the comparator outputs a logic "0". Using these sensors, it is possible to detect situations where perfect ZVS is not achieved and the reasons for this. However, in some embodiments, not all of these sensors are required.

[0063] In one aspect, a control method for a zero-voltage switching converter is provided that compensates for the detrimental effects of component non-ideality, characteristic variations due to temperature, voltage, and current operating points, and delays in the switching circuitry. This control method can be used in any converter with two complementary switches. One embodiment is a converter based on an auxiliary resonant commutator (ARCP) with an arbitrary number of phases, where each phase includes two main switches and associated anti-parallel diodes connected between the phase output point and the positive and negative rails of the DC link. For example, the switches can be IGBTs or MOSFETs. Two resonant capacitors are connected in parallel with each main switch. In another aspect, a voltage divider DC link is provided, having two capacitors, one connected in series between the positive rail and the midpoint of the DC link, and the other connected in series between the midpoint and the negative rail. An auxiliary branch can include a variable inductor and two switches connected between the midpoint of the DC link and the phase output point. In one aspect of the control method, only the feedback portion can be used, omitting the feedforward portion. Furthermore, in some embodiments, one or more sensors can be omitted, depending on the acceptability of partial hard switching. Because the closed-loop part is based on a logic-based approach, while the open-loop part benefits from very simple mathematical calculations, this control is well-suited for digital implementation and high-speed switching applications.

[0064] Although specific advantages have been listed above, various embodiments may include some of the listed advantages, exclude the listed advantages, or include all of the listed advantages.

[0065] Those skilled in the art will understand that many other possible alternative implementations and modifications exist, and the examples above are merely illustrative of one or more implementations. Therefore, the scope is limited only by the appended claims and any modifications thereof.

[0066] Terminology Explanation Unless the context explicitly requires it, throughout the specification and claims: "Including" and "containing" should be interpreted as inclusive, not exclusive or exhaustive; that is, it means "including but not limited to". "Connection", "coupling" or any variation thereof means any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements can be physical, logical or a combination thereof; The words “this document,” “above,” “below,” and similar terms, when used to describe this specification, shall refer to the entire specification and not any particular part thereof. When “or” refers to a list of two or more items, it encompasses all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list; The singular forms such as “a”, “an”, and “the” also include the meaning of any appropriate plural form.

[0067] Terms indicating direction, such as “vertical,” “horizontal,” “upward,” “downward,” “forward,” “backward,” “inward,” “outward,” “vertical,” “lateral,” “left,” “right,” “front,” “back,” “top,” “bottom,” “below,” “above,” and “below,” are used in this specification and any appended claims (if any) depending on the specific orientation of the described and illustrated device. The subject matter described herein can be adopted in various alternative orientations. Therefore, these directional terms are not strictly limited and should not be interpreted narrowly.

[0068] Embodiments of the present invention may be implemented using specially designed hardware, configurable hardware, a programmable data processor configured by providing software (optionally including "firmware") executable on a data processor, a dedicated computer or data processor specifically programmed, configured, or constructed to perform one or more steps of the methods explained in detail herein, and / or a combination of two or more of these. Examples of specially designed hardware include: logic circuits, application-specific integrated circuits ("ASICs"), large-scale integrated circuits ("LSIs"), very large-scale integrated circuits ("VLSIs"), etc. Examples of configurable hardware include: one or more programmable logic devices, such as programmable array logic ("PALs"), programmable logic arrays ("PLAs"), and field-programmable gate arrays ("FPGAs"). Examples of programmable data processors include: microprocessors, digital signal processors ("DSPs"), embedded processors, graphics processors, math coprocessors, general-purpose computers, server computers, cloud computers, mainframe computers, computer workstations, etc. For example, one or more data processors in the control circuitry of a device may implement the methods described herein by executing software instructions in a processor-accessible program memory.

[0069] For example, while processes or blocks may be presented in a given order, alternative examples may execute routines with multiple steps in a different order or employ systems with multiple blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternatives or sub-combinations. Each of these processes or blocks can be implemented in a variety of different ways. Furthermore, while processes or blocks are sometimes shown as being executed in sequence, these processes or blocks may be executed in parallel or at different times.

[0070] Furthermore, although the elements are sometimes shown to be executed sequentially, they may also be executed simultaneously or in a different order. Therefore, the following claims are intended to be construed as including all such variations within their intended scope.

[0071] Where references to elements (e.g., switches, processors, components, devices, circuits, etc.) are made above, unless otherwise stated, references to such elements (including references to “method”) shall be construed as including any element that performs the function of said element as an equivalent of that element (i.e., functionally equivalent), including elements that are structurally different from the disclosed structure that performs the function in the exemplary embodiments illustrated in the present invention.

[0072] Various features are described herein as existing in “some embodiments.” These features are not essential and are not present in all embodiments. Embodiments of the invention may include zero, any one of these features, or any combination of two or more such features. This is limited to the extent that some of these features are incompatible with others, in a sense that it would be impossible for someone skilled in the art to construct a practical embodiment incorporating these incompatible features. Therefore, the description of “some embodiments” having feature A and “some embodiments” having feature B should be interpreted as an explicit indication that the inventors have also considered embodiments combining features A and B (unless otherwise stated in the description or features A and B are fundamentally incompatible).

[0073] Therefore, the appended claims and subsequently introduced claims are to be interpreted to include all modifications, arrangements, additions, omissions, and sub-combinations that can be reasonably inferred. The scope of the claims should not be limited to the preferred embodiments set forth in the examples, but should be given the broadest interpretation consistent with the entire specification.

[0074] References [A] TD Batzel and K. Adams, “Variable timing control for ARCPvoltage source inverters operating at low DC voltage”, IEEE Transportation Electrification 2012 International Conference and Exhibition (ITEC) Dearborn, Michigan, USA, 2012, pp. 1–8, doi:10.1109 / ITEC.2012.6243478.

[0075] [B] Ke Ma, Dehong Xu, Tao Zhang and S. Igarashi, “The evaluation of control strategies for Auxiliary Resonant Commutated Pole inverter”, 2009 IEEE Energy Conversion Conference & Expo (ECCE) San Jose, California, USA, 2009, pp. 810-816, doi:10.1109 / ECCE.2009.5315974.

[0076] [C] J. Voss, J. Henn, and RW De Doncker, “Control techniques of the auxiliary-resonant commutated pole with special regards on the dual-activebridge DC-DC converter,” CPSS Journal of Power Electronics Technology and Application, Vol. 3, No. 4, pp. 352-361, December 2018, doi: 10.24295 / CPSSTPEA.2018.00034.

Claims

1. A controller for an auxiliary resonant commutator ARCP converter, the controller comprising: The sensor component includes: The ZVD sensor is configured to measure the voltage across the switch of the converter and detect the time when the voltage across the switch is equal to zero. A dv / dt sensor is configured to measure the change in voltage across the switch over time and to detect voltage transitions across the switch; and A gate sensor is configured to measure the gate-source voltage of the switch and detect the time during which the gate-source voltage is sufficient to cause the switch to switch between off and on states; and The control section is configured as follows: Receives measurement values ​​from the ZVD sensor, the dv / dt sensor, and the gate sensor; and Control signals for the switch are generated based at least in part on the measurements received from the ZVD sensor, the dv / dt sensor, and the gate sensor.

2. The controller according to claim 1, wherein, The control section is also configured to receive a load current, a first DC link voltage VC1, and a second DC link voltage VC2, wherein one or both of VC1 and VC2 can be measured directly or indirectly, and to generate a control signal for the switch based at least in part on the load current, VC1, and VC2.

3. The controller according to claim 2, wherein, The controller is configured to determine one of VC1 and VC2 based on the DC voltage.

4. The controller according to any one of claims 1 to 3, wherein, The switch is the main switch of the converter.

5. The controller according to any one of claims 1 to 3, wherein, The switch is an auxiliary switch for the converter.

6. The controller according to any one of claims 1 to 5, wherein, The control unit is also configured to: Determine the resonant time of the converter; and The control signal is generated at least in part based on the resonant time.

7. The controller according to any one of claims 1 to 6, wherein, The control section also includes a feedforward section, and the control section is further configured to: The ideal switching signal for the switch is determined using the feedforward portion; and The control signal is generated at least in part based on the ideal switching signal.

8. The controller according to claim 7, wherein, The sensor section further includes a DC link voltage sensor and a load current sensor, and determining the ideal switching signal of the switch includes: determining the ideal switching signal based at least in part on the DC link voltage measured by the DC link voltage sensor and the load current measured by the load current sensor.

9. The controller according to claim 7 or 8, wherein, Determining the ideal switching signal includes determining the ideal switching signal based at least in part on one or more nominal values ​​of one or more electrical components of the converter.

10. The controller according to any one of claims 1 to 9, wherein, Generating the control signal for the switch includes determining the charging time of the switch, and generating the control signal includes generating the control signal at least in part based on the charging time.

11. The controller according to any one of claims 1 to 10, wherein, Generating the control signal for the switch includes determining the dead time of the switch, and generating the control signal includes generating the control signal at least in part based on the dead time.

12. A controller for an auxiliary resonant commutator ARCP converter, the controller comprising: The sensor component includes: A first ZVD sensor is configured to measure the voltage across a first switch of the converter and detect the time when the voltage across the first switch is equal to zero. A first dv / dt sensor is configured to measure the change in voltage across the first switch over time and to detect voltage transitions across the first switch; and A first gate sensor is configured to measure the gate-source voltage of the first switch and detect the time during which the gate-source voltage is sufficient to cause the first switch to switch between off and on. The second ZVD sensor is configured to measure the voltage across the second switch of the converter and detect the time when the voltage across the second switch is equal to zero. A second dv / dt sensor is configured to measure the change in voltage across the second switch over time and to detect voltage transitions across the second switch; and A second gate sensor is configured to measure the gate-source voltage of the second switch and detect the time during which the gate-source voltage is sufficient to cause the second switch to switch between off and on states; and The control section is configured as follows: Receive measurement values ​​from the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor; A first control signal for the first switch is generated, at least in part, based on measurements received from one or more of the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor; and A second control signal for the second switch is generated based at least in part on measurements received from one or more of the first control signal, the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor.

13. The controller according to claim 12, wherein, The first switch is one of the first main switch and the first auxiliary switch of the converter.

14. The controller according to claim 12 or 13, wherein, The second switch is one of the second main switch and the second auxiliary switch of the converter.

15. A method for controlling an auxiliary resonant commutator ARCP converter, the method comprising: Receive a ZVD sensor signal from the ZVD sensor, wherein the ZVD sensor signal represents the voltage across the switch of the ARCP converter; Receive dv / dt sensor signal from dv / dt sensor, wherein the dv / dt sensor signal represents the change of voltage across the switch over time; Receive a gate sensor signal from a gate sensor, wherein the gate sensor signal represents the gate-source voltage of the switch; and Control signals for the switch are generated based at least in part on the ZVD sensor signal, the dv / dt sensor signal, and the gate sensor signal.

16. The method according to claim 15, wherein, The ZVD sensor signal indicates the time when the voltage across the switch is equal to zero.

17. The method according to any one of claims 15 and 16, wherein, The dv / dt sensor signal indicates the time when the voltage transition occurs across the switch.

18. The method according to any one of claims 15 to 17, wherein, The gate sensor signal indicates the time during which the voltage is sufficient to cause the switch to switch between off and on.

19. The method according to any one of claims 15 to 18, wherein, The switch is the main switch of the converter.

20. The method according to any one of claims 15 to 18, wherein, The switch is an auxiliary switch for the converter.

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