High-noise-margin self-adaptive rotating speed signal processing device, tachometer and rotating speed determination method

Abstract

The invention discloses a high-noise-margin self-adaptive rotating speed signal processing device, a tachometer and a rotating speed determination method, which are applied to the technical field of signal processing and are used for solving the problem that the real rotating speed cannot be accurately obtained because the rotating speed measurement result exceeds the range due to noise interference in the prior art. Specifically, a current rotating speed peak value is detected; setting a corresponding candidate threshold value as a target comparison threshold value according to the gear selection signal; filtering noise in the current pulse rotating speed signal by using the target comparison threshold to obtain a target pulse rotating speed signal; determining the current rotating speed according to the target pulse rotating speed signal, and judging the current rotating speed; if the continuous preset number of rotating speed judgment results are rotating speed outrange, switching the target comparison threshold value until the continuous preset number of rotating speed judgment results are effective rotating speed, and outputting the current rotating speed. Through peak value dynamic detection and self-adaptive threshold adjustment, noise signals are effectively filtered out, it is ensured that rotating speed measurement is within a rotating speed range, and the accuracy and reliability of measurement are improved.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a high noise-tolerance adaptive speed signal processing device, a tachometer, and a speed determination method. Background Technology

[0002] In nuclear testing systems, tachometers are critical safety instruments for monitoring the rate of power change during reactor startup, power operation, and shutdown. Their accuracy directly impacts reactor safety. In engineering practice, magnetoelectric sensors typically collect magnetic pulse signals from the reactor rotor, which are then converted into frequency signals by the tachometer to calculate the rotational speed. However, in complex nuclear industrial environments, strong electromagnetic interference often contaminates the magnetic pulse signals, leading to abnormal fluctuations in rotational speed display, inaccurate measurements within the specified range, and even outputs exceeding the range. This results in the inability to obtain the true rotational speed, posing a safety hazard.

[0003] Currently, to avoid the influence of noise signals on effective magnetic pulse signals and accurately measure the rotational speed of the target turntable, traditional tachometers generally use a fixed voltage threshold for pulse discrimination. However, this method cannot adapt to dynamic fluctuations in signal amplitude caused by sensor installation gaps, changes in operating conditions, and transmission attenuation, easily leading to missed detection of effective signals or misjudgment of noise, resulting in incorrect rotational speed calculations. Existing improvement methods rely on technicians manually adjusting the threshold on-site, but in the special environment of nuclear facilities, such adjustments are difficult to implement, costly, and dependent on human experience, lacking real-time adaptability, severely restricting the reliability and accuracy of measurements. Therefore, there is an urgent need for a rotational speed signal processing device that can automatically adapt to signal changes and has high noise tolerance, to fundamentally solve the problem of measurement over-range caused by noise interference and ensure the continuous accuracy of rotational speed measurements in nuclear measurement systems. Summary of the Invention

[0004] This application provides a high noise-tolerance adaptive speed signal processing device and tachometer to solve the problem in the prior art where the speed measurement result is out of range due to noise interference, making it impossible to accurately obtain the true speed.

[0005] The technical solutions provided in this application are as follows: On the one hand, embodiments of this application provide a high noise-tolerance adaptive speed signal processing device, including: a signal preprocessing module, a peak dynamic detection module, an adaptive threshold generation module, and a CPLD module; The input terminal of the signal preprocessing module is connected to the output terminal of the speed sensor; the signal preprocessing module is used to receive the original speed signal, perform pulse shaping processing on the original speed signal, and obtain the current pulse speed signal. The input of the peak dynamic detection module is connected to the output of the signal preprocessing module. The peak dynamic detection module is used to detect the instantaneous voltage amplitude of the current pulse speed signal in real time and obtain the current speed peak value. The input of the adaptive threshold generation module is connected to the output of the signal preprocessing module and the peak dynamic detection module, respectively. The adaptive threshold generation module is used to generate multiple candidate thresholds corresponding to different gears based on the current speed peak. It receives the gear selection signal output by the CPLD module, uses the candidate threshold corresponding to the gear selection signal as the target comparison threshold, and performs noise filtering on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal. The input terminal of the CPLD module is connected to the output terminal of the adaptive threshold generation module, the first output terminal of the CPLD module is connected to the control terminal of the adaptive threshold generation module, and the second output terminal of the CPLD module is connected to an external display device. The CPLD module is used to determine the current speed based on the target pulse speed signal; to perform speed judgment on the current speed based on the effective speed range, and to obtain the speed judgment result; when a preset number of speed judgment results show that the speed is out of range, the target comparison threshold used by the adaptive threshold generation module is adjusted through the gear selection signal until a preset number of speed judgment results show that the speed is valid, and then the corresponding current speed is output to the external display device.

[0006] Optionally, the CPLD module includes: a pulse counting module, a speed filtering analysis module, a range judgment module, and a gear management module; the pulse counting module, speed filtering analysis module, range judgment module, and gear management module are connected in series; the input terminal of the pulse counting module is connected to the output terminal of the adaptive threshold generation module; the first output terminal of the gear management module is connected to the control terminal of the adaptive threshold generation module, and the second output terminal of the gear management module is connected to an external display device. The pulse counting module is used to count the number of valid pulses of the target pulse speed signal within the measurement window, and to determine the original speed based on the number of valid pulses; The speed filtering and analysis module is used to perform exponential smoothing on the original speed to obtain the current speed; The range judgment module is used to compare the current speed with the effective speed range and output the speed judgment result of speed exceeding the range or speed being valid; among them, the speed judgment result of speed exceeding the range includes the upper limit of speed exceeding the range and the lower limit of speed exceeding the range. The gear management module is used to gradually increase the target comparison threshold through the gear selection signal when the number of consecutive speed judgment results exceeding the upper limit of the range reaches a preset number, until the preset number of valid speed results are received. Then, it controls the adaptive threshold generation module to maintain the corresponding target comparison threshold and outputs the current speed to the external display device. Conversely, when the number of consecutive speed judgment results exceeding the lower limit of the range reaches a preset number, it gradually decreases the target comparison threshold through the gear selection signal, until the preset number of valid speed results are received. Then, it controls the adaptive threshold generation module to maintain the corresponding target comparison threshold and outputs the current speed to the external display device.

[0007] Optionally, the speed filtering analysis module is also used to obtain the speed after exponential smoothing in the previous measurement window as the historical speed; calculate the speed change between the current speed and the historical speed; and output the historical speed as the current speed when the speed change is greater than the preset speed change threshold.

[0008] Optionally, the gear management module is also used to determine the current speed change rate based on the speed change within a preset mutation monitoring time when the number of continuously received speed judgment results exceeding the lower limit of the range reaches a preset number; when the current speed change rate is greater than the corresponding speed mutation threshold, the target comparison threshold is lowered by a preset number of gears through the gear selection signal; when the current speed change rate is not greater than the speed mutation threshold, the target comparison threshold is lowered by one gear through the gear selection signal; until a preset number of valid speed judgment results are continuously received, the current target comparison threshold is maintained and the current speed is output.

[0009] Optionally, the CPLD module also includes: a peak sampling timing control module; and a peak dynamic detection module including a peak hold module and at least two peak detection modules. The input terminal of each peak detection module is connected to the output terminal of the signal preprocessing module, the output terminal of each peak detection module is connected to the input terminal of the peak hold module, the control terminal of each peak detection module is connected to the output terminal of the peak sampling timing control module, and the output terminal of the peak hold module is connected to the input terminal of the adaptive threshold generation module. The peak sampling timing control module is used to select two peak detection modules from at least two peak detection modules as a peak detection module group, and output timing-interleaved rotation control signals to the two peak detection modules in the peak detection module group, so that the two peak detection modules in the peak detection module group alternately enter detection mode and discharge mode, and at any time at least one peak detection module is in detection mode; In detection mode, the peak detection module detects the instantaneous voltage amplitude of the current pulse speed signal and outputs the valid signal peak value to the peak holding module; in discharge mode, it performs a reset operation and stops outputting the valid signal peak value. The peak hold module is used to buffer and convert the effective signal peak value to digital-to-analog conversion, obtain the current speed peak value, and output it.

[0010] Optionally, the peak detection module includes: a first comparator, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a first controllable switch, and a second controllable switch; The non-inverting input of the first comparator is connected to the output of the first operational amplifier, the inverting input of the first comparator is connected to the output of the signal preprocessing module, and the output of the first comparator is connected to the inverting input of the first operational amplifier via the first resistor. The non-inverting input of the first operational amplifier is connected to ground, and the output of the first operational amplifier is connected to the non-inverting input of the second operational amplifier via the second resistor; the third resistor, the first capacitor, and the first controllable switch are connected in parallel between the inverting input of the first operational amplifier and the output of the first operational amplifier, respectively. The first terminal of the second capacitor is connected between the second resistor and the non-inverting input terminal of the second operational amplifier, and the second terminal of the second capacitor is connected to ground; the second controllable switch is connected in parallel with the second capacitor; The inverting input of the second operational amplifier is connected to the output of the second operational amplifier, and the output of the second operational amplifier is connected to the input of the peak hold module. The control terminals of the first and second controllable switches are respectively connected to the peak sampling timing control module.

[0011] Optionally, the adaptive threshold generation module includes: a multi-threshold generation module, a gating switch, a timing selection logic circuit, and a noise filtering module; The input terminal of the multi-threshold generation module is connected to the output terminal of the peak dynamic detection module, and each output terminal of the multi-threshold generation module is connected to the corresponding input terminal of the gating switch; the control terminal of the gating switch is connected to the output terminal of the timing selection logic circuit, and the output terminal of the gating switch is connected to the input terminal of the noise filtering module; the output terminal of the noise filtering module is connected to the input terminal of the CPLD module; the input terminal of the timing selection logic circuit is connected to the first output terminal of the CPLD module. The timing selection logic circuit is used to generate the channel selection signal for the gating switch based on the gear selection signal; The multi-threshold generation module is used to generate multiple candidate thresholds for different gears based on the current peak speed; The gating switch is used to select the candidate threshold corresponding to the gear selection signal as the target comparison threshold under the control of the channel selection signal; The noise filtering module is used to perform noise filtering on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal.

[0012] Optionally, the multi-threshold generation module includes: a series voltage divider resistor network and multiple buffers; A series voltage divider resistor network is connected between the current speed peak and ground, forming multiple voltage divider nodes. Each voltage divider node corresponds to a candidate threshold. Each voltage divider node is connected to the input terminal of the gating switch via a corresponding buffer.

[0013] Optionally, the signal preprocessing module includes: a shaping filter circuit and a one-way integrating comparison circuit; The input terminal of the shaping filter circuit is connected to the output terminal of the speed sensor, and the output terminal of the shaping filter circuit is connected to the input terminal of the one-way integral comparison circuit; the output terminal of the one-way integral comparison circuit is connected to the input terminals of the peak dynamic detection module and the adaptive threshold generation module, respectively. The shaping and filtering circuit is used to limit, bandpass filter and pulse shape the original speed signal to obtain a pre-shaped pulse signal; The unidirectional integration and comparison circuit is used to perform threshold comparison on the pre-shaped pulse signal, and to perform unidirectional integration on the pre-shaped pulse signal that passes the comparison to obtain the current pulse speed signal.

[0014] Optionally, the unidirectional integrator-comparator circuit includes: a second comparator, a threshold voltage divider network, and a unidirectional integrator; The non-inverting input of the second comparator is connected to the output of the shaping filter circuit, the inverting input of the second comparator is connected to the output of the threshold voltage divider network, and the output of the second comparator is connected to the input of the one-way integrator. The output of the one-way integrator is connected to the inputs of the peak dynamic detection module and the adaptive threshold generation module, respectively. The threshold voltage divider network is used to output the integral threshold; The second comparator is used to compare the pre-shaped pulse signal with the integration threshold and output the effective pulses in the pre-shaped pulse signal that are higher than the integration threshold. A one-way integrator is used to perform one-way integration on the effective pulse to generate the current pulse speed signal.

[0015] Optionally, the high noise-tolerant adaptive speed signal processing device also includes: a self-test selection module; The first input terminal of the self-test selection module is connected to the output terminal of the speed sensor, the second input terminal of the self-test selection module is connected to an external standard pulse source, and the output terminal of the self-test selection module is connected to the CPLD module. The self-test selection module is used to connect the speed sensor to the signal preprocessing module, or to connect an external standard pulse source to the signal preprocessing module. The CPLD module, when self-test enable is active, sends a channel switching command to the self-test selection module, enabling the self-test selection module to connect the external standard pulse source and the signal preprocessing module. After connecting the standard pulse source, the current speed when the speed determination result is valid is used as the measured speed. The speed error between the measured speed and the theoretical speed of the standard pulse source is determined. If the speed error is within the preset error range, a self-test result of passing is generated; if the speed error is not within the preset error range, a self-test result of failing is generated.

[0016] Optionally, the high noise-tolerant adaptive speed signal processing device also includes: a fault indication module; The input terminal of the fault indication module is connected to the CPLD module; The fault indication module is used to execute the fault indication corresponding to the fault signal after receiving the first fault signal, the second fault signal or the third fault signal; The CPLD module is used to determine a sensor detachment fault when no target pulse speed signal is received within a preset detection time and the target comparison threshold of the adaptive threshold generation module is the candidate threshold of the lowest gear, and sends a first fault signal to the fault indication module; when the target comparison threshold of the adaptive threshold generation module is the candidate threshold of the highest gear and a preset number of speed judgment results show speed exceeding the range, it determines a hardware saturation fault and sends a second fault signal to the fault indication module; when it is determined that the adaptive threshold generation module has failed to maintain the target comparison threshold within a preset deadlock time, it determines a logic deadlock fault and sends a third fault signal to the fault indication module.

[0017] On the other hand, embodiments of this application provide a high noise-tolerant adaptive tachometer, including: a speed sensor, a display device, and the aforementioned high noise-tolerant adaptive speed signal processing device; The output of the speed sensor is connected to the input of the speed signal processing device; the input of the display device is connected to the output of the speed signal processing device.

[0018] On the other hand, embodiments of this application provide a high-noise-tolerance adaptive rotational speed determination method, including: The original speed signal output by the speed sensor is acquired, and the original speed signal output by the speed sensor is pulse shaped to obtain the current pulse speed signal. Real-time detection of the instantaneous voltage amplitude of the current pulse speed signal to obtain the current peak speed; Multiple candidate thresholds corresponding to different gears are generated based on the current peak speed, and one of the candidate thresholds is set as the target comparison threshold according to the gear selection signal; noise filtering is performed on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal; The current speed is determined based on the target pulse speed signal; the current speed is judged based on the effective speed range to obtain the speed judgment result; if the speed judgment result is over the range for a consecutive preset number of times, the gear selection signal is adjusted to switch the target comparison threshold until the speed judgment result is valid for a consecutive preset number of times, and then the current speed is output.

[0019] The beneficial effects of the embodiments of this application are as follows: In this embodiment, the peak value of the pulse speed signal is acquired in real time by the peak dynamic detection module, and multiple candidate thresholds are dynamically generated by the adaptive threshold generation module based on the peak value. The CPLD module performs range verification on the speed calculation results under each candidate threshold and autonomously selects the target comparison threshold that best matches the current signal amplitude and noise environment, thereby effectively overcoming the defect of the traditional fixed threshold method being susceptible to interference in strong noise environment. This adaptive mechanism can effectively filter out noise signals and avoid the problem of the speed output exceeding the effective range due to noise signal interference, which makes it impossible to accurately measure the target turntable speed. It ensures that the speed measurement is always stable within the effective range, which significantly improves the accuracy of measurement, anti-interference ability and overall reliability of the system under complex working conditions.

[0020] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the first circuit functional structure of the high noise-tolerant adaptive speed signal processing device in the embodiments of this application; Figure 2 This is a schematic diagram of the second circuit functional structure of the high noise-tolerance adaptive speed signal processing device in the embodiments of this application; Figure 3 This is a schematic diagram of the third circuit functional structure of the high noise-tolerance adaptive speed signal processing device in the embodiments of this application; Figure 4 This is a schematic diagram of the circuit structure of the peak detection module in an embodiment of this application; Figure 5 This is a schematic diagram of the fourth circuit functional structure of the high noise-tolerant adaptive speed signal processing device in the embodiments of this application; Figure 6 This is a schematic diagram of the gear division circuit structure of the multi-threshold generation module in the embodiments of this application; Figure 7 This is a schematic diagram of the fifth circuit functional structure of the high noise-tolerance adaptive speed signal processing device in the embodiments of this application; Figure 8 This is a schematic diagram of the circuit structure of the unidirectional integration and comparison circuit in an embodiment of this application; Figure 9 This is a schematic diagram of the sixth circuit functional structure of the high noise-tolerant adaptive speed signal processing device in the embodiments of this application; Figure 10 This is a schematic diagram of the seventh circuit functional structure of the high noise-tolerant adaptive speed signal processing device in the embodiments of this application; Figure 11 This is a schematic diagram of the circuit functional structure of the high noise-tolerant adaptive tachometer in the embodiments of this application; Figure 12 This is a flowchart outlining the high noise tolerance adaptive speed determination method in the embodiments of this application.

[0022] Icons: 100 - High noise-tolerance adaptive speed signal processing device; 110 - Signal preprocessing module; 120 - Peak dynamic detection module; 130 - Adaptive threshold generation module; 140 - CPLD module; 141 - Pulse counting module; 142 - Speed ​​filtering and analysis module; 143 - Range judgment module; 144 - Gear management module; 145 - Peak sampling timing control module; 121 - Peak detection module; 122 - Peak hold module; U1 - First comparator; U2 - First operational amplifier; U3 - Second operational amplifier; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; C1 - First capacitor; C2 - Second capacitor; S1 - First controllable switch; S2 - Second controllable switch; 131 - Multi-threshold generation module; 132 - Gating switch; 133 - Timing selection logic circuit; 134 - Noise filtering module; 135 - Series voltage divider resistor network; 136 - Buffer; 111 - Shaping filter circuit; 112 - One-way integration comparator circuit; U4 - Second comparator; 113 - Threshold voltage divider network; 114 - One-way integrator; 150 - Self-test selection module; 160 - Fault indication module; 200 - High noise tolerance adaptive tachometer; 210 - Speed ​​sensor; 220 - Display device. Detailed Implementation

[0023] To make the objectives, technical solutions, and beneficial effects of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] This application provides a high-noise-tolerant adaptive speed signal processing device 100, see reference. Figure 1 As shown, the high noise-tolerant adaptive speed signal processing device 100 provided in this application embodiment includes at least: a signal preprocessing module 110, a peak dynamic detection module 120, an adaptive threshold generation module 130, and a CPLD module 140; The input terminal of the signal preprocessing module 110 is connected to the output terminal of the speed sensor; the signal preprocessing module 110 is used to receive the original speed signal, perform pulse shaping processing on the original speed signal, and obtain the current pulse speed signal. The input terminal of the peak dynamic detection module 120 is connected to the output terminal of the signal preprocessing module 110. The peak dynamic detection module 120 is used to detect the instantaneous voltage amplitude of the current pulse speed signal in real time and obtain the current speed peak value. The input of the adaptive threshold generation module 130 is connected to the output of the signal preprocessing module 110 and the peak dynamic detection module 120, respectively. The adaptive threshold generation module 130 is used to generate multiple candidate thresholds corresponding to different gears based on the current peak speed. It receives the gear selection signal output by the CPLD module 140, uses the candidate threshold corresponding to the gear selection signal as the target comparison threshold, and performs noise filtering on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal. The input terminal of the CPLD module 140 is connected to the output terminal of the adaptive threshold generation module 130, the first output terminal of the CPLD module 140 is connected to the control terminal of the adaptive threshold generation module 130, and the second output terminal of the CPLD module 140 is connected to an external display device. The CPLD module 140 is used to determine the current speed based on the target pulse speed signal; to perform speed determination on the current speed based on the effective speed range, and to obtain the speed determination result; when a preset number of speed determination results are consecutively found to be speed exceeding the range, the target comparison threshold used by the adaptive threshold generation module 130 is adjusted through the gear selection signal until a preset number of speed determination results are consecutively found to be valid, and then the corresponding current speed is output to the external display device.

[0025] exist Figure 1In the high noise-tolerance adaptive speed signal processing device 100 shown, the signal preprocessing module 110 serves as the front end, performing shaping processes such as amplitude limiting and bandpass filtering on the raw speed signal sensed by the speed sensor, converting the raw speed signal into a regular current pulse speed signal. The raw speed signal is the magnetic pulse signal detected by the speed sensor. The peak dynamic detection module 120 tracks the instantaneous voltage amplitude of the current pulse speed signal in real time and accurately, and outputs the current speed peak value. The current speed peak value serves as the logical reference for subsequent adaptive adjustments, reflecting the energy level of the pulse speed signal. The adaptive threshold generation module 130 is the core execution unit for noise filtering. The adaptive threshold generation module 130 has two input ports, receiving the current speed peak value from the peak dynamic detection module 120 and the current pulse speed signal from the signal preprocessing module 110, respectively. The adaptive threshold generation module 130 can generate candidate thresholds proportional to the current speed peak value in parallel by voltage division of the current speed peak value according to multiple preset proportional coefficients. These multiple candidate thresholds represent different noise filtering levels, from lenient to strict. The adaptive threshold generation module 130 receives a gear selection signal from the CPLD module 140. This signal selects one of the candidate thresholds from the aforementioned candidate thresholds as the target comparison threshold. Based on the target comparison threshold, it performs noise filtering on the current pulse speed signal to obtain the target pulse speed signal. The CPLD module 140, as the digital logic control center of the entire device, does not rely on a general-purpose microprocessor (MCU) based on serial instruction execution or any operating system. Instead, it is implemented using parallel logic circuits defined by a hardware description language. The CPLD module 140 internally implements a master control state machine, managing the entire process from reset, initialization, self-test, normal operation, and fault handling. This state machine and all control logic are implemented using the CPLD's pure hardware parallel processing architecture, providing deterministic timing with no risk of system crashes. The CPLD module 140 receives the target pulse speed signal output by the adaptive threshold generation module 130 and accurately calculates the current speed using either frequency measurement or period measurement. The threshold adaptive control logic of the CPLD module 140 is implemented through a specially designed state machine. The state machine continuously compares the calculated current rotational speed with the upper and lower limits of the effective rotational speed range pre-stored in a register, generating a determination result of whether the rotational speed is valid or out of range. The state machine can have two configurable counters: an out-of-range continuous counter and a valid continuous counter.When the CPLD module 140 continuously detects a preset number of speed over-range results, it determines that the current working gear is not suitable for the environmental noise level. It then adjusts the output to the gear selection signal of the adaptive threshold generation module 130 to switch to the gear corresponding to a higher or lower target comparison threshold. After the threshold adjustment is performed, the state machine clears the counter and re-monitors. If the effective continuous counter accumulates to a preset number in the new gear, it determines that the device has returned to stability and locks the gear. Once in a stable state, the CPLD module 140 outputs the corresponding current speed through its second output terminal.

[0026] In this way, the peak speed of the current pulse speed signal is acquired in real time by the peak dynamic detection module, and multiple candidate thresholds are dynamically generated by the adaptive threshold generation module based on this peak value. The CPLD module, with its pure hardware parallel processing architecture, performs high-speed, parallel range verification on the speed calculation results under each candidate threshold, and autonomously selects the target comparison threshold that best matches the current signal amplitude and noise environment. This effectively overcomes the shortcomings of traditional fixed threshold methods, which are susceptible to interference in strong noise environments. This adaptive mechanism is entirely driven by the deterministic hardware logic of the CPLD, requiring no software intervention, fundamentally eliminating the risk of software crashes or operating system shutdowns, and ensuring extremely high operational reliability of the device. This adaptive mechanism can effectively filter out noise signals, avoiding the problem of the speed output exceeding the effective range due to noise interference, thus ensuring that the speed measurement remains stable within the effective range. This significantly improves the measurement accuracy, anti-interference ability, and overall reliability of the device under complex operating conditions.

[0027] In practical implementation, the CPLD module 140 of the high noise-tolerant adaptive speed signal processing device has various structures to achieve its function, see [reference]. Figure 2 As shown, the CPLD module 140 includes: a pulse counting module 141, a speed filtering and analysis module 142, a range judgment module 143, and a gear management module 144; the pulse counting module 141, the speed filtering and analysis module 142, the range judgment module 143, and the gear management module 144 are connected in series; the input terminal of the pulse counting module 141 is connected to the output terminal of the adaptive threshold generation module 130; the first output terminal of the gear management module 144 is connected to the control terminal of the adaptive threshold generation module 130, and the second output terminal of the gear management module 144 is connected to an external display device. The pulse counting module 141 is used to count the number of effective pulses of the target pulse speed signal within the measurement window, and to determine the original speed based on the number of effective pulses; The speed filtering and analysis module 142 is used to perform exponential smoothing on the original speed to obtain the current speed; The range judgment module 143 is used to compare the current speed with the effective speed range and output the speed judgment result of speed exceeding the range or speed being valid; wherein, the speed judgment result of speed exceeding the range includes the upper limit of speed exceeding the range and the lower limit of speed exceeding the range. The gear management module 144 is used to gradually increase the target comparison threshold through the gear selection signal when the number of continuously received speed judgment results exceeding the upper limit of the range reaches a preset number, until the preset number of valid speed results are continuously received. Then, it controls the adaptive threshold generation module 130 to maintain the corresponding target comparison threshold and outputs the current speed to the external display device. When the number of continuously received speed judgment results exceeding the lower limit of the range reaches a preset number, it controls the adaptive threshold generation module 130 to maintain the corresponding target comparison threshold and outputs the current speed to the external display device.

[0028] exist Figure 2 In the high noise-tolerant adaptive speed signal processing device 100 shown, the pulse counting module 141 can be a measurement circuit driven by a high-speed clock and based on a hardware counter and edge detection circuit. The pulse counting module 141 receives the target pulse speed signal after noise filtering. The pulse counting module 141 has a built-in timer driven by a high-frequency clock to generate a fixed measurement window time. Within each measurement window, the pulse counting module 141 captures and counts the specified valid rising edges of the target pulse speed signal to obtain the number of valid pulses within that window. Then, the module converts the number of valid pulses into the original speed according to a preset parameter of pulses per revolution corresponding to the characteristics of the speed sensor. The specific calculation formula is: ;in, The original rotational speed is given by T_win, the measurement window time is given by cnt_pulse, the number of valid pulses within the measurement window time is given by m, and the number of pulses per revolution is given by m. The rotational speed filtering and analysis module 142, as a hardware logic unit within the CPLD, implements the filtering algorithm through a fixed data path composed of hardware multipliers, adders, and register arrays. The rotational speed filtering and analysis module 142 is used to smooth the original rotational speed using a first-order exponential smoothing algorithm or a Kalman filter algorithm to suppress instantaneous interference. Specifically, to avoid speed jumps caused by accidental interference pulses or the loss of individual pulses, the rotational speed filtering and analysis module 142 can use the following formula to perform a first-order exponential smoothing algorithm on the original rotational speed. Using a first-order exponential smoothing algorithm can effectively smooth random fluctuations while maintaining fast response capability, resulting in a more stable and reliable current rotational speed output.

[0029]

[0030] in, This is the current rotational speed. It is the current rotational speed obtained from the previous calculation. It is a smoothing coefficient, typically ranging from 0.7 to 0.9. That's the original rotational speed.

[0031] The range judgment module 143 pre-stores the upper and lower limits of the effective speed range. It receives the filtered current speed in real time, compares it synchronously with the upper and lower limits, and outputs the speed judgment result. Specifically, if the current speed is greater than the upper limit, the output speed judgment result is "speed exceeds the upper limit"; if the current speed is less than the lower limit, the output speed judgment result is "speed exceeds the lower limit"; if the current speed is between the upper and lower limits, the output speed judgment result is "speed is valid". The gear management module 144, as the core of adaptive control, receives the speed judgment result from the range judgment module 143. The gear management module 144 integrates a counter for monitoring continuous over-range states and a counter for confirming stable states. When the number of consecutive speed judgment results exceeding the upper limit reaches a preset number, it indicates that too many false trigger pulses have been generated due to noise interference. At this time, the gear management module 144 sends a gear selection signal corresponding to the upshift command to the adaptive threshold generation module 130 through its first output terminal, gradually increasing the target comparison threshold to enhance noise suppression capability. When the number of consecutive speed judgment results exceeding the lower limit of the range reaches a preset number, it indicates that the effective signal may be submerged or attenuated. At this time, the gear management module 144 sends a gear selection signal corresponding to the downshift command to the adaptive threshold generation module 130 through its first output terminal, gradually decreasing the target comparison threshold to improve the sensitivity to capture weak signals. After performing gear adjustment, the gear management module 144 monitors subsequent speed judgment results. Once the number of consecutive valid speed judgment results received in the new gear reaches a preset number, it is determined that a stable state has been reached under this operating condition. The gear management module 144 locks the current gear selection signal and outputs the current speed corresponding to this stable state to the external display device in the form of parallel data or standard serial communication protocol through its second output terminal.

[0032] In this way, by configuring the CPLD module as a series structure of a pulse counting module, a speed filtering and analysis module, a range judgment module, and a gear management module, the logical flow of speed judgment and threshold adjustment is refined. The gear management module adjusts the target comparison threshold level by level based on the continuous speed judgment results output by the range judgment module and finally locks it. This adjustment mechanism based on continuous confirmation effectively prevents frequent threshold oscillations caused by single-pulse interference, ensuring that the adaptive threshold generation module can work stably at the optimal gear, thereby enabling the entire device to output reliable and continuous speed information.

[0033] In one possible implementation, the speed filtering analysis module is further used to obtain the speed after exponential smoothing within the previous measurement window as the historical speed; calculate the speed change between the current speed and the historical speed; and output the historical speed as the current speed when the speed change is greater than a preset speed change threshold.

[0034] In practical applications, the speed filtering and analysis module acquires the current speed calculated by the pulse counting module within the latest measurement window, and retrieves the speed output from the previous measurement window after exponential smoothing as the historical speed. To prevent abnormal speed jumps caused by sudden strong interference or pulse counting errors, the speed filtering and analysis module calculates the absolute difference between the current speed and the historical speed to obtain the speed change. The module pre-stores a positive speed change threshold, which defines the maximum reasonable speed change amplitude allowed within a single measurement window. The module compares the speed change with the speed change threshold using hardware circuitry. If the speed change is not greater than the threshold, the current speed is directly output; if the speed change is greater than the threshold, it is determined that there is a possibility of abnormal speed change, and for stability considerations, the historical speed is used as the current speed output.

[0035] In this way, the speed filtering analysis module, on the basis of completing the exponential smoothing process, adds the function of judging and suppressing sudden changes in speed. It can effectively smooth the speed output spikes caused by occasional strong noise or signal anomalies, avoid the interference of such instantaneous abnormal values ​​on the decision-making process of the subsequent range judgment module and gear management module, and improve the robustness of the overall decision-making of the device.

[0036] In one possible implementation, the gear management module is further configured to determine the current speed change rate based on the speed change within a preset mutation monitoring period when the number of continuously received speed judgment results exceeding the lower limit of the range reaches a preset number; when the current speed change rate is greater than the corresponding speed mutation threshold, the target comparison threshold is lowered by a preset number of gears through the gear selection signal; when the current speed change rate is not greater than the speed mutation threshold, the target comparison threshold is lowered by one gear through the gear selection signal; until a preset number of valid speed judgment results are continuously received, the current target comparison threshold is maintained and the current speed is output.

[0037] In practical applications, after receiving a preset number of speed exceeding the lower limit threshold detection results, the gear management module retrieves the recorded speed changes within a preset abrupt change monitoring period from its internal cache and calculates the current speed change rate within that monitoring period based on the speed changes at multiple different times. The gear management module pre-stores a speed abrupt change threshold that distinguishes between slow speed decay and sudden speed drops. It compares the calculated current speed change rate with the speed abrupt change threshold using hardware circuitry and executes differentiated gear control based on the comparison results. Specifically, if the current speed change rate is greater than the speed abrupt change threshold, it indicates a possible rapid speed decrease due to sudden signal loss or severe interference. In this case, the gear management module uses a gear selection signal to control the adaptive threshold generation module to lower the target comparison threshold by a preset number of gears at once, rapidly and significantly improving sensitivity and attempting to quickly reacquire the signal. If the current speed change rate is not greater than the speed abrupt change threshold, it indicates a possible slow speed decay or persistently low speed caused by gradual sensor drift or slow gap changes. At this point, the gear management module, through the gear selection signal, controls the adaptive threshold generation module to lower the target comparison threshold by only one gear, performing a fine adjustment to avoid introducing noise due to excessive threshold reduction. After performing any of the above threshold reduction operations, the gear management module clears the relevant counters and continuously monitors subsequent speed determination results. When the number of consecutive valid speed determination results received reaches a preset number, the gear management module determines that it has re-entered a stable state, locks the current gear selection signal to maintain the corresponding target comparison threshold, and outputs the corresponding current speed as a valid speed result to the external display device.

[0038] This introduces a differentiated threshold adjustment strategy based on the rate of change of rotational speed. When a threshold needs to be lowered, the gear management module first calculates the current rate of change of rotational speed based on data within the abrupt change monitoring period and compares it with the rotational speed abrupt change threshold. For high rate of change conditions, the gear management module controls the adaptive threshold generation module to lower the target comparison threshold by several gears to achieve rapid tracking; for low rate of change conditions, the gear management module controls the adaptive threshold generation module to lower the target comparison threshold by one gear. This intelligent differentiation significantly improves the device's tracking capability and adaptability to conditions where the rotational speed signal drops sharply and rapidly.

[0039] In one possible implementation, see [reference] Figure 3 As shown, the CPLD module 140 also includes: a peak sampling timing control module 145; and a peak dynamic detection module 120 including a peak hold module 122 and at least two peak detection modules 121. The input terminal of each peak detection module 121 is connected to the output terminal of the signal preprocessing module 110, the output terminal of each peak detection module 121 is connected to the input terminal of the peak hold module 122, the control terminal of each peak detection module 121 is connected to the output terminal of the peak sampling timing control module 145, and the output terminal of the peak hold module 122 is connected to the input terminal of the adaptive threshold generation module 130. The peak sampling timing control module 145 is used to select two peak detection modules 121 from at least two peak detection modules 121 as a peak detection module group 121, and output timing-interleaved rotation control signals to the two peak detection modules 121 in the peak detection module group 121, so that the two peak detection modules 121 in the peak detection module group 121 alternately enter detection mode and discharge mode, and at any time at least one peak detection module 121 is in detection mode; In detection mode, peak detection module 121 detects the instantaneous voltage amplitude of the current pulse speed signal and outputs the effective signal peak value to peak holding module 122; in discharge mode, it performs a reset operation and stops outputting the effective signal peak value. The peak hold module 122 is used to buffer and convert the effective signal peak value to digital-to-analog conversion, obtain the current speed peak value, and output it.

[0040] exist Figure 3In the high noise-tolerant adaptive speed signal processing device 100 shown, each of the at least two peak detection modules 121 can independently perform peak detection and hold functions for the current pulse speed signal. Each peak detection module 121 has two controlled states: detection mode and discharge mode. In detection mode, the peak detection module 121 performs its basic function, namely, detecting the instantaneous voltage amplitude of the current input pulse speed signal and outputting the effective signal peak value in real time. In discharge mode, the peak detection module 121 performs an internal reset operation, namely, quickly releasing the charge of the holding capacitor and stopping the output of the effective signal. The peak sampling timing control module 145 can be a sophisticated hardware timing generator inside the CPLD, consisting of a counter, decoder, and output drive logic, used to generate multiple rotation control signals. The peak sampling timing control module 145 sequentially activates a peak detection module group consisting of two physically adjacent peak detection modules 121, strictly executing a three-step rotation timing within the group to ensure gapless sampling. When the predetermined work cycle is completed or the switching condition is triggered, the peak sampling timing control module 145 does not perform complex dynamic selection, but instead switches to the next adjacent group of modules in a fixed manner. For example, it switches from the peak detection module group composed of peak detection module A and peak detection module B to the peak detection module group composed of peak detection module B and peak detection module C, and so on, forming a cyclical step-by-step rotation. This ensures that all available peak detection modules 121 can obtain an equal use and maintenance cycle. The three-step rotation timing is configured as follows: in the first stage, peak detection module A and peak detection module B are controlled to enter detection mode simultaneously; in the second stage, peak detection module A is controlled to be in detection mode, while peak detection module B is controlled to enter discharge mode; in the third stage, peak detection module A is controlled to be in discharge mode, while peak detection module B is controlled to enter detection mode. The three-step rotation timing ensures that at least one peak detection module is in detection mode at any time, realizing truly continuous and gapless capture of the peak value of the current pulse speed signal, and providing the adaptive threshold generation module 130 with a peak reference signal with extremely high update rate and integrity. The peak hold module 122 typically consists of multiple high input impedance voltage buffers, which are responsible for receiving and holding the peak value of the currently strobed valid signal.

[0041] Thus, by introducing a peak sampling timing control module and a detection unit consisting of at least two peak detection modules and a peak hold module, the signal blind zone problem in the peak detection process is solved. Peak sampling timing control drives at least two peak detection modules to alternately operate in detection and discharge modes, ensuring that at least one peak detection module is always in an effective detection state. The peak hold module holds and converts the peak values ​​of the alternately input effective signals. This achieves continuous and uninterrupted sampling of the current pulse speed signal peak value, providing a highly reliable current speed peak reference for the adaptive threshold generation module.

[0042] In practical implementation, the peak detection module 121 of the high noise-tolerant adaptive speed signal processing device 100 has various structures to achieve its function, see [reference]. Figure 4 As shown, the peak detection module 121 includes: a first comparator U1, a first operational amplifier U2, a second operational amplifier U3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a first controllable switch S1, and a second controllable switch S2. The non-inverting input of the first comparator U1 is connected to the output of the first operational amplifier U2, the inverting input of the first comparator U1 is connected to the output of the signal preprocessing module 110, and the output of the first comparator U1 is connected to the inverting input of the first operational amplifier U2 via the first resistor R1. The non-inverting input of the first operational amplifier U2 is connected to ground, and the output of the first operational amplifier U2 is connected to the non-inverting input of the second operational amplifier U3 via the second resistor R2; the third resistor R3, the first capacitor C1, and the first controllable switch S1 are connected in parallel between the inverting input of the first operational amplifier U2 and the output of the first operational amplifier U2, respectively. The first terminal of the second capacitor C2 is connected between the second resistor R2 and the non-inverting input terminal of the second operational amplifier U3, and the second terminal of the second capacitor C2 is connected to ground; the second controllable switch S2 is connected in parallel with the second capacitor C2. The inverting input terminal of the second operational amplifier U3 is connected to the output terminal of the second operational amplifier U3, and the output terminal of the second operational amplifier U3 is connected to the input terminal of the peak hold module 122. The control terminals of the first controllable switch S1 and the second controllable switch S2 are respectively connected to the peak sampling timing control module 145.

[0043] exist Figure 4In the high-noise-tolerance adaptive speed signal processing device shown, the peak detection module 121 can adopt a dual-power supply architecture, for example, using a +5V power supply VDD and a -5V power supply VSS to power the first comparator U1, the first operational amplifier U2, and the second operational amplifier U3. The dual-power supply design ensures that the circuit can handle input signals with positive and negative swings, avoiding signal cutoff distortion that may occur under a single power supply, and providing an ideal operating bias for the device. The first comparator U1 performs a real-time, continuous analog comparison between the instantaneous voltage of the current pulse speed signal and the currently held peak voltage reference value output by the first operational amplifier U2. When the instantaneous voltage of the current pulse speed signal is higher than the currently held peak reference value, the first comparator U1 outputs a valid high level, controlling the subsequent circuit to charge the first capacitor C1, thereby updating and maintaining a higher peak voltage; conversely, it outputs an invalid low level, allowing the circuit to maintain the original peak value. The first operational amplifier U2 and the first capacitor C1 constitute the core of the peak detector, used to stably store and output the tracked current peak voltage. The output of the second operational amplifier U3 is directly connected to its inverting input, forming a voltage follower to provide impedance transformation and isolation for subsequent circuits. The first resistor R1 acts as a current-limiting resistor, controlling the charging rate of the first capacitor C1 to smooth noise. The second resistor R2 and the second capacitor C2 together form an inter-stage low-pass filter network, further filtering out high-frequency noise and smoothing the output. The third resistor R3 provides a high-resistance discharge circuit for the first capacitor C1, preventing voltage drift and ensuring long-term reliability. The second capacitor C2 also serves as the sample-and-hold capacitor for the output stage, temporarily storing the current peak voltage for stable output. The first controllable switch S1 and the second controllable switch S2 act as fast discharge control switches. When closed under control, they can instantaneously short-circuit and discharge the first capacitor C1 and the second capacitor C2, thereby achieving a complete and rapid reset of the peak detection module 121 and immediately stopping the output of the valid signal peak.

[0044] In practical applications, the peak detection module 121 has two states: detection mode and discharge mode. In detection mode, both the first controllable switch S1 and the second controllable switch S2 are open. At this time, the first operational amplifier U2, the first capacitor C1, and the related first resistor R1, third resistor R3, and first controllable switch S1 constitute a dynamic peak detection circuit. When the input current pulse speed signal voltage is higher than the voltage held at the output of the first operational amplifier U2, the first comparator U1 outputs a high level, charging the first capacitor C1 through the first resistor R1, so that the output voltage of the first operational amplifier U2 follows and holds the peak value of the input signal. This voltage charges the second capacitor C2 through the second resistor R2, and is buffered by the second operational amplifier U3 before being output as the valid signal peak value sent to the peak holding module 122. In discharge mode, the alternate enable signal controls the first controllable switch S1 and the second controllable switch S2 to close. The first controllable switch S1 closes, causing the first capacitor C1 to discharge rapidly, resetting the held peak voltage; the second controllable switch S2 closes, causing the second capacitor C2 to discharge, clearing the previously sampled output value, thereby achieving a complete reset of the peak detection module 121 and stopping the output of valid signal peaks.

[0045] Thus, the peak detection module, composed of a first comparator U1, a first operational amplifier U2, a second operational amplifier U3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a first controllable switch S1, and a second controllable switch S2, utilizes the first comparator U1 to achieve rapid peak value determination. The low output impedance of the operational amplifiers enables active, rapid charging of the energy storage capacitors, effectively avoiding the conduction voltage drop loss of diode detection in existing technologies and improving peak value capture accuracy. Simultaneously, the controllable switches connected in parallel with the capacitors provide a direct physical control means for forced rapid "discharge," ensuring the speed and reliability of module state switching.

[0046] In practical implementation, the adaptive threshold generation module 130 of the high noise-tolerant adaptive speed signal processing device 100 has various structures to achieve its function, see [reference]. Figure 5 As shown, the adaptive threshold generation module 130 includes: a multi-threshold generation module 131, a gating switch 132, a timing selection logic circuit 133, and a noise filtering module 134; The input terminal of the multi-threshold generation module 131 is connected to the output terminal of the peak dynamic detection module 120, and each output terminal of the multi-threshold generation module 131 is connected to the corresponding input terminal of the gating switch 132; the control terminal of the gating switch 132 is connected to the output terminal of the timing selection logic circuit 133, and the output terminal of the gating switch 132 is connected to the input terminal of the noise filtering module 134; the output terminal of the noise filtering module 134 is connected to the input terminal of the CPLD module 140; the input terminal of the timing selection logic circuit 133 is connected to the first output terminal of the CPLD module 140. The timing selection logic circuit 133 is used to generate the channel selection signal of the gating switch 132 according to the gear selection signal; The multi-threshold generation module 131 is used to generate multiple candidate thresholds for different gears based on the current peak speed; The gating switch 132 is used to select the candidate threshold corresponding to the gear selection signal as the target comparison threshold under the control of the channel selection signal; The noise filtering module 134 is used to perform noise filtering on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal.

[0047] exist Figure 5In the high noise-tolerant adaptive speed signal processing device 100 shown, the input of the multi-threshold generation module 131 is electrically connected to the output of the peak dynamic detection module 120. The multi-threshold generation module 131 receives a real-time changing analog voltage signal, i.e., the current speed peak value. The multi-threshold generation module 131 generates this single current speed peak value into multiple candidate thresholds with fixed proportional relationships and different levels at once. The gating switch 132 is a multi-channel analog selector with multiple inputs, one output, and one control terminal. The multiple inputs of the gating switch 132 correspond one-to-one with the multiple outputs of the multi-threshold generation module 131, each receiving multiple candidate thresholds. Under the action of the channel selection signal, the gating switch 132 is responsible for connecting one of the multiple candidate thresholds to the output terminal. The input of timing selection logic circuit 133 is connected to the first output of CPLD module 140, receiving a gear selection signal sent in digital encoding form. It decodes the digital encoding in the received gear selection signal and outputs a corresponding gear selection logic signal (e.g., binary encoding) to the control terminal of gating switch 132. This allows gating switch 132, under the control of the channel selection signal, to dynamically connect its common output to the selected input, thus outputting the selected candidate threshold as the target comparison threshold. One input of noise filtering module 134 is connected to the output of gating switch 132 to receive the dynamically selected target comparison threshold; the other input is connected to the output of signal preprocessing module 110 to receive the current pulse speed signal. The core of noise filtering module 134 is a high-speed, precise voltage comparator. Noise filtering module 134 continuously compares the instantaneous voltage of the current pulse speed signal with the target comparison threshold in real time. When the instantaneous voltage of the current pulse speed signal exceeds the target comparison threshold, the output state of the voltage comparator undergoes a definitive flip from low to high. For any noise, glitches, or interference signals with amplitudes below this threshold, the comparator output state remains unchanged. Through this process, the original, noise-contaminated pulse signal is converted into a well-defined, logically sound digital pulse sequence, i.e., the target pulse speed signal, which is then sent to the input of the CPLD module 140 for subsequent precise timing and calculation.

[0048] In this way, the timing selection logic circuit 133 generates a channel selection signal to control the gating switch based on the gear selection signal from the CPLD module, thereby quickly switching from multiple candidate thresholds and outputting the target comparison threshold to the noise filtering module. This hardware-based channel gating implementation enables the threshold switching action to have extremely high speed and determinism, ensuring that the adaptive adjustment loop of the device can respond to signal changes in real time.

[0049] In one possible implementation, see [reference] Figure 6As shown, the multi-threshold generation module 131 includes: a series voltage divider resistor network 135 and multiple buffers 136; A series voltage divider resistor network 135 is connected between the current speed peak and ground to form multiple voltage divider nodes, each voltage divider node corresponding to a candidate threshold; each voltage divider node is connected to the input terminal of the gating switch 132 via the corresponding buffer 136.

[0050] exist Figure 6 In the high-noise-margin adaptive speed signal processing device shown, multiple resistors are connected in series between the current peak speed and ground in the series voltage divider network 135. Based on the ratio of the individual resistor values, a fixed node voltage is generated at each voltage divider node. The node voltage of each voltage divider node is a series of proportionally decreasing candidate thresholds. For example, if the current peak speed is Vp, using N resistors with the same resistance value, Vp can be obtained. , , … , Candidate threshold values ​​are determined. A buffer 136 is inserted between each voltage divider node and the input of the subsequent gating switch 132. The high input impedance of the buffer 136 ensures that almost no current is drawn from the series voltage divider resistor network 135, thus guaranteeing the accuracy and stability of the voltage division ratio, unaffected by changes in the input impedance of the subsequent gating switch 132. The low output impedance of the buffer 136 provides a stable voltage source for the gating switch 132, ensuring that the threshold voltage does not attenuate during transmission.

[0051] In practical implementation, the signal preprocessing module 110 of the high noise-tolerant adaptive speed signal processing device 100 has various structures to achieve its function, see [reference]. Figure 7 As shown, the signal preprocessing module 110 includes: a shaping filter circuit 111 and a one-way integration and comparison circuit 112; The input terminal of the shaping filter circuit 111 is connected to the output terminal of the speed sensor, and the output terminal of the shaping filter circuit 111 is connected to the input terminal of the one-way integration comparison circuit 112; the output terminal of the one-way integration comparison circuit 112 is connected to the input terminals of the peak dynamic detection module 120 and the adaptive threshold generation module 130, respectively. The shaping and filtering circuit 111 is used to limit, bandpass filter and pulse shape the original speed signal to obtain a pre-shaped pulse signal; The unidirectional integration and comparison circuit 112 is used to perform threshold comparison on the pre-shaping pulse signal, and to perform unidirectional integration processing on the pre-shaping pulse signal that passes the comparison to obtain the current pulse speed signal.

[0052] exist Figure 7In the high-noise-tolerance adaptive speed signal processing device 100 shown, the shaping and filtering circuit 111 is used for basic conditioning of the raw speed signal output by the speed sensor, which may contain various interferences and distortions, including amplitude limiting, bandpass filtering, and pulse shaping. Amplification protection protects the subsequent circuitry from overvoltage surges; bandpass filtering allows signals within a specific frequency range to pass through while suppressing out-of-band high-frequency noise and low-frequency drift; pulse shaping shapes the filtered signal into a pre-shaped pulse signal with clear edges and regular amplitude. The one-way integration and comparison circuit 112 compares the pre-shaped pulse signal with a preset integration threshold. Only pulse portions with amplitudes exceeding the threshold are considered valid and pass through. The pre-shaped pulse signals that pass the comparison are then subjected to one-way integration processing. One-way integration processing refers to integrating the positive polarity of the pulse, converting the pulse sequence into a slowly varying voltage signal whose amplitude is related to the pulse energy, i.e., the current pulse speed signal.

[0053] Thus, by employing two stages of pure hardware processing circuits—a cascaded shaping and filtering circuit 111 and a unidirectional integrating and comparing circuit 112—the original rotational speed signal is progressively processed. The shaping and filtering circuit performs basic noise suppression and waveform regularization, while the pre-stage threshold comparison stage filters out a large amount of low-amplitude noise early on, preventing it from accumulating and amplifying in subsequent integrators. The subsequent unidirectional integrating stage converts the effective pulse sequence into a stable analog signal, greatly improving the signal-to-noise ratio and regularity, and providing a high-quality input signal for subsequent peak detection and threshold comparison.

[0054] In one possible implementation, see [reference] Figure 8 As shown, the unidirectional integrator-comparator circuit 112 includes: a second comparator U4, a threshold voltage divider network 113, and a unidirectional integrator 114; The non-inverting input of the second comparator U4 is connected to the output of the shaping filter circuit 111, the inverting input of the second comparator U4 is connected to the output of the threshold voltage divider network 113, and the output of the second comparator U4 is connected to the input of the one-way integrator 114; the output of the one-way integrator 114 is connected to the input of the peak dynamic detection module 120 and the adaptive threshold generation module 130, respectively. Threshold divider network 113 is used to output the integral threshold; The second comparator U4 is used to compare the pre-shaped pulse signal with the integration threshold and output the effective pulses in the pre-shaped pulse signal that are higher than the integration threshold. The unidirectional integrator 114 is used to perform unidirectional integration on the effective pulse to generate the current pulse speed signal.

[0055] exist Figure 8In the high-noise-tolerance adaptive speed signal processing device shown, the threshold voltage divider network 113 is typically composed of two resistors connected in series, dividing the power supply voltage to provide a stable and fixed integration threshold. The non-inverting input of the second comparator U4 receives the pre-shaped pulse signal, and the inverting input receives the integration threshold. Only when the input pulse amplitude is higher than the integration threshold does the output jump to a high level, thus outputting a valid pulse to completely block noise with amplitudes below the threshold. The unidirectional integrator 114 is typically implemented using an RC integrator circuit consisting of a resistor and a capacitor. The unidirectional integrator 114 receives the valid pulse output from the second comparator U4. The unidirectional integrator 114 integrates the valid pulse, converting the pulse width and amplitude information into a charging voltage on the capacitor. The final output current pulse speed signal is a voltage signal proportional to the frequency of the valid pulse.

[0056] In this way, the threshold voltage divider network 113 provides a stable initial screening threshold, and the second comparator U4 performs precise amplitude discrimination, effectively blocking interference below the threshold. The unidirectional integrator accumulates and smooths the energy of the valid pulses that pass the discrimination, outputting a slowly varying voltage signal that reflects the pulse frequency. This achieves efficient noise stripping at the front end of the signal chain and is a crucial foundation for improving the noise tolerance of the entire device.

[0057] In one possible implementation, see [reference] Figure 9 As shown, the high noise-tolerant adaptive speed signal processing device 100 also includes a self-test selection module 150; The first input terminal of the self-test selection module 150 is connected to the output terminal of the speed sensor, the second input terminal of the self-test selection module 150 is connected to an external standard pulse source, and the output terminal of the self-test selection module 150 is connected to the CPLD module 140. The self-test selection module 150 is used to connect the speed sensor to the signal preprocessing module 110, or to connect an external standard pulse source to the signal preprocessing module 110. When the self-test enable is active, the CPLD module 140 sends a channel switching command to the self-test selection module 150, enabling the self-test selection module 150 to connect the external standard pulse source and the signal preprocessing module 110. After connecting the standard pulse source, the current speed when the speed determination result is valid is used as the measured speed. The speed error between the measured speed and the theoretical speed of the standard pulse source is determined. If the speed error is within the preset error range, a self-test result of passing the self-test is generated. If the speed error is not within the preset error range, a self-test result of failing the self-test is generated.

[0058] In practical applications, the core function of the self-test selection module 150 is to reliably switch between two operating modes based on the received channel switching command. The first mode is the normal operating mode. In the normal operating mode, the internal channel of the self-test selection module 150 connects the speed sensor and the signal preprocessing module 110. At this time, the device processes the actual physical speed signal. The second mode is the self-test mode. In the self-test mode, the self-test selection module 150 disconnects from the speed sensor according to the command and instead connects the external standard pulse source to the signal preprocessing module 110. At this time, the device's processing link will receive a standard test signal with known frequency and amplitude and high stability. After the external standard pulse source is successfully connected, the CPLD module 140 starts the self-test logic flow, and the entire device's signal preprocessing, adaptive threshold generation, pulse counting, and filtering begin to process the standard pulse signal. The CPLD module 140 monitors the speed judgment result output by the range judgment module 143. When a preset number of speed judgment results show that the speed is valid, it records the current speed output by the speed filtering analysis module 142 and uses it as the measured speed for this self-test. Simultaneously, the CPLD module 140 reads the theoretical rotational speed corresponding to the preset standard pulse source. After obtaining the measured rotational speed and the theoretical rotational speed, it calculates the absolute error between the measured and theoretical rotational speeds, i.e., the rotational speed error. The rotational speed error is compared with a preset error range stored in the CPLD module 140, representing the maximum allowable measurement deviation of the device. If the rotational speed error falls within the preset error range, it indicates that the overall performance of the gain, threshold, counting, and time base of the entire signal processing link is normal, and the CPLD module 140 generates and outputs a self-test qualified result identifier. Conversely, if the rotational speed error exceeds the preset error range, it indicates that there may be drift, misalignment, or fault in one or more links from signal input to rotational speed calculation. The CPLD module 140 generates and outputs a self-test unqualified result identifier and can selectively record the specific rotational speed error for diagnosis. After completing the self-test process, the CPLD module 140 sends a command to the self-test selection module 150 again to switch it back to normal working mode, reconnect the rotational speed sensor, and ensure that the device restores normal monitoring function. The self-test process can be executed periodically or after the device is powered on and initialized. After the self-test is completed, if the self-test result is qualified, the CPLD module device will start normal operation; if the self-test result is unqualified, the CPLD module control device will stop operating.

[0059] In this way, the self-test selection module, under the control of the CPLD module, can switch the input signal channel between the actual speed sensor and an external standard pulse source. By connecting a standard pulse source of known frequency, the CPLD module, with its deterministic logic without software intervention, can automatically calculate the error between the measured speed and the theoretical speed, and determine the current operating accuracy of the device accordingly. This makes the reliability assessment and periodic calibration of the device more convenient, improving the maintainability of the device and its application value in applications with high reliability requirements.

[0060] Furthermore, an external standard pulse source can generate multiple standard signals of different frequencies to simulate low-speed, medium-speed, and high-speed operating conditions. The CPLD module can control the sequential self-test at different frequencies, thereby plotting the device's accuracy curve across the entire range and achieving a more comprehensive performance evaluation. The CPLD module can generate richer diagnostic information based on the magnitude and sign of the error. For example, a uniform positive deviation may indicate a slight drift in the pulse counting reference clock; changes in error with signal frequency may indicate that specific filter parameters need calibration.

[0061] In one possible implementation, see [reference] Figure 10 As shown, the high noise-tolerant adaptive speed signal processing device 100 also includes a fault indication module 160; The input terminal of the fault indication module 160 is connected to the CPLD module 140; The fault indication module 160 is used to execute the fault indication corresponding to the fault signal after receiving the first fault signal, the second fault signal or the third fault signal; The CPLD module 140 is used to determine a sensor detachment fault when no target pulse speed signal is received within a preset detection time and the target comparison threshold of the adaptive threshold generation module 130 is the candidate threshold of the lowest gear, and sends a first fault signal to the fault indication module 160; when the target comparison threshold of the adaptive threshold generation module 130 is the candidate threshold of the highest gear and a preset number of speed determination results show speed exceeding range, it determines a hardware saturation fault and sends a second fault signal to the fault indication module 160; when it is determined that the adaptive threshold generation module 130 has failed to maintain the target comparison threshold within a preset deadlock time, it determines a logic deadlock fault and sends a third fault signal to the fault indication module 160.

[0062] In practical applications, the input terminal of the fault indication module 160 is connected to a dedicated status output port of the CPLD module 140. The CPLD module 140 integrates a fault diagnosis logic module, which can identify abnormal patterns of the device based on operational data and generate discrete first, second, or third fault signals, which are then sent to the fault indication module 160. Upon receiving any fault signal, the fault indication module 160 immediately activates a specific indication behavior pre-bound to that signal, such as driving different LEDs to flash at a specific frequency or triggering buzzers with different tones. The fault diagnosis logic module inside the CPLD module 140 is a hardware logic circuit used for fault diagnosis. The fault diagnosis logic module monitors multiple hardware status signals in parallel and generates discrete first, second, or third fault signals. Specifically, the fault diagnosis logic module contains a hardware timer to measure a preset detection duration. The fault diagnosis logic module simultaneously monitors the effective edges of the target pulse speed signal from the pulse counting module 141, and the gear status signal indicating the current target comparison threshold gear position fed back from the adaptive threshold generation module 130 or its own gear management module 144. When the hardware timer times out and the edge detection circuit is not effectively triggered, and the gear status signal is a specific code representing the lowest gear, the fault diagnosis logic module sets and outputs a first fault signal. The fault diagnosis logic module continuously latches the hardware status signal of the current target comparison threshold gear position. When the status signal is a specific code representing the highest gear position, a monitoring logic for the speed determination result is triggered. The fault diagnosis logic module includes a hardware counter that counts consecutive speed over-range determination results directly provided by the hardware output of the range determination module 143. When the value of the hardware counter reaches its preset number, the fault diagnosis logic module outputs a second fault signal. The fault diagnosis logic module also includes a timer for monitoring system stability and a gear switching frequency detection logic circuit. The duration of the timer is set to a preset deadlock duration. The gear shifting frequency detection logic circuit monitors changes in the gear selection signal output by the gear management module 144. If the gear selection signal is not detected to remain stable before the timer expires, i.e., the gear selection signal continues to shift, the timer expiration signal will trigger the fault diagnosis logic module to output a third fault signal.

[0063] By adding a fault indication module and defining in detail the CPLD module's judgment logic for three specific faults, the device is endowed with precise fault diagnosis and indication capabilities. The CPLD module comprehensively analyzes information such as the presence or absence of the target pulse speed signal, the target comparison threshold position, and the stable position duration. This allows it to distinguish the root cause of the fault and drive the fault indication module to issue corresponding alarms. This greatly facilitates on-site maintenance personnel in quickly locating and resolving problems, improving the device's availability.

[0064] Based on the above embodiments, this application provides a high-noise-tolerance adaptive tachometer 200, see reference. Figure 11 As shown, the high noise-tolerant adaptive tachometer 200 provided in this application embodiment includes at least: a speed sensor 210, a display device 220, and the aforementioned high noise-tolerant adaptive speed signal processing device 100; The output terminal of the speed sensor 210 is connected to the input terminal of the speed signal processing device; the input terminal of the display device 220 is connected to the output terminal of the speed signal processing device.

[0065] In practical applications, the speed sensor 210 provides the raw speed signal, and the display device 220 displays the final speed. The high-noise-tolerance adaptive speed signal processing device 100, as the core of the entire tachometer, integrates a signal preprocessing module 110, a peak dynamic detection module 120, an adaptive threshold generation module 130, and a CPLD module 140, operating entirely according to the working principle described in the aforementioned embodiments. It receives the raw signal from the sensor, filters out strong noise interference through fully hardware adaptive closed-loop processing, and finally outputs a stable and accurate digital or pulse signal of the current speed. The input terminal of the display device 220 is connected to the output terminal of the high-noise-tolerance adaptive speed signal processing device 100, and is used to receive and visually display the valid current speed calculated and determined by the high-noise-tolerance adaptive speed signal processing device 100.

[0066] Thus, the high-noise-tolerant adaptive tachometer provided in this application embodiment realizes a complete functional chain from physical signal sensing and intelligent anti-interference processing to reliable result output. The core advantage of this tachometer relies entirely on the pure hardware adaptive architecture of its built-in high-noise-tolerant adaptive speed signal processing device. Compared with traditional tachometers using general-purpose microprocessors (MCUs) and operating systems, the high-noise-tolerant adaptive tachometer completely eliminates the risks of software crashes, infinite loops, or task scheduling delays. All signal processing, threshold judgment, and gear adjustment logic of the high-noise-tolerant adaptive speed signal processing device are implemented by hardware parallel circuits within the CPLD, ensuring deterministic timing and microsecond-level response speed throughout the entire chain from signal input to result display. Therefore, the high-noise-tolerant adaptive tachometer 200 can maintain measurement accuracy and stability under complex industrial conditions with severe electromagnetic noise and large signal amplitude fluctuations, significantly improving the overall reliability, environmental adaptability, and long-term maintainability of the product.

[0067] It should be noted that the principle of the high noise tolerance adaptive tachometer 200 provided in this application embodiment to solve the technical problem is similar to that of the high noise tolerance adaptive speed signal processing device 100 provided in this application embodiment. Therefore, the implementation of the high noise tolerance adaptive tachometer 200 provided in this application embodiment can refer to the implementation of the high noise tolerance adaptive speed signal processing device 100 provided in this application embodiment, and the repeated parts will not be described again.

[0068] Based on the above embodiments, this application provides a high-noise-tolerance adaptive speed determination method, see reference. Figure 12 As shown, the high noise-tolerance adaptive speed determination method includes: Step 101: Obtain the raw speed signal output by the speed sensor, and perform pulse shaping on the raw speed signal output by the speed sensor to obtain the current pulse speed signal.

[0069] Step 102: Detect the instantaneous voltage amplitude of the current pulse speed signal in real time to obtain the current speed peak value.

[0070] Step 103: Generate multiple candidate thresholds corresponding to different gears based on the current peak speed, and set one of the candidate thresholds as the target comparison threshold according to the gear selection signal; perform noise filtering on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal.

[0071] Step 104: Determine the current speed based on the target pulse speed signal; perform speed determination on the current speed based on the effective speed range to obtain the speed determination result; if the speed determination result is over the range for a consecutive preset number of times, adjust the gear selection signal to switch the target comparison threshold until the speed determination result is valid for a consecutive preset number of times, and then output the current speed.

[0072] In one possible implementation, the current rotational speed is determined based on the target pulse rotational speed signal; the current rotational speed is judged based on the effective rotational speed range to obtain a rotational speed judgment result; if a preset number of consecutive rotational speed judgment results indicate that the rotational speed is out of range, the gear selection signal is adjusted to switch the target comparison threshold until a preset number of consecutive rotational speed judgment results indicate that the rotational speed is valid, at which point the current rotational speed is output. This can be achieved, but is not limited to, the following methods: First, count the number of valid pulses of the target pulse speed signal within the measurement window, and determine the original speed based on the number of valid pulses; Then, exponential smoothing is performed on the original rotational speed to obtain the current rotational speed; Next, the current speed is compared with the effective speed range, and the speed determination result of speed exceeding the range or speed being valid is output; among them, the speed determination result of speed exceeding the range includes the upper limit of speed exceeding the range and the lower limit of speed exceeding the range. Finally, when the number of consecutive speed judgment results exceeding the upper limit of the range reaches a preset number, the target comparison threshold is gradually increased through the gear selection signal until the preset number of valid speed results are received. Then, the adaptive threshold generation module is controlled to maintain the corresponding target comparison threshold and output the current speed to the external display device. When the number of consecutive speed judgment results exceeding the lower limit of the range reaches a preset number, the target comparison threshold is gradually decreased through the gear selection signal until the preset number of valid speed results are received. Then, the adaptive threshold generation module is controlled to maintain the corresponding target comparison threshold and output the current speed to the external display device.

[0073] In one possible implementation, the high-noise-tolerance adaptive speed determination method further includes: First, the exponentially smoothed rotational speed within the previous measurement window is obtained as the historical rotational speed. Then, calculate the change in rotational speed between the current speed and the historical speed; Finally, when the change in rotational speed exceeds the preset threshold for rotational speed change, the historical rotational speed is used as the current rotational speed for output.

[0074] In one possible implementation, when the number of continuously received speed determination results exceeding the lower limit of the range reaches a preset number, the high-noise-tolerance adaptive speed determination method further includes: First, the current speed change rate is determined based on the speed change within a preset mutation monitoring period; Then, when the current speed change rate is greater than the corresponding speed change threshold, the target comparison threshold is lowered by a preset number of gears through the gear selection signal; when the current speed change rate is not greater than the speed change threshold, the target comparison threshold is lowered by one gear through the gear selection signal. Finally, after receiving a preset number of valid speed determination results, the current target comparison threshold is maintained and the current speed is output.

[0075] In one possible implementation, the high-noise-tolerance adaptive speed determination method further includes: Select two peak detection modules from at least two peak detection modules as a peak detection module group, and output time-interleaved rotating control signals to the two peak detection modules in the peak detection module group, so that the two peak detection modules in the peak detection module group alternate between detection mode and discharge mode, and at any time at least one peak detection module is in detection mode; The effective signal peak value is buffered and converted from digital to analog to obtain the current speed peak value and output.

[0076] In one possible implementation, multiple candidate thresholds corresponding to different gears are generated based on the current peak speed, and one of the candidate thresholds is set as the target comparison threshold according to the gear selection signal; noise filtering is performed on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal, which can be done in ways including but not limited to the following: Generate a channel selection signal for the gating switch based on the gear selection signal; Multiple candidate thresholds for different gears are generated based on the current peak speed; Under the control of the channel selection signal, the candidate threshold corresponding to the gear selection signal is used as the target comparison threshold; The target pulse speed signal is obtained by filtering out noise from the current pulse speed signal based on the target comparison threshold.

[0077] In one possible implementation, the raw speed signal output by the speed sensor is acquired, and pulse shaping is performed on the raw speed signal output by the speed sensor to obtain the current pulse speed signal. This can be done in, but is not limited to, the following ways: First, the original speed signal is subjected to amplitude limiting, bandpass filtering and pulse shaping to obtain a pre-shaped pulse signal; Then, the pre-shaping pulse signal is compared with a threshold, and the pre-shaping pulse signal that passes the comparison is integrated in one direction to obtain the current pulse speed signal.

[0078] In one possible implementation, the high-noise-tolerance adaptive speed determination method further includes: First, when the self-test enable is valid, a channel switching command is sent to the self-test selection module, so that the self-test selection module connects the external standard pulse source and the signal preprocessing module. Then, after connecting to the standard pulse source, the current speed when the speed determination result is valid is taken as the measured speed; Next, determine the speed error between the measured speed and the theoretical speed of the standard pulse source; Finally, if the speed error is within the preset error range, a self-test result indicating that the self-test is qualified is generated; if the speed error is not within the preset error range, a self-test result indicating that the self-test is unqualified is generated.

[0079] In one possible implementation, the high-noise-tolerance adaptive speed determination method further includes: If no target pulse speed signal is received within the preset detection time, and the target comparison threshold of the adaptive threshold generation module is the candidate threshold of the lowest gear, a sensor detachment fault is determined, and a first fault signal is sent to the fault indication module. When the target comparison threshold of the adaptive threshold generation module is the candidate threshold of the highest gear, and a preset number of speed determination results show that the speed exceeds the range, a hardware saturation fault is determined to have occurred, and a second fault signal is sent to the fault indication module. If the adaptive threshold generation module fails to maintain the target comparison threshold within the preset deadlock duration, a logical deadlock fault is determined, and a third fault signal is sent to the fault indication module.

[0080] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0081] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0082] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0083] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A high noise-tolerance adaptive speed signal processing device, characterized in that, include: Signal preprocessing module, peak dynamic detection module, adaptive threshold generation module, and CPLD module; The input terminal of the signal preprocessing module is connected to the output terminal of the speed sensor; The signal preprocessing module is used to receive the original rotation speed signal, perform pulse shaping processing on the original rotation speed signal, and obtain the current pulse rotation speed signal. The input terminal of the peak dynamic detection module is connected to the output terminal of the signal preprocessing module. The peak dynamic detection module is used to detect the instantaneous voltage amplitude of the current pulse speed signal in real time to obtain the current speed peak value. The input of the adaptive threshold generation module is connected to the output of the signal preprocessing module and the peak dynamic detection module, respectively. The adaptive threshold generation module is used to generate multiple candidate thresholds corresponding to different gears based on the current peak speed. It receives the gear selection signal output by the CPLD module, uses the candidate threshold corresponding to the gear selection signal as the target comparison threshold, and performs noise filtering on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal. The input terminal of the CPLD module is connected to the output terminal of the adaptive threshold generation module, the first output terminal of the CPLD module is connected to the control terminal of the adaptive threshold generation module, and the second output terminal of the CPLD module is connected to an external display device. The CPLD module is used to determine the current rotational speed based on the target pulse rotational speed signal; and to perform rotational speed determination based on the effective rotational speed range to obtain the rotational speed determination result. When a preset number of speed determination results show that the speed is out of range, the target comparison threshold used by the adaptive threshold generation module is adjusted through the gear selection signal until a preset number of speed determination results show that the speed is valid. Then, the corresponding current speed is output to the external display device.

2. The high noise-tolerance adaptive speed signal processing device as described in claim 1, characterized in that, The CPLD module includes: a pulse counting module, a speed filtering and analysis module, a range judgment module, and a gear management module; the pulse counting module, the speed filtering and analysis module, the range judgment module, and the gear management module are connected in series; the input terminal of the pulse counting module is connected to the output terminal of the adaptive threshold generation module; the first output terminal of the gear management module is connected to the control terminal of the adaptive threshold generation module, and the second output terminal of the gear management module is connected to an external display device. The pulse counting module is used to count the number of effective pulses of the target pulse speed signal within the measurement window, and to determine the original speed based on the number of effective pulses; The speed filtering and analysis module is used to perform exponential smoothing on the original speed to obtain the current speed; The range determination module is used to compare the current speed with the effective speed range and output a speed determination result of speed exceeding the range or speed being valid; wherein, the speed determination result of speed exceeding the range includes the upper limit of speed exceeding the range and the lower limit of speed exceeding the range; The gear management module is used to, when the number of consecutive speed judgment results exceeding the upper limit of the range reaches a preset number, gradually increase the target comparison threshold through the gear selection signal until the preset number of valid speed results are received consecutively. Then, it controls the adaptive threshold generation module to maintain the corresponding target comparison threshold and outputs the current speed to the external display device. Conversely, when the number of consecutive speed judgment results exceeding the lower limit of the range reaches a preset number, it controls the adaptive threshold generation module to, when the number of consecutive speed judgment results exceeds the lower limit of the range reaches a preset number, gradually decrease the target comparison threshold through the gear selection signal until the preset number of valid speed results are received consecutively. Then, it controls the adaptive threshold generation module to maintain the corresponding target comparison threshold and outputs the current speed to the external display device.

3. The high noise-tolerance adaptive speed signal processing device as described in claim 2, characterized in that, The speed filtering and analysis module is also used to obtain the speed after exponential smoothing in the previous measurement window as the historical speed; calculate the speed change between the current speed and the historical speed; and output the historical speed as the current speed when the speed change is greater than a preset speed change threshold.

4. The high noise-tolerance adaptive speed signal processing device as described in claim 3, characterized in that, The gear management module is also used to determine the current speed change rate based on the speed change within a preset mutation monitoring time when the number of continuously received speed judgment results exceeding the lower limit of the range reaches a preset number. When the current speed change rate is greater than the corresponding speed change threshold, the target comparison threshold is lowered by a preset number of gears via the gear selection signal; when the current speed change rate is not greater than the speed change threshold, the target comparison threshold is lowered by one gear via the gear selection signal. Once a preset number of valid speed determination results are received consecutively, the current target comparison threshold is maintained and the current speed is output.

5. The high noise-tolerant adaptive speed signal processing device as described in any one of claims 2-4, characterized in that, The CPLD module further includes: a peak sampling timing control module; the peak dynamic detection module includes a peak hold module and at least two peak detection modules; The input terminal of each peak detection module is connected to the output terminal of the signal preprocessing module, the output terminal of each peak detection module is connected to the input terminal of the peak hold module, the control terminal of each peak detection module is connected to the output terminal of the peak sampling timing control module, and the output terminal of the peak hold module is connected to the input terminal of the adaptive threshold generation module. The peak sampling timing control module is used to select two peak detection modules from at least two peak detection modules as a peak detection module group, and output a timing-interleaved rotation control signal to the two peak detection modules in the peak detection module group, so that the two peak detection modules in the peak detection module group alternately enter the detection mode and the discharge mode, and at any time at least one peak detection module is in the detection mode. The peak detection module is used to detect the instantaneous voltage amplitude of the current pulse speed signal in detection mode and output the effective signal peak value to the peak holding module; in discharge mode, it performs a reset operation and stops outputting the effective signal peak value. The peak hold module is used to buffer and convert the effective signal peak value to digital-to-analog conversion to obtain the current speed peak value and output it.

6. The high noise-tolerant adaptive speed signal processing device as described in claim 5, characterized in that, The peak detection module includes: a first comparator, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a first controllable switch, and a second controllable switch; The non-inverting input of the first comparator is connected to the output of the first operational amplifier, the inverting input of the first comparator is connected to the output of the signal preprocessing module, and the output of the first comparator is connected to the inverting input of the first operational amplifier via the first resistor. The non-inverting input of the first operational amplifier is connected to ground, and the output of the first operational amplifier is connected to the non-inverting input of the second operational amplifier via the second resistor; the third resistor, the first capacitor, and the first controllable switch are respectively connected in parallel between the inverting input of the first operational amplifier and the output of the first operational amplifier. The first terminal of the second capacitor is connected between the second resistor and the non-inverting input terminal of the second operational amplifier, and the second terminal of the second capacitor is connected to ground; the second controllable switch is connected in parallel with the second capacitor; The inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the input terminal of the peak hold module; The control terminals of the first controllable switch and the second controllable switch are respectively connected to the peak sampling timing control module.

7. The high noise-tolerant adaptive speed signal processing device as described in claim 5, characterized in that, The adaptive threshold generation module includes: a multi-threshold generation module, a gating switch, a timing selection logic circuit, and a noise filtering module; The input terminal of the multi-threshold generation module is connected to the output terminal of the peak dynamic detection module, and each output terminal of the multi-threshold generation module is connected to the corresponding input terminal of the gating switch; the control terminal of the gating switch is connected to the output terminal of the timing selection logic circuit, and the output terminal of the gating switch is connected to the input terminal of the noise filtering module; the output terminal of the noise filtering module is connected to the input terminal of the CPLD module; the input terminal of the timing selection logic circuit is connected to the first output terminal of the CPLD module. The timing selection logic circuit is used to generate the channel selection signal of the gating switch according to the gear selection signal; The multi-threshold generation module is used to generate multiple candidate thresholds for different gears based on the current peak speed. The gating switch is used, under the control of the channel selection signal, to use the candidate threshold corresponding to the gear selection signal as the target comparison threshold. The noise filtering module is used to perform noise filtering on the current pulse speed signal based on the target comparison threshold to obtain the target pulse speed signal.

8. The high noise-tolerance adaptive speed signal processing device as described in claim 7, characterized in that, The multi-threshold generation module includes: a series voltage divider resistor network and multiple buffers; The series voltage divider resistor network is connected between the current peak speed and ground to form multiple voltage divider nodes, each of which corresponds to a candidate threshold; each voltage divider node is connected to the input terminal of the gating switch via a corresponding buffer.

9. The high noise-tolerance adaptive speed signal processing device as described in claim 1, characterized in that, The signal preprocessing module includes: a shaping filter circuit and a one-way integral comparison circuit; The input terminal of the shaping filter circuit is connected to the output terminal of the speed sensor, and the output terminal of the shaping filter circuit is connected to the input terminal of the one-way integral comparison circuit; the output terminal of the one-way integral comparison circuit is connected to the input terminals of the peak dynamic detection module and the adaptive threshold generation module, respectively. The shaping and filtering circuit is used to perform amplitude limiting, bandpass filtering and pulse shaping on the original speed signal to obtain a pre-shaped pulse signal; The unidirectional integration comparison circuit is used to perform threshold comparison on the pre-shaping pulse signal, and to perform unidirectional integration processing on the pre-shaping pulse signal that passes the comparison to obtain the current pulse speed signal.

10. The high noise-tolerant adaptive speed signal processing device as described in claim 9, characterized in that, The unidirectional integrator-comparison circuit includes: a second comparator, a threshold voltage divider network, and a unidirectional integrator; The non-inverting input of the second comparator is connected to the output of the shaping filter circuit, the inverting input of the second comparator is connected to the output of the threshold voltage divider network, and the output of the second comparator is connected to the input of the one-way integrator; the output of the one-way integrator is connected to the inputs of the peak dynamic detection module and the adaptive threshold generation module, respectively. The threshold voltage divider network is used to output the integral threshold; The second comparator is used to compare the pre-shaped pulse signal with the integration threshold, and output the effective pulses in the pre-shaped pulse signal that are higher than the integration threshold; The unidirectional integrator is used to perform unidirectional integration on the effective pulse to generate the current pulse speed signal.

11. The high noise-tolerance adaptive speed signal processing device as described in claim 9, characterized in that, Also includes: Self-test selection module; The first input terminal of the self-test selection module is connected to the output terminal of the speed sensor, the second input terminal of the self-test selection module is connected to an external standard pulse source, and the output terminal of the self-test selection module is connected to the CPLD module. The self-test selection module is used to connect the speed sensor to the signal preprocessing module, or to connect an external standard pulse source to the signal preprocessing module. When the self-test enable is active, the CPLD module sends a channel switching command to the self-test selection module, enabling the self-test selection module to connect the external standard pulse source to the signal preprocessing module; after connecting the standard pulse source, the current speed when the speed determination result is valid is used as the measured speed; and the speed error between the measured speed and the theoretical speed of the standard pulse source is determined. When the rotational speed error is within the preset error range, a self-test result indicating that the self-test is qualified is generated. If the speed error is not within the preset error range, a self-test result indicating that the self-test is unqualified will be generated.

12. The high noise-tolerant adaptive speed signal processing device as described in claim 11, characterized in that, Also includes: Fault indication module; The input terminal of the fault indication module is connected to the CPLD module; The fault indication module is used to execute a fault indication corresponding to the fault signal after receiving a first fault signal, a second fault signal, or a third fault signal. The CPLD module is used to determine a sensor detachment fault when it does not receive the target pulse speed signal within a preset detection time and the target comparison threshold of the adaptive threshold generation module is the candidate threshold of the lowest gear, and sends a first fault signal to the fault indication module; when the target comparison threshold of the adaptive threshold generation module is the candidate threshold of the highest gear and a preset number of speed determination results are continuously over the range, it determines a hardware saturation fault and sends a second fault signal to the fault indication module. When the adaptive threshold generation module fails to maintain the target comparison threshold within the preset deadlock duration, a logical deadlock fault is determined to have occurred, and a third fault signal is sent to the fault indication module.

13. A high noise-to-margin adaptive tachometer, characterized in that, include: A speed sensor, a display device, and a high noise-tolerant adaptive speed signal processing device as described in any one of claims 1-12; The output terminal of the speed sensor is connected to the input terminal of the speed signal processing device; the input terminal of the display device is connected to the output terminal of the speed signal processing device.

14. A high-noise-tolerance adaptive rotational speed determination method, characterized in that, include: The original speed signal output by the speed sensor is acquired, and the original speed signal output by the speed sensor is pulse shaped to obtain the current pulse speed signal; The instantaneous voltage amplitude of the current pulse speed signal is detected in real time to obtain the current speed peak value; Based on the current peak speed, multiple candidate thresholds corresponding to different gears are generated, and one of the candidate thresholds is set as the target comparison threshold according to the gear selection signal. Based on the target comparison threshold, the current pulse speed signal is subjected to noise filtering to obtain the target pulse speed signal; The current rotational speed is determined based on the target pulse rotational speed signal; the current rotational speed is then judged based on the effective rotational speed range to obtain the rotational speed judgment result; If a preset number of consecutive speed determination results indicate that the speed is out of range, the gear selection signal is adjusted to switch the target comparison threshold until a preset number of consecutive speed determination results indicate that the speed is valid, at which point the current speed is output.

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