DMA engine system for satellite-borne SAR in-orbit imaging processing based on instruction set

Abstract

The invention discloses a direct memory access (DMA) engine system for satellite-borne synthetic aperture radar (SAR) in-orbit imaging processing based on an instruction set, relates to the technical field of remote sensing satellites, and solves the technical problems of overuse of DMA resources and low data access efficiency caused by repeated configuration and execution of a large number of transmission commands and address increase commands in the prior art. The AXIS bus module is used for configuring a register related to transmission in the register-level instruction processing module; after the configuration of the register is completed, writing a data access operation instruction into the instruction memory read-write module through the AXIS bus module; the instruction set read-write analysis module reads the instruction data from the instruction memory read-write module and analyzes the instruction data to obtain a control instruction; controlling the state machine to jump through the control instruction, and outputting a control signal; a control signal enters the one-dimensional instruction analysis module after passing through the one-dimensional read-write instruction module; and the one-dimensional instruction analysis module is controlled by the control signal to perform read-write operation on the data.

Description

Technical Field

[0001] This invention belongs to the field of remote sensing satellites and relates to on-orbit real-time information processing technology for remote sensing satellites, specifically a DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction sets. Background Technology

[0002] Spaceborne synthetic aperture radar, or spaceborne SAR, is an active sensor based on microwave imaging principles. It transmits broadband signals and applies synthetic aperture technology to obtain two-dimensional high-resolution images. Compared with traditional optical imaging and hyperspectral imaging, spaceborne SAR imaging can eliminate interference from clouds, fog, and darkness, and has the characteristics of all-weather, all-time, high-resolution, and long-range detection. Its application scenarios include important fields such as Earth remote sensing, military reconnaissance, and resource exploration.

[0003] The DMA engine widely used in existing spaceborne SAR real-time imaging processors is ARMpl330w_DMA, which can flexibly access data from any source address and transfer it to any destination address; it is flexible in use and performs well. However, in the real-time imaging processing of spaceborne SAR, there are a large number of fixed and repetitive address jumps. In this scenario, existing technologies need to repeatedly configure and execute a large number of transmission commands and address increment commands, resulting in long CPU usage time and DMA engine execution time, causing excessive use of DMA resources and low data access efficiency. Summary of the Invention

[0004] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set, which is used to solve the technical problem that in the real-time imaging processing of spaceborne SAR, there are a large number of fixed and repetitive address jumps. In this scenario, the prior art needs to repeatedly configure and execute a large number of transmission commands and address increment commands, resulting in long CPU occupation time and DMA engine execution time, causing excessive use of DMA resources and low data access efficiency.

[0005] To achieve the above objectives, the first aspect of the present invention provides a DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set, comprising: an instruction set read / write parsing module, a register-level instruction processing module, a one-dimensional instruction read / write module, a one-dimensional instruction parsing module, a data cache read / write module, an instruction memory read / write module, and an AXIS bus module. The AXIS bus module is used to configure the transfer-related registers in the register-level instruction processing module; after the registers are configured, the data access operation instructions are written to the instruction memory read / write module through the AXIS bus module. The instruction set read / write parsing module reads instruction data from the instruction memory read / write module and parses the instruction data to obtain control instructions; it controls the state machine to jump through the control instructions and outputs control signals; the control signals pass through the one-dimensional read / write instruction module and enter the one-dimensional instruction parsing module; the control signals control the one-dimensional instruction parsing module to perform read / write operations on the data.

[0006] Preferably, the instruction set read / write parsing module is the core module of the DMA engine system, including read instruction logic, instruction decoding logic, state machine logic, and state machine control-related logic; the register-level instruction processing module contains all the registers in the DMA engine system; the one-dimensional instruction parsing module is used to implement the AXI interface read / write bus logic; and the instruction memory read / write module stores the read / write related instructions of the DMA engine system.

[0007] Preferably, the DMA engine system supports three data transfer modes during operation, including: In the first data transmission method, after the AXI read interface in the one-dimensional instruction parsing module reads data from the bus, it transmits the data to other addresses on the bus through the AXIS_master interface; In the second data transmission method, after the AXIS_slave interface receives data from the bus, it outputs the data to other addresses on the bus through the AXI write interface in the one-dimensional instruction parsing module. The third data transmission method directly interconnects the AXIS_master interface and the AXIS_slave interface outside the DMA engine system, realizing a data transmission path of AXI read interface - AXIS_master interface - AXIS_slave interface - AXI write interface.

[0008] Preferably, the DMA engine system is equipped with a dedicated instruction set for spaceborne SAR data transmission control, including: DMASTART, INS_SETADD, INS_ADDADDR, INS_LOOP, INS_LOOPEND, INS_D1D, and DMAEND; wherein each dedicated instruction set includes a read instruction set and a write instruction set; The DMASTART instruction is used to control the DMA engine system to start a data transfer task; the INS_SETADD instruction is used to set the source address or destination address; the INS_ADDADDR instruction is used to increment the source address or destination address. The INS_LOOP instruction is used to control the DMA loop to execute instruction operations; the INS_LOOPEND instruction is used to control the DMA loop to end; the INS_D1D instruction is used to control data transmission; and the DMAEND instruction is used to control the DMA engine system to end data transmission. The instructions in the dedicated instruction set are issued by the CPU and received and processed by the DMA engine system.

[0009] Preferably, the application of the dedicated instruction set includes: When the DMASTART instruction is received, the state machine starts working; when the INS_SETADD instruction is received, the state machine parses the starting address information of the AXI bus protocol; when the INS_ADDADDR instruction is received, the state machine parses the new address information after the address is incremented after a data transfer is completed. When the INS_LOOP instruction is received, the state machine parses the loop count and enters a loop state based on the loop count; the INS_LOOP instruction contains the loop count; when the INS_LOOPEND instruction is received, the state machine ends the loop state; when the INS_D1D instruction is received, the state machine parses the information required for one AXI bus protocol data transmission; when the DMAEND instruction is received, the state machine returns to the initial state.

[0010] Preferably, the instructions in the dedicated instruction set are issued by the CPU and received and processed by the DMA engine system, including: The CPU writes a dedicated instruction set into the DMA engine system via the APB bus; the dedicated instruction set includes a write instruction set and a read instruction set. The write instruction set is written to the on-chip write memory unit through the register-level instruction processing module; the read instruction set is written to the on-chip read memory unit through the register-level instruction processing module. The instruction write parsing unit reads the write instructions from the on-chip write memory unit one by one and transmits the write instructions to the data cache write unit for parsing; the instruction read parsing unit reads the read instructions from the on-chip read memory unit one by one and transmits the read instructions to the data cache read unit for parsing. The data cache read / write module parses read / write instructions to obtain circuit signals conforming to the AXI bus protocol, and reads / writes peripheral storage units through the AXI bus protocol to obtain circuit signals conforming to the AXIS bus protocol; it also reads / writes peripheral data processing units through the AXIS bus protocol; the data cache read / write module includes a data cache read unit and a data cache write unit.

[0011] Preferably, the step of controlling the state machine to perform transitions via control commands includes: The initial state of the DMA engine system is idle. The CPU starts the DMA controller to work. When the DMA controller receives the DMA_STAREAT pulse signal sent by the CPU through the APB bus, the state machine jumps to the L0 state. When the state machine jumps to the L0 state and receives the INS_LOOP instruction, the state machine jumps to the L1 state and begins the first loop state. When the state machine jumps to the L0 state and receives the DMAEND instruction, the state machine jumps to the IDLE state, putting the state machine into the idle state. When the state machine transitions to state L0 and receives no instructions, the state machine remains in its current state.

[0012] Preferably, the setting of the cyclic states of the state machine includes: The state machine has three levels of loop states: the first loop state L1, the second loop state L2, and the third loop state L3. When the state machine is in a loop state, it controls the system's energy-saving loop data access operation according to the configured transmission information; when the state machine receives the parsed instruction INS_LOOP, it jumps to the L2, L3 or L4 state. When the state machine receives the parsed instruction DMAEND, it jumps to the IDLE state; when the state machine receives the parsed instruction INS_LOOP and the number of loop states is 0, it jumps back to the loop state.

[0013] Preferably, the setting of the L4 state includes: The L4 state represents the outermost loop of the software. When the DMA engine system exceeds 4 loop levels during editing and running, the state machine will jump to the L4_ERR state and then to the IDLE state in the next clock cycle. The L4_ERR state indicates that the state machine has encountered an error.

[0014] A second aspect of the present invention provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the steps of the system described in the first aspect.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention utilizes a dedicated instruction set for spaceborne SAR data transmission control, which is highly compatible with typical application scenarios in real-time on-orbit imaging processing of spaceborne SAR. By using DMA instructions related to loop cycles, it changes the traditional instruction logic for data access, reducing the need for repetitive configuration and execution of data transmission commands, thereby significantly improving data processing efficiency. The dedicated instruction set avoids the need to repeatedly configure and execute hundreds or thousands of data transmission commands and address increment commands in scenarios with a large number of fixed and repetitive address jumps, thereby reducing instruction storage overhead and CPU usage time.

[0016] 2. The DMA engine of this invention supports three data transmission modes, including AXI-in, AXI-out, AXI-in, and AXI-in, AXI-out direct interconnection modes; covering most application scenarios of on-orbit real-time imaging processing of spaceborne SAR, providing a flexible data transmission solution; by optimizing the design of the DMA engine, the technical solution of this invention improves data processing efficiency while also enhancing the performance and reliability of the entire spaceborne SAR system; the efficient data transmission and processing capabilities enable the system to respond to external events more quickly, meeting the needs of long-term continuous observation and rapid response to major events. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the DMA engine system architecture of the present invention; Figure 2 This is a schematic diagram of the state transitions of the state machine in the DMA engine system of this invention. Detailed Implementation

[0019] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please see Figure 1The first aspect of the present invention provides a DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set, including: an instruction set read / write parsing module, a register-level instruction processing module, a one-dimensional instruction read / write module, a one-dimensional instruction parsing module, a data cache read / write module, an instruction memory read / write module, and an AXIS bus module; The AXIS bus module is used to configure the transfer-related registers in the register-level instruction processing module; after the registers are configured, the data access operation instructions are written to the instruction memory read / write module through the AXIS bus module. The instruction set read / write parsing module reads instruction data from the instruction memory read / write module and parses the instruction data to obtain control instructions; it controls the state machine to jump through the control instructions and outputs control signals; the control signals pass through the one-dimensional read / write instruction module and enter the one-dimensional instruction parsing module; the control signals control the one-dimensional instruction parsing module to perform read / write operations on the data.

[0021] It should be noted that the instruction set read / write parsing module includes an instruction set read unit and an instruction set write unit; the one-dimensional instruction read / write module includes a one-dimensional instruction read unit and a one-dimensional instruction write unit; the one-dimensional instruction parsing module includes a one-dimensional read instruction parsing unit and a one-dimensional write instruction parsing unit; the data cache read / write module includes a data cache read unit and a data cache write unit; the instruction memory read unit and the instruction memory write unit; and the AXIS bus module includes an AXIS bus transmit protocol unit and an AXIS bus receive protocol unit.

[0022] In one possible implementation of this invention, combined with Figure 1 ,like Figure 2 As shown: The instruction set read / write parsing module is the core module of the DMA engine system, including read instruction logic, instruction decoding logic, state machine logic, and state machine control-related logic; the register-level instruction processing module contains all the registers in the DMA engine system; the one-dimensional instruction parsing module is used to implement the AXI interface read / write bus logic; and the instruction memory read / write module stores the read / write related instructions of the DMA engine system.

[0023] The DMA engine system supports three data transfer modes during operation, including: In the first data transmission method, after the AXI read interface in the one-dimensional instruction parsing module reads data from the bus, it transmits the data to other addresses on the bus through the AXIS_master interface; In the second data transmission method, after the AXIS_slave interface receives data from the bus, it outputs the data to other addresses on the bus through the AXI write interface in the one-dimensional instruction parsing module. The third data transmission method directly interconnects the AXIS_master interface and the AXIS_slave interface outside the DMA engine system, realizing a data transmission path of AXI read interface - AXIS_master interface - AXIS_slave interface - AXI write interface.

[0024] The DMA engine system is equipped with a dedicated instruction set for spaceborne SAR data transmission control, including: DMASTART, INS_SETADD, INS_ADDADDR, INS_LOOP, INS_LOOPEND, INS_D1D, and DMAEND; each dedicated instruction set contains a read instruction set and a write instruction set. The DMASTART instruction is used to control the DMA engine system to start a data transfer task; the INS_SETADD instruction is used to set the source address or destination address; the INS_ADDADDR instruction is used to increment the source address or destination address. The INS_LOOP instruction is used to control the DMA loop to execute instruction operations; the INS_LOOPEND instruction is used to control the DMA loop to end; the INS_D1D instruction is used to control data transmission; and the DMAEND instruction is used to control the DMA engine system to end data transmission. The instructions in the dedicated instruction set are issued by the CPU and received and processed by the DMA engine system.

[0025] The application of the dedicated instruction set includes: When the DMASTART instruction is received, the state machine starts working; when the INS_SETADD instruction is received, the state machine parses the starting address information of the AXI bus protocol; when the INS_ADDADDR instruction is received, the state machine parses the new address information after the address is incremented after a data transfer is completed. When the INS_LOOP instruction is received, the state machine parses the loop count and enters a loop state based on the loop count; the INS_LOOP instruction contains the loop count; when the INS_LOOPEND instruction is received, the state machine ends the loop state; when the INS_D1D instruction is received, the state machine parses the information required for one AXI bus protocol data transmission; when the DMAEND instruction is received, the state machine returns to the initial state.

[0026] It should be noted that the instruction set is set according to the access characteristics of data reading and writing in the on-orbit imaging processing of spaceborne SAR. It changes the logic of traditional address-jumping data access, and describes several repetitive read and write operations with a set of loop instructions, so that it is not necessary to describe them with instructions one by one. Through the combination of dedicated instruction sets, the address-jumping data access situation with arbitrary regularity in imaging processing can be described with concise instructions.

[0027] Instructions in the dedicated instruction set are issued by the CPU and received and processed by the DMA engine system, including: The CPU writes a dedicated instruction set into the DMA engine system via the APB bus; the dedicated instruction set includes a write instruction set and a read instruction set. The write instruction set is written to the on-chip write memory unit through the register-level instruction processing module; the read instruction set is written to the on-chip read memory unit through the register-level instruction processing module. The instruction write parsing unit reads the write instructions from the on-chip write memory unit one by one and transmits the write instructions to the data cache write unit for parsing; the instruction read parsing unit reads the read instructions from the on-chip read memory unit one by one and transmits the read instructions to the data cache read unit for parsing. The data cache read / write module parses read / write instructions to obtain circuit signals conforming to the AXI bus protocol, and reads / writes peripheral storage units through the AXI bus protocol to obtain circuit signals conforming to the AXIS bus protocol; it also reads / writes peripheral data processing units through the AXIS bus protocol; the data cache read / write module includes a data cache read unit and a data cache write unit.

[0028] The step of controlling the state machine to jump via control commands includes: The initial state of the DMA engine system is idle. The CPU starts the DMA controller to work. When the DMA controller receives the DMA_STAREAT pulse signal sent by the CPU through the APB bus, the state machine jumps to the L0 state. When the state machine jumps to the L0 state and receives the INS_LOOP instruction, the state machine jumps to the L1 state and begins the first loop state. When the state machine jumps to the L0 state and receives the DMAEND instruction, the state machine jumps to the IDLE state, putting the state machine into the idle state. When the state machine transitions to state L0 and receives no instructions, the state machine remains in its current state.

[0029] The setting of the cyclic states of the state machine includes: The state machine has three levels of loop states: the first loop state L1, the second loop state L2, and the third loop state L3. When the state machine is in a loop state, it controls the system's energy-saving loop data access operation according to the configured transmission information; when the state machine receives the parsed instruction INS_LOOP, it jumps to the L2, L3 or L4 state. When the state machine receives the parsed instruction DMAEND, it jumps to the IDLE state; when the state machine receives the parsed instruction INS_LOOP and the number of loop states is 0, it jumps back to the loop state.

[0030] The setting of the L4 state includes: The L4 state represents the outermost loop of the software. When the DMA engine system exceeds 4 loop levels during editing and running, the state machine will jump to the L4_ERR state and then to the IDLE state in the next clock cycle. The L4_ERR state indicates that the state machine has encountered an error.

[0031] It should be noted that each state in the dedicated state machine of this invention can fully cover the application scenarios required for real-time on-orbit imaging processing of spaceborne SAR.

[0032] Based on the above steps, a dedicated instruction set for spaceborne SAR data transmission control is used, which is highly matched to typical application scenarios in real-time on-orbit imaging processing of spaceborne SAR. By using DMA instructions related to loop, the traditional data access instruction logic is changed, reducing the need for repeated configuration and execution of data transmission commands, thereby significantly improving data processing efficiency. The dedicated instruction set avoids the need to repeatedly configure and execute hundreds or thousands of data transmission commands and address increment commands in scenarios with a large number of fixed and repetitive address jumps, thereby reducing instruction storage overhead and CPU usage time.

[0033] The DMA engine supports three data transmission modes, including AXI-in-AXIS-out, AXIS-in-AXI-out, and AXI-in-AXI-out direct interconnection modes; it covers most application scenarios of on-orbit real-time imaging processing of spaceborne SAR and provides a flexible data transmission solution; by optimizing the design of the DMA engine, the technical solution of this invention improves data processing efficiency while also enhancing the performance and reliability of the entire spaceborne SAR system; the efficient data transmission and processing capabilities enable the system to respond to external events more quickly, meeting the needs of long-term continuous observation and rapid response to major events.

[0034] A second aspect of the present invention provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the steps of the system described in the first aspect.

[0035] Some of the data in the above formula are calculated by removing dimensions and taking their numerical values. The formula is the closest to the real situation obtained by software simulation of a large amount of collected data. The preset parameters and preset thresholds in the formula are set by those skilled in the art according to the actual situation or obtained through simulation of a large amount of data.

[0036] The working principle of this invention is as follows: This invention utilizes the AXIS bus module to configure the registers related to transmission in the register-level instruction processing module; after the registers are configured, data access operation instructions are written into the instruction memory read / write module through the AXIS bus module; the instruction set read / write parsing module reads instruction data from the instruction memory read / write module and parses the instruction data to obtain control instructions; the control instructions control the state machine to jump and output control signals; the control signals enter the one-dimensional instruction parsing module after passing through the one-dimensional read / write instruction module; the control signals control the one-dimensional instruction parsing module to perform data read / write operations.

[0037] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A DMA engine system for on-orbit imaging processing of spaceborne SAR based on an instruction set, characterized in that, include: The module includes an instruction set read / write parsing module, a register-level instruction processing module, a one-dimensional instruction read / write module, a one-dimensional instruction parsing module, a data cache read / write module, an instruction memory read / write module, and an AXIS bus module. The AXIS bus module is used to configure the transfer-related registers in the register-level instruction processing module; after the registers are configured, the data access operation instructions are written to the instruction memory read / write module through the AXIS bus module. The instruction set read / write parsing module reads instruction data from the instruction memory read / write module and parses the instruction data to obtain control instructions; it controls the state machine to jump through the control instructions and outputs control signals; the control signals pass through the one-dimensional read / write instruction module and enter the one-dimensional instruction parsing module; the control signals control the one-dimensional instruction parsing module to perform read / write operations on the data.

2. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set as described in claim 1, characterized in that, The instruction set read / write parsing module is the core module of the DMA engine system, including read instruction logic, instruction decoding logic, state machine logic, and state machine control-related logic; the register-level instruction processing module contains all the registers in the DMA engine system; the one-dimensional instruction parsing module is used to implement the AXI interface read / write bus logic; and the instruction memory read / write module stores the read / write related instructions of the DMA engine system.

3. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set as described in claim 1, characterized in that, The DMA engine system supports three data transfer modes during operation, including: In the first data transmission method, after the AXI read interface in the one-dimensional instruction parsing module reads data from the bus, it transmits the data to other addresses on the bus through the AXIS_master interface; In the second data transmission method, after the AXIS_slave interface receives data from the bus, it outputs the data to other addresses on the bus through the AXI write interface in the one-dimensional instruction parsing module. The third data transmission method directly interconnects the AXIS_master interface and the AXIS_slave interface outside the DMA engine system, realizing a data transmission path of AXI read interface - AXIS_master interface - AXIS_slave interface - AXI write interface.

4. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set as described in claim 1, characterized in that, The DMA engine system is equipped with a dedicated instruction set for spaceborne SAR data transmission control, including: DMASTART, INS_SETADD, INS_ADDADDR, INS_LOOP, INS_LOOPEND, INS_D1D, and DMAEND; each dedicated instruction set contains a read instruction set and a write instruction set. The DMASTART instruction is used to control the DMA engine system to start a data transfer task; the INS_SETADD instruction is used to set the source address or destination address; the INS_ADDADDR instruction is used to increment the source address or destination address. The INS_LOOP instruction is used to control the DMA loop to execute instruction operations; the INS_LOOPEND instruction is used to control the DMA loop to end; the INS_D1D instruction is used to control data transmission; and the DMAEND instruction is used to control the DMA engine system to end data transmission. The instructions in the dedicated instruction set are issued by the CPU and received and processed by the DMA engine system.

5. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set according to claim 4, characterized in that, The application of the dedicated instruction set includes: When the DMASTART instruction is received, the state machine starts working; when the INS_SETADD instruction is received, the state machine parses the starting address information of the AXI bus protocol; when the INS_ADDADDR instruction is received, the state machine parses the new address information after the address is incremented after a data transfer is completed. When the INS_LOOP instruction is received, the state machine parses the loop count and enters a loop state based on the loop count; the INS_LOOP instruction contains the loop count; when the INS_LOOPEND instruction is received, the state machine ends the loop state; when the INS_D1D instruction is received, the state machine parses the information required for one AXI bus protocol data transmission; when the DMAEND instruction is received, the state machine returns to the initial state.

6. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set according to claim 4, characterized in that, The instructions in the dedicated instruction set are issued by the CPU and received and processed by the DMA engine system, including: The CPU writes a dedicated instruction set into the DMA engine system via the APB bus; the dedicated instruction set includes a write instruction set and a read instruction set. The write instruction set is written to the on-chip write memory unit through the register-level instruction processing module; the read instruction set is written to the on-chip read memory unit through the register-level instruction processing module. The instruction write parsing unit reads the write instructions from the on-chip write memory unit one by one and transmits the write instructions to the data cache write unit for parsing; the instruction read parsing unit reads the read instructions from the on-chip read memory unit one by one and transmits the read instructions to the data cache read unit for parsing. The data cache read / write module parses read / write instructions to obtain circuit signals conforming to the AXI bus protocol, and reads / writes peripheral storage units through the AXI bus protocol to obtain circuit signals conforming to the AXIS bus protocol; it also reads / writes peripheral data processing units through the AXIS bus protocol; the data cache read / write module includes a data cache read unit and a data cache write unit.

7. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set according to claim 1, characterized in that, The step of controlling the state machine to jump via control commands includes: The initial state of the DMA engine system is idle. The CPU starts the DMA controller to work. When the DMA controller receives the DMA_STAREAT pulse signal sent by the CPU through the APB bus, the state machine jumps to the L0 state. When the state machine jumps to the L0 state and receives the INS_LOOP instruction, the state machine jumps to the L1 state and begins the first loop state. When the state machine jumps to the L0 state and receives the DMAEND instruction, the state machine jumps to the IDLE state, putting the state machine into the idle state. When the state machine transitions to state L0 and receives no instructions, the state machine remains in its current state.

8. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on the instruction set according to claim 7, characterized in that, The setting of the cyclic states of the state machine includes: The state machine has three levels of loop states: the first loop state L1, the second loop state L2, and the third loop state L3. When the state machine is in a loop state, it controls the system's energy-saving loop data access operation according to the configured transmission information; when the state machine receives the parsed instruction INS_LOOP, it jumps to the L2, L3 or L4 state. When the state machine receives the parsed instruction DMAEND, it jumps to the IDLE state; when the state machine receives the parsed instruction INS_LOOP and the number of loop states is 0, it jumps back to the loop state.

9. The DMA engine system for on-orbit imaging processing of spaceborne SAR based on instruction set as described in claim 8, characterized in that, The setting of the L4 state includes: The L4 state represents the outermost loop of the software. When the DMA engine system exceeds 4 loop levels during editing and running, the state machine will jump to the L4_ERR state and then to the IDLE state in the next clock cycle. The L4_ERR state indicates that the state machine has encountered an error.

10. A computer-readable storage medium storing computer program instructions that, when executed by a processor, perform the steps of any one of claims 1-9.

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