Gated clock conversion method and device, electronic equipment and storage medium

Abstract

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

Description

Technical Field

[0001] This invention relates to the fields of chip development and chip testing, and in particular to a gated clock conversion method, apparatus, electronic device, and storage medium. Background Technology

[0002] In application-specific integrated circuit (ASIC) design, clock gating is a common method to reduce system power consumption. Clock gating circuits can prevent the state transition of an entire register group when it is not necessary.

[0003] When applying gated clock circuits to FPGAs (Field Programmable Gate Arrays), the FPGA itself has advanced dedicated clock resources. Configuring a gated clock circuit on top of these resources will interfere with them. Therefore, to meet the requirements of FPGA usage, the gated clock circuit needs to be converted, that is, the gated clock is converted into a clock enable. In the existing technology, gate conversion usually requires the use of existing synthesis tools, based on the synthesis netlist during the logic synthesis stage.

[0004] However, the above-mentioned gated clock conversion method not only requires a long processing time, which greatly affects the logic synthesis performance of the chip, but also the synthesis tools themselves have poor scalability and versatility. Different synthesis tools need to be configured for different design scenarios, which further increases the complexity of gated clock conversion. Summary of the Invention

[0005] This invention provides a gated clock conversion method, apparatus, electronic device, and storage medium to solve the problems of excessively long gated conversion time and overly complex conversion process.

[0006] According to another aspect of the present invention, a gated clock conversion method is provided, comprising:

[0007] Obtain each gated clock unit in the electronic circuit design, and configure each gated clock unit in each field-programmable gate array; wherein, the field-programmable gate array includes all sequential logic devices fanned out by the currently configured gated clock unit;

[0008] Based on the logical expression of each gated clock unit, the truth table of each gated clock unit is obtained, and the truth table is split into different sub-truth tables according to the clock signal value, so as to obtain the target sub-truth table with non-constant output results.

[0009] Obtain the sub-logic expression after clock signal deletion based on the target sub-truth table, and obtain the enable signal of the sequential logic device based on the sub-logic expression.

[0010] After configuring each gated clock unit in its respective field-programmable gate array (FPGA), the method further includes: performing validity checks on each gated clock unit; wherein the validity checks include steady-state constraint checks and timing-independent constraint checks; and obtaining the truth table of each gated clock unit based on its logical expression, which includes: if the current gated clock unit passes the validity check, obtaining the truth table of the current gated clock unit based on its logical expression. Thus, by using validity checks based on truth tables, it ensures that the gated clock units to be converted have the necessary gated conversion foundation, avoiding invalid conversion operations on gated clock units that lack this foundation, and simplifying the complexity of the FPGA conversion process.

[0011] After verifying the validity of each gated clock unit, the process further includes: if the current gated clock unit fails the validity verification, sending the current gated clock unit and the electronic circuit design to a large-scale structural optimization model for structural optimization. This allows for structural optimization of the current gated clock unit by the large-scale structural optimization model. Accordingly, even when a gated clock unit lacking a conversion basis is detected, structural optimization of this type of gated clock unit is achieved, further improving the functional accuracy of the electronic circuit design.

[0012] The step of obtaining the enable signal for the sequential logic device based on the sub-logic expression includes: if the target sub-truth table is determined to be a low-level sub-truth table, inverting the sub-logic expression and using the inverted result as the enable signal for the sequential logic device. Thus, when the target sub-truth table is either a high-level or low-level sub-truth table, matching enable results are obtained through different calculation methods, ensuring the accuracy and completeness of the enable signal calculation results.

[0013] The step of configuring each gated clock unit in a field-programmable gate array (FPGA) includes: configuring multiple gated clock units in the same FPGA based on the number of sequential logic devices fanned out by each gated clock unit; wherein the number of gated clock units configured in the FPGA is negatively correlated with the number of sequential logic devices fanned out by the currently configured gated clock unit. This ensures load balancing for each FPGA, thereby ensuring efficient use of the conversion resources of each FPGA and improving the conversion efficiency of the gated clock units.

[0014] The step of configuring each gated clock unit in a field-programmable gate array (FPGA) includes: configuring multiple gated clock units in the same FPGA according to a first association relationship between the gated clock units; wherein the first association relationship is related to at least one of physical location and combinational logic; and / or configuring gated clock units corresponding to multiple sequential logic devices in the same FPGA according to a second association relationship between sequential logic devices belonging to different gated clock units; wherein the second association relationship is related to at least one of physical location, sequential logic, and device type. This enables the FPGA to perform centralized and homogenized gated clock conversion processing for gated clock units with similar physical locations and combinational logic, and for multiple sequential logic devices with similar physical locations, sequential logic, and device types, thereby improving the FPGA's conversion efficiency.

[0015] According to another aspect of the present invention, a gated clock switching device is provided, comprising:

[0016] A gated clock acquisition module is used to acquire each gated clock unit in the electronic circuit design and configure each gated clock unit in each field-programmable gate array; wherein, the field-programmable gate array includes all sequential logic devices fanned out by the currently configured gated clock unit;

[0017] The truth table acquisition module is used to acquire the truth table of each gated clock unit according to the logical expression of each gated clock unit, and to split the truth table into different sub-truth tables according to the clock signal value, so as to obtain the target sub-truth table with non-constant output results.

[0018] The enable signal acquisition module is used to acquire the sub-logic expression after clock signal deletion based on the target sub-truth table, and to acquire the enable signal of the sequential logic device based on the sub-logic expression.

[0019] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the gated clock conversion method according to any embodiment of the present invention.

[0020] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the gated clock conversion method described in any embodiment of the present invention.

[0021] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the gated clock conversion method described in any embodiment of the present invention.

[0022] The technical solution of this invention involves obtaining each gated clock unit in an electronic circuit design and configuring each gated clock unit in a field-programmable gate array (FPGA). Based on the logical expression of each gated clock unit, a truth table for each gated clock unit is obtained. This truth table is then split into different sub-truth tables based on the clock signal value to obtain a target sub-truth table with non-constant output results. Based on the target sub-truth table, a sub-logic expression after clock signal deletion is obtained, and the enable signal for the sequential logic device is obtained based on the sub-logic expression. This not only reduces the gated clock conversion time and greatly improves the logic synthesis performance of the electronic circuit design, but also avoids the poor scalability and versatility inherent in synthesis tools, reducing the complexity of gated clock conversion.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a gated clock conversion method provided in Embodiment 1 of the present invention;

[0026] Figure 2 This is a schematic diagram of the structure of multiple FPGAs after the electronic circuit design is divided according to Embodiment 1 of the present invention;

[0027] Figure 3 This is a truth representation of a gated circuit unit provided according to Embodiment 1 of the present invention;

[0028] Figure 4 This is a schematic diagram of the process for obtaining the sub-truth table and sub-logic expression according to Embodiment 1 of the present invention;

[0029] Figure 5 This is a schematic diagram of the fan-out processing after conversion of the gate control circuit unit according to Embodiment 1 of the present invention;

[0030] Figure 6This is a flowchart of another gated clock conversion method provided in Embodiment 2 of the present invention;

[0031] Figure 7 This is a schematic diagram of a gated clock conversion device according to Embodiment 3 of the present invention;

[0032] Figure 8 This is a schematic diagram of the structure of an electronic device that implements the gated clock conversion method of this invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] Example 1

[0036] Figure 1 This is a flowchart of a gated clock conversion method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where the enable signal of a sequential logic device is obtained based on the truth table of the gated clock unit. This method can be executed by the gated clock conversion device in any embodiment of the present invention. The gated clock conversion device can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes:

[0037] S101. Obtain each gated clock unit in the electronic circuit design, and configure each gated clock unit in each field-programmable gate array; wherein, the field-programmable gate array includes all sequential logic devices fanned out by the currently configured gated clock unit.

[0038] A gated clock unit refers to a circuit unit that controls the on / off state of a clock signal through logic gates, thereby reducing the dynamic power consumption of digital circuits; fan-out refers to the ability of a gated clock unit to drive multiple downstream devices with its gated clock signal; sequential logic devices are electronic devices whose output signal is determined by the current input signal and the historical state, such as flip-flops (FF), memories, and counters, etc. The signal output by a sequential logic device is the sequential output signal; where historical state refers to the historical state information stored through internal storage elements.

[0039] By traversing the electronic circuit design, the gated clock units and the sequential logic devices fanned out by each gated clock unit are obtained. For example, when a group of registers shares the same enable condition, multiple registers originally driven by a clock can be merged into one gated clock unit, significantly reducing the number of fan-outs. At this time, the gated clock unit obviously fans out multiple sequential logic devices. Each gated clock unit, as well as the sequential logic devices fanned out by the current gated clock unit, is divided into an FPGA, thereby avoiding timing problems across FPGAs.

[0040] For example, each partitioned FPGA can independently process one gated clock unit, and 10 FPGAs can simultaneously process the conversion of 10 gated clock units, significantly reducing the conversion processing time; Figure 2 As shown, three gated clock units and their fan-out sequential logic devices are configured in different FPGAs to complete the gated clock segmentation of the electronic circuit design. In particular, since the number of gated clock units in the electronic circuit design is usually greater than the number of FPGAs available during the testing process, multiple gated clock units are usually configured in each FPGA.

[0041] Optionally, in this embodiment of the invention, configuring each gated clock unit in each field-programmable gate array includes: configuring multiple gated clock units in the same field-programmable gate array according to the number of sequential logic devices fanned out by each gated clock unit; wherein the number of gated clock units configured in the field-programmable gate array is negatively correlated with the number of sequential logic devices fanned out by the currently configured gated clock unit.

[0042] Specifically, the more sequential logic devices fan out by the gated clock unit, the more conversion resources are consumed during FPGA operation. To balance the operating load of each FPGA, a corresponding load value can be configured for each device (including the gated clock unit and sequential logic devices) according to the device type, and a preset load threshold can be configured for each FPGA. Each gated clock unit and its fan-out sequential logic devices are treated as a whole and placed into each FPGA sequentially until the sum of the load values ​​after the current gated clock unit is placed is greater than the preset load threshold of the current FPGA. Then, the current gated clock unit is placed into the next FPGA to ensure load balance of each FPGA. This ensures reasonable utilization of the conversion resources of each FPGA and improves the conversion efficiency of the gated clock unit.

[0043] Optionally, in this embodiment of the invention, configuring each gated clock unit in a field-programmable gate array (FPGA) includes: configuring multiple gated clock units in the same FPGA according to a first association relationship between the gated clock units; wherein the first association relationship is related to at least one of physical location and combinational logic; and / or configuring gated clock units corresponding to multiple sequential logic devices in the same FPGA according to a second association relationship between sequential logic devices belonging to different gated clock units; wherein the second association relationship is related to at least one of physical location, sequential logic, and device type.

[0044] Specifically, in addition to the correlation between the gated clock unit and its fan-out sequential logic devices, the gated clock units may also be correlated based on the proximity of their physical locations and the similarity of their combinational logic. In this case, multiple gated clock units that are physically close and have similar combinational logic can be configured in the same FPGA so that the FPGA can perform centralized and homogenized gated clock conversion processing for gated clock units that are physically close and have similar combinational logic, thereby improving the conversion efficiency of the FPGA.

[0045] Furthermore, sequential logic devices belonging to different gated clock units may also be correlated. In this case, multiple sequential logic devices that are physically close, have similar sequential logic, and are of the same type are configured in the same FPGA. Correspondingly, the gated clock units corresponding to the aforementioned correlated sequential logic devices also need to be configured in the current FPGA, and other sequential logic devices fanned out by the aforementioned gated clock units also need to be configured in the current FPGA. This allows the FPGA to perform centralized and homogenized gated clock conversion processing for multiple sequential logic devices that are physically close, have similar sequential logic, and are of the same type, further improving the conversion efficiency of the FPGA.

[0046] S102. Based on the logical expression of each gated clock unit, obtain the truth table of each gated clock unit, and split the truth table into different sub-truth tables according to the clock signal value, so as to obtain the target sub-truth table with non-constant output results.

[0047] Based on the netlist information of the electronic circuit design, the logical expression of each gated clock unit can be obtained, and a truth table for each gated clock unit can be constructed based on this logical expression. The truth table, in two-dimensional tabular form, lists all possible combinations of input variables and provides the corresponding output values, thus transforming the logical proposition into a computable mathematical model. For example... Figure 3 As shown, the logical expression of the gated clock unit A is “(clk|a)&b”; where clk represents the clock signal, a represents the gated logic signal a, b represents the gated logic signal b, and output represents the output result of the gated clock unit A under the current values ​​of clock signal clk, gated logic signal a, and gated logic signal b.

[0048] The above logical expression means that the clock signal is ORed with the gated logic signal a, and the result is then ANDed with the gated logic signal b, thereby constructing the truth table of the gated clock unit A. Similarly, the logical expression for the gated clock unit B is "clk|a|b"; where the clock signal clk is ORed with the gated logic signal a, and the result is then ORed with the gated logic signal b, thereby constructing the truth table of the gated clock unit B.

[0049] The clock signal value includes low level (i.e., clk=0) and high level (i.e., clk=1). Based on whether the clock signal value is low or high, the truth table is split into two sub-truth tables: a low-level sub-truth table when the clock signal is 0, and a high-level sub-truth table when the clock signal is 1. Figure 4 For example, the upper half of the truth table is the low-level sub-truth table, and the lower half is the high-level sub-truth table.

[0050] In the two sub-truth tables mentioned above, the output result (i.e., the F value) of the high-level sub-truth table is always 1, which means that the output result of the gated clock unit is completely determined by the value of the clock signal, that is, the output result is always equal to the value of the clock signal; the output result of the low-level sub-truth table is not constant, but depends on different combinations (i.e., clock signal clk + gate logic signal a + gate logic signal b), the output result is 0 or 1, and the low-level sub-truth table with an inconsistent output result is selected as the target sub-truth table.

[0051] S103. Obtain the sub-logic expression after clock signal deletion according to the target sub-truth table, and obtain the enable signal of the sequential logic device according to the sub-logic expression.

[0052] Similarly Figure 4 For example, in the target sub-truth table, the clock signal is deleted, and the remaining sub-truth table is retained. Based on the remaining sub-truth table, the corresponding sub-logic expression "a|b" is obtained. If the target sub-truth table is a high-level sub-truth table, the sub-logic expression is the enable signal of the sequential logic device. According to this, the clock signal of the sequential logic device is the original clock signal clk, and the enable signal is the obtained sub-logic expression. This completes the conversion process of the gated logic unit.

[0053] Optionally, in this embodiment of the invention, obtaining the enable signal of the sequential logic device based on the sub-logic expression includes: if the target sub-truth table is determined to be a low-level sub-truth table, inverting the sub-logic expression and using the inverted result as the enable signal of the sequential logic device. Specifically, if the target sub-truth table is a low-level sub-truth table, the sub-logic expression needs to be inverted, and the inverted result is used as the enable signal of the sequential logic device, for example, as described above. Figure 4 The sub-logic expression in the table is “a|b”, and its corresponding inverted result is “!(a|b)”. This inverted result serves as the enable signal for the sequential logic device. Thus, when the target sub-truth table is a high-level sub-truth table or a low-level sub-truth table, the matching enable result is obtained through different calculation methods, ensuring the accuracy and completeness of the enable signal calculation result.

[0054] like Figure 5 As shown, based on the clock signal clk of the clock logic device (i.e., FF) and the enable signal "!(a|b)", the gated clock conversion of the electronic circuit design can be obtained. That is, the original clock signal is used as the clock input of the fan-out sequential logic device, and the enable logic output is used as the enable input of the fan-out sequential logic device. After the parallel processing of each FPGA is completed, the parallel logic synthesis of the electronic circuit design is performed. Since the gated clock conversion has been completed, the gated clock conversion process can be turned off in this step to further improve the logic synthesis performance of the electronic circuit design.

[0055] The technical solution of this invention involves obtaining each gated clock unit in an electronic circuit design and configuring each gated clock unit in a field-programmable gate array (FPGA). Based on the logical expression of each gated clock unit, a truth table for each gated clock unit is obtained. This truth table is then split into different sub-truth tables based on the clock signal value to obtain a target sub-truth table with non-constant output results. Based on the target sub-truth table, a sub-logic expression after clock signal deletion is obtained, and the enable signal for the sequential logic device is obtained based on the sub-logic expression. This not only reduces the gated clock conversion time and greatly improves the logic synthesis performance of the electronic circuit design, but also avoids the poor scalability and versatility inherent in synthesis tools, reducing the complexity of gated clock conversion.

[0056] Example 2

[0057] Figure 6 This is a flowchart of a gated clock conversion method provided in Embodiment 2 of the present invention. The relationship between this embodiment and the above embodiments is that each gated clock unit is pre-verified, such as... Figure 6 As shown, the method includes:

[0058] S201. Obtain each gated clock unit in the electronic circuit design, and configure each gated clock unit in each field-programmable gate array; wherein, the field-programmable gate array includes all sequential logic devices fanned out by the currently configured gated clock unit.

[0059] S202. Perform validity checks on each of the gated clock units; wherein, the validity checks include steady-state constraint checks and timing-independent constraint checks.

[0060] Steady-state constraints refer to the existence of at least one set of gated logic signals (i.e., each gated logic signal has a specified value) that makes the output of the gated clock unit constant. In other words, under this set of gated logic signals, the output does not change with the change of the clock signal. Timing-independent constraints refer to the fact that when the clock signal is at a certain value (i.e., 0 or 1), the change of each gated logic signal will not change the output of the gated clock unit. In other words, when the clock signal is at this value, the output of the gated clock unit remains constant.

[0061] In the above technical solutions Figure 3For example, regarding the logical expression "(clk|a)&b" for gated clock unit A, when the clock signal clk is 0 or 1, the output of the gated clock unit is not constant; it may be 0 or 1. Therefore, gated clock unit A fails the timing-independent constraint check, i.e., it fails the validity check. Regarding the logical expression "clk|a|b" for gated clock unit B, when the clock signal clk is 1, the output is constant at 1, satisfying the timing-independent constraint check. When the gated logic signal a is 0 and the gated logic signal b is 1, the output is constant at 1, satisfying the steady-state constraint check. Therefore, gated clock unit B passes the validity check.

[0062] S203. If it is determined that the current gated clock unit passes the validity check, obtain the truth table of the current gated clock unit according to the logical expression of the current gated clock unit.

[0063] For gated clock units that pass the validity check, they have the foundation for gated conversion and can be converted using the conversion method described in the above technical solution. For gated clock units that fail the validity check, they do not have the foundation for gated conversion and have design defects. In this case, a repair prompt message is issued to guide the designer to repair the gated clock units that fail the validity check, thereby completing the conversion foundation test of the gated clock units based on the truth table.

[0064] Optionally, in this embodiment of the invention, after performing validity checks on each of the gated clock units, the method further includes: if it is determined that the current gated clock unit has failed the validity check, sending the current gated clock unit and the electronic circuit design to the structural optimization model, so as to perform structural optimization on the current gated clock unit through the structural optimization model.

[0065] Specifically, the structural optimization large model refers to the large language model (LLM) based on deep learning. It is a large language model trained with multiple structural optimization samples to meet the structural optimization requirements of the gated clock unit on the basis of the existing general large model. The structural optimization samples include gated clock units that pass the validity check (i.e., positive samples), gated clock units that fail the validity check (i.e., negative samples), and the optimization results corresponding to the negative samples.

[0066] The gated clock units that failed the validity check, along with the current electronic circuit design, are sent to the structural optimization model. The structural optimization model then optimizes these gated clock units, thus completing the validity check of the gated clock units. Based on this, even when gated clock units lacking a conversion basis are detected, structural optimization of this type of gated clock unit is achieved, further improving the functional accuracy of the electronic circuit design. Simultaneously, the optimization results of the structural optimization model are sent to the designers, providing them with a basis for repairing the gated clock units and improving the optimization convenience of the electronic circuit design.

[0067] S204. The truth table is split into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with non-constant output results.

[0068] S205. Obtain the sub-logic expression after deleting the clock signal according to the target sub-truth table, and obtain the enable signal of the sequential logic device according to the sub-logic expression.

[0069] The technical solution of this invention, after performing validity checks on each gated clock unit, if it is determined that the current gated clock unit passes the validity check, obtains the corresponding truth table based on the logical expression of the current gated clock unit. Thus, by performing validity checks based on the truth table, it ensures that the gated clock unit to be converted has the basis for gated conversion, avoids invalid conversion operations on gated clock units that do not have the basis for gated conversion, and simplifies the complexity of the FPGA conversion process.

[0070] Example 3

[0071] Figure 7 This is a structural block diagram of a gated clock conversion device provided in Embodiment 3 of the present invention. The device specifically includes:

[0072] The gated clock acquisition module 301 is used to acquire each gated clock unit in the electronic circuit design and configure each gated clock unit in each field-programmable gate array; wherein, the field-programmable gate array includes all sequential logic devices fanned out by the currently configured gated clock unit;

[0073] The truth table acquisition module 302 is used to acquire the truth table of each gated clock unit according to the logical expression of each gated clock unit, and to split the truth table into different sub-truth tables according to the clock signal value, so as to obtain the target sub-truth table with non-constant output results.

[0074] The enable signal acquisition module 303 is used to acquire the sub-logic expression after clock signal deletion according to the target sub-truth table, and acquire the enable signal of the sequential logic device according to the sub-logic expression.

[0075] The technical solution of this invention involves obtaining each gated clock unit in an electronic circuit design and configuring each gated clock unit in a field-programmable gate array (FPGA). Based on the logical expression of each gated clock unit, a truth table for each gated clock unit is obtained. This truth table is then split into different sub-truth tables based on the clock signal value to obtain a target sub-truth table with non-constant output results. Based on the target sub-truth table, a sub-logic expression after clock signal deletion is obtained, and the enable signal for the sequential logic device is obtained based on the sub-logic expression. This not only reduces the gated clock conversion time and greatly improves the logic synthesis performance of the electronic circuit design, but also avoids the poor scalability and versatility inherent in synthesis tools, reducing the complexity of gated clock conversion.

[0076] Optionally, the gated clock conversion device is further configured to perform validity checks on each of the gated clock units; wherein the validity checks include steady-state constraint checks and timing-independent constraint checks; if it is determined that the current gated clock unit passes the validity check, the truth table of the current gated clock unit is obtained according to the logical expression of the current gated clock unit.

[0077] Optionally, the gated clock conversion device is further configured to, if it is determined that the current gated clock unit has failed the validity check, send the current gated clock unit and the electronic circuit design to the structural optimization large model, so as to perform structural optimization on the current gated clock unit through the structural optimization large model.

[0078] Optionally, the enable signal acquisition module 303 is specifically used to, if it is determined that the target sub-truth table is a low-level sub-truth table, invert the sub-logic expression and use the inversion result as the enable signal of the sequential logic device.

[0079] Optionally, the gated clock acquisition module 301 is further configured to configure multiple gated clock units in the same field-programmable gate array according to the number of sequential logic devices fanned out by each gated clock unit; wherein the number of gated clock units configured in the field-programmable gate array is negatively correlated with the number of sequential logic devices fanned out by the currently configured gated clock unit.

[0080] Optionally, the gated clock acquisition module 301 is further configured to configure multiple gated clock units in the same field-programmable gate array according to a first association relationship between the gated clock units; wherein the first association relationship is related to at least one of physical location and combinational logic; and / or configure the gated clock units corresponding to multiple sequential logic devices in the same field-programmable gate array according to a second association relationship between sequential logic devices belonging to different gated clock units; wherein the second association relationship is related to at least one of physical location, sequential logic, and device type.

[0081] The above-described apparatus can execute the gated clock conversion method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the gated clock conversion method provided in any embodiment of the present invention.

[0082] Example 4

[0083] Figure 8 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, electronic devices, blade electronic devices, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0084] like Figure 8 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0085] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0086] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the gated clock conversion method.

[0087] In some embodiments, the gated clock conversion method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as a memory cell. In some embodiments, part or all of the computer program may be loaded and / or installed on a heterogeneous hardware accelerator via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the gated clock conversion method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the gated clock conversion method by any other suitable means (e.g., by means of firmware).

[0088] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0089] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0090] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0091] To provide user interaction, the systems and techniques described herein can be implemented on a heterogeneous hardware accelerator, which includes: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the heterogeneous hardware accelerator. Other types of devices can also be used to provide user interaction; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or haptic feedback); and input from the user can be received in any form (including sound input, voice input, or haptic input).

[0092] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0093] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0094] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0095] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gated clock conversion method, characterized in that, include: Obtain each gated clock unit in the electronic circuit design, and configure each gated clock unit in each field-programmable gate array; wherein, the field-programmable gate array includes all sequential logic devices fanned out by the currently configured gated clock unit; Based on the logical expression of each gated clock unit, the truth table of each gated clock unit is obtained, and the truth table is split into different sub-truth tables according to the clock signal value, so as to obtain the target sub-truth table with non-constant output results. Obtain the sub-logic expression after clock signal deletion based on the target sub-truth table, and obtain the enable signal of the sequential logic device based on the sub-logic expression.

2. The gated clock conversion method according to claim 1, characterized in that, After configuring each of the gated clock units in its respective field-programmable gate array, the method further includes: Each gated clock unit is validated for validity; wherein, the validity validation includes steady-state constraint validation and timing-independent constraint validation. The step of obtaining the truth table of each gated clock unit based on the logical expression of each gated clock unit includes: If the current gated clock unit is determined to have passed the validity check, the truth table of the current gated clock unit is obtained based on its logical expression.

3. The gated clock conversion method according to claim 2, characterized in that, After performing validity checks on each of the gated clock units, the process further includes: If it is determined that the current gated clock unit has failed the validity check, the current gated clock unit and the electronic circuit design are sent to the structural optimization model so that the current gated clock unit can be structurally optimized by the structural optimization model.

4. The gated clock conversion method according to claim 1, characterized in that, The step of obtaining the enable signal of the sequential logic device based on the sub-logic expression includes: If the target sub-truth table is determined to be a low-level sub-truth table, the sub-logic expression is inverted, and the inversion result is used as the enable signal for the sequential logic device.

5. The gated clock conversion method according to claim 1, characterized in that, The step of configuring each of the gated clock units in a field-programmable gate array includes: Based on the number of sequential logic devices fanned out by each gated clock unit, multiple gated clock units are configured in the same field-programmable gate array (FPGA); wherein the number of gated clock units configured in the FPGA is negatively correlated with the number of sequential logic devices fanned out by the currently configured gated clock unit.

6. The gated clock conversion method according to claim 1, characterized in that, The step of configuring each of the gated clock units in a field-programmable gate array includes: Based on a first association between the gated clock units, multiple gated clock units are configured in the same field-programmable gate array; wherein, the first association is related to at least one of physical location and combinational logic; And / or, based on a second association between sequential logic devices belonging to different gated clock units, the gated clock units corresponding to multiple sequential logic devices are configured in the same field-programmable gate array; wherein, the second association is related to at least one of physical location, sequential logic, and device type.

7. A gated clock switching device, characterized in that, include: A gated clock acquisition module is used to acquire each gated clock unit in the electronic circuit design and configure each gated clock unit in each field-programmable gate array; wherein, the field-programmable gate array includes all sequential logic devices fanned out by the currently configured gated clock unit; The truth table acquisition module is used to acquire the truth table of each gated clock unit according to the logical expression of each gated clock unit, and to split the truth table into different sub-truth tables according to the clock signal value, so as to obtain the target sub-truth table with non-constant output results. The enable signal acquisition module is used to acquire the sub-logic expression after clock signal deletion based on the target sub-truth table, and to acquire the enable signal of the sequential logic device based on the sub-logic expression.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the gated clock conversion method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the gated clock conversion method according to any one of claims 1-6.

10. A computer program product comprising a computer program that, when executed by a processor, implements the gated clock conversion method according to any one of claims 1-6.

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