Chip abnormal defect identification method based on multi-template fusion and storage medium

Abstract

The invention discloses a chip abnormal defect identification method based on multi-template fusion and a storage medium. The method comprises the following steps: step 1, constructing a chip defect detection model based on deep learning; step 2, collecting each type of chip image; 3, based on median fusion, obtaining an ideal chip image of each type of chips; step 4, carrying out image difference; step 5, performing sliding cutting on the difference image to obtain chip difference images with the same size and overlapped set sizes; step 6, training a chip defect detection model; step 7, performing differential operation and sliding cutting on the to-be-detected chip image; step 8, predicting a chip defect type and a defect position in a corresponding set chip difference image by using the trained chip defect detection model; and finally, determining the position of the defect in the original to-be-detected chip according to the difference image number of the chip with the set size. According to the invention, the appearance difference between chips of different models can be reduced, the universality of the model is improved, and the defect identification precision is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of industrial anomaly detection, and in particular to a chip anomaly defect identification method based on multi-template fusion and a storage medium. BACKGROUND

[0002] Chip defect detection is one of the important applications of industrial anomaly detection. Chip detection is mainly divided into two stages of front and back. The front detection is mainly for the detection of wafers, and the back detection is for the detection of finished chips. In back detection, wafers are first cut to obtain individual die (also known as "Die"). After processes such as mounting, bonding, encapsulation, and marking, the die becomes a usable finished chip. In these processes, especially after cutting, the chip is prone to defects such as dust, dirt, edge collapse, scratches, color difference, and cracks. These defects may affect the performance and reliability of the chip, or cause the chip to fail. Therefore, strict defect detection is required at every step of chip production to screen out unqualified products.

[0003] After cutting the wafer, the appearance of the cut die needs to be detected for defects to exclude unqualified chips. The traditional detection is completed by manual visual inspection. The manufacturer will arrange quality inspection personnel to visually inspect the chips one by one according to the process requirements to screen out unqualified chips. However, this method has great subjectivity, and the quality of visual inspection will decrease due to fatigue after a long time of work. Generally, defect detection based on machine vision is mainly based on template matching method. A standard chip is used to make a template, and during detection, the template is used to difference with the chip image to be detected, and then the abnormal pixel value in the difference image is used to judge and detect defects. This method can detect relatively obvious defects, but the stability of the detection result depends largely on the threshold setting of the difference image abnormal value. If the threshold is set too loosely, defects may be missed, and if the threshold is set too strictly, false positives may occur. Moreover, using a uniform threshold parameter globally may also cause false positives due to imaging differences caused by different chip positions. The present application uses a target detection model to detect defects in the difference image, and uses the different scale receptive fields of the neural network to ensure that defects of the same scale are detected.

[0004] Furthermore, various defects may occur on chips during the manufacturing process. Even among defects of the same type, their appearances can vary significantly. Therefore, using target detection methods based on defect feature morphology can easily lead to missed detections, especially for unlabeled defects. Each time a new defect is discovered, the dataset needs to be supplemented and the detection model retrained. On the other hand, if an anomaly detection model is used based on positive sample training, the significant differences in appearance between different chip models necessitate training with chips of all models in the dataset. However, sample collection is a major challenge, and the size compatibility of different product models can also affect the model's detection performance. Therefore, defect detection for bare chips currently relies primarily on manual visual inspection. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a chip anomaly defect identification method based on multi-template fusion. This chip anomaly defect identification method based on multi-template fusion can reduce the appearance differences between different chip models, improve the universality of the model, and has high defect identification accuracy.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A chip anomaly defect identification method based on multi-template fusion includes the following steps.

[0008] Step 1: Construct a deep learning-based chip defect detection model. Its input is a differential image of a chip of a set size, and its output is the chip defect type and the defect location in the differential image of the chip of the set size.

[0009] Step 2: Determine the total number of all types of chips to be tested and collect N images of each type of chip; where N > M.

[0010] Step 3: Align the M chip images for each type of chip and fuse them based on the median to obtain the ideal chip image for each type of chip.

[0011] Step 4: Perform a difference operation on N chip images of each type of chip and an ideal chip image of the same type to obtain the corresponding chip difference image.

[0012] Step 5: Slide and cut each chip differential image of each type according to the set size in Step 1 to obtain chip differential images of the same size and with overlap, thereby forming an input sample library; then, mark the defect type and location of each chip differential image of the set size in the input sample library to obtain an output sample library.

[0013] Step 6: Train the chip defect detection model using the input and output sample libraries.

[0014] Step 7: Apply the differential operation from Step 4 and the sliding cut from Step 5 to the image of the chip under test to obtain several differential images of the chip under test with a set size and record the corresponding numbers.

[0015] Step 8: Input each differential image of the chip under test with a set size obtained in Step 7 into the trained chip defect detection model to obtain the chip defect type and the defect location in the corresponding differential image of the chip under test; finally, determine the location of the defect in the original chip under test according to the differential image number of the chip under test with a set size.

[0016] It also includes step 9: when the types of chips to be tested increase, repeat steps 2 to 6 to update the chip defect detection model.

[0017] In step 3, at least M / 2 of the M chip images are free of abnormal defects.

[0018] Step 3, the method for obtaining the ideal chip image for each type of chip, includes the following steps:

[0019] Step 3-1: Select one image from the M chip images of each type of chip, after grayscale transformation, as the reference template image.

[0020] Step 3-2: Perform grayscale transformation and affine transformation on the remaining M-1 chip images of each type of chip to form M-1 standard chip images that are the same size and aligned with the reference template image.

[0021] Step 3-3: Perform pixel-by-pixel fusion of M-1 standard chip images with the reference template image, and use the median value of each pixel as the corresponding pixel value of the ideal chip image of the corresponding type of chip.

[0022] In step 3-3, the pixel value of the pixel in the m-th row and n-th column of the ideal chip image. The calculation formula is:

[0023] .

[0024] In the formula, These are the pixel values ​​of the m-th row and n-th column pixel in the 1st, 2nd, ..., Mth standard chip images or reference template images, respectively.

[0025] This is a function for finding the median.

[0026] In step 4, grayscale transformation and affine transformation are performed on N chip images of each type of chip to form standard chip images with the same specifications and dimensions as the reference template image. Then, a difference operation is performed between each standard chip image and the ideal chip image to eliminate the identical parts between the two images, retaining the difference pairs, i.e.:

[0027] .

[0028] In the formula, Let be the pixel value of the pixel in the m-th row and n-th column of the chip differential image;

[0029] This represents the pixel value of the pixel in the m-th row and n-th column of the standard chip image.

[0030] Let be the pixel value of the pixel in the m-th row and n-th column of the ideal chip image.

[0031] C is a constant.

[0032] Step 5, the sliding cutting method includes the following steps:

[0033] Step 5-1: Based on the width and height of the chip differential image DiffImage, and size Determining the horizontal and vertical directions requires a number of sliding divisions.

[0034] Step 5-2: Slide and segment the chip differential image DiffImage sequentially from left to right and from top to bottom; during the sliding and segmentation process, maintain the overlap of the sliding windows of OverV in the horizontal direction and maintain the overlap of the sliding windows of OverH in the vertical direction.

[0035] Step 5-3: Calculate the pixel value corresponding to the pixel in the m-th row and n-th column of the i-th segmented image. for:

[0036] .

[0037] In the formula, , .

[0038] In step 1, the chip defect detection model is the YOLOv11 model.

[0039] A storage medium storing a computer program that, when run, executes a chip anomaly defect identification method based on multi-template fusion.

[0040] An electronic device, including a storage medium.

[0041] The present invention has the following beneficial effects:

[0042] 1. This invention first creates a standard chip template, then uses the standard template to perform affine transformations on multiple chip images to obtain a series of standard chip images. The affine transformation ensures high consistency between different standard chip images. Median fusion is performed on the series of standard images to obtain a reliable ideal image. Subsequently, the chip to be detected is affine transformed and its difference from the ideal chip image is calculated. The difference image is then slidably segmented according to certain rules to obtain several smaller difference images. These segmented difference images are then fed into a pre-trained anomaly detection model for detection. Based on the model's output, defect localization is performed, ultimately revealing the chip's defect anomaly status.

[0043] 2. This invention utilizes a median fusion method, which can obtain an ideal chip image even without a large number of positive samples, making it very convenient for chip defect detection with small sample sizes. Pre-training the model using difference images can minimize appearance differences between different chip models, improving the model's versatility. Introducing a sliding segmentation method, which cuts an image into several standard-sized images, ensures both the consistency of model input and the versatility of the pre-trained model for chips of different sizes. Attached Figure Description

[0044] Figure 1 The flowchart of a chip anomaly defect identification method based on multi-template fusion according to the present invention is shown.

[0045] Figure 2 This diagram illustrates the process of automatically focusing and acquiring a reference template image in an embodiment of the present invention.

[0046] Figure 3 This diagram illustrates how an ideal chip image is obtained from a series of chip images in an embodiment of the present invention.

[0047] Figure 4 The pixel value distribution of a certain pixel in a series of chip images in an embodiment of the present invention is shown.

[0048] Figure 5 The distribution of pixel values ​​after singular value filtering is shown in an embodiment of the present invention.

[0049] Figure 6 The image shown is of a chip under test containing defects according to an embodiment of the present invention, wherein the defects present in the chip are indicated by the red box.

[0050] Figure 7 The image shown is a differential image after differential processing of the chip image to be detected and the ideal chip image in an embodiment of the present invention, wherein the defects present in the chip are within the red box.

[0051] Figure 8 The figure shows a series of standard difference images obtained by sliding segmentation of the difference image in an embodiment of the present invention, wherein the defects in the chip are within the red box; (a) shows a schematic diagram of sliding window segmentation; (b) shows a schematic diagram after segmentation.

[0052] Figure 9 The diagram shows the detection results of the defect detection model on the differential image in an embodiment of the present invention, where the defects detected are shown in the blue box.

[0053] Figure 10 This illustration shows a defect detection diagram after relocating the model detection results in the original image in an embodiment of the present invention, where the defects present in the chip are shown in the red box. Detailed Implementation

[0054] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0055] like Figure 1 As shown, a chip anomaly defect identification method based on multi-template fusion includes the following steps.

[0056] Step 1: Construct a deep learning-based chip defect detection model. Its input is a differential image of a chip of a set size, and its output is the chip defect type and the defect location in the differential image of the chip of the set size.

[0057] In this embodiment, the chip defect detection model is preferably a YOLOv11 model pre-trained on a large general dataset (such as COCO).

[0058] Step 2: Determine the total number of all types of chips to be tested and collect N images of each type of chip; where N > M.

[0059] Step 3: Align the M chip images for each type of chip and fuse them based on the median to obtain the ideal chip image for each type of chip. The M chip images must contain at least M / 2 images without abnormal defects, meaning the number of positive samples is greater than the number of defective samples.

[0060] like Figure 2 and Figure 3 As shown, the method for obtaining the ideal chip image for each type of chip preferably includes the following steps.

[0061] Step 3-1: Select one image from the M chip images of each type of chip, after grayscale transformation, as the reference template image.

[0062] A. For chips that do not significantly affect the appearance, they can be used to build a chip matching template. Images can be acquired from the chip, and the chip can be clearly imaged by autofocus (or manual focus). Click "New Template" to create a reference template for matching.

[0063] B. Convert the created baseline template from a three-channel color image to a single-channel grayscale image. Specifically, the processing rules during the image conversion are as follows:

[0064]

[0065] Where Gray[m,n] is the grayscale value of the pixel in the m-th row and n-th column of the single-channel grayscale image, and R[m,n], G[m,n], and B[m,n] are the pixel values ​​of the pixel in the m-th row and n-th column of the color image in the R, G, and B channels, respectively. The conversion from a three-channel color image to a single-channel grayscale image is achieved by weighted summing of the pixel values ​​from different channels of the color image.

[0066] C. After obtaining the grayscale image, the specific region of the chip in the image is obtained by using operations such as grayscale threshold segmentation, morphological operations, and region feature filtering. The grayscale image is then cropped using this region to obtain an image containing only one chip, which is the reference template image. This image is saved in the corresponding template folder for easy template matching.

[0067] Step 3-2: Perform grayscale transformation and affine transformation on the remaining M-1 chip images of each type of chip to form M-1 standard chip images that are the same size and aligned with the reference template image.

[0068] A. Select a chip and focus it to achieve a clear image. Perform grayscale transformation on the chip image to be added, obtaining a single-channel chip grayscale image.

[0069] B. Obtain the approximate region Region1 of the chip to be added in its grayscale image through threshold segmentation, morphological processing and other methods.

[0070] C. Using the reference template image obtained in step 3-1, perform template search in Region1 of the grayscale image to obtain the specific position of the chip in the grayscale image and perform registration, and obtain the center coordinates [Center_Row, Center_Column] of the chip to be added in the image, and the rotation angle Rotate_Angle relative to the reference template image.

[0071] D. Calculate the center coordinates [Row, Column] of the reference template image and set the angle of the reference template image to 0 degrees; then, calculate the center coordinates [Center_Row, Center_Column] and its rotation angle Rotate_Angle of the image to be added to obtain a transformation matrix Trans for rigidly transforming (rotating, translating) the image:

[0072]

[0073] In the formula, It is a translation matrix. It is a rotation matrix. The matrix satisfies:

[0074]

[0075]

[0076] Furthermore, since the translation matrix and rotation matrix can be written as:

[0077] ,

[0078] Right now,

[0079]

[0080] In the formula, X and Y are the coefficients to be determined, while Rotate_Angle is the counterclockwise angle between the vector formed by the coordinates [Row, Column] and the origin and the vector formed by the coordinates [Center_Row, Center_Column] and the origin.

[0081] After solving for the transformation matrix Trans, the chip image to be added can be transformed to match the size of the reference template image, thereby completing the acquisition of a series of highly consistent standard images.

[0082] Step 3-3: Perform pixel-by-pixel fusion of the M-1 standard chip images and the reference template image, and use the median value of each pixel as the corresponding pixel value of the ideal chip image for the corresponding type of chip. Replacing the original values ​​with the median value can, to some extent, overcome the influence of imaging noise on pixel values ​​and improve the robustness of the synthesized image. Furthermore, singular value filtering before median fusion can further suppress the influence of abrupt pixel values ​​(such as defect points) on the fusion process, thus ensuring that the fused image is "perfect". The specific steps are as follows:

[0083] First, we statistically analyze the pixel value distribution g(n) of the N images at the pixel location to be merged, such as... Figure 4As shown. Then, singular value filtering is applied to the obtained pixel value distribution g of a specific pixel to remove outliers and prevent them from affecting the final synthesized image during the fusion process. The filtering rules are as follows:

[0084]

[0085]

[0086]

[0087] in, It is half the length of the filter window. Here are the filter coefficients, and the filtering result is as follows: Figure 5 As shown.

[0088] The data obtained after singular value filtering is more stable. Finally, median fusion is performed on the filtered data to obtain the fused pixel value of a certain pixel. Here, the pixel value of the pixel in the m-th row and n-th column of the ideal chip image is... The calculation formula is:

[0089] .

[0090] In the formula, These are the pixel values ​​of the m-th row and n-th column pixel in the 1st, 2nd, ..., Mth standard chip images or reference template images, respectively.

[0091] This is a function for finding the median.

[0092] Step 4: Perform a difference operation on N chip images of each type of chip and an ideal chip image of the same type to obtain the corresponding chip difference image.

[0093] Specifically, the process involves: performing grayscale and affine transformations on N chip images of each chip type to create standard chip images with the same dimensions as the reference template image; then, performing a difference operation between each standard chip image and the ideal chip image to eliminate identical parts and retain the difference pairs, i.e.:

[0094] .

[0095] In the formula, Let be the pixel value of the pixel in the m-th row and n-th column of the chip differential image;

[0096] This represents the pixel value of the pixel in the m-th row and n-th column of the standard chip image.

[0097] Let be the pixel value of the pixel in the m-th row and n-th column of the ideal chip image.

[0098] C is a constant.

[0099] Step 5: Slide and cut each chip differential image of each type according to the size set in Step 1 to obtain chip differential images of the same size and with overlap, thereby forming the input sample library.

[0100] The above-mentioned sliding cutting method preferably includes the following steps.

[0101] Step 5-1: Based on the width and height of the chip differential image DiffImage, and size Determining the horizontal and vertical directions requires a number of sliding divisions.

[0102] Step 5-2: Slide and segment the chip differential image DiffImage sequentially from left to right and from top to bottom; during the sliding and segmentation process, maintain the overlap of the sliding windows of OverV in the horizontal direction and maintain the overlap of the sliding windows of OverH in the vertical direction.

[0103] Step 5-3: Calculate the pixel value corresponding to the pixel in the m-th row and n-th column of the i-th segmented image. for:

[0104] .

[0105] In the formula, , .

[0106] Next, each differential image of a chip of a set size in the input sample library is finely annotated with the defect type and location, including the defect bounding box and category information, thus obtaining the output sample library.

[0107] Object detection networks have requirements regarding the size of the input image; for example, the YOLO series networks require an input image size of 640 pixels. Larger images, such as those with a resolution of 640, require downsampling before being input into the network to meet its requirements. However, downsampling typically leads to a loss of image precision, even missing smaller defects. This invention employs sliding cutting to replace the downsampling process. It utilizes a window of a specific size (typically 640). 640) Regular cropping of the input image ensures that the cropped image meets the input requirements of the detection model without losing image accuracy or filtering out small defects. Furthermore, during the sliding cropping process, adjacent cropping windows overlap, ensuring that most defects on the boundary lines are removed intact and distributed across multiple images. This means a single defect is detected multiple times, further improving the defect detection rate. As shown in the figure below, after cropping, the large rectangular image is divided into four smaller images of equal size, and the defect in the lower right corner is divided into two images. Figure 8 As shown.

[0108] Step 6: Train the chip defect detection model using the input and output sample libraries.

[0109] Initial training phase: Freeze the parameters of the backbone network and the neck network.

[0110] Training only the detection head part allows the model to quickly learn specific features of a new dataset without destroying the general features extracted by the pre-trained model.

[0111] After several rounds of training (such as when the loss of the detection model on the validation set begins to stabilize), unfreeze all network layers and perform smooth end-to-end fine-tuning using a lower learning rate (such as 1 / 8 of the previous learning rate) until the model training is complete.

[0112] This invention utilizes a chip defect detection model to detect defects in differentially analyzed images, and leverages the receptive fields of different scales in a neural network to ensure the detection of defects at the same scale.

[0113] Step 7, for example Figure 6 The chip under test shown is used in step 4 for differential operation to obtain the following result: Figure 7 The chip differential image shown; Figure 7 The chip differential image is then sliced ​​using a sliding method according to step 5 to obtain the following... Figure 6 Several differential images of the chip under test with a set size are shown, and their corresponding numbers are recorded.

[0114] Step 8: Input each differential image of the chip under test with a set size obtained in Step 7 into the trained chip defect detection model to obtain the chip defect type and the defect location in the corresponding differential image of the set size chip; finally, determine the location of the defect in the original chip under test according to the differential image number of the chip with the set size chip, such as 9 and Figure 10 As shown.

[0115] Step 9: When the types of chips to be tested increase, repeat steps 2 to 6 to update the chip defect detection model.

[0116] The present invention also provides a storage medium, wherein a computer program stored in the storage medium executes the above-described chip anomaly defect identification method based on multi-template fusion when running. The present invention also provides an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the above-described chip anomaly defect identification method based on multi-template fusion through the computer program.

[0117] The sequence numbers of the above embodiments of the present invention are merely for description and do not represent the superiority or inferiority of the embodiments. In the above embodiments of the present invention, the descriptions of each embodiment have their own emphasis; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units can be a logical functional division, and in actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces; the indirect coupling or communication connection of units or modules can be electrical or other forms. The units described as separate components may or may not be physically separated; the components shown as units may or may not be physical units, that is, they can be located in one place or distributed across multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of this embodiment. Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, optical disks, and other media capable of storing program code.

[0118] The chip anomaly defect identification method based on multi-template fusion provided by this invention uses a multi-image fusion approach to obtain standard chip images. The fusion process can use both qualified and defective samples, significantly reducing the need for standard samples in synthesizing standard chip images. It also effectively reduces the impact and interference of imaging noise on the standard image, improving the robustness of the standard image. Secondly, this invention utilizes a differential method to retain only the anomalies in the image as much as possible, reducing the impact of differences between chips on the detection effect. Furthermore, a sliding image cropping method is introduced to make the defect detection model compatible with chip image inputs of various sizes without affecting image resolution. Finally, this invention performs frozen training on a target detection model pre-trained on a large general dataset to achieve model transfer, resulting in a defect detection model suitable for chips.

[0119] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A chip anomaly defect identification method based on multi-template fusion, characterized in that: Includes the following steps: Step 1: Construct a chip defect detection model based on deep learning. Its input is a differential image of a chip of a set size, and its output is the chip defect type and the defect location in the differential image of the chip of the set size. Step 2: Determine the total number of all types of chips to be tested and collect N images of each type of chip; where N > M; Step 3: Align the M chip images for each type of chip and fuse them based on the median to obtain the ideal chip image for each type of chip; Step 4: Perform a difference operation on N chip images of each type of chip and an ideal chip image of the same type to obtain the corresponding chip difference image; Step 5: Slide and cut each chip differential image of each type according to the set size in Step 1 to obtain chip differential images of the same size and with overlap, thereby forming an input sample library; then, mark the defect type and location of each chip differential image of the set size in the input sample library to obtain an output sample library. Step 6: Train the chip defect detection model using the input and output sample libraries; Step 7: Apply the differential operation from Step 4 and the sliding cut from Step 5 to the image of the chip under test to obtain several differential images of the chip under test of a set size and record the corresponding numbers. Step 8: Input each differential image of the chip under test with a set size obtained in Step 7 into the trained chip defect detection model to obtain the chip defect type and the defect location in the corresponding differential image of the chip under test; finally, determine the location of the defect in the original chip under test according to the differential image number of the chip under test with a set size.

2. The chip anomaly defect identification method based on multi-template fusion according to claim 1, characterized in that: It also includes step 9: when the types of chips to be tested increase, repeat steps 2 to 6 to update the chip defect detection model.

3. The chip anomaly defect identification method based on multi-template fusion according to claim 1, characterized in that: In step 3, at least M / 2 of the M chip images are free of abnormal defects.

4. The chip anomaly defect identification method based on multi-template fusion according to claim 1, characterized in that: Step 3, the method for obtaining the ideal chip image for each type of chip, includes the following steps: Step 3-1: Select one image from the M chip images of each type of chip, after grayscale transformation, as the reference template image; Step 3-2: Perform grayscale transformation and affine transformation on the remaining M-1 chip images of each type of chip to form M-1 standard chip images that are the same size and aligned with the reference template image. Step 3-3: Perform pixel-by-pixel fusion of M-1 standard chip images with the reference template image, and use the median value of each pixel as the corresponding pixel value of the ideal chip image of the corresponding type of chip.

5. The chip anomaly defect identification method based on multi-template fusion according to claim 4, characterized in that: In step 3-3, the pixel value of the pixel in the m-th row and n-th column of the ideal chip image. The calculation formula is: ； In the formula, These are the pixel values ​​of the m-th row and n-th column pixel in the 1st, 2nd, ..., Mth standard chip images or reference template images, respectively. This is a function for finding the median.

6. The chip anomaly defect identification method based on multi-template fusion according to claim 1, characterized in that: In step 4, grayscale transformation and affine transformation are performed on N chip images of each type of chip to form standard chip images with the same specifications and dimensions as the reference template image. Then, a difference operation is performed between each standard chip image and the ideal chip image to eliminate the identical parts between the two images, retaining the difference pairs, i.e.: ； In the formula, Let be the pixel value of the pixel in the m-th row and n-th column of the chip differential image; This represents the pixel value of the pixel in the m-th row and n-th column of the standard chip image. Let be the pixel value of the pixel in the m-th row and n-th column of the ideal chip image; C is a constant.

7. The chip anomaly defect identification method based on multi-template fusion according to claim 1, characterized in that: Step 5, the sliding cutting method includes the following steps: Step 5-1: Based on the width and height of the chip differential image DiffImage, and size Determining the horizontal and vertical directions requires the number of sliding divisions; Step 5-2: Slide and segment the chip differential image DiffImage sequentially from left to right and from top to bottom; during the sliding and segmentation process, maintain the overlap of the sliding windows over V in the horizontal direction and maintain the overlap of the sliding windows over H in the vertical direction. Step 5-3: Calculate the pixel value corresponding to the pixel in the m-th row and n-th column of the i-th segmented image. for: ； In the formula, , .

8. The chip anomaly defect identification method based on multi-template fusion according to claim 1, characterized in that: In step 1, the chip defect detection model is the YOLOv11 model.

9. A storage medium, characterized in that: When the computer program stored in the storage medium is run, it executes the chip abnormality defect identification method based on multi-template fusion as described in any one of claims 1-8.

10. An electronic device, characterized in that: Includes the storage medium as described in claim 9.

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