Voltage conversion circuit based on thin gate oxide device

Abstract

The invention provides a voltage conversion circuit based on a thin gate oxide device, which comprises a charge pump circuit and a level conversion circuit connected with the control end of the charge pump circuit, and is characterized in that the level conversion circuit converts a plurality of input control signals in a power domain from 0 to VDD into output control signals in a plurality of target power domains, the charge pump circuit boosts the VDD based on the plurality of output control signals to obtain an output voltage. The voltage difference between the lowest voltage and the highest voltage of each target power supply domain is set to be smaller than the gate-source breakdown voltage of the thin gate-oxide device, so that the absolute value of the gate-source voltage of each transistor in the charge pump circuit is smaller than the gate-source breakdown voltage of the thin gate-oxide device, and the thin gate-oxide device can be adopted by each transistor in the charge pump circuit; according to the invention, the high-voltage output charge pump based on the thin gate oxide device can be realized, the area occupied by the circuit can be reduced to realize circuit miniaturization, and the circuit cost can also be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a voltage conversion circuit based on a thin gate oxide device. BACKGROUND

[0002] Conventional low-voltage output charge pumps are mostly designed based on thin gate oxide devices, and high-voltage output charge pumps are mostly designed based on thick gate oxide devices. This is because, due to the process gate oxide limitation of a Metal Oxide Semiconductor Field Effect (MOS) transistor, high voltage will cause gate oxide breakdown, so that the thin gate oxide device cannot meet the high-voltage output requirement.

[0003] However, since the area and cost of the thin gate oxide device are lower than those of the thick gate oxide device, if a high-voltage output charge pump is designed based on the existing thick gate oxide device, the area occupied by the circuit will be large and the cost of the circuit will be high. SUMMARY

[0004] The present disclosure provides a voltage conversion circuit based on a thin gate oxide device, which can reduce the area occupied by the circuit to realize miniaturization of the circuit, and also can reduce the cost of the circuit.

[0005] The present disclosure provides a voltage conversion circuit based on a thin gate oxide device, which includes a charge pump circuit and a level conversion circuit connected to a control end of the charge pump circuit.

[0006] The level conversion circuit is configured to convert a plurality of input control signals in a power supply domain of 0 to a power supply voltage into output control signals in a plurality of target power supply domains, and the voltage difference between the lowest voltage and the highest voltage of each target power supply domain is less than the gate-source breakdown voltage of the thin gate oxide device.

[0007] The charge pump circuit is configured to perform voltage boosting processing on the power supply voltage based on the plurality of output control signals to obtain an output voltage, and the absolute value of the gate-source voltage of each transistor in the charge pump circuit under the action of the plurality of output control signals is less than the gate-source breakdown voltage.

[0008] In the technical solution of the present disclosure, the voltage conversion circuit based on the thin gate oxide device includes a charge pump circuit and a level conversion circuit connected to the control end of the charge pump circuit. The level conversion circuit converts a plurality of input control signals in a power supply domain of 0 to a power supply voltage VDD into output control signals in a plurality of target power supply domains. The charge pump circuit performs voltage boosting processing on VDD based on the plurality of output control signals to obtain an output voltage. By setting the voltage difference between the lowest voltage and the highest voltage of each target power supply domain to be less than the gate-source breakdown voltage of the thin gate oxide device, the absolute value of the gate-source voltage of each transistor in the charge pump circuit is less than the gate-source breakdown voltage of the thin gate oxide device. Thus, each transistor in the charge pump circuit can use a thin gate oxide device, a high-voltage output charge pump based on the thin gate oxide device can be realized, the area occupied by the circuit can be reduced to realize miniaturization of the circuit, and the cost of the circuit can be reduced.

[0009] The above description is only a summary of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which form a part of the present application, are used to provide a further understanding of the present application, so that other features, purposes and advantages of the present application become more obvious. The schematic embodiment drawings of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A structure schematic diagram of a voltage conversion circuit based on a thin gate oxide device is provided for the embodiments of the present disclosure.

[0011] Figure 2 A structure schematic diagram of another voltage conversion circuit based on a thin gate oxide device is provided for the embodiments of the present disclosure.

[0012] FIGS. 3(a) and 3(b) are working timing diagrams of a forward charge pump circuit provided for the embodiments of the present disclosure.

[0013] Figure 4 A structure schematic diagram of another voltage conversion circuit based on a thin gate oxide device is provided for the embodiments of the present disclosure.

[0014] Figure 5 A working timing diagram of a negative charge pump circuit is provided for the embodiments of the present disclosure.

[0015] Figure 6 A circuit schematic diagram of a forward level converter is provided for the embodiments of the present disclosure.

[0016] Figure 7A circuit schematic diagram of a negative level shifter provided for an embodiment of the present disclosure.

[0017] Figure 8 A structure schematic diagram of still another voltage conversion circuit based on a thin gate oxide device provided for an embodiment of the present disclosure.

[0018] Figure 9 A circuit schematic diagram of a signal generation circuit provided for an embodiment of the present disclosure.

[0019] Figure 10 An output signal timing diagram of the signal generation circuit provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present disclosure.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "electrically connected" together shall mean that the parts are either directly connected to one another or connected to one another through one or more intermediary parts.

[0022] Reference in the specification to "an embodiment", "another embodiment", "an example", "an alternate example", etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will understand that the embodiments described and illustrated herein are presented by way of example only and are not intended to limit the scope of the application.

[0023] In addition, the terms "first", "second", and the like in the description and in the claims of the present disclosure or above-described drawings are used to distinguish different objects, and are not used to describe a particular order, and can explicitly or implicitly include one or more of the features.

[0024] The term "and / or", in the present disclosure, is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent three cases of existence of A, existence of A and B, and existence of B. In addition, the character " / " in this paper generally represents that the front and rear associated objects are an "or" relationship.

[0025] In the description of the present disclosure, unless otherwise specified, the meanings of "a plurality of" and "at least two" are two or more (including two), and similarly, "a plurality of groups" and "at least two groups" mean two or more groups (including two groups).

[0026] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings.

[0027] Figure 1 The structural schematic diagram of a voltage conversion circuit based on a thin gate oxide device provided by an embodiment of the present disclosure is shown in Figure 1 As shown, the voltage conversion circuit 100 includes a level conversion circuit 110 and a charge pump circuit 120. A plurality of input terminals of the level conversion circuit 110 are connected one by one with a plurality of input control signals (CLK_IN_1 to CLK_IN_m) under a power supply domain of 0 to a power supply voltage (VDD), a plurality of output terminals of the level conversion circuit 110 are connected one by one with a plurality of control terminals of the charge pump circuit 120, an input terminal of the charge pump circuit 120 is connected with VDD, and an output terminal of the charge pump circuit 120 is connected with an output terminal of the voltage conversion circuit 100.

[0028] The level conversion circuit 110 is configured to convert a plurality of input control signals (CLK_IN_1 to CLK_IN_m) under a power supply domain of 0 to VDD into a plurality of output control signals (CLK_OUT_1 to CLK_OUT_m) under a plurality of target power supply domains, and the voltage difference between the lowest voltage and the highest voltage of each target power supply domain is less than the gate-source breakdown voltage BVgs of the thin gate oxide device.

[0029] The charge pump circuit 120 is configured to perform voltage boosting processing on VDD based on a plurality of output control signals (CLK_OUT_1 to CLK_OUT_m) to obtain an output voltage Vout, and under the action of the plurality of output control signals (CLK_OUT_1 to CLK_OUT_m), the absolute value of the gate-source voltage of each transistor in the charge pump circuit 120 is less than the gate-source breakdown voltage BVgs.

[0030] An exemplary Figure 2 The structural schematic diagram of another voltage conversion circuit based on a thin gate oxide device provided by an embodiment of the present disclosure is shown in Figure 2As shown, the level conversion circuit 110 includes a positive level conversion circuit 111, and the charge pump circuit 120 includes a positive charge pump circuit 121.

[0031] Multiple positive input control signals (CLK_INP_1 to CLK_INP_4) are connected one-to-one with multiple input terminals of the positive level conversion circuit 111, and multiple output terminals of the positive level conversion circuit 111 are connected one-to-one with multiple control terminals of the positive charge pump circuit 121 to output multiple positive output control signals (CLK_OUTP_1 to CLK_OUTP_4). The input terminal of the positive charge pump circuit 121 is connected to VDD, and the output terminal of the positive charge pump circuit 121 is connected to the positive output terminal of the voltage conversion circuit 100.

[0032] See also Figure 2 The forward charge pump circuit 121 includes a first flying capacitor Cfly1. The forward level shifting circuit 111 includes a first forward level shifter LS_P_1, a second forward level shifter LS_P_2, a third forward level shifter LS_P_3, and a fourth forward level shifter LS_P_4. The ground terminals of the first forward level shifter LS_P_1, the second forward level shifter LS_P_2, the third forward level shifter LS_P_3, and the fourth forward level shifter LS_P_4 are connected to reference ground (GND). The first power supply terminals of the first forward level shifter LS_P_1, the second forward level shifter LS_P_2, the third forward level shifter LS_P_3, and the fourth forward level shifter LS_P_4 are connected to VDD.

[0033] The second power supply terminal of the first positive level converter LS_P_1 is connected to VDD, the input terminal of the first positive level converter LS_P_1 is connected to the first positive input control signal CLK_INP_1, and the output terminal of the first positive level converter LS_P_1 is connected to the first control terminal of the positive charge pump circuit 121 to output the first positive output control signal CLK_OUTP_1.

[0034] The second power supply terminal of the second positive level converter LS_P_2 is connected to VDD. The input terminal of the second positive level converter LS_P_2 is connected to the second positive input control signal CLK_INP_2. The output terminal of the second positive level converter LS_P_2 is connected to the second control terminal of the positive charge pump circuit 121 to output the second positive output control signal CLK_OUTP_2.

[0035] The second power supply terminal of the third positive level converter LS_P_3 is connected to the positive output terminal of the voltage conversion circuit 100 to receive the positive output voltage (Voutp). The input terminal of the third positive level converter LS_P_3 is connected to the third positive input control signal CLK_INP_3. The output terminal of the third positive level converter LS_P_3 is connected to the third control terminal of the positive charge pump circuit 121 to output the third positive output control signal CLK_OUTP_3.

[0036] The second power supply terminal of the fourth positive level converter LS_P_4 is connected to the positive plate of the first flying capacitor Cfly1. The input terminal of the fourth positive level converter LS_P_4 is connected to the fourth positive input control signal CLK_INP_4. The output terminal of the fourth positive level converter LS_P_4 is connected to the fourth control terminal of the positive charge pump circuit 121 to output the fourth positive output control signal CLK_OUTP_4.

[0037] Among them, the first positive output control signal CLK_OUTP_1 and the second positive output control signal CLK_OUTP_2 are signals in the power domain from 0 to VDD. The third positive output control signal CLK_OUTP_3 is Voutp minus the preset voltage Vpre (Voutp-Vpre) to Voutp (maximum value is...). The signal under the power supply domain of the first flying capacitor Cfly1 is the signal under the power supply domain of the first flying capacitor Cfly1, which is the positive plate voltage (Vcpp) minus the preset voltage Vpre (Vcpp-Vpre). The power supply domains from 0 to VDD, Voutp-Vpre to Voutp, and Vcpp-Vpre to Vcpp are included in multiple first target power supply domains.

[0038] See also Figure 2 The forward charge pump circuit 121 also includes a first load capacitor Cload1, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The control terminal of the first transistor M1 is connected to the output terminal of the first forward level converter LS_P_1, the control terminal of the second transistor M2 is connected to the output terminal of the second forward level converter LS_P_2, the control terminal of the third transistor M3 is connected to the output terminal of the third forward level converter LS_P_3, and the control terminal of the fourth transistor M4 is connected to the output terminal of the fourth forward level converter LS_P_4.

[0039] The first transistor M1 and the second transistor M2 are connected in series between the input terminal of the positive charge pump circuit 121 and GND. The third transistor M3 and the fourth transistor M4 are connected in series between the output terminal and the input terminal of the positive charge pump circuit 121. The negative plate of the first flying capacitor Cfly1 is connected to the connection point of the first transistor M1 and the second transistor M2. The positive plate of the first flying capacitor Cfly1 is connected to the connection point of the third transistor M3 and the fourth transistor M4 and the second power supply terminal of the fourth positive level shifter LS_P_4. The first load capacitor Cload1 is connected between the output terminal of the positive charge pump circuit 121 and GND.

[0040] Exemplarily, as Figure 2 shown, the first transistor M1, the third transistor M3, and the fourth transistor M4 are PMOS, and the second transistor M2 is NMOS. The source of the first transistor M1 and the drain of the fourth transistor M4 are connected to the input terminal of the positive charge pump circuit 121. The source of the second transistor M2 is connected to GND. The source of the third transistor M3 is connected to the output terminal of the positive charge pump circuit 121.

[0041] Since the first positive output control signal CLK_OUTP_1 and the second positive output control signal CLK_OUTP_2 are signals in the power supply domain from 0 to VDD, the gate voltages of the first transistor M1 and the second transistor M2 are from 0 to VDD. Then, the source-gate voltage of the first transistor M1 and the gate-source voltage of the second transistor M2 are less than or equal to VDD. Among them, VDD is from 3V to 3.6V, and the gate-source breakdown voltage BVgs of the thin gate oxide device is approximately 5.5V. Then VDD < BVgs. Therefore, the first transistor M1 and the second transistor M2 can adopt thin gate oxide devices.

[0042] It should be understood that when the positive charge pump circuit 121 starts to work, the voltage of the first power supply terminal is powered on (i.e., reaches the preset rated working voltage). The voltage of the positive plate of the first flying capacitor Cfly1 (Vcpp) is pulled up to near the voltage of the first power supply terminal (the initial state voltage of Vcpp) through the body parasitic diode of the fourth transistor M4. At the same time, Voutp is also pulled to the voltage of the first power supply terminal by the external circuit. The voltage of the first power supply terminal pre-charges the positive plate of the first flying capacitor Cfly1 through the body parasitic diode of the fourth transistor M4, making Vcpp stable near the voltage of the first power supply terminal.

[0043] FIG. 3 is a working timing diagram of the positive charge pump circuit provided by the embodiment of the present disclosure, which is divided into two stages. In the first stage, Voutp < V ITP , the auxiliary control signal CTRL is at a high level, and the working timing of the positive charge pump circuit is as shown in FIG. 3(a); in the second stage, Voutp ≥ V ITP, when the auxiliary control signal CTRL is at a low level, the working timing of the positive charge pump circuit is shown in Fig. 3(b).

[0044] Among them, V ITP is a threshold voltage for detecting the output of the positive charge pump circuit 121 (the positive output of the voltage conversion circuit 100), and VDD < V ITP ≤ V0, V0 < BVgs. For example, V0 = 5V.

[0045] As shown in Fig. 3(a), at this time, Voutp < V ITP , the third positive output control signal CLK_OUTP_3 is a signal in the power domain from 0 to Voutp, and the fourth positive output control signal CLK_OUTP_4 is a signal in the power domain from 0 to Vcpp. Therefore, the gate voltages of the third transistor M3 and the fourth transistor M4 are from 0 to Voutp and from 0 to Vcpp respectively, and the source-gate voltages of the third transistor M3 and the fourth transistor M4 are Voutp and Vcpp respectively. At this time, Voutp < V ITP < BVgs, VDD ≤ Vcpp < V ITP < BVgs. Then the third transistor M3 and the fourth transistor M4 can use thin gate oxide devices.

[0046] As Figure 3b shown, after the positive charge pump circuit 121 goes through multiple cycles, Voutp ≥ V ITP , at this time, the third positive output control signal CLK_OUTP_3 is a signal in the power domain from Voutp - Vpre to Voutp, and the fourth positive output control signal CLK_OUTP_4 is a signal in the power domain from Vcpp - Vpre to Vcpp. Therefore, the gate voltages of the third transistor M3 and the fourth transistor M4 are from Voutp - Vpre to Voutp and from Vcpp - Vpre to Vcpp respectively, and the source-gate voltages of the third transistor M3 and the fourth transistor M4 are less than or equal to Vpre. Among them, Vpre < BVgs, then the third transistor M3 and the fourth transistor M4 can use thin gate oxide devices.

[0047] In the first phase Φ1, the first positive output control signal CLK_OUTP_1, the second positive output control signal CLK_OUTP_2, and the third positive output control signal CLK_OUTP_3 are at a high level, and the fourth positive output control signal CLK_OUTP_4 is at a low level. Then the first transistor M1 and the third transistor M3 are in the off state, and the second transistor M2 and the fourth transistor M4 are in the on state, so as to connect the first flying capacitor Cfly1 between the input end of the positive charge pump circuit 121 and GND.

[0048] At this time, the negative plate of the first flying capacitor Cfly1 is pulled to GND, and the positive plate of the first flying capacitor Cfly1 is charged to VDD. That is, the voltage (Vcpn) of the negative plate of the first flying capacitor Cfly1 is 0V, and Vcpp is VDD.

[0049] In the second phase Φ2, the first positive output control signal CLK_OUTP_1, the second positive output control signal CLK_OUTP_2, and the third positive output control signal CLK_OUTP_3 are at a low level, and the fourth positive output control signal CLK_OUTP_4 is at a high level. Then, the second transistor M2 and the fourth transistor M4 are in the off state, and the first transistor M1 and the third transistor M3 are in the on state, so that the first flying capacitor Cfly1 is connected between the output terminal and the input terminal of the positive charge pump circuit 121.

[0050] At this point, Vcpn jumps from 0V to VDD. Since the voltage on the first flying capacitor Cfly1 cannot change abruptly, Vcpp will pump from VDD to Voutp.

[0051] It should be noted that the capacitance value of the first load capacitor Cload1 is typically 10 times that of the first flying capacitor Cfly1. Therefore, in the second phase Φ2, the charge will be redistributed between the first load capacitor Cload1 and the first flying capacitor Cfly1, and thus Vcpp (Voutp) will not immediately reach its maximum value. That is, after the first cycle, Voutp is VDD+ Cfly1 / (Cload1+Cfly1), after the second cycle, Voutp becomes VDD+ Cfly1 / (Cload1 +Cfly1) + Cload1 / (Cload1 + Cfly1) 2 And so on, with the continuous switching between the first phase Φ1 and the second phase Φ2, Voutp = can eventually be achieved. .

[0052] Thus, the forward level conversion circuit 111 can convert multiple forward input control signals (CLK_INP_1 to CLK_INP_4) into multiple forward output control signals (CLK_OUTP_1 to CLK_OUTP_4) under the first target power domain, and based on the multiple forward output control signals (CLK_OUTP_1 to CLK_OUTP_4), control the forward charge pump circuit 121 to switch between the first phase Φ1 and the second phase Φ2, so that the forward charge pump circuit 121 converts VDD to .

[0053] In this embodiment, the level conversion circuit converts multiple input control signals from the 0 to VDD power domain into multiple output control signals from the target power domain. The charge pump circuit boosts VDD based on these multiple output control signals to obtain the output voltage. By setting the voltage difference between the lowest and highest voltages of each target power domain to be less than the gate-source breakdown voltage of the thin-gate oxide device, the absolute value of the gate-source voltage of each transistor in the charge pump circuit is less than the gate-source breakdown voltage of the thin-gate oxide device. This allows the transistors in the charge pump circuit to use thin-gate oxide devices, enabling a high-voltage output charge pump based on thin-gate oxide devices. This reduces the circuit area, achieving circuit miniaturization and lowering circuit cost.

[0054] In some embodiments, Figure 4 A schematic diagram of another voltage conversion circuit based on a thin gate oxide device provided in this disclosure is shown below. Figure 4 As shown, the level conversion circuit 110 also includes a negative level conversion circuit 112, and the charge pump circuit 120 includes a negative charge pump circuit 122.

[0055] Multiple negative input control signals (CLK_INN_1 to CLK_INN_4) are connected one-to-one with multiple input terminals of the negative level conversion circuit 112, and multiple output terminals of the negative level conversion circuit 112 are connected one-to-one with the control terminals of the negative charge pump circuit 122 to output multiple negative output control signals (CLK_OUTN_1 to CLK_OUTN_4). The input terminal of the negative charge pump circuit 122 is connected to the output terminal of the positive charge pump circuit 121, and the output terminal of the negative charge pump circuit 122 is connected to the negative output terminal of the voltage conversion circuit 100.

[0056] The negative level conversion circuit 112 is configured to convert multiple negative input control signals (CLK_INN_1 to CLK_INN_4) into multiple negative output control signals (CLK_OUTN_1 to CLK_OUTN_4) under a second target power domain, and based on the multiple negative output control signals (CLK_OUTN_1 to CLK_OUTN_4), control the negative charge pump circuit 122 to switch between a third phase Φ3 and a fourth phase Φ4 so that the negative charge pump circuit 122 converts Voutp into a negative voltage output voltage (Voutn).

[0057] Among them, the multiple second target power domains include the power domain from Voutp-Vpre to Voutp, the power domain from 0 to Vpre, the power domain from the negative plate voltage (Vcnn) of the flying capacitor in the negative charge pump circuit 122 to Vcnn+Vpre, and the power domain from Voutn to Voutn+Vpre.

[0058] For example, such asFigure 4 As shown, the negative level conversion circuit 112 includes a first negative level converter LS_N_1, a second negative level converter LS_N_2, a third negative level converter LS_N_3 and a fifth positive level converter LS_P_5, and the negative charge pump circuit 122 includes a second flying capacitor Cfly2.

[0059] The first power supply terminals of the first negative level converter LS_N_1, the second negative level converter LS_N_2, the third negative level converter LS_N_3, and the fifth positive level converter LS_P_5 are connected to VDD. The second power supply terminals of the first negative level converter LS_N_1, the second negative level converter LS_N_2, the third negative level converter LS_N_3, and the fifth positive level converter LS_P_5 are connected to the positive output terminal. The first ground terminal of the first negative level converter LS_N_1, the second negative level converter LS_N_2, and the third negative level converter LS_N_3, and the ground terminal of the fifth positive level converter LS_P_5 are connected to GND.

[0060] The second ground terminal of the first negative level converter LS_N_1 is connected to the negative output terminal. The input terminal of the first negative level converter LS_N_1 is connected to the first negative input control signal CLK_INN_1. The output terminal of the first negative level converter LS_N_1 is connected to the first control terminal of the negative charge pump circuit 122 to output the first negative output control signal CLK_OUTN_1.

[0061] The second ground terminal of the second negative level converter LS_N_2 is connected to the negative plate of the second flying capacitor Cfly. The input terminal of the second negative level converter LS_N_2 is connected to the second negative input control signal CLK_INN_2. The output terminal of the second negative level converter LS_N_2 is connected to the second control terminal of the negative charge pump circuit 122 to output the second negative output control signal CLK_OUTN_2.

[0062] The second ground terminal of the third negative level converter LS_N_3 is connected to GND. The input terminal of the third negative level converter LS_N_3 is connected to the third negative input control signal CLK_INN_3. The output terminal of the third negative level converter LS_N_3 is connected to the third control terminal of the negative charge pump circuit 122 to output the third negative output control signal CLK_OUTN_3.

[0063] The input terminal of the fifth positive level converter LS_P_5 is connected to the fourth negative input control signal CLK_INN_4, and the output terminal of the fifth positive level converter LS_P_5 is connected to the fourth control terminal of the negative charge pump circuit 122 to output the fourth negative output control signal CLK_OUTN_4.

[0064] Among them, the first negative output control signal CLK_OUTN_1 is the signal in the power domain from Voutn to Voutn+Vpre, the second negative output control signal CLK_OUTN_2 is the signal in the power domain from the negative plate voltage (Vcnn) of the second flying capacitor Cfly2 to Vcnn+Vpre, the third negative output control signal CLK_OUTN_3 is the signal in the power domain from 0 to Vpre, and the fourth negative output control signal CLK_OUTN_4 is the signal in the power domain from Voutp-Vpre to Voutp.

[0065] See also Figure 4 The negative charge pump circuit 122 also includes a second load capacitor Cload2, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The control terminal of the fifth transistor M5 is connected to the output terminal of the first negative level converter LS_N_1, the control terminal of the sixth transistor M6 is connected to the output terminal of the second negative level converter LS_N_2, the control terminal of the seventh transistor M7 is connected to the output terminal of the third negative level converter LS_N_3, and the control terminal of the eighth transistor M8 is connected to the output terminal of the fifth positive level converter LS_P_5.

[0066] The fifth transistor M5 and the sixth transistor M6 are connected in series between the output of the negative charge pump circuit 122 and GND. The seventh transistor M7 and the eighth transistor M8 are connected in series between GND and the input of the negative charge pump circuit 122. The negative plate of the second flying capacitor Cfly2 is connected to the connection point of the fifth transistor M5 and the sixth transistor M6 and the second ground terminal of the second negative level converter LS_N_2. The positive plate of the second flying capacitor Cfly2 is connected to the connection point of the seventh transistor M7 and the eighth transistor M8. The second load capacitor Cload2 is connected between the output of the negative charge pump circuit 122 and GND.

[0067] For example, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are NMOS transistors, and the eighth transistor M8 is a PMOS transistor. The source of the fifth transistor M5 is connected to the output terminal of the negative charge pump circuit 122, the source of the sixth transistor M6 is connected to the negative plate of the second flying capacitor Cfly2, the source of the seventh transistor M7 is connected to GND, and the source of the eighth transistor M8 is connected to the input terminal of the negative charge pump circuit 122.

[0068] Since the first negative output control signal CLK_OUTN_1 is a signal in the power domain from Voutn to Voutn+Vpre, the gate voltage of the fifth transistor M5 is from Voutn to Voutn+Vpre. Therefore, the gate-source voltage of the fifth transistor M5 is less than or equal to Vpre, and the fifth transistor M5 can be a thin gate oxide device.

[0069] Since the second negative output control signal CLK_OUTN_2 is a signal in the power domain from Vcnn to Vcnn+Vpre, the gate voltage of the sixth transistor M6 is from Vcnn to Vcnn+Vpre. Therefore, the gate-source voltage of the sixth transistor M6 is less than or equal to Vpre, and the sixth transistor M6 can be a thin gate oxide device.

[0070] Since the third negative output control signal CLK_OUTN_3 is a signal in the power domain from 0 to Vpre, the gate voltage of the seventh transistor M7 is from 0 to Vpre. Therefore, the gate-source voltage of the seventh transistor M7 is less than or equal to Vpre, and the fifth transistor M5 can be a thin gate oxide device.

[0071] Since the fourth negative output control signal CLK_OUTN_4 is a signal in the power domain from Voutp to Vpre to Voutp, the gate voltage of the eighth transistor M8 is from Voutp to Vpre to Voutp. Therefore, the source-gate voltage of the eighth transistor M8 is less than or equal to Vpre, and the eighth transistor M8 can be a thin gate oxide device.

[0072] It should be understood that the operation of the negative charge pump circuit 122 is controlled by Voutp. When Voutp... <V ITP When Vcnn is enabled and set to ground, the negative charge pump circuit 122 does not operate; however, when Voutp ≥ V... ITP When the ground setting of Vcnn is canceled, but Vcnn is initially grounded, the negative charge pump circuit 122 starts to work.

[0073] Figure 5 A timing diagram of a negative charge pump circuit provided in an embodiment of this disclosure is shown below. Figure 5 As shown, under the third phase Φ3, the first negative output control signal CLK_OUTN_1, the third negative output control signal CLK_OUTN_3, and the fourth negative output control signal CLK_OUTN_4 are at low level, and the second negative output control signal CLK_OUTN_2 is at high level. Then, the fifth transistor M5 and the seventh transistor M7 are in the off state, and the sixth transistor M6 and the eighth transistor M8 are in the on state, so that the second flying capacitor Cfly2 is connected between the input terminal of the negative charge pump circuit 122 and GND.

[0074] At this time, the negative plate of the second flying capacitor Cfly2 is pulled to GND, and the positive plate of the second flying capacitor Cfly2 is charged to Voutp, that is, Vcnn is 0V, and the voltage (Vcnp) of the positive plate of the second flying capacitor Cfly2 is Voutp.

[0075] In the fourth phase Φ4, the first negative output control signal CLK_OUTN_1, the third negative output control signal CLK_OUTN_3, and the fourth negative output control signal CLK_OUTN_4 are at high level, and the second negative output control signal CLK_OUTN_2 is at low level. Then, the sixth transistor M6 and the eighth transistor M8 are in the off state, and the fifth transistor M5 and the seventh transistor M7 are in the on state, so as to connect the second flying capacitor Cfly2 between GND and the output terminal of the negative charge pump circuit 122.

[0076] At this point, Vcnp jumps from Voutp to 0V. Since the voltage on the second flying capacitor Cfly2 cannot change abruptly, Vcnn will pump from 0V to -Voutp, i.e., Voutn = -Voutp.

[0077] It should be noted that the capacitance of the second load capacitor Cload2 is typically greater than that of the second flying capacitor Cfly2, approximately ten times. Therefore, in the fourth phase Φ4, the charge will be redistributed between the second load capacitor Cload2 and the second flying capacitor Cfly2, and thus Vcnn (Voutn) will not immediately reach its maximum value. Instead, as Voutn continuously switches between the third phase Φ3 and the fourth phase Φ4, it causes Voutn = .

[0078] In this embodiment of the present disclosure, the level conversion circuit can convert multiple positive input control signals into multiple positive output control signals under a first target power domain. Based on the multiple positive output control signals, the positive charge pump circuit is controlled to switch between a first phase and a second phase so that the positive charge pump circuit converts VDD to Voutp. The circuit can also convert multiple negative input control signals into multiple negative output control signals under a second target power domain. Based on the multiple negative output control signals, the negative charge pump circuit is controlled to switch between a third phase and a fourth phase so that the negative charge pump circuit converts Voutp to Voutn, thereby realizing positive voltage output and negative voltage output to adapt to positive output environment and negative output environment.

[0079] In some embodiments, Figure 6 A circuit diagram of a positive level converter provided in an embodiment of this disclosure is shown below. Figure 6As shown, the components are: first resistor R1, first inverter INV1, second inverter INV2, auxiliary NMOS transistor Mn0, first PMOS transistor Mp1, second PMOS transistor Mp2, third PMOS transistor Mp3, fourth PMOS transistor Mp4, fifth PMOS transistor Mp5, sixth PMOS transistor Mp6, seventh PMOS transistor Mp7, first NMOS transistor Mn1, second NMOS transistor Mn2, third NMOS transistor Mn3, fourth NMOS transistor Mn4, fifth NMOS transistor Mn5, sixth NMOS transistor Mn6, seventh NMOS transistor Mn7, and eighth NMOS transistor Mn8.

[0080] The first power supply terminal of the positive level converter is connected to the gate of the first NMOS transistor Mn1, the gate of the second NMOS transistor Mn2, and the gate of the third NMOS transistor Mn3. The source of the first NMOS transistor Mn1 is connected to the bias current Ib. The drain of the first NMOS transistor Mn1 is connected to the first terminal of the first resistor R1, the gate of the first PMOS transistor Mp1, the gate of the second PMOS transistor Mp2, and the gate of the third PMOS transistor Mp3. The second NMOS transistor Mn2 is connected to the drain of the fourth NMOS transistor Mn4 and the drain of the first PMOS transistor Mp1. The third NMOS transistor Mn3 is connected to the drain of the fifth NMOS transistor Mn5 and the drain of the second PMOS transistor Mp2.

[0081] The second power supply terminal of the positive level converter is connected to the second terminal of the first resistor R1, the source of the fourth PMOS transistor Mp4, the source of the fifth PMOS transistor Mp5, the source of the sixth PMOS transistor Mp6, and the source of the seventh PMOS transistor Mp7. The drain of the fourth PMOS transistor Mp4 is connected to the source of the first PMOS transistor Mp1, the gate of the fifth PMOS transistor Mp5, the gate of the seventh PMOS transistor Mp7, and the drain of the sixth NMOS transistor Mn6. The drain of the fifth PMOS transistor Mp5 is connected to the source of the second PMOS transistor Mp2, the gate of the fourth PMOS transistor Mp4, the gate of the sixth PMOS transistor Mp6, and the gate of the sixth NMOS transistor Mn6.

[0082] The input terminal of the forward level converter is connected to the gate of the fourth NMOS transistor Mn4 and the input terminal of the second inverter INV2 through the first inverter INV1. The output terminal of the second inverter INV2 is connected to the gate of the fifth NMOS transistor Mn5. The source of the third PMOS transistor Mp3 is connected to the source of the sixth NMOS transistor Mn6, the source of the seventh NMOS transistor Mn7, the source of the eighth NMOS transistor Mn8, and the drain of the auxiliary NMOS transistor Mn0. The drain of the seventh NMOS transistor Mn7 is connected to the drain of the sixth PMOS transistor Mp6 and the gate of the eighth NMOS transistor Mn8. The drain of the eighth NMOS transistor Mn8 is connected to the drain of the seventh PMOS transistor Mp7, the gate of the seventh NMOS transistor Mn7, and the output terminal of the forward level converter.

[0083] The ground terminal of the positive level converter is connected to the source of the fourth NMOS transistor Mn4, the source of the fifth NMOS transistor Mn5, the drain of the third PMOS transistor Mp3, and the source of the auxiliary NMOS transistor Mn0. The gate of the auxiliary NMOS transistor Mn0 is connected to the auxiliary control signal CTRL.

[0084] For example, the fourth PMOS transistors Mp4 to Mp7, the auxiliary NMOS transistors Mn0, and the fourth NMOS transistors Mn4 to Mn8 are low-voltage devices responsible for converting the positive input control signal CLK_INP from the power supply domain of 0 to VDD to the first target power supply domain, thus obtaining the positive output control signal CLK_OUTP. The first PMOS transistors Mp1 to Mp3 and the first NMOS transistors Mn1 to Mn3 are high-voltage devices responsible for clamping and protecting the circuit, preventing high voltage from damaging the low-voltage devices.

[0085] Specifically, as the voltage at the second power supply terminal of the forward level converter continuously increases, the source voltages of the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are clamped to V. X +VGS_P, where VGS_P is the source-gate voltage of the first PMOS transistor Mp1 and the second PMOS transistor Mp2, V X This represents the gate voltage of the first PMOS transistor Mp1, the second PMOS transistor Mp2, and the third PMOS transistor Mp3. Therefore, the gate voltages of the fourth PMOS transistor Mp4 through the seventh PMOS transistor Mp7 are clamped to V. X If +VGS_P is applied, then the first PMOS transistor Mp1 and the second PMOS transistor Mp2 can protect the fourth PMOS transistor Mp4 to the seventh PMOS transistor Mp7.

[0086] Simultaneously, the source voltages of the second NMOS transistor Mn2 and the third NMOS transistor Mn3 are clamped to VDD-VGS_N, where VGS_N is the gate-source voltage of the first NMOS transistor Mn1, the second NMOS transistor Mn2, and the third NMOS transistor Mn3. Therefore, the drain voltages of the fifth NMOS transistor Mn5 and the fourth NMOS transistor Mn4 are clamped to VDD-VGS_N, thus the third NMOS transistor Mn3 and the second NMOS transistor Mn2 can protect the fifth NMOS transistor Mn5 and the fourth NMOS transistor Mn4.

[0087] When the second power supply terminal of the positive level converter is connected to Voutp and Voutp ≥ V ITP When the auxiliary control signal CTRL is low, the auxiliary NMOS transistor Mn0 is turned off. At this time, Ib flows through the first resistor R1 and forms a voltage drop (Vr) across the first resistor R1, then V X= Voutp - Vr, the source voltage (V Y of the third PMOS transistor Mp3) is Voutp - Vr + Vth, where Vth is the absolute value of the threshold voltage of the MOS transistor. Let Vr - Vth = Vpre, then V Y = Voutp - Vpre, and the voltage range of the positive output control signal CLK_OUTP output by the positive level converter is from Voutp - Vpre to Voutp.

[0088] By setting Vr to be less than or equal to the gate-source breakdown voltage BVgs, Vpre can be made less than BVgs. For example, if the resistance value of the first resistor R1 is 500 KΩ and Ib is 10 μA, then Vr = 5V < BVgs, so Vpre = 5V - Vth < BVgs.

[0089] When CLK_INP is at a low level, the fourth NMOS transistor Mn4 conducts. At this time, the source potential of the first PMOS transistor Mp1 is pulled down to a low level, while the fifth NMOS transistor Mn5 is in an off state and the seventh PMOS transistor Mp7 conducts. Therefore, CLK_OUTP outputs a high level, that is, CLK_OUTP outputs the voltage of the second power supply terminal.

[0090] When CLK_INP is at a high level, the fifth NMOS transistor Mn5 conducts. At this time, the source potential of the second PMOS transistor Mp2 is pulled down to a low level, while the fourth NMOS transistor Mn4 is in an off state and the sixth PMOS transistor Mp6 conducts. The drain potential of the sixth PMOS transistor Mp6 is high and the eighth NMOS transistor Mn8 conducts. Therefore, CLK_OUTP outputs a low level, that is, CLK_OUTP outputs V[[ID=!14]] Y 。

[0091] When the second power supply terminal of the positive level converter is connected to Voutp and Voutp < V ITP at this time, the auxiliary control signal CTRL is at a high level, the auxiliary NMOS transistor Mn0 conducts, Vy is pulled to 0, and the voltage range of the positive output control signal CLK_OUTP output by the positive level converter is from 0 to Voutp.

[0092] In this way, when the second power supply terminal of the positive level converter is connected to Voutp and Voutp ≥ V ITP at this time, the positive input control signal CLK_INP in the power supply domain from 0 to VDD can be first converted into a signal in the power supply domain from 0 to Voutp, and then converted into the positive output control signal CLK_OUTP in the voltage domain from Voutp - Vpre to Voutp, so as to avoid the gate overvoltage of the transistors in the positive charge pump circuit 121.

[0093] When the second power supply terminal of the positive level converter is connected to the positive plate of the first flying capacitor Cfly1, that is, connected to Vcpp, the working principle of the positive level converter is the same as that when the second power supply terminal of the positive level converter is connected to Voutp, and will not be repeated here.

[0094] Thus, when the second power supply terminal of the positive level converter is connected to Vcpp and Voutp ≥ V ITP In this case, the positive input control signal CLK_INP under the power domain from 0 to VDD can be first converted into a signal under the power domain from 0 to Vcpp, and then converted into a positive output control signal CLK_OUTP under the voltage domain from Vcpp to Vpre to Vcpp, so as to avoid gate overvoltage of the transistor in the positive charge pump circuit 121.

[0095] When the second power supply terminal of the forward level converter is connected to VDD, the auxiliary control signal CTRL is high, the auxiliary NMOS transistor Mn0 is turned on, and Vy is pulled to 0. The voltage range of the forward output control signal CLK_OUTP output by the forward level converter is from 0 to VDD.

[0096] In some embodiments, see continue to see Figure 6 The forward level converter also includes the eighth PMOS transistor Mp8, the ninth PMOS transistor Mp9, the ninth NMOS transistor Mn9, and the tenth NMOS transistor Mn10.

[0097] Specifically, the source of the eighth PMOS transistor Mp8 and the source of the ninth PMOS transistor Mp9 are connected to the second power supply terminal of the positive level converter; the source of the ninth NMOS transistor Mn9 and the source of the tenth NMOS transistor Mn10 are connected to the source of the third PMOS transistor Mp3; the gate of the eighth PMOS transistor Mp8 and the gate of the ninth NMOS transistor Mn9 are connected to the drain of the seventh PMOS transistor Mp7; the drain of the eighth PMOS transistor Mp8 is connected to the drain of the ninth NMOS transistor Mn9, the gate of the ninth PMOS transistor Mp9, and the gate of the tenth NMOS transistor Mn10; and the drain of the ninth PMOS transistor Mp9 and the drain of the tenth NMOS transistor Mn10 are connected to the output terminal of the positive level converter.

[0098] For example, the eighth PMOS transistor Mp8 and the ninth NMOS transistor Mn9 constitute the first-stage inverter, and the ninth PMOS transistor Mp9 and the tenth NMOS transistor Mn10 constitute the second-stage inverter. These two stages of inverters form a buffer to shape the positive output control signal CLK_OUTP.

[0099] In some embodiments, see continue to see Figure 6The forward level converter also includes a third resistor R3. The first power supply terminal of the forward level converter is connected to the gate of the first NMOS transistor Mn1, the gate of the second NMOS transistor Mn2, and the gate of the third NMOS transistor Mn3 through the third resistor R3, which can provide ESD protection for the first power supply terminal of the forward level converter.

[0100] In some embodiments, see continue to see Figure 6 The positive level converter also includes a fourth resistor R4, which is connected between the gate and source of the sixth PMOS transistor Mp6.

[0101] For example, when the input terminal of the positive level converter does not receive the positive input control signal CLK_INP, the fourth resistor R4 and the sixth PMOS transistor Mp6 together constitute the default state of the positive output control signal CLK_OUTP, so that the positive charge pump circuit 121 stops working.

[0102] In some embodiments, Figure 7 A circuit diagram of a negative level converter provided in an embodiment of this disclosure is shown below. Figure 7 As shown, the negative level converter includes a second resistor R2, a third inverter INV3, a fourth inverter INV4, a tenth PMOS transistor Mp10, an eleventh PMOS transistor Mp11, a twelfth PMOS transistor Mp12, a thirteenth PMOS transistor Mp13, a fourteenth PMOS transistor Mp14, a fifteenth PMOS transistor Mp15, a sixteenth PMOS transistor Mp16, a seventeenth PMOS transistor Mp17, an eleventh NMOS transistor Mn11, a twelfth NMOS transistor Mn12, a thirteenth NMOS transistor Mn13, a fourteenth NMOS transistor Mn14, a fifteenth NMOS transistor Mn15, a sixteenth NMOS transistor Mn16, and a seventeenth NMOS transistor Mn17.

[0103] The first power supply terminal of the negative level converter is connected to the source of the fourteenth PMOS transistor Mp14 and the source of the fifteenth PMOS transistor Mp15. The drain of the fourteenth PMOS transistor M14 is connected to the drain of the fourteenth NMOS transistor Mn14, the gate of the fifteenth NMOS transistor Mn15, the gate of the sixteenth NMOS transistor Mn16, and the gate of the thirteenth PMOS transistor Mp13 through the eleventh PMOS transistor Mp11 and the eleventh NMOS transistor Mn11 in sequence. The drain of the fifteenth PMOS transistor Mp15 is connected to the drain of the fifteenth NMOS transistor Mn15, the gate of the fourteenth NMOS transistor Mn14, the gate of the seventeenth NMOS transistor Mn17, and the drain of the thirteenth PMOS transistor Mp13 in sequence through the twelfth PMOS transistor Mp12 and the twelfth NMOS transistor Mn12 in sequence.

[0104] The input of the negative level converter is connected to the gate of the fourteenth PMOS transistor Mp14 and the input of the fourth inverter INV4 via the third inverter INV3. The output of the fourth inverter INV4 is connected to the gate of the fifteenth PMOS transistor Mp15. The first ground terminal of the negative level converter is connected to the gates of the tenth PMOS transistor Mp10, the eleventh PMOS transistor Mp11, and the twelfth PMOS transistor Mp12. The source of the tenth PMOS transistor Mp10 receives the bias current Ib, and the drain of the tenth PMOS transistor Mp10 is connected to the first terminal of the second resistor R2, the gate of the eleventh NMOS transistor Mn11, the gate of the twelfth NMOS transistor Mn12, and the gate of the thirteenth NMOS transistor Mn13.

[0105] The second power supply terminal of the negative level converter is connected to the drain of the thirteenth NMOS transistor Mn13. The source of the thirteenth NMOS transistor Mn13 is connected to the source of the thirteenth PMOS transistor Mp13, the source of the sixteenth PMOS transistor Mp16, and the source of the seventeenth PMOS transistor Mp17. The drain of the sixteenth PMOS transistor Mp16 is connected to the gate of the seventeenth PMOS transistor Mp17 and the drain of the sixteenth NMOS transistor Mn16. The drain of the seventeenth PMOS transistor is connected to the gate of the sixteenth PMOS transistor Mp16, the drain of the seventeenth NMOS transistor Mn17, and the output terminal of the negative level converter. The second ground terminal of the negative level converter is connected to the second terminal of the second resistor R2, the source of the fourteenth NMOS transistor Mn14, the source of the fifteenth NMOS transistor Mn15, the source of the sixteenth NMOS transistor Mn16, and the source of the seventeenth NMOS transistor Mn17.

[0106] For example, the thirteenth PMOS transistors Mp13 to Mp17 and the fourteenth NMOS transistors Mn14 to Mn17 are low-voltage devices responsible for converting the negative input control signal CLK_INN from the power supply domain of 0 to VDD to the second target power supply domain, thus obtaining the negative output control signal CLK_OUTN. The tenth PMOS transistors Mp10 to Mp12 and the eleventh NMOS transistors Mn11 to Mn13 are high-voltage devices responsible for clamping and protecting the circuit, preventing high voltage from damaging the low-voltage devices.

[0107] Specifically, as the voltage at the second ground terminal of the negative level converter continuously decreases, the source voltages of the eleventh NMOS transistor Mn11 and the twelfth NMOS transistor Mn12 are clamped to V. M -VGS_N, where VGS_N is the gate-source voltage of the eleventh NMOS transistor Mn11 and the twelfth NMOS transistor Mn12, V MThis represents the gate voltage of the eleventh NMOS transistor Mn11, the twelfth NMOS transistor Mn12, and the thirteenth NMOS transistor Mn13. Therefore, the gate voltages of the fourteenth NMOS transistor Mn14 through the seventeenth NMOS transistor Mn17 are clamped to V. M If -VGS_N is enabled, then the eleventh NMOS transistor Mn11 and the twelfth NMOS transistor Mn12 can protect the fourteenth NMOS transistor Mn14 to the seventeenth NMOS transistor Mn17.

[0108] Simultaneously, the source voltages of the eleventh PMOS transistor Mp11 and the twelfth PMOS transistor Mp12 are clamped to VGS_P, where VGS_P is the source-gate voltage of the tenth PMOS transistor Mp10, the eleventh PMOS transistor Mp11, and the twelfth PMOS transistor Mp12. Therefore, the drain voltages of the fourteenth PMOS transistor Mp14 and the fifteenth PMOS transistor Mp15 are clamped to VGS_P, thus the eleventh PMOS transistor Mp11 and the twelfth PMOS transistor Mp12 can protect the fourteenth PMOS transistor Mp14 and the fifteenth PMOS transistor Mp15.

[0109] When the second ground terminal of the negative level converter is connected to Voutn, Ib flows through the second resistor R2 and forms a voltage drop (Vr) across the second resistor R2. Then V M =Voutn+Vr, the source voltage of the thirteenth NMOS transistor Mn13 (V N Let Voutn + Vr - Vth be the sum of its components. Then V... N =Voutn+Vpre, the voltage range of the negative output control signal CLK_OUTN output by the negative level converter is from Voutn to Voutn+Vpre.

[0110] By setting Vr to be less than or equal to the gate-source breakdown voltage BVgs, Vpre can be made less than BVgs. For example, if the resistance of the second resistor R2 is 500KΩ and Ib is 10μA, then Vr = 5V. <BVgs,Vpre=5V-Vth<BVgs。

[0111] When CLK_INN is low, the fifteenth PMOS transistor Mp15 is turned on, the fourteenth PMOS transistor Mp14 is turned off, the drain potential of the fifteenth NMOS transistor Mn15 is high, and the seventeenth NMOS transistor Mn17 is turned on. Therefore, the CLK_OUTN output is low, that is, the CLK_OUTN output is the voltage of the second ground terminal.

[0112] When CLK_INN is high, the fourteenth PMOS transistor Mp14 is turned on, the fifteenth PMOS transistor Mp15 is turned off, the drain potential of the fourteenth NMOS transistor Mn14 is high, the sixteenth NMOS transistor Mn16 is turned on, and its drain potential is low. Subsequently, the seventeenth PMOS transistor Mp17 is turned on, and its drain potential is high. Therefore, the CLK_OUTN output is high, i.e., the CLK_OUTN output is V. N .

[0113] Thus, when the negative level converter is connected to Voutn at the second ground terminal, it can first convert the negative input control signal CLK_INP in the power domain from 0 to VDD into a signal in the power domain from Voutn to VDD, and then convert it into the negative output control signal CLK_OUTN in the voltage domain from Voutn to Voutn+Vpre, so as to avoid gate overvoltage of the transistor in the negative charge pump circuit 122.

[0114] When the second ground terminal of the negative level converter is connected to GND, Ib flows through the second resistor R2 and forms a voltage drop (Vr) across the second resistor R2. Then V M =Vr, the source voltage of the thirteenth NMOS transistor Mn13 (V N Let Vr be Vth. Then V N =Vpre, the voltage range of the negative output control signal CLK_OUTN output by the negative level converter is from 0 to Vpre.

[0115] When the second ground terminal of the negative level converter is connected to the negative plate of the second flying capacitor Cfly2, i.e., connected to Vcnn, Ib flows through the second resistor R2 and forms a voltage drop (Vr) across the second resistor R2. Then V M =Vcnn+Vr, the source voltage of the thirteenth NMOS transistor Mn13 (V N Let V be Vcnn + Vr - Vth. Then V N =Vcnn+Vpre, the voltage range of the negative output control signal CLK_OUTN output by the negative level converter is from Vcnn to Vcnn+Vpre.

[0116] In some embodiments, see continue to see Figure 7 The negative level converter also includes the eighteenth NMOS transistor Mn18, the nineteenth NMOS transistor Mn19, the eighteenth PMOS transistor Mp18, and the nineteenth PMOS transistor Mp19.

[0117] Specifically, the source of the eighteenth PMOS transistor Mp18 and the source of the nineteenth PMOS transistor Mp19 are connected to the source of the thirteenth NMOS transistor Mn13; the source of the eighteenth NMOS transistor Mn18 and the source of the nineteenth NMOS transistor Mn19 are connected to the second ground terminal of the negative level converter; the gate of the eighteenth PMOS transistor Mp18 and the gate of the eighteenth NMOS transistor Mn18 are connected to the drain of the seventeenth PMOS transistor Mp17; the drain of the eighteenth PMOS transistor Mp18 is connected to the drain of the eighteenth NMOS transistor Mn18, the gate of the nineteenth PMOS transistor Mp19, and the gate of the nineteenth NMOS transistor Mn19; and the drain of the nineteenth PMOS transistor Mp19 and the drain of the nineteenth NMOS transistor Mn19 are connected to the output terminal of the negative level converter.

[0118] For example, the eighteenth NMOS transistor Mn18 and the eighteenth PMOS transistor Mp18 constitute the first-stage inverter, and the nineteenth NMOS transistor Mn19 and the nineteenth PMOS transistor Mp19 constitute the second-stage inverter. These two stages of inverters form a buffer to shape the negative output control signal CLK_OUTN.

[0119] In some embodiments, see continue to see Figure 7 The negative level converter also includes a fifth resistor R5. The first ground terminal of the negative level converter is connected to the gate of the tenth PMOS transistor Mp10, the gate of the eleventh PMOS transistor Mp11, and the gate of the twelfth PMOS transistor Mp12 through the fifth resistor R5, which can provide ESD protection for the first ground terminal of the negative level converter.

[0120] In some embodiments, see [continued] Figure 7 The negative level shifter also includes a sixth resistor R6, which is connected between the gate and source of the sixteenth NMOS transistor Mn16.

[0121] For example, when the input terminal of the negative level converter does not receive the negative input control signal CLK_INN, the sixth resistor R6 and the sixteenth NMOS transistor Mn16 together constitute the default state of the negative output control signal CLK_OUTN, so that the negative charge pump circuit 122 stops working.

[0122] In some embodiments, Figure 8 A schematic diagram of another voltage conversion circuit based on a thin gate oxide device provided in this disclosure is shown below. Figure 8 As shown, the voltage conversion circuit 100 also includes a signal generation circuit 130, and the multiple output terminals of the signal generation circuit 130 are connected one-to-one with the multiple input terminals of the level conversion circuit 110.

[0123] The signal generation circuit 130 is configured to generate a clock signal CLK and, based on the clock signal CLK, generate multiple pairs of input control signals with dead time (signal pairs consisting of CLK_IN_11 and CLK_IN_12 to signal pairs consisting of CLK_IN_n1 and CLK_IN_n2, n=m / 2).

[0124] For example, Figure 9 This is a circuit diagram of a signal generation circuit provided in an embodiment of the present disclosure, such as... Figure 9 As shown, the signal generation circuit 130 includes an oscillator OSC, a frequency divider counter DIV_Fre, a fifth inverter INV5, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, a second NOR gate NOR2, a first delay unit Delay1, a second delay unit Delay2, a third delay unit Delay3, and a fourth delay unit Delay4.

[0125] The oscillator OSC is connected to the input of the fifth inverter INV5, the first input of the first NAND gate NAND1, and the first input of the second NOR gate NOR2 via the frequency divider counter DIV_Fre. The output of the fifth inverter INV5 is connected to the first input of the second NAND gate NAND2 and the first input of the first NOR gate NOR1.

[0126] The output of the first NAND gate NAND1 is connected to the second input of the second NAND gate NAND2 and the first output of the signal generation circuit 130 via a first delay unit Delay1. The output of the second NAND gate NAND2 is connected to the second input of the first NAND gate NAND1 and the second output of the signal generation circuit 130 via a second delay unit Delay2. The output of the first NOR gate NOR1 is connected to the second input of the second NOR gate NOR2 and the third output of the signal generation circuit 130 via a third delay unit Delay3. The output of the second NOR gate NOR2 is connected to the second input of the first NOR gate NOR1 and the fourth output of the signal generation circuit 130 via a fourth delay unit Delay4.

[0127] The oscillator OSC generates a high-frequency oscillating clock signal CLK. The frequency divider counter DIV_Fre divides the clock signal CLK by a factor of eight, thereby reducing the frequency of the clock signal CLK and obtaining the control signal CLK1.

[0128] For example, Figure 10 The output signal timing diagram of the signal generation circuit provided in the embodiments of this disclosure is as follows: Figure 10As shown, after the falling edge of the control signal CLK1 is triggered, after a first preset delay time, the signal CLK_IN_11 flips from low level to high level, and the signal CLK_IN_21 flips from high level to low level; after the rising edge of the signal CLK_IN_11 is triggered, after a second preset delay time, the signal CLK_IN_12 flips from high level to low level, and the signal CLK_IN_22 flips from low level to high level.

[0129] After the rising edge of control signal CLK1 is triggered, after a third preset delay time, signal CLK_IN_12 toggles from low to high, and signal CLK_IN_22 toggles from high to low; after the rising edge of signal CLK_IN_12 is triggered, after a fourth preset delay time, signal CLK_IN_11 toggles from high to low, and signal CLK_IN_21 toggles from low to high.

[0130] The second preset delay time and the fourth preset delay time are usually referred to as the dead time.

[0131] For example, CLK_IN_11 can be the first positive input control signal CLK_INP_1 / the first negative input control signal CLK_INN_1, CLK_IN_11 can be the second positive input control signal CLK_INP_2 / the second negative input control signal CLK_INN_2, CLK_IN_21 can be the third positive input control signal CLK_INP_3 / the third negative input control signal CLK_INN_3, and CLK_IN_21 can be the fourth positive input control signal CLK_INP_4 / the fourth negative input control signal CLK_INN_4.

[0132] It should be noted that, Figure 9 The signal generation circuit 130 is shown only as an example. In actual applications, a buffer can be connected between each delay and the output of the corresponding signal generation circuit 130, and / or an inverter can be connected between the fifth inverter INV5 and the frequency divider counter DIV_Fre.

[0133] In addition, depending on the type of transistor controlled by the input control signal CLK_IN, an inverter can be connected between the delay circuit Delay and the output of the corresponding signal generation circuit 130 to match the type of the input control signal CLK_IN with the type of transistor.

[0134] In this embodiment of the disclosure, by setting the signal generation circuit 130, multiple pairs of input control signals with dead time can be generated, avoiding shoot-through when the charge pump circuit 120 is working, thereby improving the stability of the circuit.

[0135] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0136] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0137] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A voltage conversion circuit based on thin gate oxide devices, characterized in that, Includes a charge pump circuit and a level conversion circuit connected to the control terminal of the charge pump circuit; The level conversion circuit is configured to convert multiple input control signals in a power domain from 0 to the power supply voltage into output control signals in multiple target power domains, wherein the voltage difference between the lowest and highest voltages of each target power domain is less than the gate-source breakdown voltage of the thin gate oxide device. The charge pump circuit is configured to boost the power supply voltage based on multiple output control signals to obtain an output voltage; under the action of the multiple output control signals, the absolute value of the gate-source voltage of each transistor in the charge pump circuit is less than the gate-source breakdown voltage.

2. The voltage conversion circuit according to claim 1, characterized in that, The level conversion circuit includes a positive level conversion circuit, and the charge pump circuit includes a positive charge pump circuit; The output terminal of the positive level conversion circuit is connected to the control terminal of the positive charge pump circuit, the input terminal of the positive charge pump circuit is connected to the power supply voltage, and the output terminal of the positive charge pump circuit is connected to the positive output terminal of the voltage conversion circuit. The positive level conversion circuit is configured to convert multiple positive input control signals into multiple positive output control signals under a first target power domain, and based on the multiple positive output control signals, control the positive charge pump circuit to switch between a first phase and a second phase so that the positive charge pump circuit converts the power supply voltage into a positive output voltage. The plurality of first target power domains include a power domain from 0 to the power supply voltage, a power domain from the positive output voltage minus a preset voltage to the positive output voltage, and a power domain from the positive plate voltage of the flying capacitor in the positive charge pump circuit minus the preset voltage to the positive plate voltage of the flying capacitor in the positive charge pump circuit, wherein the preset voltage is less than the gate-source breakdown voltage.

3. The voltage conversion circuit according to claim 2, characterized in that, The level conversion circuit further includes a negative level conversion circuit, and the charge pump circuit includes a negative charge pump circuit; The output terminal of the negative level conversion circuit is connected to the control terminal of the negative charge pump circuit, the input terminal of the negative charge pump circuit is connected to the output terminal of the positive charge pump circuit, and the output terminal of the negative charge pump circuit is connected to the negative output terminal of the voltage conversion circuit. The negative level conversion circuit is configured to convert multiple negative input control signals into multiple negative output control signals under a second target power domain, and based on the multiple negative output control signals, control the negative charge pump circuit to switch between a third phase and a fourth phase so that the negative charge pump circuit converts the positive output voltage into a negative output voltage. The plurality of second target power domains include the power domain from the positive output voltage minus the preset voltage to the positive output voltage, the power domain from 0 to the preset voltage, the power domain from the negative plate voltage of the flying capacitor in the negative charge pump circuit to the sum of the negative plate voltage of the flying capacitor in the negative charge pump circuit and the preset voltage, and the power domain from the negative output voltage to the sum of the negative output voltage and the preset voltage.

4. The voltage conversion circuit according to claim 2, characterized in that, The positive level conversion circuit includes a first positive level converter, a second positive level converter, a third positive level converter, and a fourth positive level converter. The ground terminal of the positive level converter is connected to a reference ground, and the first power supply terminal of the positive level converter is connected to the power supply voltage. The positive charge pump circuit includes a first flying capacitor. The second power supply terminals of the first and second positive level converters are connected to the power supply voltage. The input terminal of the first positive level converter is connected to the first positive input control signal. The output terminal of the first positive level converter is connected to the first control terminal of the positive charge pump circuit to output the first positive output control signal. The input terminal of the second positive level converter is connected to the second positive input control signal. The output terminal of the second positive level converter is connected to the second control terminal of the positive charge pump circuit to output the second positive output control signal. The second power supply terminal of the third positive level converter is connected to the positive output terminal of the voltage conversion circuit. The second power supply terminal of the fourth positive level converter is connected to the positive plate of the first flying capacitor. The input terminal of the third positive level converter is connected to the third positive input control signal. The output terminal of the third positive level converter is connected to the third control terminal of the positive charge pump circuit to output the third positive output control signal. The input terminal of the fourth positive level converter is connected to the fourth positive input control signal. The output terminal of the fourth positive level converter is connected to the fourth control terminal of the positive charge pump circuit to output the fourth positive output control signal. Wherein, the first positive output control signal and the second positive output control signal are signals in the power domain from 0 to the power supply voltage; when the positive output voltage is greater than or equal to the threshold voltage, the third positive output control signal is the positive output voltage minus the preset voltage to the signal in the power domain of the positive output voltage; and the fourth positive output control signal is the voltage of the positive plate of the first flying capacitor minus the preset voltage to the signal in the power domain of the positive plate of the first flying capacitor. When the positive output voltage is less than the threshold voltage, the third positive output control signal is a signal in the power supply domain from 0 to the positive output voltage, the fourth positive output control signal is a signal in the power supply domain from 0 to the positive plate voltage of the first flying capacitor, and the threshold voltage is less than the gate-source breakdown voltage.

5. The voltage conversion circuit according to claim 4, characterized in that, The positive charge pump circuit further includes a first load capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all thin-gate oxide devices; The first transistor and the second transistor are connected in series between the input terminal of the positive charge pump circuit and the reference ground. The third transistor and the fourth transistor are connected in series between the output terminal and the input terminal of the positive charge pump circuit. The negative plate of the first flying capacitor is connected to the connection point of the first transistor and the second transistor. The positive plate of the first flying capacitor is connected to the connection point of the third transistor and the fourth transistor. The first load capacitor is connected between the output terminal of the positive charge pump circuit and the reference ground. The control terminal of the first transistor is connected to the output terminal of the first positive level converter, the control terminal of the second transistor is connected to the output terminal of the second positive level converter, the control terminal of the third transistor is connected to the output terminal of the third positive level converter, and the control terminal of the fourth transistor is connected to the output terminal of the fourth positive level converter. In the first phase, the second transistor and the fourth transistor are in the on state to connect the first flying capacitor between the input terminal of the positive charge pump circuit and the reference ground; In the second phase, the first transistor and the third transistor are in the on state to connect the first flying capacitor between the output and input of the positive charge pump circuit.

6. The voltage conversion circuit according to claim 3, characterized in that, The negative level conversion circuit includes a first negative level converter, a second negative level converter, a third negative level converter, and a fifth positive level converter; the negative charge pump circuit includes a second flying capacitor. The first power supply terminal of the negative level converter and the first power supply terminal of the fifth positive level converter are connected to the power supply voltage; the second power supply terminal of the negative level converter and the second power supply terminal of the fifth positive level converter are connected to the positive output terminal; and the first ground terminal of the negative level converter and the ground terminal of the fifth positive level converter are connected to the reference ground. The second ground terminal of the first negative level converter is connected to the negative output terminal, the input terminal of the first negative level converter is connected to the first negative input control signal, and the output terminal of the first negative level converter is connected to the first control terminal of the negative charge pump circuit to output the first negative output control signal. The second ground terminal of the second negative level converter is connected to the negative plate of the second flying capacitor, the input terminal of the second negative level converter is connected to the second negative input control signal, and the output terminal of the second negative level converter is connected to the second control terminal of the negative charge pump circuit to output the second negative output control signal. The second ground terminal of the third negative level converter is connected to the reference ground, the input terminal of the third negative level converter is connected to the third negative input control signal, and the output terminal of the third negative level converter is connected to the third control terminal of the negative charge pump circuit to output the third negative output control signal. The input terminal of the fifth positive level converter is connected to the fourth negative input control signal, and the output terminal of the fifth positive level converter is connected to the fourth control terminal of the negative charge pump circuit to output the fourth negative output control signal. Wherein, the first negative output control signal is a signal in the power domain from the negative output voltage to the sum of the negative output voltage and the preset voltage; the second negative output control signal is a signal in the power domain from the negative plate voltage of the second flying capacitor to the sum of the negative plate voltage of the second flying capacitor and the preset voltage; the third negative output control signal is a signal in the power domain from 0 to the preset voltage; and the fourth negative output control signal is a signal in the power domain from the positive output voltage minus the preset voltage to the positive output voltage.

7. The voltage conversion circuit according to claim 6, characterized in that, The negative charge pump circuit further includes a second load capacitor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all thin-gate oxide devices; The fifth and sixth transistors are connected in series between the output of the negative charge pump circuit and the reference ground; the seventh and eighth transistors are connected in series between the reference ground and the input of the negative charge pump circuit; the negative plate of the second flying capacitor is connected to the connection point of the fifth and sixth transistors and the second ground terminal of the second negative level converter; the positive plate of the second flying capacitor is connected to the connection point of the seventh and eighth transistors; and the second load capacitor is connected between the output of the negative charge pump circuit and the reference ground. The control terminal of the fifth transistor is connected to the output terminal of the first negative level converter, the control terminal of the sixth transistor is connected to the output terminal of the second negative level converter, the control terminal of the seventh transistor is connected to the output terminal of the third negative level converter, and the control terminal of the eighth transistor is connected to the output terminal of the fifth positive level converter. In the third phase, the sixth transistor and the eighth transistor are in the on state to connect the second flying capacitor between the input terminal of the negative charge pump circuit and the reference ground; In the fourth phase, the fifth and seventh transistors are in the on state to connect the second flying capacitor between the reference ground and the output of the negative charge pump circuit.

8. The voltage conversion circuit according to claim 4, characterized in that, The forward level converter includes a first resistor, a first inverter, a second inverter, an auxiliary NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The first power supply terminal of the positive level converter is connected to the gate of the first NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor. The source of the first NMOS transistor is connected to the bias current. The drain of the first NMOS transistor is connected to the first terminal of the first resistor, the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the gate of the third PMOS transistor. The second NMOS transistor is connected to the drain of the fourth NMOS transistor and the drain of the first PMOS transistor. The third NMOS transistor is connected to the drain of the fifth NMOS transistor and the drain of the second PMOS transistor. The second power supply terminal of the positive level converter is connected to the second terminal of the first resistor, the source of the fourth PMOS transistor, the source of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the source of the seventh PMOS transistor. The drain of the fourth PMOS transistor is connected to the source of the first PMOS transistor, the gate of the fifth PMOS transistor, the gate of the seventh PMOS transistor, and the drain of the sixth NMOS transistor. The drain of the fifth PMOS transistor is connected to the source of the second PMOS transistor, the gate of the fourth PMOS transistor, the gate of the sixth PMOS transistor, and the gate of the sixth NMOS transistor. The input terminal of the forward level converter is connected to the gate of the fourth NMOS transistor and the input terminal of the second inverter through the first inverter. The output terminal of the second inverter is connected to the gate of the fifth NMOS transistor. The source of the third PMOS transistor is connected to the source of the sixth NMOS transistor, the source of the seventh NMOS transistor, the source of the eighth NMOS transistor, and the drain of the auxiliary NMOS transistor. The drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor and the gate of the eighth NMOS transistor. The drain of the eighth NMOS transistor is connected to the drain of the seventh PMOS transistor, the gate of the seventh NMOS transistor, and the output terminal of the forward level converter. The ground terminal of the positive level converter is connected to the source of the fourth NMOS transistor, the source of the fifth NMOS transistor, the drain of the third PMOS transistor, and the source of the auxiliary NMOS transistor. The gate of the auxiliary NMOS transistor is connected to an auxiliary control signal.

9. The voltage conversion circuit according to claim 6, characterized in that, The negative level converter includes a second resistor, a third inverter, a fourth inverter, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor; The first power supply terminal of the negative level converter is connected to the source of the fourteenth PMOS transistor and the source of the fifteenth PMOS transistor. The drain of the fourteenth PMOS transistor is connected to the drain of the fourteenth NMOS transistor, the gate of the fifteenth NMOS transistor, the gate of the sixteenth NMOS transistor, and the gate of the thirteenth PMOS transistor in sequence through the eleventh PMOS transistor and the eleventh NMOS transistor. The drain of the fifteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate of the fourteenth NMOS transistor, the gate of the seventeenth NMOS transistor, and the drain of the thirteenth PMOS transistor in sequence through the twelfth PMOS transistor and the twelfth NMOS transistor. The input terminal of the negative level converter is connected to the gate of the fourteenth PMOS transistor and the input terminal of the fourth inverter through the third inverter. The output terminal of the fourth inverter is connected to the gate of the fifteenth PMOS transistor. The first ground terminal of the negative level converter is connected to the gate of the tenth PMOS transistor, the gate of the eleventh PMOS transistor, and the gate of the twelfth PMOS transistor. The source of the tenth PMOS transistor receives the bias current. The drain of the tenth PMOS transistor is connected to the first terminal of the second resistor, the gate of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor. The second power supply terminal of the negative level converter is connected to the drain of the thirteenth NMOS transistor. The source of the thirteenth NMOS transistor is connected to the source of the thirteenth PMOS transistor, the source of the sixteenth PMOS transistor, and the source of the seventeenth PMOS transistor. The drain of the sixteenth PMOS transistor is connected to the gate of the seventeenth PMOS transistor and the drain of the sixteenth NMOS transistor. The drain of the seventeenth PMOS transistor is connected to the gate of the sixteenth PMOS transistor, the drain of the seventeenth NMOS transistor, and the output terminal of the negative level converter. The second ground terminal of the negative level converter is connected to the second terminal of the second resistor, the source of the fourteenth NMOS transistor, the source of the fifteenth NMOS transistor, the source of the sixteenth NMOS transistor, and the source of the seventeenth NMOS transistor.

10. The voltage conversion circuit according to any one of claims 1-9, characterized in that, The voltage conversion circuit further includes a signal generation circuit, wherein multiple output terminals of the signal generation circuit are connected one-to-one with multiple input terminals of the level conversion circuit. The signal generation circuit is configured to generate a clock signal and generate multiple pairs of input control signals with dead time based on the clock signal. The signal generation circuit includes an oscillator, a frequency divider counter, a fifth inverter, a first NAND gate, a second NAND gate, a first NOR gate, a second NOR gate, a first delay unit, a second delay unit, a third delay unit, and a fourth delay unit. The oscillator is connected to the input terminal of the fifth inverter, the first input terminal of the first NAND gate, and the first input terminal of the second NOR gate through the frequency divider counter. The output terminal of the fifth inverter is connected to the first input terminal of the second NAND gate and the first input terminal of the first NOR gate. The output of the first NAND gate is connected to the second input of the second NAND gate and the first output of the signal generation circuit through the first delay. The output of the second NAND gate is connected to the second input of the first NAND gate and the second output of the signal generation circuit through the second delay. The output of the first NOR gate is connected to the second input of the second NOR gate and the third output of the signal generation circuit through the third delay. The output of the second NOR gate is connected to the second input of the first NOR gate and the fourth output of the signal generation circuit through the fourth delay.

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