Phase-locked loop locking state detection circuit and method
By using first and second comparators and XOR gates in the phase-locked loop (PLL), combined with a delay module and a hysteresis latch comparator, the problems of long detection time and false judgment in PLL locking state are solved, and fast and accurate PLL state detection is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, the method for detecting the locking state of a phase-locked loop requires multiple cycles to make an accurate judgment, resulting in long time consumption and a high risk of misjudgment.
By employing first and second comparators and an XOR gate, the state of the phase-locked loop is determined by comparing the edge changes of the reference clock and the frequency divider output clock within a single cycle and using different thresholds. The detection accuracy and speed are improved by combining a delay module and a hysteresis latch comparator.
It enables rapid and accurate detection of the phase-locked loop's locking state within a single cycle, reducing time consumption and improving detection reliability.
Smart Images
Figure CN121814082A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic circuits, and specifically relates to a phase-locked loop (PLL) locking state detection circuit and method. Background Technology
[0002] Phase-locked loops (PLLs) are an important module in frequency synthesis and clock recovery circuits. A PLL consists of a phase detector, loop filter, voltage-controlled oscillator (VCO), and frequency divider, such as... Figure 1 As shown. It is mainly used to generate the required clock frequency and a low-jitter clock signal. A phase-locked loop (PLL) is a nonlinear negative feedback system, and its phase lock time is much lower than the operating frequency. The lock time is affected by the initial operating frequency, the target operating frequency, the charge pump current, the loop filter, etc. During the unlocked period, the output clock frequency and phase can cause the system to malfunction. Therefore, in practical applications, detecting PLL lock-up is a basic configuration of the PLL. The traditional method for detecting PLL lock-up is to count the reference clock and the distributor output clock, and then compare whether the counts are equal to determine whether it is locked. The counting method judges whether the periods are the same, so the larger the count is set, the more accurately it can indicate that the phase is locked. This will bring more time consumption. Too small a count will lead to an incorrect indication of a locked state, even if the counting periods are the same, because the phase has not yet been locked. Summary of the Invention
[0003] To address the technical problems existing in the prior art, the present invention aims to provide a phase-locked loop (PLL) locking state detection circuit capable of rapidly detecting the PLL state (locked state or unlocked state) within a single cycle.
[0004] The circuit is configured to include a first comparator, a second comparator, and an XOR gate; The first comparator is triggered when the first trigger signal is at the rising edge or falling edge stage, and compares the first input signal with the first threshold to output a first output; The second comparator is triggered when the second trigger signal is at the rising edge or falling edge stage, and compares the second input signal with the second threshold to output a second output; The XOR gate outputs a state indication output to indicate the state of the phase-locked loop based on the first output and the second output. The first trigger signal, the second trigger signal, the first input signal, and the second input signal are configured as the reference clock of the phase-locked loop or the output clock of the frequency divider in the phase-locked loop.
[0005] Furthermore, the first threshold is less than 90% of the circuit power supply level and greater than the second threshold, or the second threshold is greater than 10% of the circuit power supply level and less than the first threshold.
[0006] Furthermore, the first trigger signal and the second trigger signal trigger the first comparator and the second comparator respectively via the first delay module.
[0007] Furthermore, the first delay module employs a cascaded inverter.
[0008] Furthermore, the first input signal and the second input signal are respectively input to the first comparator and the second comparator via the second delay module.
[0009] Furthermore, the second delay module employs a cascaded inverter.
[0010] Furthermore, the output of the second delay module is connected to an RC module.
[0011] Furthermore, the first comparator and the second comparator are comparators with hysteresis and latch.
[0012] Another aspect of the present invention provides a method for detecting the locked state of a phase-locked loop (PLL). When the reference clock of the PLL or the output clock of the frequency divider in the PLL is at its rising edge or falling edge, the method compares the output clock of the frequency divider in the PLL or the reference clock of the PLL with a first threshold and a second threshold, respectively, to generate a state indication output for indicating the state of the PLL.
[0013] The beneficial effects of this invention include: This invention directly compares whether the edges of the reference clock and the output clock of the frequency divider change simultaneously, which can be understood as comparing the phase difference between the reference clock and the output clock of the frequency divider, realizing detection in a single cycle, so it can quickly detect the state of the phase-locked loop. Attached Figure Description
[0014] To more clearly illustrate the embodiments of this application, the accompanying drawings used or involved in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and other drawings can be obtained based on these drawings without creative effort: Figure 1 This is a basic structural principle block diagram of a phase-locked loop; Figure 2 A circuit diagram of the detection circuit provided by the present invention; Figure 3 This diagram illustrates the working principle of the rapid detection and locking mechanism of the present invention. Figure 4 This is a diagram illustrating the working principle of an unlocked state as described in this invention; Figure 5 This is a diagram illustrating the working principle of another unlocked state described in this invention; Figure 6This is a schematic diagram illustrating the principle of one specific embodiment of the present invention. Detailed Implementation
[0015] This section describes the invention more fully with reference to the accompanying drawings, in which illustrative embodiments of the invention are shown. However, the invention is also embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure is thorough and complete, and to fully convey the scope of the invention to those skilled in the art.
[0016] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0017] Unless defined to the contrary, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or highly formal sense unless specifically defined herein.
[0018] The detection circuit provided by this invention is used to detect the state of a phase-locked loop (PLL). Based on the detection result, it directly outputs a state indication output to indicate the PLL's state. This output determines whether the PLL is in a locked state. The locked state of the PLL means that the frequency of the PLL's (voltage-controlled oscillator) output clock is synchronized with the frequency of the reference clock.
[0019] Please refer to Figure 2 The detection circuit provided by the present invention is configured to include a first comparator 201, a second comparator 202, and an XOR gate 203; the input terminals of the first comparator 201 and the second comparator 202 are respectively connected to the output terminals of the frequency divider of the phase-locked loop, and the comparison thresholds are respectively configured as a first threshold (threshold level of the first comparator 201) and a second threshold (threshold level of the second comparator 202); the trigger terminals of the first comparator 201 and the second comparator 202 are respectively connected to the reference clock of the phase-locked loop.
[0020] The input terminals of the XOR gate 203 are connected to the output terminals of the first comparator 201 and the second comparator 202, respectively. The logic level output by the XOR gate 203 is the lockout indication signal, which is used to indicate the state of the phase-locked loop.
[0021] Reference Figure 2 The circuit structure shown compares the divider output clock with two comparators of different thresholds triggered simultaneously on the edge (rising or falling) of the reference clock. If the reference clock and the divider output clock are phase-locked, as... Figure 3 As shown, at this time, the level compared by the first comparator 201 is lower than the threshold level of the first comparator 201, and the first comparator 201 outputs a low level. The level compared by the second comparator 202 is higher than the threshold level of the second comparator 202, and the second comparator 202 outputs a high level. The high and low levels pass through the two-input first XOR gate 203, and the first XOR gate outputs a high level, indicating that the phase-locked loop has been locked.
[0022] If the reference clock lags behind the divider output clock, such as Figure 4 As shown, at this time, the level compared by the first comparator 201 is higher than the threshold level of the first comparator 201, and the first comparator 201 outputs a high level. The level compared by the second comparator 202 is higher than the threshold level of the second comparator 202, and the second comparator 202 outputs a high level. The two high levels pass through the two-input first XOR gate 203, and the first XOR gate outputs a low level, indicating that the phase-locked loop is not locked.
[0023] If the reference clock leads the divider output clock, such as Figure 5 As shown, at this time, the level compared by the first comparator 201 is lower than the threshold level of the first comparator 201, and the first comparator 201 outputs a low level. The level compared by the second comparator 202 is lower than the threshold level of the second comparator 202, and the second comparator 202 outputs a low level. The two low levels pass through the two-input first XOR gate 203, and the first XOR gate outputs a low level, indicating that the phase-locked loop is not locked.
[0024] When the reference clock is in the edge (rising edge or falling edge) stage, the first and second comparators are triggered to compare the output clock of the frequency divider with the first threshold and the second threshold, respectively. If the output clock of the frequency divider is also in the edge (rising edge or falling edge) stage, it means that the frequency of the output clock of the frequency divider is synchronized with the frequency of the reference clock. Since the output clock of the frequency divider is N times the output clock of the phase-locked loop, when the output clock of the frequency divider and the reference clock are synchronized, it means that the output clock of the phase-locked loop and the reference clock are synchronized, the phase difference between them remains unchanged, and the phase-locked loop is in a locked state.
[0025] The first and second thresholds are set based on the amplitude of the reference clock and the output clock of the frequency divider. Here, the first threshold can be set to 90% of the circuit power supply level, and the second threshold can be set to 10% of the circuit power supply level. When the output clock of the frequency divider is in the edge phase, the level is in the changing phase. When compared with the first and second thresholds respectively, the level is between the two, and the comparator outputs one high and one low.
[0026] The above description is based on Figure 2 The circuit structure shown describes a phase-locked loop (PLL) with its reference clock as the comparator's trigger clock and the frequency divider's output clock as the comparator's input clock. In this circuit, the positions of the reference clock and the frequency divider's output clock can be interchanged. Therefore, the second circuit structure of this detection circuit is: the frequency divider's output clock is used as the comparator's trigger clock, and the PLL's reference clock is used as the comparator's input clock. The circuit connection is as follows: the input terminals of the first comparator 201 and the second comparator 202 are respectively connected to the PLL's reference clock, and the comparison thresholds are configured to different values for the first and second thresholds; the trigger terminals of the first comparator 201 and the second comparator 202 are respectively connected to the frequency divider's output terminal.
[0027] The second circuit structure also works by comparing phases to determine the state of the phase-locked loop, compared to... Figure 2 The difference in the circuit structure shown is that in the second circuit structure, the output clock of the frequency divider is used as the trigger signal of the comparator, and the reference clock of the phase-locked loop is used as the comparison object.
[0028] In practical implementation, the detection accuracy configuration depends on the comparator's comparison speed and comparison threshold. The smaller the range between the first and second thresholds, the higher the accuracy, but the faster the comparator needs to be. To obtain high-precision detection results, the first threshold can be configured to be less than 90% of the power supply level and greater than the second threshold. Alternatively, the second threshold can be configured to be greater than 10% of the power supply level and less than the first threshold.
[0029] When applied in a phase-locked loop, the comparison operation of the comparator will have a backlash effect on the reference clock signal and the frequency divider output signal. In order not to affect the reference clock signal and the frequency divider output signal, this detection circuit adds a first delay module 204 and a second delay module 205 to process the first trigger signal, the second trigger signal, the first input signal, and the second input signal, respectively.
[0030] Please refer to Figure 6As shown, the first trigger signal and the second trigger signal are reference clocks, which are processed by the first delay module 204 and then connected to the first comparator 201 and the second comparator 202 respectively as the trigger signals of the comparators. The first input signal and the second input signal are the output clocks of the frequency divider, which are processed by the second delay module 205 and then connected to the first comparator 201 and the second comparator 202 respectively as the compared signals.
[0031] The first and second delay modules use cascaded inverters.
[0032] Please refer to Figure 6 The detection circuit also includes an RC module 206, which consists of a series resistor and a bypass capacitor. The main function of the RC module is to delay the rise and fall times of the signal. This module can reduce the speed requirements of the comparator, but sacrifices the detection accuracy.
[0033] The first and second comparators can be comparators with hysteresis and latch, which can further improve the stability of the circuit's output signal.
[0034] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A phase-locked loop (PLL) locking state detection circuit, characterized in that, The circuit is configured to include a first comparator (201), a second comparator (202), and an XOR gate (203). The first comparator (201) is triggered when the first trigger signal is at the rising edge or falling edge stage, and compares the first input signal with the first threshold to output the first output; The second comparator (202) is triggered when the second trigger signal is at the rising edge or falling edge stage, and compares the second input signal with the second threshold to output a second output; The XOR gate (203) outputs a state indication output to indicate the state of the phase-locked loop based on the first output and the second output; The first trigger signal, the second trigger signal, the first input signal, and the second input signal are configured as the reference clock of the phase-locked loop or the output clock of the frequency divider in the phase-locked loop.
2. The phase-locked loop locking state detection circuit according to claim 1, characterized in that, The first threshold is less than 90% of the circuit power supply level and greater than the second threshold, or the second threshold is greater than 10% of the circuit power supply level and less than the first threshold.
3. The phase-locked loop locking state detection circuit according to claim 1, characterized in that, The first trigger signal and the second trigger signal trigger the first comparator (201) and the second comparator (202) respectively via the first delay module (204).
4. The phase-locked loop locking state detection circuit according to claim 3, characterized in that, The first delay module (204) uses a cascaded inverter.
5. The phase-locked loop locking state detection circuit according to claim 1, characterized in that, The first input signal and the second input signal are input to the first comparator (201) and the second comparator (202) respectively via the second delay module (205).
6. The phase-locked loop locking state detection circuit according to claim 5, characterized in that, The second delay module (205) uses a cascaded inverter.
7. The phase-locked loop locking state detection circuit according to claim 5, characterized in that, The output of the second delay module (205) is connected to an RC module (206).
8. The phase-locked loop locking state detection circuit according to claim 1, characterized in that, The first comparator (201) and the second comparator (202) are comparators with hysteresis and latch.
9. A method for detecting the locking state of a phase-locked loop, characterized in that, This method compares the output clock of the frequency divider in the phase-locked loop or the reference clock of the phase-locked loop with a first threshold and a second threshold respectively when the reference clock of the phase-locked loop or the output clock of the frequency divider in the phase-locked loop is at the rising edge or the falling edge, to generate a status indication output for indicating the state of the phase-locked loop.