Impedance coupon characterization method, impedance coupon and PCB

Abstract

The invention discloses an impedance coupon characterization method, an impedance coupon and a PCB in the field of PCB manufacturing impedance coupon design, and the method comprises the steps: obtaining the copper thickness of a continuous superposition layer to determine a power supply layer, and analyzing a copper-free region in the power supply layer to determine the arrangement type of a segmentation gap; determining a signal layer according to the power supply layer, obtaining an impedance line and a necking layer structure corresponding to the signal layer, and extracting a structure factor related to impedance; the impedance lines, the necking layers and the segmentation gaps are arranged on the impedance coupon according to corresponding factors, and combined design is carried out, so that the impedance coupon capable of representing the impedance characteristic of the signal layer under the segmentation gap superposition condition is constructed; according to the invention, through impedance coupon, the representativeness and reliability of the impedance test on the actual impedance state in the PCB can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for characterizing an impedance coupon, an impedance coupon and a PCB board, and belongs to the field of PCB manufacturing impedance coupon design. BACKGROUND

[0002] In the process of PCB manufacturing and detection, the impedance of the signal line in the board is usually tested and verified by setting an impedance coupon outside the PCB board to determine whether the PCB meets the design requirements.

[0003] The existing impedance coupon design method is usually based on idealized laminated structure and uniform reference layer environment for wiring, without fully considering the actual distribution of the non-copper area in the power layer. Especially in multi-layer PCB, the power layer often adopts thick copper large-area copper design, in order to realize functional isolation or meet the wiring demand, different forms of non-copper area are often set in the power layer. When multiple power layers are continuously stacked along the thickness direction of the board, the non-copper areas in each power layer may overlap in space, resulting in deviation or fluctuation of the signal layer impedance.

[0004] However, the existing impedance coupon design does not distinguish and characterize the superimposed arrangement of the non-copper area in the power layer, and is usually designed only according to a single power layer or ideal reference layer condition, which is difficult to truly reflect the actual impedance characteristics of the signal layer under the superimposed condition of the non-copper area in the power layer. In addition, the existing scheme lacks a systematic design method for the corresponding relationship between the signal layer impedance line, the necking layer and the split gap, resulting in insufficient consistency between the impedance coupon and the target area inside the PCB in the electromagnetic environment, thereby affecting the representativeness and reliability of the impedance test results. SUMMARY

[0005] The purpose of the present application is to overcome the problem that the existing impedance coupon design method does not fully consider the split gap arrangement characteristics formed by the continuous superposition of the non-copper area in the power layer along the thickness direction of the multi-layer PCB, resulting in difficulty in truly reflecting the impedance change of the signal layer under the actual reference environment.

[0006] To solve the above technical problems, the present application is realized by using the following technical scheme: In a first aspect, a method for characterizing an impedance coupon is provided, comprising: Based on the laminated structure of the PCB, the copper thickness of each continuous superposition layer along the thickness direction of the board is obtained, and the power layer is determined according to the copper thickness; The non-copper area of the power layer is obtained, and the arrangement type of the non-copper area is determined; The non-copper area with the determined arrangement type is determined as the corresponding split gap, and the corresponding split gap factor is obtained; According to the power layer, the signal layer is determined, the impedance line and the necking layer corresponding to the signal layer are obtained, and the impedance line factor and the necking layer factor are obtained; The impedance line is arranged in parallel along the surface of the coupon according to the impedance line factor, and a first inflection point is arranged at one end of the coupon, the necking layer is arranged on the coupon according to the necking layer factor, and one end of the necking layer is connected with the first inflection point; The other end of the necking layer is arranged as a second inflection point, and the second inflection point is connected with the processing core; The segmentation gap of the determined arrangement type is arranged on the coupon according to the segmentation gap factor; The impedance line, the necking layer, the segmentation gap and the processing core are arranged in combination.

[0007] Further, the confirmation of the power layer includes: obtaining continuous superposition layers by a superposition method; The continuous superposition layers include at least four continuous superposition layers.

[0008] Further, the arrangement type of the copper-free area includes a coincidence type, an intersection type and a staggered type.

[0009] Further, the determination of the signal layer according to the power layer includes: determining the signal layer by obtaining impedance parameters and residual copper rates in an impedance control table.

[0010] Further, the segmentation gap factor includes the width of the segmentation gap and the differential line length on both sides of the segmentation gap.

[0011] Further, the impedance line factor and the necking layer factor include the line width of the impedance line, the line spacing of the impedance line and the line length of the necking layer.

[0012] Further, the position proportion of the segmentation gap on the surface of the coupon is the same as the position proportion of the segmentation gap on the current layer.

[0013] In a second aspect, an impedance coupon is provided, which is prepared by using the impedance coupon characterization method of the first aspect.

[0014] In a third aspect, a PCB board is provided, which includes the impedance coupon of the second aspect.

[0015] Compared with the prior art, the present application has the following beneficial effects: 1、The present application can accurately identify the key layer structure which has a significant impact on the reference environment of the signal layer in the design stage by analyzing the copper thickness of the continuous superimposed layer based on the PCB laminated structure and determining the power layer accordingly, and provide reliable structure basis for subsequent impedance characterization; by identifying the arrangement type of the copper-free area of the power layer and determining it as the partition gap, the impedance coupon can reflect the actual distribution characteristics formed by the copper-free area of the power layer along the thickness direction in the design process, avoiding the deviation caused by the impedance test based on a single reference layer condition.

[0016] 2、The present application can make the wiring structure of the impedance coupon consistent with the signal path actually affected by the partition gap in the PCB by determining the corresponding signal layer according to the power layer and obtaining the impedance line and necking layer structure in the signal layer; at the same time, by introducing the impedance line factor, the necking layer factor and the partition gap factor, the relative position and arrangement mode of the impedance line, the necking layer and the partition gap on the coupon are uniformly characterized, so that the impedance coupon is closer to the target area inside the PCB in the electromagnetic environment. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a schematic diagram of the power layer and the signal layer close to the power layer of the characterization method of the impedance coupon provided by the present application; Figure 2 is a schematic diagram of the staggered type of each power layer partition gap of the characterization method of the impedance coupon provided by the present application; Figure 3 is a schematic diagram of the signal layer impedance line of the characterization method of the impedance coupon provided by the present application; Figure 4 is a schematic diagram of the signal layer impedance line and the necking layer in the coupon of the characterization method of the impedance coupon provided by the present application; Figure 5 is a schematic diagram of the partition gap in the coupon of the characterization method of the impedance coupon provided by the present application; Figure 6 is a schematic diagram of the impedance coupon provided by the present application. DETAILED DESCRIPTION

[0018] The technical solutions of the present application will be described in detail below with the help of the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and the embodiments of the present application are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments and the embodiments of the present application can be combined with each other.

[0019] The term "and / or", used herein merely describes an associated relationship, which means that there can be three relationships, for example, A and / or B, which means that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " herein generally represents that the front and rear associated objects have an "or" relationship.

[0020] In one embodiment, as shown in Figure 1 , a method for characterizing impedance coupons is provided. First, based on the laminated structure of the PCB, the copper thickness information of each continuous laminated layer in the thickness direction of the board is obtained. By comparing and analyzing the copper thickness of each continuous laminated layer, the continuous laminated layer with copper thickness significantly greater than the signal layer copper thickness is identified, and the corresponding layer is determined as the power layer according to the copper thickness characteristics. In this embodiment, at least four continuous laminated thick copper layers are confirmed to exist by the overlay method, and the continuous laminated thick copper layer is determined as the power layer; as shown in Figure 1 , the copper thickness of L15~24 layers is greater than 2oz, and is significantly greater than the adjacent layer, i.e. L15~24 layers are power layers.

[0021] As shown in Figure 2 , the power layer is analyzed to obtain the copper-free area in the power layer, and the planar position relationship of the copper-free area in different power layers is compared to determine the arrangement type of the copper-free area; the copper-free area in different power layers presents a completely coincident or partially overlapping arrangement form, which is determined as a coincident copper-free area, an intersecting copper-free area and a staggered copper-free area, and the copper-free area is determined as a power gap. In this embodiment, as shown in Figure 2 , a structure diagram of the staggered copper-free area is given.

[0022] On this basis, for the power gap, the power gap factor related thereto is obtained, including the width of the power gap and the line length information of the differential lines on both sides of the power gap.

[0023] Then, according to the determined power layer, the signal layer arranged adjacent to the power layer is further determined; by referring to the impedance control table, combining the impedance parameter requirements and the residual copper rate information of the corresponding layer, the signal layer meeting the impedance requirement is determined as the target signal layer. Specifically, as shown in Figure 1 , the residual copper rate of L13 is 32.8%, and the residual copper rate of L26 is 36.2%, which are significantly lower than L14 and L25, and then L13 and L26 layers are the signal layers closest to the power layer; After determining the target signal layer, the impedance line corresponding to the power gap position and its corresponding neck down layer structure are extracted from the signal layer, and the impedance-related impedance line factor and neck down layer factor are obtained. The impedance line factor includes the line width and line spacing of the impedance line, and the neck down layer factor includes the line length of the neck down layer.

[0024] like Figure 3 As shown, in the design process of the impedance coupon, according to the impedance line factor, the impedance line is arranged parallel to the surface of the coupon, and a first inflection point is set at one end of the coupon. According to the necking layer factor, a necking layer is arranged on the coupon, and one end of the necking layer is connected to the first inflection point, so that the impedance line and the necking layer form a continuous wiring structure.

[0025] like Figure 4 As shown, the other end of the necking layer is set as the second inflection point, and the second inflection point is connected to the processing core, which is a honeycomb structure as shown in the figure.

[0026] After completing the arrangement of the impedance lines and necking layers, the dividing gaps are arranged on the impedance coupon according to the arrangement type and dividing gap factor determined above, and the position ratio of the dividing gaps on the coupon surface is consistent with the position ratio of the corresponding power layer.

[0027] Finally, as Figure 5 As shown, the impedance lines, necking layers, partition gaps, and processing core are combined and arranged to form a complete impedance coupon structure. This impedance coupon is set on the outer area of ​​the PCB board and is used to characterize and detect the impedance characteristics of the signal layer when there are overlapping partition gaps in the power layer.

[0028] This embodiment also provides an impedance coupon, which is prepared using the impedance coupon characterization method described above.

[0029] This embodiment also provides a PCB board equipped with an impedance coupon as mentioned in the above embodiments.

[0030] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An impedance coupon characterization method, characterized in that, include: Based on the PCB's stack-up structure, the copper thickness of each consecutive stacked layer along the board thickness direction is obtained, and the power layer is determined based on the copper thickness. Obtain the copper-free areas of the power layer and determine the layout type of the copper-free areas; The copper-free area of ​​a given layout type is identified as the corresponding partition gap, and the corresponding partition gap factor is obtained. The signal layer is determined based on the power layer, the impedance line and necking layer corresponding to the signal layer are obtained, and the impedance line factor and necking layer factor are obtained. The impedance lines are arranged parallel to the surface of the coupon according to the impedance line factor, and a first inflection point is set at one end of the coupon. The necking layer is arranged on the coupon according to the necking layer factor, and one end of the necking layer is connected to the first inflection point. The other end of the necking layer is set as a second inflection point, which is connected to the processing core; Arrange the partition gaps, which determine the layout type, on the coupon according to the partition gap factor; The arrangement includes impedance lines, necking layers, segmentation gaps, and processing cores.

2. The impedance coupon characterization method according to claim 1, characterized in that, The confirmation of the power layer includes: obtaining consecutive overlay layers through the overlay method; The continuous stacked layer includes at least four consecutive stacked layers.

3. The impedance coupon characterization method according to claim 1, characterized in that, The arrangement types of the copper-free areas include overlapping, intersecting, and staggered types.

4. The impedance coupon characterization method according to claim 1, characterized in that, The step of determining the signal layer based on the power layer includes: determining the signal layer by obtaining the impedance parameters and residual copper ratio in the impedance control table.

5. The impedance coupon characterization method according to claim 1, characterized in that, The segmentation gap factor includes the width of the segmentation gap and the length of the difference lines on both sides of the segmentation gap.

6. The impedance coupon characterization method according to claim 1, characterized in that, The impedance line factor and necking factor include: the linewidth of the impedance line, the line spacing of the impedance line, and the line length of the necking layer.

7. The impedance coupon characterization method according to claim 1, characterized in that, The proportion of the dividing gap on the coupon surface is the same as the proportion of the dividing gap in the current layer.

8. An impedance coupon, characterized in that, It was prepared using the impedance coupon characterization method as described in any one of claims 1-7.

9. A PCB board, characterized in that, Includes the impedance coupon as described in claim 8.

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