Semiconductor package

Abstract

A semiconductor package includes a substrate, a logic die on the substrate, a base insulating layer on a side surface and an upper surface of the logic die, an insulating layer through-via extending through the base insulating layer at a side of the logic die, a high bandwidth memory on the upper surface of the base insulating layer, and a gate on the upper surface of the high bandwidth memory. At least one optical structure on an upper surface of the base insulating layer and at least one optical connector comprising an optical fiber configured to transmit optical signals between the at least one optical structure and an external device, wherein the high bandwidth memory includes a plurality of memory dies stacked in a first direction perpendicular to an upper surface of the base insulating layer, and at least one optical structure is connected to the logic die in the first direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package. Background Technology

[0002] With the development of technologies such as biomedical health, artificial intelligence (AI), virtual reality (VR), autonomous driving, and robotics, data traffic is increasing exponentially. Therefore, there is a need for ultra-high-speed data communication, and the demand for optical transceivers for communicating with optical signals rather than electrical signals is increasing.

[0003] Silicon photonics is a technology that enables the realization of photonic integrated circuits capable of processing optical signals on silicon chips. Silicon photonics offers advantages such as low light propagation loss, low power consumption, high bandwidth, and compatibility with mature commercial complementary metal-oxide-semiconductor (CMOS) processes. Along with these silicon photonics technologies, silicon photonics-based packaging technologies are also being developed to integrate photonic modules with existing semiconductor packages.

[0004] The information disclosed in this background section was already known or derived by the inventors before or during the implementation of the embodiments of this application, or it is technical information acquired during the implementation of the embodiments. Therefore, it may contain information that does not form prior art already known to the public. Summary of the Invention

[0005] One or more example embodiments provide a semiconductor package that can improve the speed of optical communication with external devices and reduce signal loss.

[0006] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented.

[0007] According to one aspect of an example embodiment, a semiconductor package may include: a substrate, a logic die on the substrate, a base insulating layer on a side surface and a top surface of the logic die, an insulating layer through-path extending through the base insulating layer at one side of the logic die, a high-bandwidth memory on the top surface of the base insulating layer, at least one optical structure on the top surface of the base insulating layer, and at least one optical connector including an optical fiber configured to transmit optical signals between the at least one optical structure and an external device, wherein the high-bandwidth memory includes a plurality of memory dies stacked in a first direction perpendicular to the top surface of the base insulating layer, and the at least one optical structure is connected to the logic die in the first direction.

[0008] According to one aspect of an example embodiment, a semiconductor package may include: a substrate, a logic die on the substrate, a base insulating layer on a side surface and a top surface of the logic die, an insulating layer through-path extending through the base insulating layer at one side of the logic die, a high-bandwidth memory on the top surface of the base insulating layer, an optical structure on the top surface of the base insulating layer, and an optical connector including an optical fiber configured to transmit optical signals between the optical structure and an external device, wherein the high-bandwidth memory includes a plurality of memory dies stacked in a first direction perpendicular to the top surface of the base insulating layer, and in a plan view, the optical structure overlaps with at least a portion of the logic die, and the optical structure is connected to the logic die in the first direction.

[0009] According to one aspect of an example embodiment, a semiconductor package may include: a substrate and a plurality of chips on the substrate, each of the plurality of chips including: a logic die on the substrate, a base insulating layer on a side surface and a top surface of the logic die, an insulating layer through-path extending through the base insulating layer at one side of the logic die, a high-bandwidth memory on the top surface of the base insulating layer, an optical structure on the top surface of the base insulating layer, and an optical connector including an optical fiber configured to transmit optical signals between the optical structure and an external device, wherein the high-bandwidth memory includes a plurality of memory dies stacked in a first direction perpendicular to the top surface of the base insulating layer, and the optical structure is connected to the logic die in the first direction. Attached Figure Description

[0010] The above and other aspects, features, and advantages of certain exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 It is a top plan view of a semiconductor package according to one or more embodiments;

[0012] Figure 2 According to one or more embodiments along Figure 1 A cross-sectional view of the semiconductor package taken by line A-A';

[0013] Figure 3 This is a schematic block diagram illustrating components of an optical structure according to one or more embodiments;

[0014] Figure 4 This schematically illustrates a cross-sectional view of a photonic integrated circuit according to one or more embodiments;

[0015] Figure 5 It is a cross-sectional view of a semiconductor package according to one or more embodiments;

[0016] Figure 6 It is a cross-sectional view of a semiconductor package according to one or more embodiments;

[0017] Figure 7 It is a cross-sectional view of a semiconductor package according to one or more embodiments;

[0018] Figure 8 It is a cross-sectional view of a semiconductor package according to one or more embodiments;

[0019] Figure 9 It is a cross-sectional view of a semiconductor package according to one or more embodiments;

[0020] Figure 10 It is a top plan view of a semiconductor package according to one or more embodiments;

[0021] Figure 11 According to one or more embodiments along Figure 10 A cross-sectional view of the semiconductor package taken by line B-B';

[0022] Figure 12 According to one or more embodiments along Figure 10 A cross-sectional view of the semiconductor package taken by line B-B'; and

[0023] Figures 13 to 19 This is a process cross-sectional view illustrating a manufacturing method for semiconductor packaging according to one or more embodiments. Detailed Implementation

[0024] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms.

[0025] For the sake of clarity in describing this disclosure, parts that are not relevant to the description have been omitted, and throughout the specification, the same reference numerals denote the same or similar parts.

[0026] As used herein, expressions such as "at least one of..." modify the entire list of elements when preceding it, without modifying any individual element in the list. For example, the expression "at least one of a, b, or c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0027] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0028] It should be understood that when a component or layer is referred to as being "above," "over," "on," "below," "under," "connected to," or "attached to" another component or layer, it can be directly above, above, below, under, connected to, or attached to the other component or layer, or there may be intermediate components or layers present. In contrast, when a component is referred to as being "directly above," "directly above," "directly on," "directly below," "directly under," "directly connected to," or "directly attached to," there are no intermediate components or layers present.

[0029] In the following text, reference will be made to Figure 1 and Figure 2 Describes a semiconductor package according to one or more embodiments.

[0030] Figure 1 It is a top plan view of a semiconductor package according to one or more embodiments.

[0031] Figure 2 According to one or more embodiments along Figure 1 A cross-sectional view of a semiconductor package taken by line A-A'.

[0032] refer to Figure 1 and Figure 2 According to one or more embodiments, a semiconductor package 100 may include a substrate 110, a logic die 10 positioned on the substrate 110, a base insulating layer 120 positioned on the side and top surfaces of the logic die 10, an insulating layer through-passage 125 (i.e., an insulating layer through-passage) extending through the base insulating layer 120 on opposite sides of the logic die 10, a high bandwidth memory (HBM) 20 positioned on the top surface of the base insulating layer 120, and an optical structure 30, and an optical connector 40 including an optical fiber for transmitting optical signals between the optical structure 30 and an external device.

[0033] Substrate 110 may be a substrate for packaging, such as a printed circuit board (PCB) or a ceramic substrate. If substrate 110 is a PCB, it may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. Substrate 110 may include an integrated circuit. Substrate 110 may include one or more wirings.

[0034] The substrate 110 may include a first surface and a second surface facing each other. Each of the first surface and the second surface may be aligned in a first direction DR1 and a second direction DR2. The second direction DR2 may intersect the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. The first side and the second side may face each other along a third direction DR3. The third direction DR3 may be a direction perpendicular to the first direction DR1 and the second direction DR2.

[0035] Multiple first connection pads 118 may be positioned on a first surface of substrate 110, and multiple external connection members 111 may be positioned on a second surface of substrate 110. The external connection members 111 may electrically connect the semiconductor package 100 to an external device (e.g., a motherboard).

[0036] External connection member 111 may include a conductive material. For example, external connection member 111 may include a metal such as copper, aluminum, or an alloy thereof. For example, external connection member 111 may be a solder ball.

[0037] Multiple first connection pads 118 can electrically connect components located on a first surface of substrate 110 to substrate 110. Logic die 10 and base insulating layer 120 can be positioned on the first surface of substrate 110. Multiple second connection pads 122 can be positioned on the lower surface of logic die 10 and the lower surface of base insulating layer 120. Some of the second connection pads 122 can be positioned on the lower surface of logic die 10, and other second connection pads 122 can be positioned on the lower surface of base insulating layer 120. The second connection pads 122 can be connected to the first connection pads 118. For example, the second connection pads 122 can be connected to the first connection pads 118 via first connection members 121. Each first connection member 121 can be positioned between the lower surface of each second connection pad 122 and the upper surface of each first connection pad 118.

[0038] Each of the first connection pad 118, the second connection pad 122, and the first connection member 121 may include a conductive material. For example, each of the first connection pad 118, the second connection pad 122, and the first connection member 121 may include a metal such as copper, aluminum, or an alloy thereof. For example, the external connection member 121 may be a solder ball.

[0039] The logic die 10 may have an upper surface and side surfaces covered by a base insulating layer 120. The lower surface of the logic die 10 may be positioned at approximately the same level as the lower surface of the base insulating layer 120. In a plan view, the logic die 10 may be positioned at the center portion of the base insulating layer 120. The logic die 10 may be surrounded by the base insulating layer 120.

[0040] The logic die 10 can be connected to the high-bandwidth memory 20 and the optical structure 30. The logic die 10 can generate electrical signals to control and transmit data to the high-bandwidth memory 20. The logic die 10 can read data from or write data to the high-bandwidth memory 20. The logic die 10 can process data read from the high-bandwidth memory 20. The logic die 10 can generate electrical signals to control and transmit data to the optical structure 30. The logic die 10 can process electrical signals received from the optical structure 30.

[0041] For example, the logic die 10 may include an application-specific integrated circuit (ASIC), a central processing unit (CPU), a graphics processing unit (GPU), or a field-programmable gate array (FPGA).

[0042] Multiple third connection pads 124 may be positioned on the upper surface of the logic die 10. Some of the third connection pads 124 may be connected to the high-bandwidth memory 20, and the other third connection pads 124 may be connected to the optical structure 30.

[0043] Multiple logic paths 105 can be provided to extend through the logic die 10. The logic paths 105 can extend through the logic die 10 on the third-party DR3. Signals can be transmitted between the high-bandwidth memory 20 and the substrate 110 and between the optical structure 30 and the substrate 110 through the logic paths 105.

[0044] Logic path 105 may include a conductive material. For example, logic path 105 may include a metal such as copper, aluminum, or an alloy thereof.

[0045] A base insulating layer 120 may cover the side and top surfaces of the logic die 10. In a cross-sectional view, the base insulating layer 120 may be positioned on opposite sides of the logic die 10. Multiple insulating layer through-paths 125 extending through the base insulating layer 120 may be provided. The insulating layer through-paths 125 may extend through the base insulating layer 120 at opposite sides of the logic die 10. The insulating layer through-paths 125 may extend on a third-direction DR3. Signals may be transmitted between the optical structure 30 and the substrate 110 through the insulating layer through-paths 125.

[0046] A base insulating layer 120 can be positioned on the upper surface of the insulating layer through-path 125 and the upper surface of the third connection pad 124. A plurality of fourth connection pads 128 can be positioned on the upper surface of the base insulating layer 120. The side and lower surfaces of the fourth connection pads 128 can be covered by the base insulating layer 120. The upper surface of the fourth connection pads 128 can be positioned at a level substantially the same as the upper surface of the base insulating layer 120. The fourth connection pads 128 can be embedded in the upper surface of the base insulating layer 120.

[0047] The base insulating layer 120 may include an insulating material. For example, the base insulating layer 120 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide nitride (SiONx), or combinations thereof, but the embodiments are not limited thereto. The insulating layer through-path 125 may include a conductive material. For example, the insulating layer through-path 125 may include a metal such as copper, aluminum, or alloys thereof.

[0048] Some of the fourth connection pads 128 can be connected to the insulating layer through-hole 125, and other fourth connection pads 128 can be connected to the third connection pad 124. The fourth connection pads 128 can be connected by the insulating layer through-hole 125, the third connection pad 124, and a plurality of connection paths 127. Connection paths 127 can extend on a third-direction DR3. The side surfaces of the connection paths 127 can be surrounded by the base insulating layer 120. Some of the connection paths 127 can be connected on the third-direction DR3 between the lower surface of the fourth connection pad 128 and the upper surface of the insulating layer through-hole 125. Other connection paths 127 can be connected on the third-direction DR3 between the lower surface of the fourth connection pad 128 and the upper surface of the third connection pad 124.

[0049] Each of the third connection pad 124, the fourth connection pad 128, and the connection path 127 may include a conductive material. For example, the third connection pad 124, the fourth connection pad 128, and the connection path 127 may each include a metal such as copper, aluminum, or an alloy thereof.

[0050] High-bandwidth memory 20 can be positioned on the upper surface of the base insulating layer 120 and on the upper surface of a plurality of fourth connection pads 128. High-bandwidth memory 20 can be electrically connected to some of the fourth connection pads 128, which are connected to logic die 10. High-bandwidth memory 20 and logic die 10 can be electrically connected via the fourth connection pads 128. High-bandwidth memory 20 can be positioned in the center portion of the base insulating layer 120 in a plan view. High-bandwidth memory 20 can be located vertically above logic die 10d on a third-direction DR3. High-bandwidth memory 20 can be positioned in the center portion of logic die 10.

[0051] The high-bandwidth memory 20 may include a plurality of memory dies 21, 22, 23, and 24. The memory dies 21, 22, 23, and 24 may be stacked in a direction perpendicular to the upper surface of the base insulating layer 120 (e.g., on a third-direction DR3). For example, each of the memory dies 21, 22, 23, and 24 may be (but is not limited to) dynamic random access memory (DRAM).

[0052] In an embodiment, the high-bandwidth memory 20 may include a memory die and may not include a buffer die. That is, the high-bandwidth memory 20 according to one or more embodiments may be a bufferless HBM. The high-bandwidth memory 20 may be electrically connected to the logic die 10, so the logic die 10 may be used as a buffer die without including a separate buffer die.

[0053] Multiple memory through-paths 205 can be provided to extend through memory dies 21, 22, 23, and 24. Memory through-paths 205 can extend through memory dies 21, 22, 23, and 24 on a third-party DR3. Signals can be transmitted between memory dies 21, 22, 23, and 24 and between memory dies 21, 22, and 23 and logic die 10 via memory through-paths 205. Memory dies 21, 22, 23, and 24 can transmit data together via memory through-paths 205, thereby increasing bandwidth. Memory through-paths 205 can shorten signal transmission distances, which can reduce power consumption.

[0054] Memory dies 21, 22, 23, and 24 can be connected via multiple solder bumps and can be molded by molding components. For example, the MR (mass reflow)-MUF (molded underfill) method can be used, in which solder is melted by a reflow process to join the memory dies before molding, and then underfill and molding are performed simultaneously, but the embodiments are not limited thereto. As another example, the TC (thermo compression)-NCF (non-conductive film) method can also be used, in which NCF is inserted between the memory dies, heat and pressure are applied to join them, and then molding is performed.

[0055] Optical structure 30 can be positioned on the upper surface of the base insulating layer 120 and the upper surface of a plurality of fourth connection pads 128. Optical structure 30 can be electrically connected to some of the fourth connection pads 128 connected to the insulating layer via the through-path 125. Optical structure 30 can be electrically connected to the insulating layer through-path 125 via the fourth connection pads 128. A plurality of fifth connection pads 322 can be positioned on the lower surface of optical structure 30. A first insulating layer 324 can be located between the fifth connection pads 322. The side surface of each of the fifth connection pads 322 can be surrounded by the first insulating layer 324. The fifth connection pads 322 can be separated by the first insulating layer 324. The lower surface of the fifth connection pads 322 can contact the upper surface of the fourth connection pads 128, and the lower surface of the first insulating layer 324 can contact the upper surface of the base insulating layer 120.

[0056] The fifth connection pad 322 may include a conductive material. For example, the fifth connection pad 322 may include a metal such as copper, aluminum, or an alloy thereof. The first insulating layer 324 may include an insulating material. For example, the first insulating layer 324 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide nitride (SiONx), or a combination thereof, but the embodiments are not limited thereto.

[0057] In other words, the optical structure 30 can be bonded to the base insulating layer 120 using a hybrid copper bonding (HCB) method, but the embodiments are not limited to this. The way the optical structure 30 is bonded to the base insulating layer 120 can vary in various ways.

[0058] The optical structure 30 can be positioned on the edge of the base insulating layer 120 in a plan view. The optical structure 30 can overlap with at least a portion of the logic die 10 on the third-direction DR3. In a plan view, the optical structure 30 can be positioned on the edge of the logic die 10. The optical structure 30 can overlap with the insulating layer through-path 125 on the third-direction DR3.

[0059] Optical structure 30 can be positioned along a direction parallel to the upper surface of the high-bandwidth memory 20 and the base insulating layer 120 (e.g., a first direction DR1 or a second direction DR2). Optical structure 30 can also be positioned along a direction perpendicular to the upper surface of the logic die 10 and the base insulating layer 120 (e.g., a third direction DR3). Optical structure 30 can be connected to the logic die 10 in a direction perpendicular to the upper surface of the logic die 10 (e.g., on the third direction DR3). For example, optical structure 30 can be connected to the logic die 10 via a fourth connection pad 128, a connection path 127, and a third connection pad 124, but the embodiment is not limited thereto. Therefore, compared to a comparative example where optical structure 30 is positioned on the first surface along a direction parallel to the first surface of the logic die 10 and the substrate 110, the signal transmission path between optical structure 30 and logic die 10 can be shortened, thereby enabling high-speed communication and reducing signal loss.

[0060] The optical structure 30 can be separated from the first surface of the substrate 110 via the base insulating layer 120. The optical structure 30 can be connected to the substrate 110 in a direction perpendicular to the first surface of the substrate 110 (e.g., on the third direction DR3) via the insulating layer through-path 125. For example, the optical structure 30 can be connected to the substrate 110 via the fourth connection pad 128, the connection path 127, the insulating layer through-path 125, the second connection pad 122, the first connection member 121, and the first connection pad 118, but the embodiments are not limited thereto.

[0061] Multiple optical structures 30 can be provided, and the optical structures 30 can be arranged on the upper surface of the base insulating layer 120, with the high-bandwidth memory 20 disposed therebetween. As shown, the optical structures 30 can be arranged on opposite sides of the high-bandwidth memory 20, but the embodiments are not limited thereto.

[0062] The optical structure 30 may include a photonic integrated circuit 32 and an electronic integrated circuit 34. The photonic integrated circuit 32 may be positioned on the upper surface of the base insulating layer 120. The photonic integrated circuit 32 may also be located on the fourth connection pad 128. The electronic integrated circuit 34 may be located on at least a portion of the upper surface of the photonic integrated circuit 32. In one or more embodiments, the photonic integrated circuit 32 and the electronic integrated circuit 34 may overlap with the logic die 10 on the third-direction DR3. The photonic integrated circuit 32 and the electronic integrated circuit 34 may overlap with the edge portion of the logic die 10 on the third-direction DR3. The photonic integrated circuit 32 may be positioned on the upper surface of the base insulating layer 120 in the region where it overlaps with the edge portion of the logic die 10 on the third-direction DR3. The electronic integrated circuit 34 may be positioned on the upper surface of the photonic integrated circuit 32 in the region where it overlaps with the edge portion of the logic die 10 on the third-direction DR3.

[0063] The lower surface of the optical structure 30 can be the lower surface of the photonic integrated circuit 32. A fifth connection pad 322 and a first insulating layer 324 surrounding the fifth connection pad 322 can be positioned on the lower surface of the photonic integrated circuit 32. The photonic integrated circuit 32 can be electrically connected to the logic die 10 and the insulating layer through-path 125 via the fifth connection pad 322. The photonic integrated circuit 32 can be electrically connected to the substrate 110 via the insulating layer through-path 125.

[0064] Multiple sixth connection pads 326 may be positioned on the upper surface of the photonic integrated circuit 32. A second insulating layer 328 may be located between the sixth connection pads 326. The side surface of each of the sixth connection pads 326 may be surrounded by the second insulating layer 328. The sixth connection pads 326 may be separated by the second insulating layer 328.

[0065] Multiple seventh connection pads 342 may be positioned on the lower surface of the electronic integrated circuit 34. A third insulating layer 344 may be located between the seventh connection pads 342. The side surface of each of the seventh connection pads 342 may be surrounded by the third insulating layer 344. The seventh connection pads 342 may be separated by the third insulating layer 344. The lower surface of the seventh connection pads 342 may contact the upper surface of the sixth connection pad 326, and the lower surface of the third insulating layer 344 may contact the upper surface of the second insulating layer 328.

[0066] Each of the sixth connection pad 326 and the seventh connection pad 342 may include a conductive material. For example, each of the sixth connection pad 326 and the seventh connection pad 342 may include a metal such as copper, aluminum, or an alloy thereof. Each of the second insulating layer 328 and the third insulating layer 344 may include an insulating material. For example, the second insulating layer 328 and the third insulating layer 344 may each include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide nitride (SiONx), or a combination thereof, but the embodiments are not limited thereto.

[0067] In other words, the electronic integrated circuit 34 can be bonded to the photonic integrated circuit 32 using the HCB method, but the embodiments are not limited to this. The way the electronic integrated circuit 34 is bonded to the photonic integrated circuit 32 can vary in various ways.

[0068] As described above, the photonic integrated circuit 32 and the electronic integrated circuit 34 can be electrically connected as they are joined together.

[0069] For example, photonic integrated circuit 32 can convert optical signals received from optical fiber 42 into electrical signals for transmission to electronic integrated circuit 34, and electronic integrated circuit 34 can convert or amplify electrical signals received from photonic integrated circuit 32 for transmission to logic die 10. Electronic integrated circuit 34 can transmit electrical signals received from logic die 10 to photonic integrated circuit 32, and photonic integrated circuit 32 can convert and modulate electrical signals received from electronic integrated circuit 34 into optical signals for transmission to optical fiber 42. This will refer to... Figure 3 and Figure 4 To describe in more detail.

[0070] A photonic layer through-path 325 extending through the photonic integrated circuit 32 can be provided. The photonic layer through-path 325 can extend through the photonic integrated circuit 32 on the third-direction DR3. The photonic layer through-path 325 can be connected between the fifth connection pad 322 and the sixth connection pad 326. The electronic integrated circuit 34 can be electrically connected to the logic die 10 and the insulating layer through-path 125 through the photonic layer through-path 325. The electronic integrated circuit 34 can be electrically connected to the substrate 110 through the photonic layer through-path 325 and the insulating layer through-path 125.

[0071] exist Figure 2 The image shows a photonic layer through-path 325, but the embodiments are not limited to this and multiple photonic layer through-paths 325 may be provided.

[0072] The photonic layer penetration path 325 may include a conductive material. For example, the photonic layer penetration path 325 may include a metal, such as copper, aluminum, or an alloy thereof.

[0073] The photonic integrated circuit 32 may include a grating connector 455 optically connected to an optical fiber. The grating connector 455 can be used to transmit optical signals received via the optical fiber in different directions. For example, the grating connector 455 can transmit optical signals received in the vertical direction towards the upper surface of the photonic integrated circuit 32 in a horizontal direction parallel to the upper surface of the photonic integrated circuit 32. The grating connector 455 can transmit optical signals generated from the photonic integrated circuit 32 to the optical fiber.

[0074] The grating connector 455 can be covered by the second insulating layer 328. Figure 2 In the illustration, the second insulating layer 328 is shown covering the side surface of the grating connector 455; however, the embodiment is not limited to this, and the second insulating layer 328 may further cover the upper surface of the grating connector 455. When the second insulating layer 328 covers the upper surface of the grating connector 455, the second insulating layer 328 may include a light-transmitting material. For example, the second insulating layer 328 may include silicon oxide, silicon nitride, silicon oxide nitride, or a combination thereof.

[0075] The grating connector 455 can be positioned on the third-direction DR3 without overlapping with the electronic integrated circuit 34. That is, the electronic integrated circuit 34 can be positioned between the grating connector 455 and the optical connector 40 without being located on the third-direction DR3.

[0076] In one or more embodiments, the optical structure 30 may include a light-transmitting insulating layer 36 located on the upper surface of the photonic integrated circuit 32 and the side surface of the electronic integrated circuit 34. In one or more embodiments, the electronic integrated circuit 34 may be positioned on a portion of the upper surface of the photonic integrated circuit 32. The light-transmitting insulating layer 36 may be positioned on another portion of the upper surface of the photonic integrated circuit 32. The light-transmitting insulating layer 36 may cover the upper surface of the grating connector 455 and the upper surface of the second insulating layer 328. The light-transmitting insulating layer 36 may also comprise a light-transmitting material. For example, the light-transmitting insulating layer 36 may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The light-transmitting insulating layer 36 may be formed as a single layer or multiple layers.

[0077] like Figure 2 As shown, the light-transmitting insulating layer 36 can contact the upper surface of the second insulating layer 328. In one or more embodiments, the light-transmitting insulating layer 36 and the second insulating layer 328 may comprise the same material. When the light-transmitting insulating layer 36 and the second insulating layer 328 comprise the same material, the interface between the light-transmitting insulating layer 36 and the second insulating layer 328 may not be discernible.

[0078] exist Figure 2 In the illustration, the upper surface of the light-transmitting insulating layer 36 is shown positioned at substantially the same level as the upper surface of the electronic integrated circuit 34, but the embodiment is not limited thereto. For example, the light-transmitting insulating layer 36 may be further positioned on the upper surface of the electronic integrated circuit 34.

[0079] In one or more embodiments, the optical structure 30 may include a capping layer 38 on the upper surface of the electronic integrated circuit 34. The capping layer 38 may cover both the upper surface of the photonic integrated circuit 32 and the upper surface of the electronic integrated circuit 34. The capping layer 38 may contact the upper surface of the electronic integrated circuit 34. The capping layer 38 may be spaced apart from the upper surface of the photonic integrated circuit 32 on a third-direction DR3. On the third-direction DR3, a light-transmitting insulating layer 36 may be located between the capping layer 38 and the photonic integrated circuit 32. The capping layer 38 may be positioned on the upper surface of the light-transmitting insulating layer 36. The capping layer 38 may contact the upper surface of the light-transmitting insulating layer 36.

[0080] The capping layer 38 may include a light-transmitting material. For example, the capping layer 38 may include, but is not limited to, glass or silicon (Si).

[0081] Optical connector 40 can be positioned on the upper surface of cover layer 38. Optical connector 40 may include optical fiber 42. Figure 2 In this illustration, for convenience, the optical connector 40 is shown to include one optical fiber 42, but the optical connector 40 may include multiple optical fibers 42, and the optical fibers 42 may be provided in an array.

[0082] The cover layer 38 can be located between the end portion of the optical fiber 42 of the optical connector 40 and the upper surface of the photonic integrated circuit 32. The cover layer 38 can be used to protect the photonic integrated circuit 32 and the electronic integrated circuit 34 while transmitting light between the optical connector 40 and the photonic integrated circuit 32.

[0083] The optical connector 40 can be positioned such that the end portion of the optical fiber 42 faces the upper surface of the cover layer 38. The end portion of the optical fiber 42 can be spaced apart from the upper surface of the cover layer 38. An air gap can be positioned between the end portion of the optical fiber 42 and the upper surface of the cover layer 38.

[0084] The optical connector 40 can be connected through a hole provided in the frame covering the semiconductor package 100. For example, the optical connector 40 and the hole can be coupled to each other in a male-female configuration.

[0085] Multiple optical connectors 40 can be provided, and each optical connector 40 can be connected between the optical structure 30 and the external device 1000. The first end of the optical fiber 42 of each of the optical connectors 40 can be optically connected to each of the optical structures 30, and the second end of the optical fiber 42 of each of the optical connectors 40 can be optically connected to the external device 1000.

[0086] Semiconductor package 100 may include a first molding member 190 that molds a high-bandwidth memory 20 and an optical structure 30 on the upper surface of a base insulating layer 120. The first molding member 190 may cover the upper and side surfaces of the high-bandwidth memory 20. The first molding member 190 may cover the side surfaces of the optical structure 30. The first molding member 190 may not cover the upper surface of the optical structure 30. That is, the upper surface of the cover layer 38 may not be covered by the first molding member 190 and may be exposed. The upper surface of the first molding member 190 may be positioned at substantially the same level as the upper surface of the cover layer 38. The first molding member 190 may include, for example, an epoxy molding compound (EMC), but embodiments are not limited thereto.

[0087] The semiconductor package 100 is not limited to the components described above, and may include other components. According to one or more embodiments, the semiconductor package 100 may include a front redistribution layer between the lower surface of the logic die 10 and the upper surface of the substrate 110, or may include a rear redistribution layer between the upper surface of the logic die 10 and the lower surface of the high-bandwidth memory 20 and the lower surface of the optical structure 30, or may include both a front redistribution layer and a rear redistribution layer.

[0088] In the following text, reference will be made to Figure 3 and Figure 4 describe Figure 1 and Figure 2 The optical structure 30 includes optical and electronic components.

[0089] Figure 3 This is a schematic block diagram illustrating components of an optical structure according to one or more embodiments. Figure 4 This is a schematic cross-sectional view of a photonic integrated circuit according to one or more embodiments.

[0090] In one or more embodiments, the photonic integrated circuit 32 may include optical components, and the electronic integrated circuit 34 may include electronic components. The electronic components of the electronic integrated circuit 34 may be formed of a transistor array, and the optical components of the photonic integrated circuit 32 may include a portion of the transistor array.

[0091] For example, the photonic integrated circuit 32 may include, but is not limited to, a multiplexer (MUX) 310, multiple optical modulators 315, a demultiplexer (DEMUX) 350, and multiple photodetectors 355, and may further include other components. For example, the electronic integrated circuit 34 may include a current-to-voltage converter 360, an output driver 370, an input buffer 330, and a modulator driver 320, but embodiments are not limited thereto, and the controller 340 may also include other components. The current-to-voltage converter 360, output driver 370, input buffer 330, modulator driver 320, and controller 340 can be categorized according to the function performed by each component.

[0092] The optical connector 40 can serve as an input and output port for optical signals between the optical fiber 42 connected to an external device and the semiconductor package 100. In the following description, each component will be presented separately for the cases of receiving optical signals and transmitting optical signals via the optical fiber 42.

[0093] refer to Figure 3The optical signal received through optical connector 40 can reach multiple photodetectors 355 via demultiplexer 350. Photodetectors 355 can convert the optical signal into an analog electrical signal. Current-to-voltage converter 360 can convert the current signal output from photodetectors 355 into a voltage signal. For example, current-to-voltage converter 360 can amplify the current output of photodetector 355 of photonic integrated circuit 32 or another type of sensor to a usable voltage. The converted electrical signal can be output to the outside of optical structure 30 (e.g., logic die 10) via output driver 370.

[0094] When an electrical signal is received in the input buffer 330, the light source element emits light based on the received signal, and the modulator driver 320 can drive the optical modulator 315 to modulate the light emitted from the light source element. The electronic components can operate under the control of the controller 340. The modulated light can be transmitted to the optical connector 40 via the multiplexer 310, and the optical signal can be transmitted via the optical fiber 42 connected to the optical connector 40.

[0095] refer to Figure 4 The photonic integrated circuit 32 may include a buried oxide layer (BOX) 400, a silicon layer 410 on the buried oxide layer 400, and a cladding layer 420 on the silicon layer 410.

[0096] The buried oxide layer 400 can be positioned on the silicon-based component. The buried oxide layer 400 can be formed on the entire upper surface of the silicon-based component, or it can be formed on only a portion of it.

[0097] Silicon layer 410 may be located on buried oxide layer 400. Silicon layer 410 may include optical components. In one or more embodiments, silicon layer 410 may include optical waveguide 450, grating connector 455, optical modulator 460, and photodetector 465.

[0098] For example, a silicon material layer can be formed on the buried oxide layer 400, and a silicon layer 410 can be formed by extending through the silicon material layer using photolithography and etching processes. The patterned silicon layer 410 may include optical components. An overlay layer 420 may be stacked on top of the patterned silicon layer 410. A nitride layer may be further positioned on the patterned silicon layer 410.

[0099] The optical connector 40 can be optically connected to other optical components. The optical waveguide 450 can realize an optical path for confining and transmitting light within the photonic integrated circuit 32. The optical waveguide 450 can be formed as a single structure or multiple structures. For example, the optical waveguide 450 may include optical fiber, silicon waveguide components, silicon nitride waveguide components, etc.

[0100] The grating connector 455 can be a medium for receiving optical signals transmitted from an external device via optical fiber 42 or for transmitting optical signals to an external device via optical fiber 42. In one or more embodiments, the grating connector 455 can be used as a medium for transmitting and receiving optical signals through the photonic integrated circuit 32; however, those skilled in the art will understand that an edge connector can be used as a medium for transmitting and receiving optical signals from the photonic integrated circuit 32. When using the grating connector 455, optical signals can be transmitted and received vertically across the upper surface of the photonic integrated circuit 32, and when using the edge connector, optical signals can be transmitted and received horizontally across the side surface (or edge) of the photonic integrated circuit 32.

[0101] The optical modulator 460 can convert light emitted from the light source element into an optical signal containing information by modulating the light according to the signal to be transmitted. For example, the optical modulator 460 may be a phase modulator. In one or more embodiments, the optical modulator 460 may be, but is not limited to, a Mach-Zehnder modulator, a microring modulator, an electroabsorption modulator, and one of an LN / Si hybrid and a thin-film lithium niobate (TFLN) modulator.

[0102] The photodetector 465 can generate and output an electrical signal based on the received optical signal. The photodetector 465 can be, for example, a positive-intrinsic-negative (PIN) structure including a germanium (Ge) region. The photonic integrated circuit 32 can also include a ring resonator. The ring resonator can be a device for filtering signals of a desired wavelength from the optical signal transmitted through the optical waveguide 450.

[0103] The embodiments described herein are not limited to the optical components described above, and the photonic integrated circuit 32 may further include switches, splitters, heaters, etc., in addition to the components described above.

[0104] Optical components can be divided into passive and active components. The optical waveguide 450 and grating connector 455 can be considered passive components, while the optical modulator 460 and photodetector 465 can be considered active components. To electrically connect the active components to the electronic components, they can be electrically connected to contact terminals 470 and 475, which extend through the cladding layer 420 and are exposed on the upper surface of the cladding layer 420. Figure 2 The sixth connection pad 326 can be shown as a connection pad exposed on the upper surface of the cladding layer 420 among contact terminals 470 and 475. Figure 2 The second insulating layer 328 can be shown as part of the covering layer 420. Contact terminals 470 and 475 can have various structures for electrically connecting active components to electronic components of the electronic integrated circuit 34, and are not limited to... Figure 4 The structure of contact terminals 470 and 475 is shown.

[0105] Figure 4 The illustration shows a schematic structure of an optical component according to one or more embodiments, and the optical component is not limited to... Figure 4 The structure shown in the diagram.

[0106] A semiconductor package 100 according to one or more embodiments may include a base insulating layer 120 covering the side and top surfaces of a logic die 10, an insulating layer through-path 125 extending through the base insulating layer 120 located on opposite sides of the logic die 10, a high-bandwidth memory 20 located on the top surface of the base insulating layer 120, and an optical structure 30. The high-bandwidth memory 20 and the optical structure 30 may be connected to the logic die 10 in a direction perpendicular to the top surface of the logic die 10. Therefore, compared to a comparative example where the optical structure 30 is positioned on a first surface in a direction parallel to the first surface of the logic die 10 and the substrate 110, the signal transmission path between the optical structure 30 and the logic die 10 can be shortened, thereby enabling high-speed communication and reducing signal loss.

[0107] According to one or more embodiments, the optical structure 30 of the semiconductor package 100 may overlap with the logic die 10 in a plan view. Therefore, the size of the semiconductor package 100 can be reduced compared to a comparative example in which the optical structure 30 is positioned on the first surface and the substrate 110 along a direction parallel to the first surface of the logic die 10.

[0108] In the following text, it will be related to Figure 5 and Figure 6 Each of them is described together Figures 1 to 4 A modified example of semiconductor package 100.

[0109] Figure 5 It is a cross-sectional view of a semiconductor package according to one or more embodiments. Figure 6 This is a cross-sectional view of a semiconductor package according to one or more embodiments. Descriptions of aspects that are the same as or similar to those described above may be omitted.

[0110] exist Figure 5 In this process, the molding structure of the optical structure 30 may differ slightly from the molding structure described above. Figure 5 In the embodiments shown, the bonding structure of the optical structure 30 may differ in part from those described above.

[0111] refer to Figure 5The semiconductor package 100 may further include a second molding member 192 positioned between a side surface of the optical structure 30 and a first molding member 190. The second molding member 192 may cover the side surface of the optical structure 30. The second molding member 192 may not cover the upper surface of the optical structure 30. The upper surface of the second molding member 192 may be positioned at a level substantially the same as the upper surface of the optical structure 30. The upper surface of the second molding member 192 may be positioned at a level substantially the same as the upper surface of the cover layer 38.

[0112] The first molding member 190 may cover the upper and side surfaces of the high-bandwidth memory 20 and the side surface of the second molding member 192. The first molding member 190 may be separable from the side surface of the optical structure 30 via the second molding member 192. The first molding member 190 may not cover the upper surface of the second molding member 192 and the upper surface of the optical structure 30. The upper surface of the first molding member 190 may be positioned at substantially the same level as the upper surface of the second molding member 192 and the upper surface of the optical structure 30. The upper surface of the first molding member 190 may be positioned at substantially the same level as the upper surface of the cover layer 38.

[0113] In one or more embodiments, the optical structure 30 may be molded first together with the second molding component 192, and then together with the high-bandwidth memory 20 and the first molding component 190. That is, the optical structure 30 may be double-molded.

[0114] The second molding member 192 may include the same material as the first molding member 190, or may include a different material than the first molding member 190. For example, the second molding member 192 may include, but is not limited to, EMC.

[0115] refer to Figure 6 The semiconductor package 100 may include a first bottom filler 323 positioned between the lower surface of the optical structure 30 and the upper surface of the base insulating layer 120. Figure 6 In the middle, a first bottom filling member 323 can be added because the joining method of the optical structure 30 is similar to... Figures 1 to 4 The implementation methods differ.

[0116] exist Figures 1 to 4 In this configuration, the fifth connection pad 322 can contact the fourth connection pad 128, and the first insulating layer 324 can contact the base insulating layer 120. That is, the optical construct 30 can be bonded to the base insulating layer 120 using the HCB method. Conversely, in... Figure 6In this configuration, the fifth connection pad 322 can be electrically connected to the fourth connection pad 128 via the second connection member 321. For example, the second connection member 321 can be a solder bump. That is, the optical structure 30 can be bonded to the base insulating layer 120 using solder bumps.

[0117] In one or more embodiments, the semiconductor package 100 may include second connection members 321, each second connection member 321 positioned on the lower surface of the fifth connection pad 322. A first underfill member 323 may surround the side surface of the fifth connection pad 322 and the side surface of the second connection member 321. The first underfill member 323 may fill the remaining space between the lower surface of the photonic integrated circuit 32 and the upper surface of the base insulating layer 120. The first underfill member 323 may fill the space between the second connection members 321. The first underfill member 323 may prevent adjacent second connection members 321 from short-circuiting.

[0118] In one or more embodiments, the semiconductor package 100 may include third connection members 341, each third connection member 341 being positioned on the lower surface of a seventh connection pad 342. The seventh connection pad 342 may be electrically connected to a sixth connection pad 326 via the third connection members 341. For example, the third connection member 341 may be a solder bump. That is, an electronic integrated circuit 34 may be bonded to a photonic integrated circuit 32 using solder bumps.

[0119] In one or more embodiments, the semiconductor package 100 may include a second underfill member 343 positioned between the lower surface of the electronic integrated circuit 34 and the upper surface of the photonic integrated circuit 32. The second underfill member 343 may surround the side surface of the seventh connection pad 342 and the side surface of the third connection member 341. The second underfill member 343 may fill the remaining space between the lower surface of the electronic integrated circuit 34 and the upper surface of the photonic integrated circuit 32. The second underfill member 343 may fill the space between the third connection members 341. The second underfill member 343 may prevent short circuits between adjacent third connection members 341.

[0120] exist Figure 6 The diagram shows that electronic integrated circuit 34 and photonic integrated circuit 32, as well as photonic integrated circuit 32 and base insulating layer 120, can be bonded using solder bumps, but the embodiments are not limited to this. For example, electronic integrated circuit 34 and photonic integrated circuit 32 can be bonded using the HCB method, and the bonding of photonic integrated circuit 32 and base insulating layer 120 can be achieved using solder bumps or other different bonding methods.

[0121] The following will refer to Figure 7 describe Figures 1 to 4 A variation of the semiconductor package 100.

[0122] Figure 7 This is a cross-sectional view of a semiconductor package according to one or more embodiments. Descriptions of aspects that are the same as or similar to those described above may be omitted. Figure 7 The difference from the other figures mentioned above lies in the addition of a heat-conducting block 50.

[0123] refer to Figure 7 The semiconductor package 100 may further include a thermal pad 52 positioned on the upper surface of the base insulating layer 120, and a thermal block 50 positioned on the thermal pad 52 and in a direction parallel to the optical structure 30. The thermal pad 52 may be connected to the insulating layer through-path 125 and the logic die 10. The lower surface of the thermal block 50 may contact the upper surface of the thermal pad 52. The upper surface of the thermal block 50 may be exposed and may not be covered by the first molding member 190. The thermal pad 52 and the thermal block 50 may be used to release or dissipate heat generated from the logic die 10 and the substrate 110 to the outside.

[0124] In one or more embodiments, the thermal pad 52 may overlap the insulating layer through-path 125 and the logic die 10 in a direction perpendicular to the upper surface of the base insulating layer 120 (e.g., on the third-direction DR3). The thermal pad 52 may be connected to the insulating layer through-path 125 and the logic die 10 on the third-direction DR3. Therefore, the distance between the substrate 110 and the logic die 10 and the thermal pad 52 can be shortened, thereby transferring heat to the thermal block 50 more quickly and improving heat dissipation performance.

[0125] The thermal pad 52 may include a thermal interface material (TIM). For example, the TIM may include, but is not limited to, a metal with high thermal conductivity, such as copper or aluminum.

[0126] The heat-conducting block 50 may include a material with high thermal conductivity. The heat-conducting block 50 may include, but is not limited to, metals such as copper or aluminum, or ceramics.

[0127] The following will refer to Figure 8 describe Figures 1 to 4 A variation of the semiconductor package 100.

[0128] Figure 8 This is a cross-sectional view of a semiconductor package according to one or more embodiments. Descriptions of aspects identical or similar to those described above may be omitted. Figure 8 In this case, the configuration of the optical structure 30 may differ in some ways from those described above.

[0129] refer to Figure 8The optical structure 30 may include a photoelectronic integrated circuit 33 positioned on the upper surface of the base insulating layer 120, a cover layer 38 covering the upper surface of the photoelectronic integrated circuit 33, and a light-transmitting insulating layer 36 positioned between the photoelectronic integrated circuit 33 and the cover layer 38. The cover layer 38 and the light-transmitting insulating layer 36 may include light-transmitting materials.

[0130] exist Figures 1 to 4 In some embodiments, the photonic integrated circuit 32 and the electronic integrated circuit 34 can be functionally and structurally separated. Conversely, in Figure 8 In this embodiment, photonic integrated circuit 32 and electronic integrated circuit 34 can be functionally and structurally integrated to realize optoelectronic integrated circuit 33. Optoelectronic integrated circuit 33 can convert optical signals received from optical fiber 42 into electrical signals for transmission to logic die 10, and can also convert electrical signals received from logic die 10 into optical signals for transmission to optical fiber 42. Optoelectronic integrated circuit 33 may include a grating connector 455 optically connected to optical fiber 42. Optoelectronic integrated circuit 33 can receive signals received through optical fiber 42 via grating connector 455, and can also transmit optical signals generated in optoelectronic integrated circuit 33 to optical fiber 42 via grating connector 455.

[0131] exist Figures 1 to 4 In this configuration, the electronic integrated circuit 34 can cover a portion of the upper surface of the photonic integrated circuit 32, thus the light-transmitting insulating layer 36 can cover only the remaining portion of the photonic integrated circuit 32. On the other hand, in... Figure 8 In the middle, the light-transmitting insulating layer 36 can completely cover the upper surface of the optoelectronic integrated circuit 33.

[0132] The following is for reference Figure 9 right Figures 1-4 A modified example of the semiconductor package 100 will be described.

[0133] Figure 9 This is a cross-sectional view of a semiconductor package according to one or more embodiments. Descriptions of aspects identical or similar to those described above may be omitted. Figure 9 In this context, the configuration of the high-bandwidth memory 20 may differ in some respects from those described above.

[0134] refer to Figure 9The high-bandwidth memory 20 may further include a base die 25 beneath the memory dies 21, 22, 23, and 24. The base die 25 may have a planar area larger than that of the memory dies 21, 22, 23, and 24. The base die 25 may be used to support the memory dies 21, 22, 23, and 24. The memory dies 21, 22, 23, and 24 may be stacked on the upper surface of the base die 25. The memory dies 21, 22, 23, and 24 may be molded on the upper surface of the base die 25. The molding members of the high-bandwidth memory 20 may cover the upper and side surfaces of the memory dies 21, 22, 23, and 24, as well as the upper surface of the base die 25. The side surfaces of the base die 25 may not be covered by the molding members of the high-bandwidth memory 20.

[0135] According to one or more embodiments, base die 25 may be a heterogeneous die with respect to memory dies 21, 22, 23, and 24. For example, base die 25 may be a field-programmable gate array (FPGA) die. For example, the FPGA die may include computing circuitry and may perform arithmetic or logical operations on data read from memory dies 21, 22, 23, and 24. In this case, high-bandwidth memory 20 may perform some data processing within memory without communicating with logic die 10. High-bandwidth memory 20 may support processing in memory (PIM).

[0136] For example, base die 25 can be a cache memory die. A cache memory die can provide faster data access than memory dies 21, 22, 23, and 24. A cache memory die can store frequently used data in logic die 10. A cache memory die can act as a buffer between logic die 10 and memory dies 21, 22, 23, and 24. For example, each of memory dies 21, 22, 23, and 24 can be a DRAM die, and base die 25 can be a static random access memory (SRAM) die.

[0137] The following is for reference Figures 10 to 12 right Figures 1 to 4 A modified example of the semiconductor package 100 will be described.

[0138] Figure 10 It is a top plan view of a semiconductor package according to one or more embodiments. Figure 11 According to one or more embodiments along Figure 10 A cross-sectional view of a semiconductor package taken by line B-B'. Figure 12 According to one or more embodiments along Figure 10 The image shows a cross-sectional view of the semiconductor package taken along line B-B'. Descriptions of aspects identical or similar to those described above may be omitted. Figures 10 to 12 The difference from the above is that it provides... Figures 1 to 4 The structure consists of multiple small chips CL1, CL2, CL3 and CL4.

[0139] First, refer to Figure 10 and Figure 11 The semiconductor package 100 may include a substrate 110 and chiplets CL1, CL2, CL3, and CL4 mounted on the substrate 110. According to one or more embodiments, each of the chiplets CL1, CL2, CL3, and CL4 may include components... Figures 1 to 4 The semiconductor package 100 has the same components as the components and has the same components as the semiconductor package 100. Figures 1 to 4 The components of the semiconductor package 100 have the same structure. Each of the chiplets CL1, CL2, CL3, and CL4 may include a logic die 10 positioned on a first surface of the substrate 110, a base insulating layer 120 positioned on the side and top surfaces of the logic die 10, an insulating layer through-path 125 extending through the base insulating layer 120 at opposite sides of the logic die 10, a high-bandwidth memory 20 and an optical structure 30 positioned on the top surface of the base insulating layer 120, and an optical connector 40 including an optical fiber 42 for transmitting optical signals between the optical structure 30 and an external device. The high-bandwidth memory 20 may include a plurality of memory dies 21, 22, 23, and 24 stacked vertically on the top surface of the base insulating layer 120. The optical structure 30 may be connected to the logic die 10 in a direction perpendicular to the top surface of the logic die 10.

[0140] exist Figures 1 to 4 The diagram illustrates a module comprising high-bandwidth memory 20, including memory dies 21, 22, 23, and 24, vertically stacked on logic die 10; however, the embodiment is not limited to this. For example, in... Figure 10 and Figure 11 In this configuration, the semiconductor package 100 may include multiple modules, including high-bandwidth memory dies 21, 22, 23, and 24, which are vertically stacked on a logic die 10. In this case, each of the multiple modules may be referred to as a chiplet. The logic die 10 of each of the chiplets CL1, CL2, CL3, and CL4 may include... Figures 1 to 4 The different functions of the various functions of the logic chip 10. That is to say, Figures 1 to 4 The various functions of the logic die 10 can be shared by multiple chiplets CL1, CL2, CL3, and CL4. Therefore, the size of the logic die 10 of each of the chiplets CL1, CL2, CL3, and CL4 can be smaller than [the specified size]. Figures 1 to 4 The dimensions of the logic die 10.

[0141] In one or more embodiments, the semiconductor package 100 may further include a bridging layer 115 embedded in the upper portion of the substrate 110. Chips CL1, CL2, CL3, and CL4 may be connected via the bridging layer 115. The bridging layer 115 may be positioned in a plan view between chips CL1, CL2, CL3, and CL4. The bridging layer 115 may, for example, comprise silicon and may include wires patterned into the silicon layer. Chips CL1, CL2, CL3, and CL4 may be electrically connected to each other via the bridging layer 115. The logic dies 10 of each of chips CL1, CL2, CL3, and CL4 may communicate via the bridging layer 115. The logic dies 10 of chips CL1, CL2, CL3, and CL4 may access high-bandwidth memory 20 included in the different chips via the bridging layer 115.

[0142] exist Figure 11 The illustration shows a bridging layer 115, but the embodiment is not limited to this. Multiple bridging layers 115 may be embedded in the substrate 110. For example, each bridging layer 115 may be positioned between two adjacent chips in chips CL1, CL2, CL3, and CL4.

[0143] Reference Figure 10 and Figure 12 The semiconductor package 100 may further include a redistribution layer 130 positioned between the substrate 110 and the logic die 10 of each of the chiplets CL1, CL2, CL3, and CL4. In an embodiment, the chiplets CL1, CL2, CL3, and CL4 may be connected via the redistribution layer 130. The redistribution layer 130 may include a redistribution layer 132, a redistribution path 134 connecting the redistribution layer 132 in a direction perpendicular to a first surface of the substrate 110 (e.g., third direction DR3), and a redistribution insulating layer (136) surrounding the redistribution layer 132 and the redistribution path 134. A plurality of second connection pads 122 positioned on the lower surface of each of the chiplets CL1, CL2, CL3, and CL4 may be connected to the uppermost redistribution layer 132 of the redistribution layer 130 via a plurality of first connection members 121. The chiplets CL1, CL2, CL3, and CL4 may be electrically connected to each other via the redistribution layer 130.

[0144] In one or more embodiments, a plurality of eighth connection pads 142 may be positioned on the lower surface of the redistribution layer 130, and a plurality of fourth connection members 141 may be positioned on the lower surface of the eighth connection pads 142. The eighth connection pads 142 may be connected to a first connection pad 118 located on the upper surface of the substrate 110 via the fourth connection members 141. Each of the chiplets CL1, CL2, CL3, and CL4 may be electrically connected to the substrate 110 via the redistribution layer 130.

[0145] In the following text, reference will be made to Figures 13 to 19 describe Figures 1 to 4 A method for manufacturing a semiconductor package 100.

[0146] Figures 13 to 19 This is a process cross-sectional view illustrating a manufacturing method for semiconductor packaging according to one or more embodiments.

[0147] Reference Figure 13 A logic die 10 may be disposed on the upper surface of a carrier substrate CR. The logic die 10 may include a plurality of logic paths 105 extending through the logic die 10 in a direction perpendicular to the upper surface of the carrier substrate CR (e.g., in a third direction DR3). A plurality of third connection pads 124 may be positioned on the upper surface of the logic die 10. The logic paths 105 may be connected to the plurality of third connection pads 124.

[0148] Each of the logic path 105 and the third connection pad 124 may include a metal such as copper or aluminum, but this disclosure is not limited thereto.

[0149] Reference Figure 14 Insulating material can be deposited on the carrier substrate CR to form a base insulating layer 120 covering the side and top surfaces of the logic die 10. The base insulating layer 120 can be formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, but the embodiments are not limited thereto. The base insulating layer 120 can surround the side surface of a third connection pad 124 located on the top surface of the logic die 10.

[0150] The base insulating layer 120 may include, for example, silicon oxide, silicon nitride, silicon nitride, or a combination thereof.

[0151] For example, after depositing an insulating material to cover the upper surface of the third connection pad 124, the upper surface of the third connection pad 124 can be exposed by a planarization process. The planarization process may include, for example, a chemical mechanical polishing (CMP) process. The upper surface of the base insulating layer 120 may be located at substantially the same level as the upper surface of the third connection pad 124.

[0152] refer to Figure 15Multiple insulating layer through-paths 125 extending through the base insulating layer 120 can be formed. For example, multiple vias extending through the base insulating layer 120 in a direction perpendicular to the upper surface of the carrier substrate CR (e.g., on the third direction DR3) can be formed by photolithography and etching processes. The insulating layer through-paths 125 can then be formed by filling the vias with a conductive material. The insulating layer through-paths 125 may include a metal such as copper or aluminum, but the embodiments are not limited thereto. The insulating layer through-paths 125 can be formed by plating or CVD processes, but the embodiments are not limited thereto.

[0153] The insulating layer through-path 125 may extend along the third direction DR3 through the base insulating layer 120 on the opposite side of the logic die 10. The upper surface of the insulating layer through-path 125 may be positioned at substantially the same level as the upper surface of the third connection pad 124.

[0154] refer to Figure 16 An insulating material can be additionally deposited to form a base insulating layer 120 covering the upper surface of the third connection pad 124 and the insulating layer through-path 125. Next, a plurality of connection paths 127 and a plurality of fourth connection pads 128 can be formed. For example, after patterning the additionally deposited base insulating layer 120 to form a plurality of vias, a conductive material layer can be formed to fill the interior of the vias and cover the upper surface of the base insulating layer 120, and the conductive material layer can be patterned to form the connection paths 127 and the fourth connection pads 128.

[0155] Each of the connection path 127 and the fourth connection pad 128 may include a metal such as copper or aluminum, but the embodiment is not limited thereto. The conductive material layer may be formed by a plating process or a CVD process, but the embodiment is not limited thereto. The conductive material layer may be patterned by photolithography and etching processes.

[0156] Next, an additional insulating material can be deposited to form a base insulating layer 120 covering the side surface of the fourth connection pad 128. For example, an additional insulating material can be deposited to cover the upper surface of the fourth connection pad 128, and then the upper surface of the fourth connection pad 128 can be exposed by a planarization process. The upper surface of the base insulating layer 120 can be positioned at substantially the same level as the upper surface of the fourth connection pad 128.

[0157] Some of the connection paths 127 can connect to the third connection pad 124, and other connection paths can connect to the insulating layer through-path 125. A fourth connection pad 128 can be connected to both the third connection pad 124 and the insulating layer through-path 125 via connection path 127. Some of the fourth connection pads 128 can connect to the third connection pad 124, and other fourth connection pads 128 can connect to the insulating layer through-path 125. Connection to the third connection pad 124 indicates connection to the logic die 10.

[0158] refer to Figure 17 The high-bandwidth memory 20 and the optical structure 30 can be bonded to the base insulating layer 120 and the fourth connection pad 128. For example, the high-bandwidth memory 20 and the optical structure 30 can be bonded in various ways, such as using solder bump bonding or using the HCB method without bump bonding.

[0159] In one or more embodiments, the high-bandwidth memory 20 and the optical structure 30 may overlap with the logic die 10 on the third-direction DR3. The high-bandwidth memory 20 may overlap with the central portion of the logic die 10 on the third-direction DR3. The optical structure 30 may overlap with the edge portion of the logic die 10 on the third-direction DR3. The optical structure 30 may overlap with the insulating layer through-path 125 on the third-direction DR3.

[0160] In one or more embodiments, the high-bandwidth memory 20 and the optical structure 30 may be connected to the logic die 10 on the third-direction DR3. The high-bandwidth memory 20 may be connected to the central portion of the upper surface of the logic die 10 on the third-direction DR3. The optical structure 30 may be connected to the edge portion of the upper surface of the logic die 10 on the third-direction DR3. The optical structure 30 may be connected to the insulating layer through-path 125 on the third-direction DR3.

[0161] According to one or more embodiments, the signal transmission path between the optical structure 30 and the logic die 10, and the signal transmission path between the high-bandwidth memory 20 and the logic die 10, can be shorter than in a comparative example in which the high-bandwidth memory 20 and the optical structure 30 are arranged in a horizontal direction (e.g., on the first direction DR1) relative to the logic die 10, thereby improving the communication speed of the semiconductor package and reducing signal loss during communication.

[0162] In one or more embodiments, the optical structure 30 may be positioned along a direction parallel to the upper surface of the high-bandwidth memory 20 and the base insulating layer 120 (e.g., a first direction DR1 or a second direction DR2). In one or more embodiments, multiple optical structures 30 may be provided, and the optical structures 30 may be arranged in a direction parallel to the upper surface of the base insulating layer 120 (e.g., a first direction DR1 or a second direction DR2). For example, the optical structure 30 may be located on opposite sides of the high-bandwidth memory 20, but the embodiments are not limited thereto.

[0163] The high-bandwidth memory 20 may comprise a plurality of memory dies 21, 22, 23, and 24 stacked in a vertical direction (e.g., third-direction DR3). For example, each of the memory dies 21, 22, 23, and 24 may be (but is not limited to) DRAM.

[0164] In one or more embodiments, the high-bandwidth memory 20 may include a memory die and may not include a buffer die. That is, the high-bandwidth memory 20 according to one or more embodiments may be a bufferless HBM. The high-bandwidth memory 20 may be electrically connected to the logic die 10, such that the logic die 10 can be used as a buffer die.

[0165] The high-bandwidth memory 20 may include multiple memory through-paths 205 extending through memory dies 21, 22, 23, and 24. Through the memory through-paths 205, the signal transmission paths between memory dies 21, 22, 23, and 24 and logic die 10 can be shortened and the bandwidth can be increased.

[0166] In one or more embodiments, the optical structure 30 may include a photonic integrated circuit 32, an electronic integrated circuit 34 positioned on the photonic integrated circuit 32, and a capping layer positioned on the upper surface of the electronic integrated circuit 34. The photonic integrated circuit 32 may be positioned on the upper surface of the base insulating layer 120 and on the upper surface of a plurality of fourth connection pads 128. The electronic integrated circuit 34 may be located on at least a portion of the upper surface of the photonic integrated circuit 32. In one or more embodiments, the photonic integrated circuit 32 and the electronic integrated circuit 34 may overlap with the logic die 10 on a third-direction DR3. The photonic integrated circuit 32 and the electronic integrated circuit 34 may overlap with the edge portion of the logic die 10 on the third-direction DR3. The photonic integrated circuit 32 may be positioned on the upper surface of the base insulating layer 120 in the region where it overlaps with the edge portion of the logic die 10 on the third-direction DR3. The electronic integrated circuit 34 may be positioned on the upper surface of the photonic integrated circuit 32 in the region where it overlaps with the edge portion of the logic die 10 on the third-direction DR3.

[0167] The photonic integrated circuit 32 may include a grating connector 455 in an area not covered by the electronic integrated circuit 34. The grating connector 455 can be used to transmit optical signals received via optical fiber in different directions. For example, the grating connector 455 can transmit vertically received optical signals towards the upper surface of the photonic integrated circuit 32 in a horizontal direction parallel to the upper surface of the photonic integrated circuit 32. The grating connector 455 can transmit optical signals generated from the photonic integrated circuit 32 to the optical fiber.

[0168] The lower surface of the optical structure 30 can be the lower surface of the photonic integrated circuit 32. The photonic integrated circuit 32 can be electrically connected to the logic die 10 and the insulating layer through-path 125 via a fifth connection pad 322 positioned on the lower surface of the photonic integrated circuit 32. The photonic integrated circuit 32 can be electrically connected to the substrate 110 via the insulating layer through-path 125.

[0169] In one or more embodiments, the capping layer 38 may cover the upper surface of the photonic integrated circuit 32 and the upper surface of the electronic integrated circuit 34. The capping layer 38 may be in contact with the upper surface of the electronic integrated circuit 34. The capping layer 38 may be spaced apart from the upper surface of the photonic integrated circuit 32 on a third-direction DR3. The optical structure 30 may include a light-transmitting insulating layer 36 located on the third-direction DR3 between the capping layer 38 and the photonic integrated circuit 32. The light-transmitting insulating layer 36 may be positioned on the upper surface of the photonic integrated circuit 32 and the side surface of the electronic integrated circuit 34. The capping layer 38 may be positioned on the upper surface of the light-transmitting insulating layer 36. The capping layer 38 may be in contact with the upper surface of the light-transmitting insulating layer 36.

[0170] The capping layer 38 and the light-transmitting insulating layer 36 may include light-transmitting materials. For example, the capping layer 38 may include, but is not limited to, glass or silicon (Si). For example, the light-transmitting insulating layer 36 may include silicon oxide, silicon nitride, silicon nitride, or combinations thereof.

[0171] refer to Figure 18 The high-bandwidth memory 20 and optical structure 30 can be molded on the upper surface of the base insulating layer 120 using a first molding member 190. The molding process using the first molding member 190 may include, but is not limited to, compression molding or transfer molding processes. The first molding member 190 may contain, for example, an epoxy molding compound (EMC), but the embodiments are not limited thereto.

[0172] Next, the first molding member 190 may be planarized. The planarization process may include, for example, a CMP process, but the embodiments are not limited thereto. The first molding member 190 may cover the upper and side surfaces of the high-bandwidth memory 20. The first molding member 190 may cover the side surfaces of the optical structure 30. The first molding member 190 may not cover the upper surface of the optical structure 30. That is, the upper surface of the cover layer 38 may not be covered by the first molding member 190 and may be exposed. The upper surface of the first molding member 190 may be positioned at substantially the same level as the upper surface of the cover layer 38.

[0173] exist Figure 18 The diagram shows that the optical structure 30 is molded together with the high-bandwidth memory 20 into the first molding member 190 in one step, without molding the optical structure 30 separately, but the embodiment is not limited to this. For example, after the optical structure 30 is first molded, the optical structure 30 can be molded again together with the high-bandwidth memory 20. Furthermore, depending on the manner in which the optical structure 30 is bonded to the base insulating layer 120 and the fourth connection pad 128, molding can be performed after the underside of the optical structure 30 is filled.

[0174] Reference Figure 19 Remove the carrier substrate CR, and form a plurality of second connection pads 122 and a plurality of first connection members 121 on the lower surface of the base insulating layer 120 and the lower surface of the logic die 10. Then the first connection members 121 can be bonded to the substrate 110.

[0175] Next, the optical connector 40 can be optically connected to the optical structure 30. A frame covering the semiconductor package 100 may be included. The optical connector 40 can be connected through holes provided in the frame covering the semiconductor package 100. For example, the optical connector 40 and the holes can be connected to each other in a male-female configuration.

[0176] An optical connector 40 may be positioned on the upper surface of the cover layer 38. The optical connector 40 may include an optical fiber 42. The optical connector 40 may be positioned such that the end portion of the optical fiber 42 faces the upper surface of the cover layer 38. The end portion of the optical fiber 42 may be spaced apart from the upper surface of the cover layer 38. An air gap may be positioned between the end portion of the optical fiber 42 and the upper surface of the cover layer 38.

[0177] exist Figure 19In the illustration, optical signals are shown to be transmitted and received vertically through the upper surface of the photonic integrated circuit 32, but the embodiment is not limited to this. For example, the optical connector 40 may be connected to the side surface of the semiconductor package 100, so that optical signals can be transmitted and received horizontally through the side surface or edge of the photonic integrated circuit 32. In this case, the photonic integrated circuit 32 may include an edge connector instead of the grating connector 455 described above.

[0178] In one or more embodiments, the semiconductor package 100 may include a plurality of optical structures 30, and therefore may include a plurality of optical connectors 40 optically connected to each of the optical structures 30. The optical connectors 40 may be respectively connected between the optical structure 30 and an external device. A first end of the optical fiber 42 of each of the optical connectors 40 may be optically connected to each of the optical structures 30, and a second end of the optical fiber 42 of each of the optical connectors 40 may be optically connected to an external device.

[0179] pass Figures 13 to 19 The manufacturing process can form a semiconductor package 100 that can improve the optical communication speed with external devices and reduce signal loss.

[0180] According to one or more embodiments, the communication speed of a semiconductor package that communicates with external devices using optical signals can be improved, and signal loss can be reduced.

[0181] According to one or more embodiments, the size of a semiconductor package can be reduced.

[0182] For example, in semiconductor packaging, in a vertically stacked structure of HBM and logic dies, photonic modules can be arranged parallel to the HBM and perpendicular to the logic dies. By vertically connecting photonic devices (e.g., optical modules) and logic dies, the signal transmission path is shortened, thereby increasing communication speed and minimizing signal loss. Furthermore, vertically arranging the logic dies and photonic modules allows for a reduction in package size.

[0183] It is not excluded that each embodiment provided in the above description is associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure.

[0184] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0185] Cross-references to related applications

[0186] This application is based on and claims priority to Korean Patent Application No. 10-2024-0134064, filed on October 2, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising: substrate; Logic dies are located on the substrate. A basic insulating layer is present on the side and top surfaces of the logic die; An insulating layer extends through the underlying insulating layer on one side of the logic die; High-bandwidth memory, on the upper surface of the basic insulating layer; At least one optical structure is located on the upper surface of the base insulating layer; as well as At least one optical connector, including an optical fiber configured to transmit optical signals between the at least one optical structure and an external device. The high-bandwidth memory comprises a plurality of memory dies stacked in a first direction perpendicular to the upper surface of the base insulating layer, and The at least one optical structure thereon is connected to the logic die in the first direction.

2. The semiconductor package of claim 1, wherein the at least one optical structure overlaps with the through-path of the logic die and the insulating layer in the first direction.

3. The semiconductor package according to claim 1, wherein, The at least one optical structure includes: Photonic integrated circuit, on the upper surface of the basic insulating layer, and An electronic integrated circuit, on at least a portion of the upper surface of the photonic integrated circuit.

4. The semiconductor package according to claim 3, wherein, The at least one optical structure further includes a covering layer covering the upper surface of the photonic integrated circuit and the upper surface of the electronic integrated circuit, and The covering layer includes a light-transmitting material.

5. The semiconductor package of claim 4, wherein the at least one optical connector is located on the upper surface of the cover layer, and The overlay is located between the end portion of the optical fiber and the upper surface of the photonic integrated circuit.

6. The semiconductor package of claim 5, wherein the photonic integrated circuit includes a grating connector optically connected to the optical fiber.

7. The semiconductor package of claim 4, wherein the at least one optical structure comprises a light-transmitting insulating layer between the cover layer and the photonic integrated circuit and on a side surface of the electronic integrated circuit.

8. The semiconductor package of claim 1, further comprising a plurality of first connection pads and a plurality of second connection pads on the upper surface of the logic die. The plurality of first connection pads are connected to the at least one optical structure, and the plurality of second connection pads are connected to the high-bandwidth memory.

9. The semiconductor package according to claim 1, wherein, The at least one optical structure includes a plurality of optical structures on the upper surface of the base insulating layer; The at least one optical connector includes multiple optical connectors respectively connected between the plurality of optical structures and the external device. The plurality of optical structures are arranged in a second direction parallel to the upper surface of the base insulating layer.

10. The semiconductor package according to claim 1, further comprising: A thermal pad is connected in the first direction to the through-path of the insulating layer and the logic die; as well as The heat-conducting block on the heat-conducting pad.

11. The semiconductor package according to claim 1, wherein, The at least one optical structure includes: Optoelectronic integrated circuits, on the upper surface of the basic insulating layer, A cover layer covering the upper surface of the optoelectronic integrated circuit, and A light-transmitting insulating layer is located between the optoelectronic integrated circuit and the cover layer. The covering layer and the light-transmitting insulating layer comprise light-transmitting materials.

12. The semiconductor package of claim 1, wherein the high-bandwidth memory further comprises a base die beneath the plurality of memory dies, and The base die mentioned above includes a field-programmable gate array (FPGA) die.

13. The semiconductor package of claim 1, wherein the high-bandwidth memory further comprises a base die beneath the plurality of memory dies, and The base die includes a cache memory die, which has a faster data access speed than the plurality of memory dies.

14. The semiconductor package of claim 1, further comprising a first molding member covering the side surface of the at least one optical structure and the upper and side surfaces of the high-bandwidth memory.

15. The semiconductor package of claim 14, further comprising a second molding member between the side surface of the at least one optical structure and the first molding member.

16. The semiconductor package of claim 14, further comprising a bottom filler between the lower surface of the at least one optical structure and the upper surface of the base insulating layer.

17. A semiconductor package, comprising: substrate; Logic dies are located on the substrate. A basic insulating layer is present on the side and top surfaces of the logic die; An insulating layer extends through the underlying insulating layer on one side of the logic die; High-bandwidth memory, on the upper surface of the basic insulating layer; An optical structure on the upper surface of the basic insulating layer; as well as An optical connector, including an optical fiber configured to transmit optical signals between the optical structure and an external device. The high-bandwidth memory comprises a plurality of memory dies stacked in a first direction perpendicular to the upper surface of the base insulating layer. In the plan view, the optical structure overlaps with at least a portion of the logic die, and The optical structure is connected to the logic die in the first direction.

18. A semiconductor package, comprising: substrate; and Multiple small chips on the substrate, Each of the plurality of small chips includes: Logic dies are located on the substrate. A basic insulating layer is present on the side and top surfaces of the logic die; An insulating layer extends through the underlying insulating layer on one side of the logic die; High-bandwidth memory, on the upper surface of the basic insulating layer; Optical structure, on the upper surface of the basic insulating layer; and An optical connector, including an optical fiber configured to transmit optical signals between the optical structure and an external device. The high-bandwidth memory comprises a plurality of memory dies stacked in a first direction perpendicular to the upper surface of the base insulating layer, and The optical structure is connected to the logic die in the first direction.

19. The semiconductor package of claim 18, further comprising a bridging layer in the upper portion of the substrate. The multiple small chips are connected together through the bridging layer.

20. The semiconductor package of claim 18, further comprising a redistribution layer between the substrate and the logic die of each of the plurality of chiplets. The multiple small chips are connected together through the redistribution layer.

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