Longitudinal diode based on homomorphic change k dielectric terminal and preparation method thereof

Abstract

The invention provides a longitudinal diode based on a homomorphic change k medium terminal and a preparation method thereof, the longitudinal diode comprises a substrate and two first terminal structures, an epitaxial layer is arranged above the substrate, and a cathode is arranged at the bottom of the substrate; an anode is arranged above the epitaxial layer; the two first terminal structures are arranged on the epitaxial layer at intervals, and the two first terminal structures correspond to the two end parts of the anode up and down and are partially overlapped with the two end parts of the anode; each first terminal structure comprises at least two dielectric layers, each dielectric layer in each first terminal structure is prepared based on a dielectric material of the same element, and the relative dielectric constant of each dielectric layer is gradually increased from bottom to top. The longitudinal diode based on the homomorphic change k dielectric terminal provided by the invention can accurately act on an electric field concentration region, widen the width of a depletion region, reduce the peak value of the electric field and improve the withstand voltage limit of a device; and the interface state problem can be eliminated, the electric field regulation and control effect can be better played, and the stable improvement of the voltage-resistant performance of the device is ensured.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a vertical diode based on a homogeneous k-dielectric terminal and its fabrication method. Background Technology

[0002] As an important type of electronic component in the field of semiconductor devices, vertical diodes are widely used in many key fields such as power electronics, communication equipment, and energy conversion due to their significant advantages in current carrying capacity, switching speed and integration compatibility.

[0003] Due to the inherent structural characteristics of vertical diodes, electric field concentration is prone to occur in the anode edge region. Excessive local electric field can cause premature breakdown of the device, significantly reducing the device's withstand voltage limit. It can also induce the Schottky barrier reduction effect, increasing leakage current and seriously affecting the device's operational stability and lifespan.

[0004] To address the aforementioned electric field concentration problem, existing technologies typically employ techniques such as field limiting rings, junction termination extension, or oxide passivation. While these technologies alleviate the electric field concentration problem to some extent, they all have their own limitations. They may involve complex fabrication processes, have limited electric field control effects, or introduce new performance defects, making it difficult to reliably improve the voltage withstand performance of devices. Summary of the Invention

[0005] The vertical diode based on homogeneous variable k dielectric terminals and its fabrication method provided in this invention can form homogeneous variable k dielectric terminals by using dielectric layers with the same elemental dielectric material, thereby optimizing the electric field distribution around the anode and improving the device's withstand voltage performance more stably and reliably.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: Firstly, a vertical diode based on a homogeneous k-dielectric terminal is provided, comprising: A substrate, on which an epitaxial layer is disposed, and a cathode is disposed at the bottom of the substrate; an anode is disposed above the epitaxial layer; and Two first terminal structures are disposed at intervals on the epitaxial layer, and the two first terminal structures are respectively vertically corresponding to the two ends of the anode and partially overlapping each other. Each of the first terminal structures includes at least two dielectric layers arranged in a vertical direction. In each of the first terminal structures, each dielectric layer is made of a dielectric material of the same element, and the relative permittivity of each dielectric layer increases sequentially from bottom to top.

[0007] The beneficial effects of the vertical diode based on homogeneous variable k dielectric terminals provided by this invention are as follows: Compared with the prior art, by making the two first terminal structures correspond vertically and partially overlap with the two ends of the anode, it can accurately act on the key areas of electric field concentration located at both ends of the anode; by setting at least two dielectric layers with increasing relative permittivity from bottom to top in each first terminal structure, a continuous "variable k" electric field modulation gradient can be formed, and by utilizing the modulation effect of dielectrics with different relative permittivity on the electric field, the depletion region width can be effectively widened, the local excessively high electric field intensity can be dispersed, the device can be prevented from premature breakdown due to electric field concentration, and the withstand voltage limit of the device can be greatly improved.

[0008] Meanwhile, by limiting each dielectric layer to be made of dielectric material of the same element, a "homogeneous variable k" dielectric terminal structure is formed, which can eliminate the abrupt interface between heterogeneous materials with different relative permittivity, thereby eliminating interface state problems caused by lattice mismatch, chemical bond interruption, etc., so that the variable k dielectric terminal structure can better play the role of electric field regulation and ensure the stable improvement of the device's withstand voltage performance.

[0009] In conjunction with the first aspect, in one possible implementation, the upper surface of the epitaxial layer is provided with two upward-facing first grooves, and at least two dielectric layers are sequentially filled in the first grooves, with the upper surface of the uppermost dielectric layer being flush with the upper surface of the epitaxial layer.

[0010] In some embodiments, the upper surface of the epitaxial layer is further provided with at least one upward-facing second groove, the second groove being located below the anode, and at least two dielectric layers are sequentially filled in the second groove from bottom to top to form a second terminal structure.

[0011] In conjunction with the first aspect, in one possible implementation, the dielectric material used for each of the dielectric layers is one of titanium oxide, ferrous titanate, or hafnium dioxide.

[0012] In conjunction with the first aspect, in one possible implementation, the relative permittivity of the uppermost dielectric layer is not less than 30.

[0013] In some embodiments, the difference between the relative permittivity of the uppermost dielectric layer and the relative permittivity of the lowermost dielectric layer is not less than 25.

[0014] Secondly, embodiments of the present invention also provide a method for fabricating a vertical diode based on a homogeneous k-dielectric terminal, comprising the following steps: S1. Growing an epitaxial layer on a substrate; S2. Prepare a cathode at the bottom of the substrate; S3. On the epitaxial layer, at least two dielectric layers are prepared sequentially from bottom to top in two groups to form two first terminal structures. Each dielectric layer uses a dielectric material of the same element, and the growth temperature and oxygen supply of each dielectric layer in each first terminal structure gradually increase from bottom to top so that the relative permittivity of each dielectric layer increases sequentially from bottom to top. S4. An anode is fabricated above the two first terminal structures and the epitaxial layer, such that the two ends of the anode partially overlap the two first terminal structures respectively.

[0015] The beneficial effects of the fabrication method for vertical diodes based on homogeneous k-dielectric terminals provided by this invention are as follows: Compared with existing technologies, by using a gradient control method for growth temperature and oxygen supply, the incremental design of the relative permittivity of each dielectric layer can be precisely achieved. This ensures that the first terminal structure forms an effective electric field control gradient, efficiently disperses the concentrated electric field at the anode end, widens the depletion region, suppresses leakage current, and thus improves the device's withstand voltage performance. Furthermore, this process eliminates the need to introduce heterogeneous dielectric materials, simplifying the fabrication process, reducing complexity and cost, and fundamentally reducing defects caused by heterogeneous interfaces. This ensures the compatibility and stability of the dielectric layer interfaces, guaranteeing a stable and reliable improvement in the device's withstand voltage performance.

[0016] In conjunction with the second aspect, in one possible implementation, before preparing the two sets of dielectric layers in step S3, the method further includes: preparing a mask layer pattern on the upper surface of the epitaxial layer, dry etching to form two first grooves, and preparing at least two dielectric layers from bottom to top in the two first grooves respectively.

[0017] In some embodiments, the mask layer is any one of photoresist, metal, or dielectric material.

[0018] In conjunction with the second aspect, in one possible implementation, the growth temperature of the lowest dielectric layer is 15℃-25℃; the growth temperature of the highest dielectric layer is 150℃-300℃. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a vertical diode based on a homogeneous k-dielectric terminal provided in an embodiment of the present invention; Figure 2A schematic diagram of another embodiment of a vertical diode based on a homogeneous k-dielectric terminal provided in this invention; Figure 3 This is a schematic diagram of another embodiment of a vertical diode based on a homogeneous k-dielectric terminal provided by an embodiment of the present invention.

[0020] The following are the labeling elements in the figure: 1. Substrate; 2. Epitaxial layer; 21. First groove; 22. Second groove; 3. Cathode; 4. Anode; 5. First termination structure; 51. Dielectric layer; 511. First dielectric layer; 512. Second dielectric layer; 513. Third dielectric layer; 6. Second termination structure. Detailed Implementation

[0021] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0022] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or indirectly on the other element. It should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0023] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0024] Please refer to the following: Figures 1 to 3The present invention will now describe the vertical diode based on homogeneous k-dielectric terminals and its fabrication method. The vertical diode based on homogeneous k-dielectric terminals includes a substrate 1 and two first terminal structures 5. An epitaxial layer 2 is disposed above the substrate 1, and a cathode 3 is disposed at the bottom of the substrate 1. An anode 4 is disposed above the epitaxial layer 2. The two first terminal structures 5 are spaced apart on the epitaxial layer 2, and the two first terminal structures 5 correspond vertically to and partially overlap with the two ends of the anode 4. Each first terminal structure 5 includes at least two dielectric layers 51 arranged vertically. In each first terminal structure 5, each dielectric layer 51 is fabricated based on a dielectric material of the same element, and the relative permittivity of each dielectric layer 51 increases sequentially from bottom to top.

[0025] The vertical diode based on homogeneous variable-k dielectric terminals provided in this embodiment, compared with the prior art, can precisely act on the key areas of electric field concentration located at both ends of the anode 4 by making the two first terminal structures 5 correspond vertically and partially overlap with the two ends of the anode 4; by setting at least two dielectric layers 51 with the relative permittivity (k) increasing sequentially from bottom to top in each first terminal structure 5, a continuous "variable-k" electric field modulation gradient can be formed, and by utilizing the modulation effect of dielectrics with different relative permittivity on the electric field, the depletion region width can be effectively widened, the local excessively high electric field intensity can be dispersed, the device can be prevented from premature breakdown due to electric field concentration, and the withstand voltage limit of the device can be greatly improved.

[0026] Meanwhile, by limiting each dielectric layer 51 to be made of dielectric material of the same element, a "homogeneous variable k" dielectric terminal structure is formed, which can eliminate the abrupt interface between heterogeneous materials with different relative permittivity, thereby eliminating interface state problems caused by lattice mismatch, chemical bond interruption, etc., so that the variable k dielectric terminal structure can better play the role of electric field regulation and ensure the stable improvement of the device's withstand voltage performance.

[0027] It should be noted that in existing technologies, when two dielectric layers 51 with different relative permittivity are required, heterogeneous dielectric structures with different material combinations are typically used, such as low-k SiO2 and high-k HfO2, Al2O3, etc. During the fabrication of heterogeneous dielectrics, the interface is prone to forming a large number of interface state problems due to factors such as lattice mismatch, element diffusion, and surface defects, thereby introducing new performance defects and affecting the operational stability of the device. In this embodiment, however, each dielectric layer 51 uses a dielectric material of the same element. In the actual fabrication process, the relative permittivity can be differentiated by controlling the growth temperature and oxygen atmosphere, thereby eliminating the interface state problems between different dielectric materials and stabilizing the device's withstand voltage performance.

[0028] Understandably, growth temperature and oxygen atmosphere only alter the internal crystal morphology and stoichiometry (such as oxygen content) of the material, without introducing new elements or heterogeneous lattices. Therefore, they can achieve differences in relative permittivity while eliminating interface states at their source. Specifically, the relative permittivity of a medium of the same element is determined by its internal polarization capability, which is directly related to crystal structure and oxygen content: higher growth temperatures promote ordered atomic arrangement, forming a crystalline structure with high polarization efficiency and a larger relative permittivity. In an oxygen atmosphere, oxygen atoms are saturated, the lattice is complete, and the polarization capability is strong, resulting in a corresponding increase in the relative permittivity. When the oxygen supply is low, oxygen-deficient oxides are easily formed, oxygen vacancies increase, and lattice defects disrupt polarization continuity, leading to a corresponding decrease in the relative permittivity.

[0029] In this embodiment, the two first terminal structures 5 correspond vertically to and partially overlap with the two ends of the anode 4. "Vertical correspondence" ensures that the first terminal structure 5 precisely corresponds to the region with the strongest electric field at both ends of the anode 4. "Partial overlap" means that on the transverse reference plane, the projection of the end face of the anode 4 falls within the projection of the corresponding first terminal structure 5; that is, the first terminal structure 5 extends both below the metal of the anode 4 and to the outside of the anode 4. This simultaneously optimizes the electric field below and on the outside of the edge of the anode 4, improving the effect of electric field control.

[0030] In addition, the high-k dielectric can attract and concentrate the electric field lines, while the low-k dielectric causes them to diverge. The design of the relative permittivity of each dielectric layer 51 in each first terminal structure 5 increasing from bottom to top can guide the electric field lines to transition smoothly from the edge of the anode 4 to the interior of the epitaxial layer 2, effectively alleviating the problem of electric field spikes at the metal edge of the anode 4 in the traditional structure.

[0031] Specifically, in this embodiment, substrate 1 is a heavily doped n+ substrate; epitaxial layer 2 is a lightly doped n- epitaxial layer 2 grown on substrate 1 using vapor phase epitaxy. Together, they form the basic framework of the vertical diode, determining the device's breakdown voltage and forward conduction resistance. Cathode 3 is one or more layers of metal, such as Ti / Ni / Ag, formed on the back side (bottom surface) of substrate 1 by electron beam evaporation or magnetron sputtering, followed by rapid thermal annealing to form an ohmic contact. Anode 4 is fabricated on the front side (top surface) of epitaxial layer 2 and can be either Schottky metal or a PN junction anode, forming the electrical connection between the device and external circuitry.

[0032] In some embodiments, see Figure 1 The upper surface of the epitaxial layer 2 is provided with two upward-facing first grooves 21. At least two dielectric layers 51 are sequentially filled in the first grooves 21. The upper surface of the uppermost dielectric layer 51 is flush with the upper surface of the epitaxial layer 2.

[0033] Two first grooves 21 can be formed on the upper surface of the epitaxial layer 2 by photolithography and dry etching processes. The width of the first groove 21 needs to be precisely matched with the partial overlap requirement of the end face of the anode 4 to ensure effective coverage of the edge area of ​​the anode 4. The depth of the first groove 21 needs to balance the electric field modulation depth and the structural integrity of the epitaxial layer 2 to ensure that the dielectric layer 51 filled inside can act on the electric field concentration area in the epitaxial layer 2, while avoiding penetration of the epitaxial layer 2 and damage to the structural integrity.

[0034] The flush design of the uppermost dielectric layer 51 and the upper surface of the epitaxial layer 2 provides a flat surface for subsequent metal deposition of the anode 4. On the one hand, this avoids poor contact of the anode 4 electrode caused by the protrusion of the dielectric layer 51, improving process yield and device reliability. On the other hand, the first groove 21 allows each dielectric layer 51 to be completely embedded inside the epitaxial layer 2, which can reshape the shape of the depletion region, thereby efficiently reducing the peak electric field below the anode 4 and further improving the ability to control the electric field.

[0035] In some embodiments, see Figure 2 or Figure 3 The upper surface of the epitaxial layer 2 is also provided with at least one second groove 22 with an upward opening. The second groove 22 is located below the anode 4. At least two dielectric layers 51 are sequentially filled in the second groove 22 from bottom to top to form the second terminal structure 6.

[0036] At least one upward-facing second groove 22 is added to the upper surface of the epitaxial layer 2 directly below the anode 4. The position of the second groove 22 precisely corresponds to the electric field concentration area directly below the anode 4. The second groove 22 is filled with at least two homogeneous (same element) dielectric layers 51 from bottom to top, and follows the rule that the relative permittivity increases sequentially from bottom to top, which is consistent with the design concept of the dielectric layer 51 of the first terminal structure 5.

[0037] The second groove 22 adopts the same fabrication process as the first groove 21, such as photolithography and dry etching, and can be fabricated simultaneously with the first groove 21. Within the second groove 22, dielectric layers 51 are sequentially fabricated from bottom to top to form the second terminal structure 6, ensuring that the total thickness of each dielectric layer 51 matches the depth of the second groove 22, i.e., the upper surface of the uppermost dielectric layer 51 is flush with the upper surface of the epitaxial layer 2.

[0038] The relative permittivity gradient of the dielectric layer 51 in the second groove 22 is consistent with the relative permittivity gradient of the dielectric layer 51 in the first groove 21, that is, the dielectric layer 51 in the second groove 22 and the dielectric layer 51 that are laterally opposite in the second groove 22 can be prepared synchronously under the same process conditions.

[0039] The second terminal structure 6 in this embodiment can specifically address the problem of electric field concentration directly below the anode 4. By widening the depletion region width through the dielectric layer 51 with a relative permittivity gradient within the second groove 22, it reduces the local electric field intensity directly below the anode 4, avoids the Schottky barrier reduction effect, and further reduces leakage current. Simultaneously, it forms a device-wide electric field control system with the first terminal structure 5 at the edge of the anode 4, comprehensively dispersing the electric field peaks in key areas of the device, resulting in a more significant improvement in the device's withstand voltage.

[0040] Specifically, when one second groove 22 is provided, its width must effectively cover the area directly below the anode 4, and the second groove 22 is spaced between two first grooves 21 to ensure the contact area between the anode 4 and the epitaxial layer 2. Optionally, the vertical centerline of one second groove 22 coincides with the vertical centerline of the anode 4. When two or more second grooves 22 are provided, the width of each second groove 22 can be reduced accordingly and evenly distributed between two first grooves 21.

[0041] In some embodiments, the dielectric material used for each dielectric layer 51 is one of titanium oxide (TiO2), ferrous titanate (FeTiO3), or hafnium dioxide (HfO2). All of these materials can be prepared by various methods such as sputtering, atomic layer deposition (ALD), and pulsed laser deposition (PLD), and their k-values ​​are sensitive to process parameters (such as oxygen atmosphere and growth temperature), making it easy to achieve differences in k-values ​​among the dielectric layers 51 through parameter control.

[0042] In some embodiments, the relative permittivity of the uppermost dielectric layer 51 is not less than 30. According to electrostatic field theory, the higher the relative permittivity, the stronger its polarization capability, and the higher the energy density stored internally under the same voltage. Limiting the k-value of the uppermost dielectric layer 51 to a high level greater than or equal to 30 ensures that the uppermost dielectric layer 51 has a strong ability to attract and accommodate electric field lines, which can efficiently "flatten" or "absorb" the sharp electric field peaks at the edge of the anode 4, significantly alleviating the electric field concentration of the anode 4. In addition, the high k-value design of the uppermost dielectric layer 51 creates conditions for the k-value difference between each dielectric layer 51.

[0043] In some embodiments, the difference between the relative permittivity of the uppermost dielectric layer 51 and the relative permittivity of the lowermost dielectric layer 51 is not less than 25. Based on the premise that the k-value of the uppermost dielectric layer 51 is greater than or equal to 30, the difference in k-value between the uppermost and lowermost dielectric layers 51 should be increased as much as possible to form an effective relative permittivity gradient between the dielectric layers 51.

[0044] For example, when both the first terminal structure 5 and the second terminal structure 6 have only two dielectric layers 51, please refer to [reference needed]. Figure 2The dielectric layers are named first dielectric layer 511 and second dielectric layer 512 from bottom to top. First dielectric layer 511, as the bottom dielectric layer 51, has a k-value of 6, and second dielectric layer 512, as the top dielectric layer 51, has a k-value of 32, with a difference of 26 between them. Alternatively, first dielectric layer 511 may have a k-value of 10, and second dielectric layer 512 may have a k-value of 35, with a difference of 25 between them. Maximizing the difference in k-values ​​between first dielectric layer 511 and second dielectric layer 512 ensures that a sufficiently high new electric field peak is induced at their interface. This actively attracts the electric field stress from the edge and directly below the anode 4 to the interface of dielectric layer 51, thereby better optimizing the electric field distribution and improving the device's withstand voltage performance.

[0045] When both the first terminal structure 5 and the second terminal structure 6 include three dielectric layers 51, please refer to [link / reference]. Figure 3 The dielectric layers are named sequentially from bottom to top: first dielectric layer 511, second dielectric layer 512, and third dielectric layer 513. First dielectric layer 511, as the bottommost dielectric layer 51, has a k-value of 6; second dielectric layer 512, as the middle layer, has a k-value of 15; and third dielectric layer 513, as the topmost dielectric layer 51, has a k-value of 32. Alternatively, the k-value of first dielectric layer 511 could be 10, the k-value of second dielectric layer 512 could be 23, and the k-value of third dielectric layer 513 could be 35. The sequentially increasing k-values ​​of the multiple dielectric layers 51 form a gentle step change, reducing sensitivity to defects at the interface. This helps reduce the impact of process fluctuations on device performance and improves device yield and stability.

[0046] Based on the same inventive concept, this application also provides a method for fabricating a vertical diode based on a homogeneous k-dielectric terminal, comprising the following steps: S1. An epitaxial layer 2 is grown on substrate 1; Heavily doped n+ type silicon, silicon carbide, or other semiconductor materials are selected as substrate 1. A lightly doped n- type epitaxial layer 2 (i.e., the drift region) is grown on substrate 1 using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). Substrate 1 and epitaxial layer 2 constitute the basic structure of the vertical diode, forming the path for vertical current flow and the main region that withstands reverse voltage.

[0047] S2. Prepare a cathode 3 at the bottom of substrate 1; After cleaning and activating the back side of substrate 1, one or more layers of metal, such as Ti / Ni / Ag stack, are evaporated by electron beam. Then, rapid thermal annealing is performed to alloy the metal with the heavily doped substrate 1 to form an ohmic contact cathode 3, ensuring that current can be injected or drawn out with extremely low contact resistance.

[0048] S3. On the epitaxial layer 2, at least two dielectric layers 51 are prepared sequentially from bottom to top in two groups to form two first terminal structures 5. Each dielectric layer 51 uses a dielectric material of the same element, and the growth temperature and oxygen supply of each dielectric layer 51 in each first terminal structure 5 gradually increase from bottom to top so that the relative permittivity of each dielectric layer 51 increases sequentially from bottom to top. Using photolithography, two rectangular regions are defined on the front side of the epitaxial layer 2, corresponding to the two long edges of the subsequently defined anode 4. Within each region, physical vapor deposition (such as reactive sputtering) is used to deposit material of the same element (such as titanium) in stages to obtain a first terminal structure 5 comprising at least two dielectric layers 51.

[0049] Specifically, the bottom layer is sputtered at a relatively low temperature (e.g., room temperature) and under oxygen-free (inert gas atmosphere) or low-oxygen conditions. The dielectric formed under these conditions is typically amorphous and rich in oxygen vacancies, resulting in a relatively low dielectric constant. Subsequently, the heating temperature and oxygen supply of the substrate 1 are progressively increased to gradually form the intermediate dielectric layer 51. Finally, the top layer is sputtered at a higher temperature (e.g., 250°C) and under oxygen-rich conditions. The dielectric formed under these conditions is more dense, thus significantly increasing the relative dielectric constant.

[0050] Through this gradual control of process parameters, in-situ stacks of dielectric layers 51 based on the same elements but with longitudinally gradient relative permittivity are formed within each region of the first terminal structure 5. This achieves "homogeneous transformation of k," ensuring the elemental consistency of each dielectric layer 51 from the material source and fundamentally eliminating heterogeneous interfaces and the interface state problems they bring.

[0051] S4. An anode 4 is prepared above the two first terminal structures 5 and the epitaxial layer 2, such that the two ends of the anode 4 partially overlap with the two first terminal structures 5 respectively.

[0052] The anode 4 pattern is defined by photolithography, and the long edge of this pattern should partially cover the pre-fabricated first terminal structure 5. Next, the anode 4 metal is deposited. For Schottky diodes, Pt / Ti is commonly used; for junction diodes, P+ ion implantation and annealing are required before Al deposition, and the final anode 4 electrode is formed by stripping or etching.

[0053] This step requires ensuring a “partially overlapping” layout so that the first terminal structure 5 can simultaneously be electrically coupled to the epitaxial layer 2 region below and outside the anode 4 metal, thereby achieving effective control of the peak electric field at the edge of the anode 4.

[0054] The method for fabricating a vertical diode based on a homogeneous k-dielectric terminal provided in this embodiment, compared with existing technologies, can precisely achieve the incremental design of the relative permittivity of each dielectric layer 51 through gradient control of growth temperature and oxygen supply. This ensures that the first terminal structure 5 forms an effective electric field control gradient, efficiently disperses the concentrated electric field at the anode end 4, widens the depletion region, suppresses leakage current, and thus improves the device's withstand voltage performance. Furthermore, this process eliminates the need to introduce heterogeneous dielectric materials, simplifying the fabrication process, reducing complexity and cost, and fundamentally reducing defects caused by heterogeneous interfaces. This ensures the interfacial compatibility and stability between the dielectric layers 51, guaranteeing a stable and reliable improvement in the device's withstand voltage performance.

[0055] In some embodiments, before preparing the two sets of dielectric layers 51 in step S3, the method further includes: preparing a mask layer pattern on the upper surface of the epitaxial layer 2, forming two first grooves 21 by dry etching, and preparing at least two dielectric layers 51 from bottom to top in the two first grooves 21 respectively.

[0056] The first groove 21 allows each dielectric layer 51 of the first terminal structure 5 to be embedded inside the epitaxial layer 2 (semiconductor drift region). The dielectric layer 51 forms a large-area, three-dimensional electrical coupling with the semiconductor through the sidewalls and bottom wall of the first groove 21. This embedded structure can actively and deeply reshape the electric field line distribution in the semiconductor, effectively attracting the peak electric field below the edge of the anode 4 to the dielectric layer 51 or making it spread out gently, thus more efficiently improving the bulk breakdown voltage of the device.

[0057] The depth of the first groove 21 needs to be matched with the thickness of each dielectric layer 51. After the dielectric layer 51 is prepared in the first groove 21, the surface of the uppermost dielectric layer 51 needs to be flush with the upper surface of the epitaxial layer 2 in order to obtain a flat surface of the epitaxial layer 2, which provides a reliable foundation for the subsequent preparation of the anode 4.

[0058] When the longitudinal diode also includes a second terminal structure 6, that is, when the epitaxial layer 2 is also provided with a second groove 22, the second groove 22 and the first groove 21 are obtained simultaneously by dry etching, and each dielectric layer 51 is prepared simultaneously in the first groove 21 and the second groove 22 to simplify the process flow.

[0059] In some embodiments, the mask layer is any one of photoresist, metal, or dielectric material.

[0060] Using a photoresist layer formed by spin coating, exposure, and development as a mask is the simplest and lowest-cost process. After dry etching to form the first groove 21, the photoresist mask can be directly removed by organic solvent stripping or oxygen plasma ashing. Using a metal layer (such as Al, Ti, or Cr) deposited and patterned by sputtering or evaporation as a mask offers higher etching selectivity and pattern fidelity. After etching, it needs to be removed by specific wet or dry metal etching processes. Using a dielectric layer 51 (such as SiO2 or Si3N4) patterned by chemical vapor deposition as a mask also offers high etching selectivity and good thermal and chemical stability. It can be retained in subsequent high-temperature process steps as part of the integrated device.

[0061] In some embodiments, the growth temperature of the bottommost dielectric layer 51 is 15°C-25°C; the growth temperature of the topmost dielectric layer 51 is 150°C-300°C.

[0062] In embodiments where both the first terminal structure 5 and the second terminal structure 6 include two dielectric layers 51, the first dielectric layer 511, as the bottom layer, can be prepared at room temperature (15℃-25℃) without introducing oxygen, while the second dielectric layer 512, as the top layer, is prepared at high temperature (150℃-300℃) in an oxygen-containing atmosphere. This maximizes the difference in relative permittivity between the two dielectric layers 51, thereby helping to improve the electric field control capability.

[0063] A room temperature of 15℃-25℃ is conducive to maintaining the amorphous and oxygen-deficient state of the film layer, ensuring the acquisition of a low-k dielectric layer 51; while 150℃-300℃ provides sufficient atomic mobility to grow high-quality films, forming a precise temperature environment for the high-k dielectric layer 51, and this temperature range will not cause additional damage to the electrodes and epitaxial layer 2.

[0064] In embodiments where both the first terminal structure 5 and the second terminal structure 6 include three dielectric layers 51, oxygen can be introduced during the preparation of the second dielectric layer 512, and its growth temperature is between that of the first dielectric layer 511 and the third dielectric layer 513. For example, during the preparation of the first dielectric layer 511, the growth temperature can be controlled at 15°C-20°C, and no oxygen is introduced; during the preparation of the second dielectric layer 512, the growth temperature is increased to 50°C-55°C, and oxygen is initially introduced at a flow rate of 20 sccm; during the preparation of the third dielectric layer 513, the growth temperature can be further increased to 150°C-300°C, and the oxygen flow rate can be adjusted to 50 sccm.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A longitudinal diode based on a homogeneous k-dielectric terminal, characterized in that, include: A substrate (1) has an epitaxial layer (2) on top of it, and a cathode (3) is provided at the bottom of the substrate (1); an anode (4) is provided above the epitaxial layer (2); and Two first terminal structures (5) are spaced apart on the epitaxial layer (2), and the two first terminal structures (5) correspond vertically to the two ends of the anode (4) and partially overlap. Each of the first terminal structures (5) includes at least two dielectric layers (51) arranged in the vertical direction. In each of the first terminal structures (5), each dielectric layer (51) is made of dielectric material of the same element, and the relative permittivity of each dielectric layer (51) increases sequentially from bottom to top.

2. The vertical diode based on homogeneous k-dielectric termination as described in claim 1, characterized in that, The upper surface of the epitaxial layer (2) is provided with two upward-facing first grooves (21), and at least two dielectric layers (51) are sequentially filled in the first grooves (21). The upper surface of the uppermost dielectric layer (51) is flush with the upper surface of the epitaxial layer (2).

3. The vertical diode based on a homogeneous k-dielectric terminal as described in claim 2, characterized in that, The upper surface of the epitaxial layer (2) is also provided with at least one second groove (22) with an upward opening. The second groove (22) is located below the anode (4). The second groove (22) is filled with at least two dielectric layers (51) from bottom to top to form a second terminal structure (6).

4. The vertical diode based on homogeneous k-dielectric termination as described in claim 1, characterized in that, The dielectric material used in each of the dielectric layers (51) is one of titanium oxide, ferrous titanate, or hafnium dioxide.

5. The vertical diode based on homogeneous k-dielectric termination as described in claim 1, characterized in that, The relative permittivity of the uppermost dielectric layer (51) is not less than 30.

6. The vertical diode based on homogeneous k-dielectric termination as described in claim 5, characterized in that, The difference between the relative permittivity of the uppermost dielectric layer (51) and the relative permittivity of the lowermost dielectric layer (51) is not less than 25.

7. A method for fabricating a vertical diode based on a homogeneous k-dielectric terminal, characterized in that, Includes the following steps: S1. An epitaxial layer (2) is grown on a substrate (1); S2. A cathode (3) is prepared at the bottom of the substrate (1); S3. On the epitaxial layer (2), at least two dielectric layers (51) are prepared sequentially from bottom to top in two groups to form two first terminal structures (5). Each dielectric layer (51) uses a dielectric material of the same element, and the growth temperature and oxygen supply of each dielectric layer (51) in each first terminal structure (5) gradually increase from bottom to top so that the relative permittivity of each dielectric layer (51) increases sequentially from bottom to top. S4. An anode (4) is prepared above the two first terminal structures (5) and the epitaxial layer (2), such that the two ends of the anode (4) partially overlap the two first terminal structures (5).

8. The method for fabricating a vertical diode based on a homogeneous k-dielectric terminal as described in claim 7, characterized in that, In step S3, before preparing the two sets of dielectric layers (51), the method further includes: preparing a mask layer pattern on the upper surface of the epitaxial layer (2), forming two first grooves (21) by dry etching, and preparing at least two dielectric layers (51) from bottom to top in the two first grooves (21).

9. The method for fabricating a vertical diode based on a homogeneous k-dielectric terminal as described in claim 8, characterized in that, The mask layer can be any one of photoresist, metal, or dielectric material.

10. The method for fabricating a vertical diode based on a homogeneous k-dielectric terminal as described in claim 7, characterized in that, The growth temperature of the bottommost dielectric layer (51) is 15℃-25℃; the growth temperature of the topmost dielectric layer (51) is 150℃-300℃.

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