Multi-channel SOI LIGBT device

Abstract

The invention belongs to the technical field of semiconductor devices, and particularly relates to a multi-channel SOI LIGBT device. Comprising a first conductive type epitaxial layer and an isolation groove located on the outer side; an emitter second conductive type well region I, an emitter second conductive type well region II and a collector first conductive type buffer layer are arranged on the first conductive type epitaxial layer; wherein the first second conductive type well region of the emitter is located in the second conductive type deep well region, a first conductive type doped region is arranged in the second conductive type deep well region, and the first conductive type doped region is located between the isolation groove and the second conductive type deep well region. According to the invention, the second conductive type deep well region is introduced on the basis of a traditional multi-channel SOI LIGBT device, so that the capability of extracting storage carriers of the device is improved under a turn-off condition; by arranging the first conductive type doped region, a current path is compressed, the current concentration phenomenon at the corner of the device is relieved, and the risk of starting a parasitic structure is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a multi-channel SOI LIGBT device. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are a new type of power semiconductor device and also serve as the "CPU" of power electronic devices. Because IGBTs are bipolar semiconductor devices, meaning both electrons and holes participate in current transport, they offer advantages such as high current density, low on-state voltage drop, and low conduction losses. Furthermore, IGBTs also possess the advantages of MOSFETs, such as low switching losses, fast switching speed, simple driving, and high input impedance, further reducing the requirements for external control circuits and thus expanding their application areas. Therefore, IGBTs are widely used in new energy vehicles, photovoltaic inverters, rail transportation, and solar and wind power generation. Among them, SOI LIGBTs, with their advantages of easy integration, high voltage withstand capability, strong drive current capability, and fast switching speed, have found widespread application in power integrated circuits.

[0003] With the widespread application of IGBT devices, their current capability, turn-off loss, and reliability have become key areas for device optimization. Due to limitations in its lateral structure and substrate material, the current capability of LIGBTs is significantly reduced compared to vertical IGBT structures. Therefore, to improve the current capability of LIGBT devices, researchers have proposed multi-channel LIGBT devices, such as... Figure 1The existing LIGBT device structure shown includes, from bottom to top, a first conductivity type substrate 1, an insulating dielectric layer 2, and a first conductivity type epitaxial layer 3, and an isolation trench 4 located outside the first conductivity type epitaxial layer 3. The first conductivity type epitaxial layer 3 has an emitter second conductivity type well region 6a, an emitter second conductivity type well region 6b, and a collector first conductivity type buffer layer 7. The emitter second conductivity type well region 6a and the emitter second conductivity type well region 6b contain a second conductivity type heavily doped region 8 and a first conductivity type heavily doped region 9, respectively. In emitter second conductivity type well region 6a, a second conductivity type heavily doped region 8 and a first conductivity type heavily doped region 9 are arranged adjacently; in emitter second conductivity type well region 6b, two first conductivity type heavily doped regions 9 are adjacent to each other on both sides of a second conductivity type heavily doped region 8; a second conductivity type heavily doped region 8 is provided in the first conductivity type buffer layer 7; a gate dielectric layer 10 and a drift region dielectric layer 11 are provided on the first conductivity type epitaxial layer 3, and a gate structure 12 and a collector field plate 13 are respectively provided on the gate dielectric layer 10 and the drift region dielectric layer 11. This existing LIGBT device structure improves the electron injection efficiency and further enhances the current characteristics of the LIGBT device by introducing multiple channels, but this also brings about reliability problems caused by the non-uniformity of current distribution and voltage foldback during device switching.

[0004] Therefore, in order to solve the problems of increased loss and voltage foldback caused by uneven current distribution in the device, this invention proposes a multi-channel SOI LIGBT device. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-channel SOI LIGBT device that can optimize the reliability problems caused by uneven current distribution and voltage foldback in LIGBT devices.

[0006] To address the aforementioned technical problems, this invention provides a multi-channel SOI LIGBT device, comprising a first conductivity type epitaxial layer and an isolation trench on the outer side; the first conductivity type epitaxial layer is provided with an emitter second conductivity type well region one, an emitter second conductivity type well region two, and a collector first conductivity type buffer layer; wherein the emitter second conductivity type well region one is located within a second conductivity type deep well region, and a first conductivity type doped region is provided within the second conductivity type deep well region, the first conductivity type doped region being located between the isolation trench and the second conductivity type well region.

[0007] Preferably, it also includes a substrate of a first conductivity type and an insulating dielectric layer; The first conductivity type substrate, the insulating dielectric layer, and the first conductivity type epitaxial layer are arranged sequentially from bottom to top; The emitter second conductivity type well region one and the emitter second conductivity type well region two are provided with a second conductivity type heavily doped region and a first conductivity type heavily doped region; The first conductivity type buffer layer is provided with a second conductivity type heavily doped region; The first conductivity type epitaxial layer is provided with a gate dielectric layer and a drift region dielectric layer. The gate dielectric layer and the drift region dielectric layer are respectively provided with a gate structure and a collector field plate. The gate structure is connected to the same potential through a gate edge structure.

[0008] Preferably, the concentration in the second type of conductivity deep well region is distributed in a stepped manner, that is, the bottom concentration of the second type of conductivity deep well region is higher than its top concentration.

[0009] Preferably, the bottom of the first conductivity type doped region extends downward to contact the first conductivity type epitaxial layer.

[0010] Preferably, in the top direction of the device, the second conductivity type deep well region is located at a corner of the device, and the second conductivity type deep well region is located between the isolation trench and the emitter second conductivity type well region one and the emitter second conductivity type well region two, and is connected to the emitter second conductivity type well region one and the emitter second conductivity type well region two.

[0011] Preferably, in the top-down direction of the device, the first conductivity type doped region covers the corner of the device between the isolation trench and the emitter second conductivity type well region.

[0012] Preferably, in the top-down direction of the device, the first conductivity type doped region covers the entire straight-line region between the isolation trench and the emitter second conductivity type well region, and the right end of the first conductivity type doped region contacts the first conductivity type epitaxial layer.

[0013] Preferably, in the top direction of the device, there is also an insertion region in the longitudinal direction of the device, and the insertion region is arranged alternately with the original region of the device; wherein the discrete gate structures in the insertion region are connected by a gate connection structure, and it is ensured that there is no heavily doped region of the first conductivity type on the device in the insertion region.

[0014] Preferably, the width of the insertion region is set to l1, and the width of the original region of the device is set to l2, while ensuring that l1... <l2。

[0015] Preferably, the first conductivity type doped region and the collector first conductivity type buffer layer are formed by the same implantation.

[0016] Compared with the prior art, the present invention has the following advantages: The multi-channel SOI LIGBT device provided by this invention introduces a deep well region structure of a second conductivity type to form a carrier collection layer, effectively improving the carrier extraction capability in the off-state and preventing current concentration at corners, which could trigger parasitic transistors and cause voltage foldback, thus improving device reliability. Furthermore, by introducing a doped region of a first conductivity type near the emitter side at the device corner, the current extraction path in the off-state is compressed, avoiding current concentration at corners. Based on this, the layout structure provided by this invention features a periodically arranged gate structure to ensure the synchronization of gate signal transmission, avoiding the reliability problems caused by uneven current due to inconsistent channel opening caused by the traditional gate structure's limitation of strip-shaped lead-out method. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of an existing multi-channel SOI LIGBT device.

[0018] Figure 2 This is a cross-sectional structure of a multi-channel SOI LIGBT device provided in Embodiment 1 of the present invention. Figure 1 .

[0019] Figure 3 This is a cross-sectional structure of a multi-channel SOI LIGBT device provided in Embodiment 1 of the present invention. Figure 2 .

[0020] Figure 4 This is a cross-sectional structure of a multi-channel SOI LIGBT device provided in Embodiment 2 of the present invention. Figure 3 .

[0021] Figure 5 This is a cross-sectional structure of a multi-channel SOI LIGBT device provided in Embodiment 3 of the present invention. Figure 4 .

[0022] Figure 6 This is a schematic diagram of a multi-channel SOI LIGBT device provided in Embodiment 4 of the present invention. Figure 1 Its cross-sectional view along A-A' corresponds to Figure 2 The cross-sectional view along B-B' corresponds to Figure 3 .

[0023] Figure 7 This invention provides a basis for... Figure 6 Schematic diagram of changing device layout Figure 2 .

[0024] Figure 8 This is a schematic diagram of a multi-channel SOI LIGBT device provided in Embodiment 5 of the present invention. Figure 3 Its cross-sectional view along AA' corresponds to Figure 2 .

[0025] Figure 9 This is a schematic diagram of a multi-channel SOI LIGBT device provided in Embodiment 5 of the present invention. Figure 4 Its cross-sectional view along AA' corresponds to Figure 2 .

[0026] In the figure: 1-Substrate of first conductivity type; 2-Insulating dielectric layer; 3-Epiaxial layer of first conductivity type; 4-Isolation trench; 5-Deep well region of second conductivity type; 6a-Emitter well region of second conductivity type one; 6b-Emitter well region of second conductivity type two; 7-Collector buffer zone of first conductivity type; 7a-Doped region of first conductivity type; 8-Heavily doped region of second conductivity type; 9-Heavily doped region of first conductivity type; 10-Gate dielectric layer; 11-Drift region dielectric layer; 12-Gate structure; 12a-Gate connection structure; 12b-Gate edge structure; 13-Collector field plate; 14-Insertion region. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0028] Example 1 like Figure 2 and Figure 3 As shown, this embodiment provides a multi-channel SOI LIGBT device, including a first conductivity type substrate 1 with an insulating dielectric layer 2 on it. Above the insulating dielectric layer 2, a first conductivity type epitaxial layer 3 and an isolation trench 4 are provided. In the first conductivity type epitaxial layer 3, a second conductivity type deep well region 5, an emitter second conductivity type well region 6a, an emitter second conductivity type well region 6b, and a collector first conductivity type buffer layer 7 are provided. The emitter second conductivity type well region 6a is located within the second conductivity type deep well region 5. A first conductivity type doped region 7a is provided within the second conductivity type deep well region 5, located between the isolation trench 4 and the second conductivity type well region 6a. A second conductivity type heavily doped region 8 and a first conductivity type heavily doped region 9 are provided within the emitter second conductivity type well region 6a and the emitter second conductivity type well region 6b, respectively. A second conductivity type heavily doped region 8 is provided within the first conductivity type buffer layer 7. Above the first conductivity type epitaxial layer 2, a gate dielectric layer 10 and a drift region dielectric layer 11 are provided. Above the dielectric layers, a gate structure 12 and a collector field plate 13 are provided.

[0029] As a preferred embodiment, the second conductivity type deep well region 5 is deeper than the emitter second conductivity type well region -6a.

[0030] The working principle of this embodiment is as follows: Figure 2 As shown, by introducing a deeper second conductivity type well region 6 at the edge-side emitter, the collection of second conductivity type carriers in the on-state is aided. Simultaneously, in the off-state, carriers flowing towards the emitter are collected earlier than in the body region, mitigating the phenomenon of a large number of carriers concentrating in the second conductivity type well region 6, which could trigger the parasitic transistor to turn on and lead to device failure. Furthermore, by introducing a first conductivity type doped region 7a between the isolation trench 4 and the second conductivity type well region 6, the current path of the second conductivity type carriers in the switching state is effectively compressed, reducing the current density near the isolation trench 4 and improving the device's reliability in the off-state.

[0031] Example 2 like Figure 4 As shown, as a preferred embodiment, based on Example 1, the concentration of the second conductivity type deep well region 5 is distributed in a stepped manner, that is, the concentration of the bottom 5a of the second conductivity type deep well region 5 is higher than the concentration of the top 5b of the second conductivity type deep well region 5.

[0032] The working principle of this embodiment is as follows: Based on embodiment 1, the second conductivity type deep well region 5 adopts a stepped doping distribution. The higher the bottom concentration, the better the effect of collecting charge carriers in advance, the smaller the resistance under the current path, and the stronger the ability to suppress parasitic effects.

[0033] Example 3 As a preferred embodiment, based on Example 1, the bottom of the first conductivity type doped region 7a is connected to the first conductivity type epitaxial layer 3.

[0034] As a method for fabricating a multi-channel SOI LIGBT device, the preferred method is that the first conductivity type doped region 7a and the collector first conductivity type buffer layer 7 can be formed by co-channel implantation.

[0035] The working principle of this embodiment is as follows: The known first conductivity type doped region effectively compresses the current path, reducing the current density near the trench and improving the reliability of the device in switching states. Simultaneously, this first conductivity type doped region can be implanted in the same batch as the collector first conductivity type buffer layer, saving iterations. Furthermore, increasing the junction depth of the first conductivity type doped region to connect with the first conductivity type epitaxial layer further compresses the flow path of the second conductivity type carriers, effectively reducing the risk of voltage foldback.

[0036] Example 4 As a preferred embodiment, the local layout structure of the SOI LIGBT device in Example 1 is as follows: Figure 6 , Figure 7As shown, the second conductivity type deep well region 5 is connected to the top of the emitter second conductivity type well region 6a and the emitter second conductivity type well region 6b. The first conductivity type doped region 7a covers the device corner located between the isolation trench 4 and the emitter second conductivity type well region 6a.

[0037] As a layout of a multi-channel SOI LIGBT device, the preferred method is that the first conductivity type doped region 7a is located in the entire straight channel region between the isolation trench 4 and the emitter second conductivity type well region - 6a, and its top is connected to the first conductivity type epitaxial layer 3.

[0038] The principle of this embodiment is as follows: In terms of layout structure, at the corner of the device, a first conductivity type doped region 7a is used to block the second conductivity type charge carriers, preventing current from concentrating at the corner and causing failure due to voltage foldback when flowing through the body region. Furthermore, the first conductivity type doped region 7a on the left side of the device can extend to the straight-line region between the emitter region and the isolation trench, and the top doped region can extend to the right into the first conductivity type epitaxial layer 3 to further compress the current path. At the same time, the deep well near the isolation trench 4 can also play an auxiliary role in withstand voltage.

[0039] Example 5 The partial layout structure of the SOI LIGBT device in Example 1 is as follows: Figure 8 As shown, the second conductivity type deep well region 5 is connected to the top of the emitter second conductivity type well region 1 6a and emitter second conductivity type well region 2 6b, and the gate structure 12 is connected to the same potential through the gate edge structure 12b.

[0040] The layout of a multi-channel SOI LIGBT device is as follows: Figure 9 As shown, the preferred embodiment is that, in the top direction of the device, the insertion region 14 and the original region are arranged alternately and periodically in the vertical direction, wherein the discrete gate structure 12 in the insertion region 14 is connected by the gate connection structure 12a, and there is no first conductivity type heavily doped region 9 in the insertion region 14.

[0041] As a layout method for a multi-channel SOI LIGBT device, the preferred approach is that the width l1 of the alternating insertion regions 14 is related to the width l2 of the original region as follows: l1 <l2。

[0042] The principle of this embodiment is as follows: Since traditional multi-channel SOI LIGBT devices have multiple discrete strip gates, there are certain differences and delays in the transmission of gate voltage signals, resulting in inconsistent channel opening and uneven device current distribution. In order to optimize this problem, this embodiment adopts a periodically arranged gate connection structure 12a. By periodically connecting discrete gates, an H-type gate structure layout is formed, which further optimizes the gate signal transmission delay problem and ensures uniform device opening.

[0043] In summary, this invention provides a multi-channel SOI LIGBT device that suppresses voltage foldback. Based on traditional multi-channel SOI LIGBT devices, it introduces a deep well region of a second conductivity type, improving the device's ability to extract and store carriers under off-conditions. Furthermore, a first conductivity type doped region is positioned between the device's isolation trench and the emitter's second conductivity type well region, compressing the current path of the second conductivity type carriers, preventing current concentration at device corners, reducing the risk of parasitic structure activation, and effectively improving device reliability. Moreover, periodic layout optimizes the device's current uniformity.

[0044] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A multi-channel SOI LIGBT device, comprising a first conductivity type epitaxial layer (3) and an isolation trench (4) on the outer side; characterized in that, The first conductivity type epitaxial layer (3) is provided with emitter second conductivity type well region one (6a), emitter second conductivity type well region two (6b) and collector first conductivity type buffer layer (7); wherein the emitter second conductivity type well region one (6a) is located in the second conductivity type deep well region (5), and the second conductivity type deep well region (5) is provided with a first conductivity type doped region (7a), and the first conductivity type doped region (7a) is located between the isolation trench (4) and the second conductivity type well region (6a).

2. The multi-channel SOI LIGBT device as described in claim 1, characterized in that, It also includes a first conductivity type substrate (1) and an insulating dielectric layer (2); The first conductivity type substrate (1), the insulating dielectric layer (2), and the first conductivity type epitaxial layer (3) are arranged sequentially from bottom to top; The emitter second conductivity type well region one (6a) and the emitter second conductivity type well region two (6b) are provided with a second conductivity type heavily doped region (8) and a first conductivity type heavily doped region (9). The first conductivity type buffer layer (7) is provided with a second conductivity type heavily doped region (8); The first conductivity type epitaxial layer (3) is provided with a gate dielectric layer (10) and a drift region dielectric layer (11). The gate dielectric layer (10) and the drift region dielectric layer (11) are respectively provided with a gate structure (12) and a collector field plate (13). The gate structure (12) is connected to the same potential through a gate edge structure (12b).

3. The multi-channel SOI LIGBT device as described in claim 1, characterized in that, The concentration in the second type of deep well region (5) is distributed in a stepped manner, that is, the concentration at the bottom (5a) of the second type of deep well region (5) is higher than the concentration at the top (5b).

4. A multi-channel SOI LIGBT device as described in claim 1, characterized in that, The bottom of the first conductivity type doped region (7a) extends downward to contact the first conductivity type epitaxial layer (3).

5. A multi-channel SOI LIGBT device as described in claim 1, characterized in that, On the top of the device, the second conductivity type deep well region (5) is located at the corner of the device. The second conductivity type deep well region (5) is located between the isolation trench (4) and the emitter second conductivity type well region one (6a) and the emitter second conductivity type well region two (6b), and is connected to the emitter second conductivity type well region one (6a) and the emitter second conductivity type well region two (6b).

6. A multi-channel SOI LIGBT device as described in claim 1, characterized in that, On the top of the device, the first conductivity type doped region (7a) covers the corner of the device between the isolation trench (4) and the emitter second conductivity type well region (6a).

7. A multi-channel SOI LIGBT device as described in claim 6, characterized in that, In the top direction of the device, the first conductivity type doped region (7a) covers the entire straight channel region between the isolation trench (4) and the emitter second conductivity type well region (6a), and the right end of the first conductivity type doped region (7a) contacts the first conductivity type epitaxial layer (3).

8. A multi-channel SOI LIGBT device as described in claim 2, characterized in that, In the top direction of the device, there is also an insertion region (14) in the longitudinal direction of the device, and the insertion region (14) is arranged alternately with the original region of the device; wherein the discrete gate structure (12) in the insertion region (14) is connected by a gate connection structure (12a), and it is ensured that there is no heavily doped region (9) of the first conductivity type on the device in the insertion region (14).

9. A multi-channel SOI LIGBT device as described in claim 8, characterized in that, The width of the insertion region (14) is set to l1, and the width of the original region of the device is set to l2, ensuring that l1 <l2。 10. A multi-channel SOI LIGBT device as described in claim 1, characterized in that, The first conductivity type doped region (7a) and the collector first conductivity type buffer layer (7) are formed by the same implantation.

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