Semiconductor device

Abstract

A semiconductor device includes a substrate, a first channel pattern on the substrate, a first gate electrode extending in a second direction, a first gate cap pattern on an upper surface of the first gate electrode, a second channel pattern spaced apart from the first channel pattern, a second gate electrode extending in the second direction on the second channel pattern, a second gate cap pattern on an upper surface of the second gate electrode, a source / drain pattern on at least one side of the second channel pattern, a first source / drain contact connected to the source / drain pattern, a second source / drain contact spaced apart from the first source / drain contact, and a second gate cap pattern on an upper surface of the second gate electrode, and a contact isolation film between the first source / drain contact and the second source / drain contact, the first channel pattern having a first width, and the second channel pattern having a second width. The second width is greater than the first width.

Description

TECHNICAL FIELD

[0001] Some example embodiments relate to a semiconductor device. BACKGROUND

[0002] Semiconductor devices are core components for controlling and / or amplifying electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. For example, memory devices can be mainly used for storing and retrieving data, and non-memory devices can be used for controlling and / or amplifying electrical signals. Semiconductor devices are core components of electronic devices and play an important role in various fields including computers, communication devices, consumer electronics, etc.

[0003] As the semiconductor industry continues to advance, the performance and functional requirements of electronic devices are also increasing. Therefore, higher performance characteristics of semiconductor devices are increasingly required, and the integration density of semiconductor devices is continuously increasing to meet these industrial demands. Various methods for forming semiconductor devices with improved performance and / or improved integration density are being researched. SUMMARY

[0004] Some example embodiments of the disclosure provide a semiconductor device with improved electrical characteristics and / or reliability.

[0005] According to some example embodiments of the disclosure, a second source / drain contact can be formed by forming a contact spacer on the second source / drain pattern. Therefore, the electrical characteristics and reliability of the semiconductor device can be improved.

[0006] According to some example embodiments of the disclosure, a semiconductor device can include a substrate, a first channel pattern on the substrate, a first gate electrode extending in a second direction on the first channel pattern, a first gate cap pattern on an upper surface of the first gate electrode, a second channel pattern spaced apart from the first channel pattern in a first direction, a second gate electrode extending in the second direction on the second channel pattern, a second gate cap pattern on an upper surface of the second gate electrode, a source / drain pattern on at least one side of the second channel pattern, a first source / drain contact connected to the source / drain pattern, a second source / drain contact spaced apart from the first source / drain contact in the second direction, a contact isolation film between the first source / drain contact and the second source / drain contact, and a first contact spacer between the contact isolation film and the first source / drain contact, the first channel pattern having a first width in the first direction, the second channel pattern having a second width in the first direction, and the second direction crossing the first direction. The second width is greater than the first width.

[0007] According to some example embodiments of the present disclosure, a semiconductor device can include a substrate, a first channel pattern on the substrate, a second channel pattern spaced apart from the first channel pattern in a first direction, a first source / drain pattern on at least one side of the first channel pattern, a first source / drain contact on the first source / drain pattern, a second source / drain pattern on at least one side of the second channel pattern, a second source / drain contact on the second source / drain pattern, a third source / drain contact spaced apart from the second source / drain contact in a second direction, a contact spacer around a side surface of the second source / drain contact, and a first contact isolation film between the second source / drain contact and the third source / drain contact and in contact with the contact spacer, the first channel pattern having a first width in the first direction, the second channel pattern having a second width in the first direction, the second direction crossing the first direction. The second width is greater than the first width.

[0008] According to some example embodiments of the present disclosure, a semiconductor device can include a substrate, a first channel pattern on the substrate, a first gate electrode extending on the first channel pattern in a second direction, a first gate cap pattern on an upper surface of the first gate electrode, a second channel pattern spaced apart from the first channel pattern in a first direction, a second gate electrode extending on the second channel pattern in the second direction, a second gate cap pattern on an upper surface of the second gate electrode, a gate spacer on a side surface of the second gate electrode, a source / drain pattern on at least one side of the second channel pattern, a first source / drain contact on the source / drain pattern, a second source / drain contact spaced apart from the first source / drain contact in the second direction, a contact isolation film between the first source / drain contact and the second source / drain contact, and a contact spacer between the contact isolation film and the first source / drain contact, the first channel pattern having a first width in the first direction, the second direction crossing the first direction, the second channel pattern having a second width in the first direction greater than the first width. The contact spacer surrounds at least a portion of a side surface of the first source / drain contact, and at least a portion of the contact spacer is in contact with a side surface of the gate cap pattern.

[0009] According to some example embodiments of the present disclosure, a method of manufacturing a semiconductor device can include: forming, on a substrate, a fin-type pattern including a first channel pattern and a second channel pattern spaced apart from the first channel pattern, a first source / drain pattern on at least one side of the first channel pattern, a second source / drain pattern on at least one side of the second channel pattern, a first gate electrode stack on the first channel pattern, and a second gate electrode stack on the second channel pattern; forming a protective layer on at least a portion of the first source / drain pattern and the first gate electrode stack; forming a spacer liner on the protective layer, the second source / drain pattern, and the second gate electrode stack; forming a mask layer on the protective layer; removing at least a portion of the mask layer by a first etching process such that the mask layer remains over the second source / drain pattern and is removed over the first source / drain pattern; removing the mask layer remaining over the second source / drain pattern, at least a portion of the spacer liner, and the protective layer; forming a first trench and a second trench in the first source / drain pattern and the second source / drain pattern, respectively, by a second etching process; forming a first source / drain contact in the first trench and a second source / drain contact in the second trench; and forming an upper wiring structure on the first gate electrode stack, the second gate electrode stack, the first source / drain contact, and the second source / drain contact.

[0010] According to some example embodiments of the present disclosure, the first channel pattern has a first width, the second channel pattern has a second width, and the second width is greater than the first width.

[0011] According to some example embodiments of the present disclosure, at least a portion of the first source / drain pattern is recessed to form the first trench and at least a portion of the spacer liner and at least a portion of the second source / drain pattern are recessed to form the second trench when the first trench and the second trench are formed.

[0012] According to some example embodiments of the present disclosure, the second etching process is performed using a mask patterned with a KrF or ArF patterning process as an etching mask.

[0013] According to some example embodiments of the present disclosure, the first gate electrode stack includes a first gate electrode extending in a second direction on the first channel pattern, a first gate spacer having a first gate insulating film on and between side surfaces of the first gate electrode, and a first gate cap pattern on the first gate electrode and the first gate spacer, and the second gate electrode stack includes a second gate electrode extending in the second direction on the first channel pattern, a second gate spacer having a second gate insulating film on and between side surfaces of the second gate electrode, and a second gate cap pattern on the second gate electrode and the second gate spacer. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and other embodiments and features of this disclosure will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 These are example layout diagrams provided to illustrate semiconductor devices according to some example implementations;

[0016] Figure 2 It is along Figure 1 A cross-sectional view taken from line AA;

[0017] Figure 3 It is along Figure 1 A cross-sectional view of line BB;

[0018] Figure 4 It is along Figure 1 A cross-sectional view taken from line CC;

[0019] Figure 5 These are diagrams provided to illustrate semiconductor devices according to some example embodiments;

[0020] Figure 6 and Figure 7 These are diagrams provided to illustrate semiconductor devices according to some example embodiments;

[0021] Figure 8 These are diagrams provided to illustrate semiconductor devices according to some example embodiments;

[0022] Figure 9 These are diagrams provided to illustrate semiconductor devices according to some example embodiments;

[0023] Figure 10 These are diagrams provided to illustrate semiconductor devices according to some example embodiments;

[0024] Figures 11 to 18 These are diagrams provided to illustrate methods for manufacturing semiconductor devices according to some example embodiments. Detailed Implementation

[0025] Terms such as "first," "second," etc., may be used herein to describe various devices or components, but the devices or components are not limited by these terms. It should be understood that these terms are used only to distinguish one element or component from another. Clearly, the first element or component mentioned below may be a second element or component within the technical concept of this disclosure.

[0026] Semiconductor devices and methods of manufacturing the same according to some exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0027] In the cross-sectional views of the semiconductor device according to some example embodiments of the present disclosure, a fin-type transistor (FinFET) including a channel region of a fin-type pattern is shown as an example, but example embodiments are not limited thereto. The semiconductor device according to some example embodiments can include a tunneling transistor (tunneling FET), a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor.

[0028] Figure 1 is provided to illustrate an example layout of a semiconductor device according to some example embodiments. Figure 2 is a cross-sectional view taken along line A-A of Figure 1 . Figure 3 is a cross-sectional view taken along line B-B of Figure 1 . Figure 4 is a cross-sectional view taken along line C-C of Figure 1 . For ease of description, the first gate cap pattern 145, the second gate cap pattern 245, and the upper wiring structure 300 are omitted from the illustration of Figure 1 .

[0029] Referring to Figures 1 to 4 , the semiconductor device according to some example embodiments can include a substrate 100, a first channel pattern CP1, a second channel pattern CP2, a first gate electrode 120, a second gate electrode 220, a first gate insulating film 130, a second gate insulating film 230, a first gate cap pattern 145, a second gate cap pattern 245, a first gate spacer 140, a second gate spacer 240, a first source / drain pattern 150, a second source / drain pattern 250, a first source / drain contact 170, a second source / drain contact 270, a first contact isolation film 190, a second contact isolation film 290, a contact spacer 280, an upper wiring structure 300, and the like.

[0030] The substrate 100 can be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 can include silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimony, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony, but example embodiments are not limited thereto.

[0031] The fin-type pattern FP can protrude from the substrate 100. The fin-type pattern FP can extend in a first direction D1. Adjacent fin-type patterns FP can be disposed to be spaced apart from each other in a second direction D2. The first direction D1 can be a direction crossing the second direction D2, for example, the first direction D1 can be perpendicular to the second direction D2. Each of the first direction D1 and the second direction D2 can be a direction parallel to an upper surface of the substrate 100.

[0032] The fin-type pattern FP can be a part of the substrate 100, and can include an epitaxial layer grown from the substrate 100. For example, the fin-type pattern FP can include an elemental semiconductor material such as silicon or germanium. Further, the fin-type pattern FP can include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Specifically, for the example of the group IV-IV compound semiconductor, each fin-type pattern FP can include a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or these compounds doped with a group IV element. For the example of the group III-IV compound semiconductor, each fin-type pattern FP can include one of a binary compound, a ternary compound, or a quaternary compound formed by a combination of at least one of group III elements such as aluminum (Al), gallium (Ga), and indium (In) and one of group V elements such as phosphorus (P), arsenic (As), and antimony (Sb). However, example embodiments are not limited thereto.

[0033] A field insulating film 105 can be formed on the substrate 100. The field insulating film 105 can cover a part of the fin-type pattern FP. For example, the field insulating film 105 can be disposed on a part of the sidewall of the fin-type pattern FP. The upper surface of the fin-type pattern FP can protrude upward farther than the upper surface of the field insulating film 105. The fin-type pattern FP can be defined by the field insulating film 105 on the substrate 100. For example, the field insulating film 105 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0034] The fin-type pattern FP can include a first channel pattern CP1 and a second channel pattern CP2. The first channel pattern CP1 and the second channel pattern CP2 can be disposed to be spaced apart from each other in the first direction D1. The first channel pattern CP1 can have a first width W1 in the first direction D1. The second channel pattern CP2 can have a second width W2 in the first direction D1. The second width W2 can be greater than the first width W1.

[0035] The first gate electrode 120 can extend in the second direction D2 on the fin-type pattern FP and the field insulating film 105. The first gate electrode 120 can intersect the fin-type pattern FP. The first gate electrode 120 can be disposed on the first channel pattern CP1 of the fin-type pattern FP. The first gate electrode 120 can surround three surfaces of the first channel pattern CP1. For example, the first gate electrode 120 can be disposed on the upper surface and the two side surfaces of the first channel pattern CP1.

[0036] The second gate electrode 220 can extend over the fin-type pattern FP and the field insulating film 105 in the second direction D2. The second gate electrode 220 can intersect the fin-type pattern FP. The second gate electrode 220 can be disposed on the second channel pattern CP2 of the fin-type pattern FP. The second gate electrode 220 can surround three surfaces of the second channel pattern CP2. For example, the second gate electrode 220 can be disposed on the upper surface and the two side surfaces of the second channel pattern CP2.

[0037] The second gate electrode 220 can be disposed to be spaced apart from the first gate electrode 120 in the first direction D1. A width of the second gate electrode 220 in the first direction D1 can be greater than a width of the first gate electrode 120 in the first direction D1.

[0038] Each of the first gate electrode 120 and the second gate electrode 220 can include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbon nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbon nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and a combination of these. However, example embodiments are not limited thereto.

[0039] The first gate insulating film 130 can be disposed on the first gate trench 120T. The first gate insulating film 130 can extend along the side surfaces and the bottom surface of the first gate trench 120T. The first gate insulating film 130 can be disposed between the first gate electrode 120 and the first channel pattern CP1. The first gate electrode 120 can be disposed on the first gate insulating film 130. The first gate electrode 120 can fill a remaining portion of the first gate trench 120T not occupied by the first gate insulating film 130.

[0040] A second gate insulating film 230 can be disposed on the second gate trench 220T. The second gate insulating film 230 can extend along the side surface and the bottom surface of the second gate trench 220T. The second gate insulating film 230 can be disposed between the second gate electrode 220 and the second channel pattern CP2. The second gate electrode 220 can be disposed on the second gate insulating film 230. The second gate electrode 220 can fill the remaining portion of the second gate trench 220T not occupied by the second gate insulating film 230.

[0041] In some example embodiments, each of the first gate insulating film 130 and the second gate insulating film 230 can include a high-k insulating film. The high-k insulating film can include a high-k material having a higher dielectric constant than a silicon oxide film. Each of the first gate insulating film 130 and the second gate insulating film 230 can include at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, example embodiments are not limited thereto.

[0042] The first gate spacers 140 can be disposed on both side walls of the first gate electrode 120. The first gate spacers 140 can extend in the second direction D2 along the side walls of the first gate electrode 120.

[0043] The first gate cap pattern 145 can be disposed on the upper surface of the first gate electrode 120 and the upper surface of the first gate spacers 140. The first gate cap pattern 145 can cover the upper surface of the first gate electrode 120. The first gate cap pattern 145 can overlap the first gate electrode 120 in the third direction D3.

[0044] Although the first gate cap pattern 145 is illustrated as being disposed on the upper surface of the first gate spacers 140, example embodiments are not limited thereto. For example, the first gate spacers 140 can protrude farther than the upper surface of the first gate electrode 120, such that a portion of the first gate cap pattern 145 can be disposed between the first gate spacers 140. In some example embodiments, a boundary surface between the first gate cap pattern 145 and the first gate spacers 140 can not be distinguished.

[0045] The second gate spacers 240 can be disposed on both side walls of the second gate electrode 220. The second gate spacers 240 can extend in the second direction D2 along the side walls of the second gate electrode 220.

[0046] A second gate cap pattern 245 can be disposed on an upper surface of the second gate electrode 220 and an upper surface of the second gate spacer 240. The second gate cap pattern 245 can cover the upper surface of the second gate electrode 220. The second gate cap pattern 245 can overlap the second gate electrode 220 in the third direction D3.

[0047] Although the second gate cap pattern 245 is illustrated as being disposed on the upper surface of the second gate spacer 240, example embodiments are not limited thereto. For example, the second gate spacer 240 can protrude farther than the upper surface of the second gate electrode 220, such that a portion of the second gate cap pattern 245 can be disposed between the second gate spacers 240. In some example embodiments, a boundary surface between the second gate cap pattern 245 and the second gate spacer 240 can not be distinguished.

[0048] For example, each of the first gate spacer 140 and the second gate spacer 240 can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxide boron nitride (SiOBN), silicon oxycarbide (SiOC), and a combination of these. Although each of the first gate spacer 140 and the second gate spacer 240 is illustrated as a single film, this is for the convenience of description only, and example embodiments are not limited thereto.

[0049] For example, each of the first gate cap pattern 145 and the second gate cap pattern 245 can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and a combination of these. However, example embodiments are not limited thereto.

[0050] The first source / drain pattern 150 can be disposed on the fin-type pattern FP. The first source / drain pattern 150 can be disposed on at least one side of the first channel pattern CP1. The first source / drain pattern 150 can be in contact with the first channel pattern CP1. The first source / drain pattern 150 can function as a source / drain of a transistor using the first channel pattern CP1 as a channel region.

[0051] The second source / drain pattern 250 can be disposed on the fin-type pattern FP. The second source / drain pattern 250 can be disposed on at least one side of the second channel pattern CP2. The second source / drain pattern 250 can be in contact with the second channel pattern CP2. The second source / drain pattern 250 can function as a source / drain of a transistor using the second channel pattern CP2 as a channel region.

[0052] Each of the first source / drain pattern 150 and the second source / drain pattern 250 can include a semiconductor material. For example, the first source / drain pattern 150 can include an elemental semiconductor material such as silicon (Si) or germanium (Ge). Also, for example, the first source / drain pattern 150 can include a binary compound or a ternary compound containing at least two or more of carbon (C), silicon (Si), germanium (Ge), tin (Sn), or the like, or these compounds doped with a Group IV element. For example, the first source / drain pattern 150 can include silicon (Si), silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), or the like, but example embodiments are not limited thereto.

[0053] Although each of the first source / drain pattern 150 and the second source / drain pattern 250 is illustrated as a single film, this is merely for ease of description, and example embodiments are not limited thereto. Each of the first source / drain pattern 150 and the second source / drain pattern 250 can include a plurality of films containing different materials. On the other hand, each of the first source / drain pattern 150 and the second source / drain pattern 250 can include the same material, and can include a plurality of layers having different concentrations of a constituent material.

[0054] A first silicide film 155 can be provided on an upper surface of the first source / drain pattern 150. The first silicide film 155 can be provided between the first source / drain pattern 150 and the first source / drain contact 170. A second silicide film 255 can be provided on an upper surface of the second source / drain pattern 250. The second silicide film 255 can be provided between the second source / drain pattern 250 and the second source / drain contact 270.

[0055] The first source / drain contact 170 and the second source / drain contact 270 will be described in detail below.

[0056] The first source / drain contact 170 can be provided on the first source / drain pattern 150. The first source / drain contact 170 can be in contact with the first silicide film 155. The first source / drain contact 170 can be electrically connected to the first source / drain pattern 150.

[0057] The first source / drain contact 170 can extend in the second direction D2. The first gate electrode 120 can be provided between the first source / drain contacts 170 adjacent to each other in the first direction D1. The first contact isolation film 190 can be provided between the first source / drain contacts 170 adjacent to each other in the second direction D2. The first source / drain contacts 170 adjacent to each other in the second direction D2 can overlap each other in the second direction D2.

[0058] The first source / drain contact 170 can be in contact with the first contact isolation film 190, the first gate cap pattern 145, and the first gate spacer 140. The first source / drain contact 170 can include first to fourth side surfaces 170_SS1, 170_SS2, 170_SS3, and 170_SS4. The first side surface 170_SS1 and the second side surface 170_SS2 of the first source / drain contact 170 can face each other in the first direction D1, and the third side surface 170_SS3 and the fourth side surface 170_SS4 of the first source / drain contact 170 can face each other in the second direction D2. The first side surface 170_SS1 and the second side surface 170_SS2 of the first source / drain contact 170 can be in contact with the first gate spacer 140 and the first gate cap pattern 145. The third side surface 170_SS3 and the fourth side surface 170_SS4 of the first source / drain contact 170 can be in contact with the first contact isolation film 190.

[0059] The second source / drain contact 270 can be disposed on the second source / drain pattern 250. The second source / drain contact 270 can be in contact with the second silicide film 255. The second source / drain contact 270 can be electrically connected to the second source / drain pattern 250.

[0060] The second source / drain contact 270 can extend in the second direction D2. The second gate electrode 220 can be disposed between the second source / drain contacts 270 adjacent to each other in the first direction D1. The second contact isolation film 290 can be disposed between the second source / drain contacts 270 adjacent to each other in the second direction D2. The second source / drain contacts 270 adjacent to each other in the second direction D2 can overlap each other in the second direction D2.

[0061] The second source / drain contact 270 can be disposed on a side surface of the contact spacer 280. The contact spacer 280 can be disposed around the second source / drain contact 270. The contact spacer 280 can surround at least a portion of the side surface of the second source / drain contact 270.

[0062] The contact spacer 280 can be in contact with side surfaces of the second source / drain contact 270. The second source / drain contact 270 can include first to fourth side surfaces 270_SS1, 270_SS2, 270_SS3, and 270_SS4. The first side surface 270_SS1 and the second side surface 270_SS2 of the second source / drain contact 270 can face each other in the first direction D1, and the third side surface 270_SS3 and the fourth side surface 270_SS4 of the second source / drain contact 270 can face each other in the second direction D2. The contact spacer 280 can be in contact with each of the first to fourth side surfaces 270_SS1, 270_SS2, 270_SS3, and 270_SS4 of the second source / drain contact 270.

[0063] The contact spacer 280 can be disposed on side surfaces of the second gate cap pattern 245 and the second gate spacer 240. The contact spacer 280 can be in contact with the second gate cap pattern 245 and the second gate spacer 240. The contact spacer 280 can be disposed between the second source / drain contact 270 and the second gate cap pattern 245 and between the second source / drain contact 270 and the second gate spacer 240.

[0064] In some example embodiments, a distance from the upper surface of the substrate 100 to an upper surface of the second source / drain contact 270 can be the same as a distance from the upper surface of the substrate 100 to an upper surface of the contact spacer 280. However, example embodiments are not limited thereto. The upper surface of the second source / drain contact 270 can be a surface in contact with the first upper insulating film 310, and the upper surface of the contact spacer 280 can be a surface in contact with the first upper insulating film 310.

[0065] In some example embodiments, the contact spacer 280 can be in contact with the second source / drain pattern 250. For example, a bottom surface of the contact spacer 280 can be in contact with the second source / drain pattern 250.

[0066] A width of the first source / drain contact 170 in the first direction D1 can be the same as a width of the first contact isolation film 190 in the first direction D1. A width of the second source / drain contact 270 in the first direction D1 can be smaller than a width of the second contact isolation film 290 in the first direction D1. The width of the second contact isolation film 290 in the first direction D1 can be the same as a width of the contact spacer 280 in the first direction D1.

[0067] Each of the first source / drain contact 170 and the second source / drain contact 270 can include an electrically conductive material. For example, each of the first source / drain contact 170 and the second source / drain contact 270 can include at least one of a metal, a metal alloy, an electrically conductive metal nitride, an electrically conductive metal carbide, an electrically conductive metal oxide, an electrically conductive metal carbonitride, and a two-dimensional material. However, example embodiments are not limited thereto.

[0068] Although each of the first source / drain contact 170 and the second source / drain contact 270 is illustrated herein as a single film, example embodiments are not limited thereto. For example, each of the first source / drain contact 170 and the second source / drain contact 270 can include an electrically conductive barrier film and an electrically conductive fill film disposed on the electrically conductive barrier film.

[0069] Each of the first contact isolation film 190 and the second contact isolation film 290 can include an insulating material. For example, each of the first contact isolation film 190 and the second contact isolation film 290 can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and a combination of these. However, example embodiments are not limited thereto.

[0070] The contact spacer 280 can include an insulating material. In some example embodiments, the contact spacer 280 can include a material different from a material of the second contact isolation film 290. For example, the contact spacer 280 can include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a low-k material. For example, the low-k material can include fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilane borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilane phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ, fluorosilicate glass (FSG), polyimide nanocellulose such as polypropylene oxide, carbon-doped oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination of these, although example embodiments are not limited thereto.

[0071] The upper wiring structure 300 can be disposed on the first gate cap pattern 145, the first source / drain contact 170, the second gate cap pattern 245, and the second source / drain contact 270. The upper wiring structure 300 can include a first upper insulating film 310, a second upper insulating film 320, a first wiring layer 350, and a second wiring layer 360.

[0072] The first upper insulating film 310 can be disposed on an upper surface of the first source / drain contact 170 and an upper surface of the second source / drain contact 270. The first wiring layer 350 can be disposed within the first upper insulating film 310. The first wiring layer 350 can be electrically connected to the second source / drain contact 270.

[0073] The second upper insulating film 320 can be disposed on the first upper insulating film 310. The second wiring layer 360 can be disposed within the second upper insulating film 320. The second wiring layer 360 can be disposed on the first wiring layer 350. The second wiring layer 360 can be electrically connected to the first wiring layer 350. The second wiring layer 360 can extend in the first direction D1.

[0074] Figure 5 FIG. 6 is a diagram provided to explain a semiconductor device according to some example embodiments. For ease of description, differences from the configuration described above in FIG. 1 will be mainly described. Figures 1 to 4

[0075] Referring to FIG. 6, a semiconductor device according to some example embodiments can include a first gate cap pattern 145, a first source / drain contact 170, a second gate cap pattern 245, a second source / drain contact 270, and a contact spacer 280. Figure 5 In a semiconductor device according to some example embodiments, the contact spacer 280 can be disposed on the fin-type pattern FP.

[0076] The contact spacer 280 can be disposed on the second channel pattern CP2 of the fin-type pattern FP. A bottom surface of the contact spacer 280 can be in contact with an upper surface of the second channel pattern CP2. The bottom surface of the contact spacer 280 can be disposed on the same plane as a bottom surface of the second gate electrode 220. By forming the contact spacer 280 on the second channel pattern CP2 and around at least a portion of a side surface of the second source / drain contact 270, an electrical characteristic and / or a reliability of the semiconductor device can be improved.

[0077] In some example embodiments, a width of the second source / drain contact 270 in the first direction D1 can be the same as a width of the second source / drain pattern 250 in the first direction D1.

[0078] Figure 6 FIG. 7 is a diagram provided to explain a semiconductor device according to some example embodiments. For ease of description, differences from the configuration described above in FIG. 1 will be mainly described. Figure 7 Figures 1 to 4

[0079] ​​​Semiconductor devices according to some example embodiments can include MOSFETs, and more specifically, can include gate-all-around (GAA) transistors and three-dimensional multi-stacked semiconductor devices known as multi-bridge-channel FETs (MBCFETs).

[0080] Referring to Figure 6 and Figure 7 Semiconductor devices according to some example embodiments can include a substrate 100, an active pattern AP, a first gate electrode 120, a second gate electrode 220, a first gate insulating film 130, a second gate insulating film 230, a first gate cap pattern 145, a second gate cap pattern 245, a first gate spacer 140, a second gate spacer 240, a first source / drain pattern 150, a second source / drain pattern 250, a first source / drain contact 170, a second source / drain contact 270, a first contact isolation film 190, a second contact isolation film 290, a contact spacer 280, an upper wiring structure 300, etc.

[0081] The substrate 100 can be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 can include silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimony, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony, but example embodiments are not limited thereto.

[0082] The active pattern AP can be disposed on the substrate 100. The active pattern AP can extend in a first direction D1. The active pattern AP can be disposed to be spaced apart from an adjacent active pattern AP in a second direction D2.

[0083] The active pattern AP can be a multi-channel active pattern. The active pattern AP can include a lower pattern BP, a first channel pattern CP1, and a second channel pattern CP2.

[0084] The lower pattern BP can protrude from the substrate 100. The lower pattern BP can extend in the first direction D1. The lower pattern BP can be spaced apart from an adjacent lower pattern BP in the second direction D2. The adjacent lower pattern BP can be separated by a field trench. The field trench can be defined by an upper surface of the substrate 100 and a side surface of the lower pattern BP.

[0085] The first channel pattern CP1 can be disposed on the lower pattern BP. The first channel pattern CP1 can include a plurality of first sheet patterns NS1. The plurality of first sheet patterns NS1 can be spaced apart from the lower pattern BP in a third direction D3. Each of the first sheet patterns NS1 can be spaced apart in the third direction D3. The third direction D3 can be a thickness direction of the substrate 100. The first sheet pattern NS1 can have a nanosheet shape. Although it is shown that there are three first sheet patterns NS1, example embodiments are not limited thereto.

[0086] The second channel pattern CP2 can be provided on the lower pattern BP. The second channel pattern CP2 can include a plurality of second sheet patterns NS2. The plurality of second sheet patterns NS2 can be spaced apart from the lower pattern BP in a third direction D3. Each of the second sheet patterns NS2 can be spaced apart in the third direction D3. The third direction D3 can be a thickness direction of the substrate 200. The second sheet patterns NS2 can have a nanosheet shape. Although it is illustrated that there are three second sheet patterns NS2, the example embodiments are not limited thereto.

[0087] The first channel pattern CP1 can have a first width W1 in the first direction D1. The first width W1 can be the same as a width of the first sheet pattern NS1 in the first direction D1. The second channel pattern CP2 can have a second width W2 in the first direction D1. The second width W2 can be the same as a width of the second sheet pattern NS2 in the first direction D1. The second width W2 can be greater than the first width W1.

[0088] The lower pattern BP can be formed by etching a portion of the substrate 100. However, the example embodiments are not limited thereto. For example, the lower pattern BP can include an epitaxial layer grown from the substrate 100. The lower pattern BP can include an elemental semiconductor material such as silicon (Si) or germanium (Ge). In addition, the lower pattern BP can include a compound semiconductor. For example, the lower pattern BP can include a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0089] For example, the group IV-IV compound semiconductor can be a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). However, the example embodiments are not limited thereto.

[0090] For example, the group III-V compound semiconductor can be one of a binary compound, a ternary compound, or a quaternary compound formed by a combination of at least one of group III elements such as aluminum (Al), gallium (Ga), and indium (In) and one of group V elements such as phosphorus (P), arsenic (As), and antimony (Sb). However, the example embodiments are not limited thereto.

[0091] Each of the first sheet pattern NS1 and the second sheet pattern NS2 can include one of an elemental semiconductor material such as silicon (Si) or silicon germanium (SiGe), a group IV-IV compound semiconductor, or a group III-V compound semiconductor. Each of the first sheet pattern NS1 and the second sheet pattern NS2 can include the same material as the lower pattern BP, or can include a different material from the lower pattern BP.

[0092] Each of the lower pattern BP, the first piece pattern NS1, and the second piece pattern NS2 can include silicon (Si). On the other hand, each of the lower pattern BP, the first piece pattern NS1, and the second piece pattern NS2 can include silicon germanium (SiGe). On the other hand, the lower pattern BP can include silicon (Si), and each of the first piece pattern NS1 and the second piece pattern NS2 can include silicon germanium (SiGe).

[0093] A first field insulating film 105 can be provided on the substrate 100. The first field insulating film 105 can fill a portion of the field trench. The first field insulating film 105 can be provided between adjacent lower patterns BP. The first field insulating film 105 can extend in the first direction D1. The first field insulating film 105 can be formed on an upper surface of the substrate 100. The first field insulating film 105 can cover a portion of a sidewall of the lower pattern BP.

[0094] For example, the first field insulating film 105 can include an oxide, a nitride, an oxynitride, or a combination of these. Although it is shown that the first field insulating film 105 is a single film, this is merely for ease of description, and example embodiments are not limited thereto. For example, the first field insulating film 105 can be formed of a plurality of films.

[0095] The first gate electrode 120 can extend on the substrate 100 in the second direction D2. The first gate electrode 120 can intersect the active pattern AP. The first gate electrode 120 can be provided on the lower pattern BP. Adjacent first gate electrodes 120 can be provided spaced apart from each other in the first direction D1. The first gate electrode 120 can be provided on the first channel pattern CP1. The first gate electrode 120 can surround the plurality of first piece patterns NS1. The first gate electrode 120 can surround four surfaces of the first piece pattern NS1. For example, the first gate electrode 120 can surround the upper surface, the lower surface, and the two side surfaces of the first piece pattern NS1. The upper surface and the lower surface of the first piece pattern NS1 can face each other in the third direction D3, and the two side surfaces of the first piece pattern NS1 can face each other in the second direction D2.

[0096] The first gate electrode 120 can include a first upper gate electrode 120_U and a first lower gate electrode 120_B. The first lower gate electrode 120_B can be provided between the first piece patterns NS1 adjacent to each other in the third direction D3. The first lower gate electrode 120_B can be provided between the plurality of first piece patterns NS1, and also between the lower pattern BP and the lowermost first piece pattern NS1 of the plurality of first piece patterns NS1. The first upper gate electrode 120_U can be provided on the uppermost first piece pattern NS1 of the plurality of first piece patterns NS1.

[0097] The second gate electrode 220 can extend on the substrate 100 in the second direction D2. The second gate electrode 220 can intersect the active pattern AP. The second gate electrode 220 can be disposed on the lower pattern BP. The second gate electrode 220 can be disposed to be spaced apart from an adjacent second gate electrode 220 in the first direction D1. The second gate electrode 220 can be disposed on the second channel pattern CP2. The second gate electrode 220 can surround the plurality of second sheet patterns NS2. The second gate electrode 220 can surround four surfaces of the second sheet pattern NS2. For example, the second gate electrode 220 can surround an upper surface, a lower surface, and two side surfaces of the second sheet pattern NS2. The upper surface and the lower surface of the second sheet pattern NS2 can face each other in the third direction D3, and the two side surfaces of the second sheet pattern NS2 can face each other in the second direction D2.

[0098] The second gate electrode 220 can include a second upper gate electrode 220_U and a second lower gate electrode 220_B. The second lower gate electrode 220_B can be disposed between the second sheet patterns NS2 adjacent to each other in the third direction D3. The second lower gate electrode 220_B can be disposed between the plurality of second sheet patterns NS2 and also between the lower pattern BP and a lowermost second sheet pattern NS2 of the plurality of second sheet patterns NS2. The second upper gate electrode 220_U can be disposed on an uppermost second sheet pattern NS2 of the plurality of second sheet patterns NS2.

[0099] The first gate insulating film 130 can be disposed between the first gate electrode 120 and the plurality of first sheet patterns NS1, between the first gate electrode 120 and the lower pattern BP, and between the first gate electrode 120 and the first source / drain pattern 150. Specifically, the first gate insulating film 130 can be disposed between the first upper gate electrode 120_U and an uppermost first sheet pattern NS1 of the plurality of first sheet patterns NS1. The first gate insulating film 130 can be disposed between the first lower gate electrode 120_B and the first sheet pattern NS1. The first gate insulating film 130 can surround the first sheet pattern NS1. The first gate insulating film 130 can extend in the first direction D1 along the upper surface and the lower surface of the first sheet pattern NS1.

[0100] The second gate insulating film 230 can be provided between the second gate electrode 220 and the plurality of second sheet patterns NS2, between the second gate electrode 220 and the lower pattern BP, and between the second gate electrode 220 and the second source / drain pattern 250. Specifically, the second gate insulating film 230 can be provided between the second upper gate electrode 220_U and the uppermost second sheet pattern NS2 of the plurality of second sheet patterns NS2. The second gate insulating film 230 can be provided between the second lower gate electrode 220_B and the second sheet pattern NS2. The second gate insulating film 230 can surround the second sheet pattern NS2. The second gate insulating film 230 can extend in the first direction D1 along the upper surface and the lower surface of the second sheet pattern NS2.

[0101] The descriptions of the first gate spacer 140, the first gate cap pattern 145, the first source / drain pattern 150, the first source / drain contact 170, and the first contact isolation film 190 can be the same as those described above with reference to Figures 1 to 4 The descriptions of the second gate spacer 240, the second gate cap pattern 245, the second source / drain pattern 250, the second source / drain contact 270, the second contact isolation film 290, and the contact spacer 280 can be the same as those described above with reference to Figures 1 to 4 The descriptions of the second gate spacer 240, the second gate cap pattern 245, the second source / drain pattern 250, the second source / drain contact 270, the second contact isolation film 290, and the contact spacer 280 can be the same as those described above with reference to

[0102] Figure 8 is provided to illustrate a semiconductor device according to some example embodiments. For ease of description, only the differences from the configuration described above in Figures 1 to 4 will mainly be described. For reference, Figure 8 may correspond to a cross-sectional view taken along the line C-C of Figure 1 .

[0103] Referring to Figure 8 , the semiconductor device according to some example embodiments can further include an etch stop film 252.

[0104] The etch stop film 252 can be provided on the second source / drain pattern 250. The etch stop film 252 can be provided on both side surfaces of the second source / drain pattern 250. For example, the etch stop film 252 can be provided between the side surfaces of the second source / drain pattern 250 and the second source / drain contact 270.

[0105] In some example embodiments, the etch stop film 252 can not be provided on the upper surface of the second source / drain pattern 250. That is, the upper surface of the second source / drain pattern 250 can be in contact with the second source / drain contact 270. The etch stop film 252 can be a portion that remains unremoved in an etching process for forming the second source / drain contact 270.

[0106] Figure 9 is provided to explain a semiconductor device according to some example embodiments. For ease of description, differences from the configuration described above in Figures 1 to 4 will mainly be described.

[0107] Referring to Figure 9 , in a semiconductor device according to some example embodiments, a depth of the first source / drain pattern 150 can be different from a depth of the second source / drain pattern 250.

[0108] A height from an upper surface of the substrate 100 to a bottom surface of the first source / drain pattern 150 can be a first distance H1. A height from the upper surface of the substrate 100 to a bottom surface of the second source / drain pattern 250 can be a second distance H2. The first distance H1 and the second distance H2 can be distances in the third direction D3. The first distance H1 can be greater than the second distance H2. In other words, the depth of the first source / drain pattern 150 can be smaller than the depth of the second source / drain pattern 250.

[0109] Figure 10 is provided to explain a semiconductor device according to some example embodiments. For ease of description, differences from the configuration described above in Figures 1 to 4 will mainly be described.

[0110] Referring to Figure 10 , in a semiconductor device according to some example embodiments, a width of the first contact isolation film 190 can be different from a width of the second contact isolation film 290.

[0111] The first contact isolation film 190 can have a third width W3 in the first direction D1 and can have a fourth width W4 in the second direction D2. The second contact isolation film 290 can have a fifth width W5 in the first direction D1 and can have a sixth width W6 in the second direction D2. The fifth width W5 can be equal to or substantially equal to or greater than the third width W3. The sixth width W6 can be equal to or substantially equal to or greater than the fourth width W4.

[0112] Figures 11 to 18 is provided to explain a method for manufacturing a semiconductor device according to some example embodiments. As a reference, Figure 11 is provided to explain a method for manufacturing a semiconductor device according to some example embodiments, and Figures 12 to 18 is a cross-sectional view taken along line A-A of Figure 11 .

[0113] Referring to Figure 11 and Figure 12The fin pattern FP, the first gate electrode 120, the second gate electrode 220, the first gate spacer 140, the second gate spacer 240, the first gate cap pattern 145, the second gate cap pattern 245, the first source / drain pattern 150, and the second source / drain pattern 250 can be formed on the substrate 100.

[0114] The fin pattern FP can include a first channel pattern CP1 and a second channel pattern CP2. A width of the first channel pattern CP1 in the first direction D1 can be less than a width of the second channel pattern CP2 in the first direction D1.

[0115] In some example embodiments, an upper surface of the first source / drain pattern 150 can be disposed at a higher level than a lower surface of the first gate electrode 120. A portion of the first source / drain pattern 150 can be disposed on the first gate spacer 140. An upper surface of the second source / drain pattern 250 can be disposed at a higher level than a lower surface of the second gate electrode 220. A portion of the second source / drain pattern 250 can be disposed on the second gate spacer 240.

[0116] Referring to Figure 13 A protective layer 410 can be formed on the first source / drain pattern 150 and the first gate cap pattern 145. The protective layer 410 can completely cover an upper surface of the first source / drain pattern 150. The first source / drain pattern 150 can be protected by the protective layer 410 in a subsequent process. The protective layer 410 can be formed on an upper surface of the first gate cap pattern 145. Although the protective layer 410 is illustrated as exposing a portion of the upper surface of the first gate cap pattern 145, example embodiments are not limited thereto. For example, the protective layer 410 can completely cover the upper surface of the first gate cap pattern 145.

[0117] Referring to Figure 14 A first spacer liner 280_P1 and a mask layer 430 can be formed on the protective layer 410, the second source / drain pattern 250, and the second gate cap pattern 245.

[0118] Specifically, the first spacer liner 280_P1 can be formed along the contours of the protective layer 410, the second gate cap pattern 245, the second gate spacer 240, and the second source / drain pattern 250. In some example embodiments, the first spacer liner 280_P1 can be formed conformally.

[0119] The mask layer 430 can be formed on the first spacer liner 280_P1. For example, the mask layer 430 can be a spin-on hard mask (SOH).

[0120] Referring to Figure 15A portion of the mask layer 430 can be removed. For example, the portion of the mask layer 430 can be removed by a first etching process. The mask layer 430 can remain on a portion of the first spacer pad 280_P1, i.e., on the first spacer pad 280_P1 disposed on the second source / drain pattern 250.

[0121] Referring to Figure 15 and Figure 16 A portion of the first spacer pad 280_P1 can be removed, and the protection layer 410 and the mask layer 430 can be removed.

[0122] Specifically, the first spacer pad 280_P1 and the protection layer 410 can be removed to form a second spacer pad 280_P2. An uppermost portion of the second spacer pad 280_P2 can be disposed at the same or similar level as an upper surface of the second gate cap pattern 245. The second spacer pad 280_P2 can cover an upper surface of the second source / drain pattern 250. The protection layer 410 can be removed to expose an upper surface of the first source / drain pattern 150 and an upper surface of the first gate cap pattern 145.

[0123] Referring to Figure 16 and Figure 17 The first contact trench T1 and the second contact trench T2 can be formed by a second etching process.

[0124] Specifically, a portion of the first source / drain pattern 150 can be removed by the second etching process, and the first contact trench T1 can be formed. Also, a portion of the second source / drain pattern 250 can be removed by the second etching process, and the second contact trench T2 can be formed. In this case, a portion of the second spacer pad 280_P2 can be removed to form a contact spacer 280.

[0125] The first contact trench T1 can expose the first source / drain pattern 150. The second contact trench T2 can expose the second source / drain pattern 250. The second etching process can be performed using the contact spacer 280 as an etching mask. That is, the second contact trench T2 can be formed between the contact spacers 280. The second etching process can be an etching process using a mask patterned with KrF or ArF as an etching mask.

[0126] As semiconductor devices become smaller, a fine process is required. Accordingly, in a process of forming a contact on a source / drain pattern, a photolithography process using extreme ultraviolet (EUV) can be performed for fine patterning. However, the photolithography process using EUV is expensive, and the manufacturing cost of a semiconductor device can increase. Accordingly, by performing a second etching process using a mask patterned with a KrF or ArF patterning process as an etching mask, the manufacturing cost of a semiconductor device can be reduced.

[0127] On the other hand, with the semiconductor device according to some example embodiments, an etching mask can be patterned with KrF or ArF, which is relatively inexpensive compared to EUV. For example, the protective layer 410 can be formed on the first source / drain pattern 150 by using KrF or ArF. The contact spacer 280 can be formed, and the first contact trench T1 and the second contact trench T2 can also be formed.

[0128] Reference Figure 17 and Figure 18 The first source / drain contact 170 can be formed on the first source / drain pattern 150, and the second source / drain contact 270 can be formed on the second source / drain pattern 250. The first source / drain contact 170 can fill the first contact trench T1. The second source / drain contact 270 can fill the second contact trench T2.

[0129] Reference Figure 2 The upper wiring structure 300 can be formed on the first gate cap pattern 145, the second gate cap pattern 245, the first source / drain contact 170, and the second source / drain contact 270. Accordingly, a semiconductor device according to some example embodiments can be provided.

[0130] Although some example embodiments of the disclosure have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art to which the disclosure belongs that the disclosure can be implemented in other specific forms without changing the technical idea or essential characteristics thereof. Therefore, it should be understood that the above-described example embodiments are illustrative in all aspects and are not restrictive.

Claims

1. A semiconductor device, comprising: Substrate; A first trench pattern on the substrate, the first trench pattern having a first width in a first direction; A first gate electrode extends in a second direction on the first channel pattern, the second direction intersecting the first direction; A first gate cap pattern is formed on the upper surface of the first gate electrode; The second groove pattern is spaced apart from the first groove pattern in the first direction, and the second groove pattern has a second width in the first direction; The second gate electrode extends in the second direction on the second channel pattern; The second gate cap pattern is on the upper surface of the second gate electrode; Source / drain pattern on at least one side of the second channel pattern; The first source / drain contact is connected to the source / drain pattern; The second source / drain contact is spaced apart from the first source / drain contact in the second direction; A contact isolation membrane is located between the first source / drain contact and the second source / drain contact; as well as The first contact spacer is located between the contact isolation membrane and the first source / drain contact. The second width is greater than the first width.

2. The semiconductor device of claim 1, wherein the first contact spacer surrounds at least a portion of the side surface of the first source / drain contact.

3. The semiconductor device of claim 1, wherein the first contact spacer is on the side surface of the second gate cap pattern.

4. The semiconductor device of claim 1, wherein the first source / drain contact overlaps with the second source / drain contact in the second direction.

5. The semiconductor device according to claim 1, wherein... The first source / drain contact includes: The first side surface and the second side surface that are opposite to each other in the first direction, and The third and fourth side surfaces that are opposite to each other in the second direction, and The first contact spacer contacts each of the first side surfaces to the fourth side surfaces that are in contact with the first source / drain electrode.

6. The semiconductor device of claim 1, wherein the bottom surface of the first contact spacer is in contact with the source / drain pattern.

7. The semiconductor device of claim 1, wherein the contact isolation film and the first contact spacer comprise different materials.

8. The semiconductor device according to claim 1, further comprising: The second contact spacer is located between the contact isolation membrane and the second source / drain contact. The second contact spacer surrounds at least a portion of the side surface of the second source / drain contact.

9. The semiconductor device according to claim 1, further comprising: A silicide film is placed between the source / drain pattern and the first source / drain contact.

10. The semiconductor device of claim 1, wherein the width of the contact isolation film in the first direction is greater than the width of the first source / drain contact in the first direction.

11. The semiconductor device of claim 1, further comprising: Gate spacers are located on the side surface of the second gate electrode. The first contact spacer is in contact with the gate spacer.

12. The semiconductor device of claim 1, wherein the distance from the upper surface of the substrate to the upper surface of the first source / drain contact is the same as the distance from the upper surface of the substrate to the upper surface of the first contact spacer.

13. The semiconductor device according to claim 1, wherein The first channel pattern includes a plurality of first patterns spaced apart in a third direction. The second channel pattern includes a plurality of second patterns spaced apart on the third side, and The third direction is perpendicular to the upper surface of the substrate.

14. A semiconductor device, comprising: Substrate; A first trench pattern on the substrate, the first trench pattern having a first width in a first direction; The second groove pattern is spaced apart from the first groove pattern in the first direction, and the second groove pattern has a second width in the first direction; The first source / drain pattern is on at least one side of the first channel pattern; The first source / drain contact is on the first source / drain pattern; The second source / drain pattern is on at least one side of the second channel pattern; The second source / drain contact is on the second source / drain pattern; The third source / drain contact is spaced apart from the second source / drain contact in the second direction, and the second direction intersects the first direction; Contact spacers surround the side surface of the second source / drain contact; as well as A first contact separator is located between the second source / drain contact and the third source / drain contact, and is in contact with the contact spacer. The second width is greater than the first width.

15. The semiconductor device of claim 14, wherein the width of the first source / drain contact in the first direction is smaller than the width of the second source / drain contact in the first direction.

16. The semiconductor device of claim 14, further comprising: The second contact isolation membrane overlaps the side surface of the first source / drain contact on the side surface of the first source / drain contact and in the second direction. The width of the second contact isolation film in the second direction is smaller than the width of the first contact isolation film in the second direction.

17. The semiconductor device of claim 16, wherein the width of the first source / drain contact in the first direction is the same as the width of the second contact isolation film in the first direction.

18. The semiconductor device of claim 14, further comprising: A gate electrode is located on the second channel pattern and extends in the second direction; as well as Gate spacers, on the side surface of the gate electrode. At least a portion of the contact spacer is located between the gate spacer and the second source / drain contact.

19. The semiconductor device of claim 18, further comprising: Gate cap pattern on the upper surface of the gate electrode, The upper surface of the gate cap pattern is on the same plane as the upper surface of the second source / drain contact.

20. A semiconductor device, comprising: Substrate; A first trench pattern on the substrate, the first trench pattern having a first width in a first direction; A first gate electrode extends in a second direction on the first channel pattern, the second direction intersecting the first direction; A first gate cap pattern is formed on the upper surface of the first gate electrode; The second channel pattern is spaced apart from the first channel pattern in the first direction, and the second channel pattern has a second width in the first direction that is greater than the first width; The second gate electrode extends in the second direction on the second channel pattern; The second gate cap pattern is on the upper surface of the second gate electrode; Gate spacers are located on the side surface of the second gate electrode; Source / drain pattern on at least one side of the second channel pattern; The first source / drain contact is on the source / drain pattern; The second source / drain contact is spaced apart from the first source / drain contact in the second direction; A contact isolation membrane is located between the first source / drain contact and the second source / drain contact; as well as A contact spacer is located between the contact isolation membrane and the first source / drain contact. The contact spacer surrounds at least a portion of the side surface of the first source / drain contact, and At least a portion of the contact spacer is in contact with the side surface of the gate cover pattern.

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