Inverter and bus capacitance detection method and device thereof
By controlling the start-up time of the three-phase inverter output channels to be not completely the same, and utilizing the bus voltage ripple during three-phase imbalance, the problem of low accuracy in three-phase inverter bus capacitor detection is solved, achieving higher detection accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KEHUA DATA CO LTD
- Filing Date
- 2025-11-21
- Publication Date
- 2026-04-10
AI Technical Summary
In existing technologies, the accuracy of bus capacitor detection in three-phase inverters is low and cannot be effectively improved.
By controlling the start-up time of the three-phase output channels of the inverter to make them not exactly the same, and by performing bus capacitance detection during the start-up process, the increased bus voltage ripple during three-phase imbalance is utilized to improve detection accuracy.
It significantly improves the accuracy of bus capacitor detection in three-phase inverters and increases the accuracy of capacitor detection.
Smart Images
Figure CN121831271A_ABST
Abstract
Description
Cross-references to related applications
[0001] This application is based on and claims priority to Chinese Patent Application No. 202511402548.3, filed on September 28, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of circuit testing technology, and in particular to an inverter and a method and apparatus for detecting its bus capacitance. Background Technology
[0003] In related technologies, the detection of bus capacitance is usually achieved by superimposing a triangular wave onto the bus voltage, i.e., by charging and discharging the bus, thus creating the charging and discharging process of the capacitor, and thereby performing capacitance detection based on this to improve detection accuracy.
[0004] However, for three-phase inverters, since the bus voltage is stable with minimal fluctuations, it is impossible to control the DC bus voltage to generate charging and discharging characteristics. Therefore, there is currently a lack of effective means to improve the accuracy of capacitor detection in three-phase inverters. Summary of the Invention
[0005] This application provides an inverter and its bus capacitor detection method and apparatus, which can improve the accuracy of capacitor detection for three-phase inverters.
[0006] The technical solution of this application embodiment is implemented as follows: This application provides a method for detecting the bus capacitance of an inverter, wherein the input terminal of the inverter is connected to a DC bus, and a bus capacitor is connected between the two poles of the DC bus. The method includes: During the power-on process of the inverter, the start-up time of the three-phase output channels of the inverter is controlled so that the start-up time of the three-phase output channels is not exactly the same; the three-phase output channels are used by the inverter to supply power to the load; The bus capacitor is detected after the first output channel is started and before the second output channel is started; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.
[0007] In some embodiments, controlling the start-up time of the three-phase output channels of the inverter includes: Each output channel of the three-phase output channel is started sequentially; The startup time of the output channel that is started later is after the output channel of the previous startup has completed its startup.
[0008] In some embodiments, the method further includes: After the inverter is powered on, at least one of the three-phase output channels is adjusted so that the effective values of the electrical parameters on the three-phase output channels are not completely the same. When the effective values of the electrical parameters on the three-phase output channels are not completely the same, the bus capacitance is detected.
[0009] In some embodiments, adjusting at least one of the three-phase output channels includes: Shut down one or two of the three-phase output channels.
[0010] In some embodiments, the load includes three load input terminals respectively connected to the three-phase output channel; the method further includes: From the three load input terminals, determine the target load input terminal; the target load input terminal is the load input terminal connected to the closed output channel; Switch the target load input terminal from being connected to the corresponding output channel to being connected to the target power supply circuit.
[0011] In some embodiments, adjusting at least one phase output channel of the three-phase output channels of the inverter includes: The output voltage value of at least one phase output channel in the three-phase output channels is adjusted.
[0012] In some embodiments, the inverter includes three bridge arms, with the output terminal of each bridge arm located on a single phase output channel; adjusting the output voltage value of at least one phase output channel among the three phase output channels includes: The duty cycle of the power switch of at least one bridge arm is adjusted to adjust the output voltage value of the corresponding output channel at the corresponding output terminal.
[0013] In some embodiments, adjusting the output voltage value of at least one phase output channel in the three-phase output channels includes: Increase the output voltage value of the first output channel by the target value, and decrease the output voltage value of the second output channel by the target value; the first output channel and the second output channel are any two of the three-phase output channels.
[0014] In some embodiments, the method further includes: In response to the completion of the bus capacitor detection, the three-phase output channels of the inverter are adjusted so that the effective values of the electrical parameters on each phase output channel are the same.
[0015] This application provides a bus capacitor detection device for an inverter, wherein the input terminal of the inverter is connected to a DC bus, and a bus capacitor is connected between the two poles of the DC bus. The device includes: The control module is used to control the start-up time of the three-phase output channels of the inverter during the power-on process, so that the start-up time of the three-phase output channels is not completely the same; the three-phase output channels are used by the inverter to supply power to the load. The detection module is used to detect the bus capacitor after the first output channel has started up and before the second output channel has started up; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.
[0016] In some embodiments, the control module is further configured to sequentially start each output channel of the three-phase output channel; wherein the start time of the output channel started later is after the start time of the output channel started earlier.
[0017] In some embodiments, the device further includes: an adjustment module, configured to adjust at least one of the three-phase output channels after the inverter is powered on, so that the effective values of the electrical parameters on the three-phase output channels are not completely the same; and to detect the bus capacitor when the effective values of the electrical parameters on the three-phase output channels are not completely the same.
[0018] In some embodiments, the adjustment module is further configured to shut down one or two of the three-phase output channels.
[0019] In some embodiments, the load includes three load input terminals respectively connected to the three-phase output channel; the adjustment module is further configured to determine a target load input terminal from the three load input terminals; the target load input terminal is a load input terminal connected to a closed output channel; and switch the target load input terminal from a state connected to the corresponding output channel to a state connected to the target power supply circuit.
[0020] In some embodiments, the adjustment module is further configured to adjust the output voltage value of at least one of the three-phase output channels.
[0021] In some embodiments, the inverter includes three bridge arms, with the output terminal of each bridge arm located on a phase output channel; the adjustment module is further configured to adjust the duty cycle of the power switch of at least one bridge arm to adjust the output voltage value of the corresponding output channel.
[0022] In some embodiments, the adjustment module is further configured to increase the output voltage value of the first output channel by a target value and decrease the output voltage value of the second output channel by the target value; the first output channel and the second output channel are any two phase output channels among the three-phase output channels.
[0023] This application provides an inverter, which is connected to a detection circuit. The input terminal of the inverter is connected to a DC bus, and a bus capacitor is connected between the two poles of the DC bus. The detection circuit is used to control the start-up time of the three-phase output channels of the inverter during the power-on process, so that the start-up times of the three-phase output channels are not completely the same; the three-phase output channels are used by the inverter to supply power to the load. The bus capacitor is detected after the first output channel is started and before the second output channel is started; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.
[0024] This application provides a computer-readable storage medium storing executable instructions, which, when executed by a processor, implement the inverter bus capacitance detection method provided in this application.
[0025] This application provides a computer program product storing a computer program that, when executed by a processor, implements the inverter bus capacitance detection method provided in this application.
[0026] The embodiments of this application have the following beneficial effects: By controlling the start-up time of the three-phase output channels of the inverter during the power-on process, the start-up time of the three-phase output channels is not completely the same, so that three-phase imbalance occurs during the start-up process of the three-phase output channels (i.e. after the first output channel has started up and before the second output channel has started up), thereby increasing the bus voltage ripple. During this process, bus capacitance monitoring is performed, which significantly improves the accuracy of capacitance detection. Attached Figure Description
[0027] Figure 1 This is an optional structural schematic diagram of the inverter provided in the embodiments of this application; Figure 2 This is a schematic diagram of an optional circuit structure of the inverter provided in an embodiment of this application; Figure 3 This is an optional flowchart illustrating the inverter bus capacitance detection method provided in this application embodiment; Figure 4AThis is an optional structural diagram of the load power supply circuit provided in an embodiment of this application; Figure 4B This is an optional structural diagram of the load power supply circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of an optional circuit structure of the inverter provided in an embodiment of this application; Figure 6 This is an optional structural schematic diagram of the bus capacitance detection device for the inverter provided in the embodiments of this application. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0030] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0032] This application provides an inverter and its bus capacitor detection method and apparatus, which can improve the accuracy of capacitor detection for three-phase inverters.
[0033] First, the inverter provided in the embodiments of this application will be described, see [link to relevant documentation]. Figure 1 , Figure 1This is an optional structural diagram of the inverter provided in this application embodiment. The inverter 110 is connected to a detection circuit 120. The input terminal of the inverter 110 is connected to a DC bus 130, and a bus capacitor 140 is connected between the two poles of the DC bus 130. The detection circuit 120 is used to control the startup time of the three-phase output channels 111, 112, and 113 of the inverter 110 during power-on, so that the startup times of the three-phase output channels 111, 112, and 113 are not completely identical. The three-phase output channels 111, 112, and 113 are used by the inverter 110 to supply power to the load 150. The bus capacitor 140 is detected after the first output channel has started up and before the second output channel has started up. The first output channel is the output channel with the earliest startup time among the three-phase output channels, and the second output channel is the output channel with the latest startup time among the three-phase output channels.
[0034] In some embodiments, the inverter 110 includes three bridge arms, specifically a first bridge arm 1101, a second bridge arm 1102, and a third bridge arm 1103. Each bridge arm is used to convert direct current (DC) to alternating current (AC). The phase difference between each pair of output voltages of each bridge arm is the same, for example, 120°. The output terminal of the first bridge arm 1101 is located on output channel 111. The output terminal of the second bridge arm 1102 is located on output channel 112. The output terminal of the third bridge arm 1103 is located on output channel 113.
[0035] For example, see Figure 2 , Figure 2 This is a schematic diagram of an optional circuit structure of the inverter provided in an embodiment of this application. Capacitor C1 is the bus capacitor 140. Here, the first bridge arm 1101 includes a first power switch Q1 and a second power switch Q2 connected between the two poles of the DC bus, with output terminal 1104 located on the connection line between the first power switch Q1 and the second power switch Q2. The second bridge arm 1102 includes a third power switch Q3 and a fourth power switch Q4, with output terminal 1105 located on the connection line between the third power switch Q3 and the fourth power switch Q4. The third bridge arm 1103 includes a fifth power switch Q5 and a sixth power switch Q6, with output terminal 1106 located on the connection line between the fifth power switch Q5 and the sixth power switch Q6.
[0036] In some embodiments, see Figure 1The DC bus 130 can be connected to the output terminal of a DC power supply, which supplies power to the inverter 110. In some embodiments, the detection circuit 120 is also connected to both ends of the bus capacitor 140 to obtain the capacitor voltage and capacitor current of the bus capacitor 140, and to determine the capacitance value of the bus capacitor 140 based on the capacitor voltage and capacitor current, so as to monitor the capacitance value of the bus capacitor 140.
[0037] The method for detecting the bus capacitance of an inverter provided in this application will be described below. See also... Figure 3 , Figure 3 This is an optional flowchart illustrating the inverter bus capacitance detection method provided in this application embodiment, which will be combined with... Figure 3 The steps shown are explained.
[0038] Step 301: During the power-on process of the inverter, the start-up time of the three-phase output channels of the inverter is controlled so that the start-up time of the three-phase output channels is not completely the same; the three-phase output channels are used by the inverter to supply power to the load. Step 302: After the first output channel is started and before the second output channel is started, the bus capacitor is detected; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.
[0039] In this embodiment, during the power-on startup phase of the inverter, the detection circuit controls the startup time of the three-phase output channels. In some embodiments, the startup time of one output channel can be controlled to be different from the startup times of the other two output channels, or the startup times of all three output channels can be controlled to be different. In this embodiment, after all three output channels have started up, the effective values of the three-phase output voltages are the same, and the phase difference between any two phases of the three-phase output voltages is the same, for example, 120°. Here, the startup time of each output channel is achieved by controlling the startup time of the corresponding bridge arm.
[0040] In this embodiment, startup control is achieved by controlling the power switches in the corresponding bridge arms. That is, by controlling the startup time of the power switches in the bridge arms, the startup times of the three bridge arms are not exactly the same, thereby ensuring that the startup times of the three-phase output channels are not exactly the same.
[0041] In some embodiments, one of the three output channels may have a different control loop than the other two. The different control loops involved in this embodiment are intended to achieve control through different control loops, not that the control loop types cannot be the same. For example, in other embodiments, the three-phase output channels are started through three independent control loops. These independent control loops can be of the same type, such as using voltage and current dual loops to control each output channel. After each phase output channel is started, the phase of the output voltage of that phase output channel is detected. When the next control loop starts the corresponding output channel, the phase difference between the output voltage of the output channel after the current start and the output voltage of the output channel after the previous start is made to conform to a preset phase difference. Here, the preset phase difference is 120°. In some embodiments, each control loop can gradually drive the opening of the corresponding bridge arm through a pulse width modulation (PWM) signal to achieve a soft start of the inverter's three-phase output channels. The time for the control bridge arm to complete the opening can be, for example, 1-10 seconds.
[0042] In this embodiment, the bus capacitor is detected after the first output channel in the three-phase output channels has started up and before the last output channel has started up. This is to improve the accuracy of the bus capacitor detection by taking advantage of the large three-phase unbalanced bus voltage ripple during this stage. In this embodiment, the bus capacitor can be detected once during each inverter startup process using the method provided in this embodiment, thereby achieving state monitoring of the inverter bus capacitor.
[0043] In this embodiment of the application, by controlling the start-up time of the three-phase output channels of the inverter during the power-on process, the start-up time of the three-phase output channels is not completely the same, so that three-phase imbalance occurs during the start-up process of the three-phase output channels (i.e. after the first output channel has finished starting and before the second output channel has finished starting), thereby increasing the bus voltage ripple, and bus capacitance monitoring is performed during this process, so that the accuracy of capacitance detection is significantly improved.
[0044] In some optional embodiments, controlling the start-up time of the three-phase output channels of the inverter includes: sequentially starting each output channel of the three-phase output channels; wherein the start-up time of the output channel started later is after the start-up time of the output channel started earlier.
[0045] In this embodiment, the three-phase output channels are started sequentially with a slow start. The next output channel starts only after the previous one has completed its startup, thus completing the startup of all three phase output channels and maximizing the startup time to allow for capacitor detection during this period. It should be understood that in this embodiment, the three-phase output channels are controlled to start through three different control loops.
[0046] In some optional embodiments, after the inverter is powered on, at least one of the three-phase output channels of the inverter is adjusted so that the effective values of the electrical parameters on the three-phase output channels are not completely the same; the three-phase output channels are used by the inverter to supply power to the load; when the effective values of the electrical parameters on the three-phase output channels are not completely the same, the bus capacitor is detected.
[0047] In some embodiments, bus capacitance detection can be performed at any time after the inverter is powered on and while the inverter is in operation, in response to the achievement of a preset condition, after adjusting at least one phase output channel. Here, the preset condition may be, for example, reaching a preset detection time. In some embodiments, bus capacitance detection can be performed periodically, in which case at least one phase output channel can be adjusted and bus capacitance detection can be performed in response to the arrival of a preset period. Periodic detection is used to monitor the state of the inverter's bus capacitance regularly.
[0048] It should be noted that before adjusting the three-phase output channels, the inverter's three-phase output channels are in a three-phase balanced state, and the effective values of the electrical parameters on the three-phase output channels are the same. Here, the electrical parameters can be phase voltage, line voltage, line current, or phase current. In this embodiment, when adjusting the output channels, the corresponding output channels can be adjusted by adjusting the bridge arms of the inverter corresponding to the output channels.
[0049] In some embodiments, only one phase output channel can be adjusted to change the effective value of the electrical parameters of the adjusted phase output channel, so that the effective value of the electrical parameters of the adjusted phase output channel is different from the effective value of the electrical parameters of the remaining two unadjusted phase output channels.
[0050] In some embodiments, the effective values of the electrical parameters on two-phase output channels can be adjusted to change the effective values of the electrical parameters on those two-phase output channels. In some embodiments, after adjusting the two-phase output channels, the effective values of the electrical parameters on those two-phase output channels may be the same, and different from the effective values of the electrical parameters on the unadjusted remaining phase output channel. In other embodiments, after adjusting the two-phase output channels, the effective values of the electrical parameters on those two-phase output channels are different from each other, and also different from the effective values of the electrical parameters on the unadjusted remaining phase output channel; that is, the effective values of the electrical parameters on all three-phase output channels are different.
[0051] In some embodiments, the three-phase output channels can be adjusted to change the effective values of the electrical parameters of the three-phase output channels, so that the effective values of the electrical parameters on the three-phase output channels are not completely the same.
[0052] In this embodiment, if the effective values of the electrical parameters on the three-phase output channels are not completely identical, the bus capacitor is then detected. In actual implementation, in response to the completion of the adjustment of at least one of the three-phase output channels of the inverter, the detection circuit is connected to both ends of the bus capacitor, so that the detection circuit detects the voltage and current of the bus capacitor, thereby performing capacitance detection.
[0053] It is understood that, in the embodiments of this application, when the inverter is in operation, at least one of the three-phase output channels of the inverter is adjusted so that the effective values of the electrical parameters on the three-phase output channels are not completely the same, thereby constructing a three-phase output imbalance, increasing the bus voltage ripple, and thus significantly improving the accuracy of capacitor detection based on this.
[0054] In some optional embodiments, adjusting at least one of the three-phase output channels of the inverter includes adjusting the output voltage value of at least one of the three-phase output channels.
[0055] In this embodiment, the output voltage value of at least one phase output channel is adjusted so that the output voltage values of the three phase output channels are not completely identical. In some embodiments, the adjustment of the output voltage value can increase or decrease the output voltage value. The magnitude of the effective output value between different phases can be determined according to the unbalance that the load can accept, such as a phase difference of 10%, 15%, 20%, 50%, etc.
[0056] In some embodiments, the output voltage value of only one phase output channel may be adjusted to make its output voltage value different from the output voltage values of the other two phase output channels. In some embodiments, the output voltage values of two phase output channels may be adjusted by the same adjustment value, thus making their output voltage values different from the output voltage value of the remaining phase output channel. Alternatively, the adjustment values of two phase output channels may be different, thus making the output voltage values of all three phase output channels different. In some embodiments, the output voltage values of all three phase output channels may be adjusted by different adjustment values, or two phases may have the same adjustment value that differs from the adjustment value of the remaining phase.
[0057] In some optional embodiments, adjusting at least one of the three-phase output channels includes: shutting down one or two of the three-phase output channels.
[0058] In this embodiment, one or two phases of the inverter's three-phase output channels can be shut down, preventing the shut-down output channels from outputting voltage. This results in the inverter's three-phase voltage output becoming either two-phase or one-phase, thus creating a three-phase output imbalance. It should be understood that the effective value of the electrical parameters corresponding to the shut-down output channel is 0. In some embodiments, shutting down the output channel for at least one phase can be achieved by stopping the PWM drive signal of the bridge arm corresponding to that phase, or by blocking the path of at least one phase output channel, thereby achieving an effective value of 0 for the corresponding output channel. Here, the PWM drive signal is issued by the corresponding control loop.
[0059] In some optional embodiments, the load includes three load input terminals respectively connected to the three-phase output channel; the method further includes: determining a target load input terminal from the three load input terminals; the target load input terminal is a load input terminal connected to a closed output channel; and switching the target load input terminal from a state connected to the corresponding output channel to a state connected to a target power supply circuit. The target power supply circuit can be a bypass power supply, and the input terminal of the bypass power supply is connected to an AC power source, which can be the power grid or a diesel generator, etc., and is not limited thereto.
[0060] In this embodiment, the load input terminal connected to the closed output channel is denoted as the target load input terminal. If the number of closed output channels is one phase, then there is one corresponding target load input terminal; if the number of closed output channels is two phases, then there are two corresponding target load input terminals. Here, the target load input terminal is switched from being connected to the closed output channel to being connected to the target power supply circuit. In this embodiment, the target power supply circuit is a three-phase circuit capable of providing three-phase voltage. The target power supply circuit includes three-phase output terminals, each providing one phase voltage. In some embodiments, there is a correspondence between the three-phase output terminals of the target power supply circuit and the three-phase output channels of the inverter, with the corresponding output terminals and output channels having at least the same phase angle. In this embodiment, when switching the connection of the target load input terminal, the target load input terminal is switched to the output terminal of the target power supply circuit corresponding to the closed input channel. In this embodiment, by switching at least one load input terminal connected to the closed at least one phase output channel to be connected to the target power supply circuit after closing at least one phase output channel, damage to the load due to phase loss is avoided.
[0061] In some embodiments, exemplarily, see Figure 4A , Figure 4A This is an optional structural diagram of the load power supply circuit provided in this application embodiment. Both the inverter 110 and the target power supply circuit 410 are connected to the load 150 via a switching module 400. The switching module 400 is used to switch the connection state between the inverter 110, the target power supply circuit 410, and the load 150. The detection circuit 120 is connected to the switching module 400 and is used to control the on / off state of the switching module 400. The load 150 includes three load input terminals: a first load input terminal 151, a second load input terminal 152, and a third load input terminal 153.
[0062] Before adjusting the inverter's output channels, the first output channel 111 is connected to the first load input terminal 151, the second output channel 112 is connected to the second load input terminal 152, and the third output channel 113 is connected to the third load input terminal 153.
[0063] The target power supply circuit 410 includes three-phase output terminals: a first output terminal 411, a second output terminal 412, and a third output terminal 413. The first output terminal 411 corresponds to the first output channel 111, the second output terminal 412 corresponds to the second output channel 112, and the third output terminal 413 corresponds to the third output channel 113. In some embodiments, if at least one phase output channel is closed, including the first output channel 111, the switch module 400 disconnects the connection between the first output channel 111 and the first load input terminal 151, and connects the first output terminal 411 to the first load input terminal 151.
[0064] In some alternative embodiments, see Figure 4B , Figure 4B This is an optional structural diagram of the load power supply circuit provided in an embodiment of this application. Here, the switch module 400 includes six switches, namely, a first switch 401 to a sixth switch 406. Specifically, the first switch 401 is connected between the first bridge arm 1101 and the first load input terminal 151; the second switch 402 is connected between the second bridge arm 1102 and the second load input terminal 152; the third switch 403 is connected between the third bridge arm 1103 and the third load input terminal 153; the fourth switch 404 is connected between the first output terminal 411 and the first load input terminal 151; the fifth switch 405 is connected between the second output terminal 412 and the second load input terminal 152; and the sixth switch 406 is connected between the third output terminal 413 and the third load input terminal 153. In this embodiment, each output channel is provided with a corresponding switch module for individual adjustment. In this embodiment, the detection circuit 120 is connected to the first switch 401 to the sixth switch 406 respectively, and is used to control the on / off state of each switch to realize the switching of the connection state between each output channel of the inverter 110 and each output terminal of the target power supply circuit 410 and each load input terminal of the load 150. In some embodiments, see Figure 5 , Figure 5 This is a schematic diagram of an optional circuit structure of the inverter provided in an embodiment of this application. SCR1 to SCR6 correspond to the first switch 401 to the sixth switch 406, respectively.
[0065] In some optional embodiments, the inverter includes three bridge arms, each with its output terminal located on a phase output channel; adjusting the output voltage value of at least one phase output channel of the three phase output channels includes: adjusting the duty cycle of the power switch of at least one bridge arm to adjust the output voltage value of the output channel corresponding to the corresponding output terminal.
[0066] See Figure 1 and Figure 2 In practical implementation, the output voltage of the output channel containing at least one bridge arm is adjusted by regulating the duty cycle of the power switch. In real-world scenarios, there is a corresponding relationship between the power switch duty cycle and the output voltage value; for example, it can be positively or negatively correlated. Based on this relationship, the duty cycle of the power switch is adjusted accordingly to increase or decrease the output voltage value of the corresponding output channel.
[0067] In some optional embodiments, adjusting the output voltage value of at least one phase output channel of the three-phase output channels includes: increasing the output voltage value of the first output channel by a target value and decreasing the output voltage value of the second output channel by the target value; the first output channel and the second output channel are any two phase output channels of the three-phase output channels.
[0068] In this embodiment, the output voltage values of two phases in the three-phase output channels are adjusted. Specifically, the output voltage value of the first output channel is increased by a target value, and the output voltage value of the second output channel is decreased by a target value, while the output voltage value of the third output channel is not adjusted. By adjusting the output voltage values of two phases in the three-phase output channels by increasing and decreasing the target values, the overall voltage balance of the three-phase output voltage is maintained before and after the adjustment, avoiding any impact on the power supply to the load. Here, the adjustment of increasing and decreasing the target values can be achieved by adjusting the duty cycle of the corresponding power switches.
[0069] In some alternative embodiments, the method further includes: in response to the end of bus capacitor detection, adjusting the three-phase output channels of the inverter so that the effective values of the electrical parameters on each phase output channel are the same.
[0070] In this embodiment, in response to the end of bus capacitor detection, the three-phase output channels of the inverter are restored to have the same effective values of electrical parameters. In some embodiments, at least one output channel may be restored from a closed state to an open state, and restored to supplying power to the load through the three-phase output channels of the inverter. In other embodiments, the output voltage value of at least one output channel may be restored from the adjusted value to the value before adjustment, so that the output voltage values of the three-phase output channels are the same.
[0071] In this embodiment, the adjustment of at least one of the three-phase output channels of the inverter can begin immediately after the inverter transitions from a shutdown state to an operating state. In some embodiments, the adjustment can also be performed during the inverter's operating state in response to the arrival of a preset period. The preset period can be, for example, 30-120 minutes. Those skilled in the art can set the preset period based on actual needs, and this application does not specifically limit this.
[0072] In some alternative embodiments, after the detection of the bus capacitor is completed, the three-phase output channels can also be kept in the adjusted state throughout the operation of the inverter, that is, the effective values of the electrical parameters of the three-phase output channels are not completely the same.
[0073] The following continues to describe the inverter bus capacitance detection device provided in the embodiments of this application. In some embodiments, such as... Figure 6 As shown, Figure 6 This is an optional structural diagram of the inverter bus capacitance detection device provided in the embodiments of this application. The device 600 includes: The control module 601 is used to control the start-up time of the three-phase output channels of the inverter during the power-on process, so that the start-up time of the three-phase output channels is not completely the same; the three-phase output channels are used by the inverter to supply power to the load. The detection module 602 is used to detect the bus capacitor after the first output channel has been started and before the second output channel has been started; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.
[0074] In some embodiments, the control module 601 is further configured to sequentially start each output channel of the three-phase output channel; wherein the start time of the output channel started later is after the start time of the output channel started earlier.
[0075] In some embodiments, the device further includes: an adjustment module 603, configured to adjust at least one of the three-phase output channels after the inverter is powered on, so that the effective values of the electrical parameters on the three-phase output channels are not completely the same; and to detect the bus capacitor when the effective values of the electrical parameters on the three-phase output channels are not completely the same.
[0076] In some embodiments, the adjustment module 603 is further configured to shut down one or two of the three-phase output channels.
[0077] In some embodiments, the load includes three load input terminals respectively connected to the three-phase output channel; the adjustment module 603 is further configured to determine a target load input terminal from the three load input terminals; the target load input terminal is a load input terminal connected to a closed output channel; and switch the target load input terminal from a state connected to the corresponding output channel to a state connected to the target power supply circuit.
[0078] In some embodiments, the adjustment module 603 is further configured to adjust the output voltage value of at least one phase output channel in the three-phase output channels.
[0079] In some embodiments, the inverter includes three bridge arms, with the output terminal of each bridge arm located on a phase output channel; the adjustment module 603 is also used to adjust the duty cycle of the power switch of at least one bridge arm to adjust the output voltage value of the output channel corresponding to the corresponding output terminal.
[0080] In some embodiments, the adjustment module 603 is further configured to increase the output voltage value of the first output channel by a target value and decrease the output voltage value of the second output channel by the target value; the first output channel and the second output channel are any two of the three-phase output channels.
[0081] In some embodiments, the apparatus further includes a response module 604, configured to adjust the three-phase output channels of the inverter so that the effective values of the electrical parameters on each phase output channel are the same in response to the completion of the bus capacitor detection.
[0082] It should be noted that the description of the apparatus in this application embodiment is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment, so it will not be repeated.
[0083] This application provides an inverter connected to a detection circuit. The inverter's input terminal is connected to a DC bus, and a bus capacitor is connected between the two poles of the DC bus. The detection circuit controls the startup time of the inverter's three-phase output channels during power-on, ensuring that the startup times of the three-phase output channels are not identical. The three-phase output channels are used by the inverter to supply power to a load. The bus capacitor is detected after the first output channel has finished starting and before the second output channel has finished starting. The first output channel is the output channel with the earliest startup time among the three-phase output channels, and the second output channel is the output channel with the latest startup time among the three-phase output channels.
[0084] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the inverter bus capacitance detection method described above in this application embodiment.
[0085] This application provides a computer-readable storage medium storing executable instructions. When the executable instructions are executed by a processor, the processor will execute the inverter bus capacitance detection method provided in this application.
[0086] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.
[0087] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.
[0088] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).
[0089] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.
[0090] In summary, the embodiments of this application can improve the accuracy of capacitor detection in three-phase inverters.
[0091] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.
Claims
1. A method for detecting the bus capacitance of an inverter, characterized in that, The input terminal of the inverter is connected to a DC bus, and a bus capacitor is connected between the two poles of the DC bus. The method includes: During the power-on process of the inverter, the start-up time of the three-phase output channels of the inverter is controlled so that the start-up time of the three-phase output channels is not exactly the same; the three-phase output channels are used by the inverter to supply power to the load; The bus capacitor is detected after the first output channel is started and before the second output channel is started; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.
2. The method according to claim 1, characterized in that, The start-up time of the three-phase output channels of the inverter is controlled, including: Each output channel of the three-phase output channel is started sequentially; The startup time of the output channel that is started later is after the output channel of the previous startup has completed its startup.
3. The method according to claim 1, characterized in that, The method further includes: After the inverter is powered on, at least one of the three-phase output channels is adjusted so that the effective values of the electrical parameters on the three-phase output channels are not completely the same. When the effective values of the electrical parameters on the three-phase output channels are not completely the same, the bus capacitance is detected.
4. The method according to claim 3, characterized in that, The adjustment of at least one phase output channel among the three phase output channels includes: Shut down one or two of the three-phase output channels.
5. The method according to claim 4, characterized in that, The load includes three load input terminals respectively connected to the three-phase output channel; the method further includes: From the three load input terminals, determine the target load input terminal; the target load input terminal is the load input terminal connected to the closed output channel; Switch the target load input terminal from being connected to the corresponding output channel to being connected to the target power supply circuit.
6. The method according to claim 3, characterized in that, The adjustment of at least one phase output channel in the three-phase output channels of the inverter includes: The output voltage value of at least one phase output channel in the three-phase output channels is adjusted.
7. The method according to claim 6, characterized in that, The inverter includes three bridge arms, with the output terminal of each bridge arm located on a single phase output channel; adjusting the output voltage value of at least one phase output channel among the three phase output channels includes: The duty cycle of the power switch of at least one bridge arm is adjusted to adjust the output voltage value of the corresponding output channel.
8. The method according to claim 6 or 7, characterized in that, The adjustment of the output voltage value of at least one phase output channel in the three-phase output channels includes: The output voltage value of the first output channel is increased by a target value, and the output voltage value of the second output channel is decreased by the target value; the first output channel and the second output channel are any two of the three-phase output channels.
9. A bus capacitance detection device for an inverter, characterized in that, The input terminal of the inverter is connected to a DC bus, and a bus capacitor is connected between the two poles of the DC bus. The device includes: The control module is used to control the start-up time of the three-phase output channels of the inverter during the power-on process, so that the start-up time of the three-phase output channels is not completely the same; the three-phase output channels are used by the inverter to supply power to the load. The detection module is used to detect the bus capacitor after the first output channel has started up and before the second output channel has started up; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.
10. An inverter, characterized in that, The inverter is connected to the detection circuit, the input terminal of the inverter is connected to the DC bus, and a bus capacitor is connected between the two poles of the DC bus. The detection circuit is used to control the start-up time of the three-phase output channels of the inverter during the power-on process, so that the start-up times of the three-phase output channels are not completely the same; the three-phase output channels are used by the inverter to supply power to the load. The bus capacitor is detected after the first output channel is started and before the second output channel is started; the first output channel is the output channel with the earliest start time among the three-phase output channels, and the second output channel is the output channel with the latest start time among the three-phase output channels.