Band-gap reference circuit
By introducing a startup circuit, a bias circuit, and a process angle and temperature compensation circuit into the bandgap reference circuit, the problems of process angle differences and temperature drift are solved, the reference voltage is optimized, temperature drift is reduced, and adjustment costs are saved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-04-10
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Conventional bandgap reference circuits exhibit significant differences in reference voltage at different process angles, requiring additional adjustment circuitry. Furthermore, the temperature drift of first-order bandgap reference circuits is determined by the temperature drift characteristics of the process itself, making temperature compensation difficult in high-precision bandgap reference circuits.
Design a bandgap reference circuit, including a bandgap reference core circuit, a startup circuit, a bias circuit, and a process corner and temperature compensation circuit. The startup circuit provides a startup signal, the bias circuit provides bias and comparison voltages, the process corner and temperature compensation circuit generates high-temperature and low-temperature compensation currents, and the resistance value is adjusted to optimize the reference voltage and reduce temperature drift.
The bandgap reference voltage under different process angles was optimized, the temperature drift characteristics of the bandgap reference voltage were reduced, the cost of subsequent manual adjustment was reduced, and the voltage was made approximately equal under different process angles.
Smart Images
Figure CN121832689A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a bandgap reference circuit. BACKGROUND
[0002] The bandgap reference circuit is an indispensable basic module in the semiconductor integrated circuit, and is used for generating a reference voltage independent of temperature and power voltage, and is the core of the internal voltage signal of a chip. However, the conventional bandgap reference circuit has a relatively obvious difference in reference voltage under different process corners, and needs an additional trimming circuit to adjust the deviation of different process corners, and the temperature drift of the conventional first-order bandgap reference circuit is usually determined by the temperature drift characteristics of the process itself, so that a temperature compensation circuit is needed to optimize the temperature drift curve in the high-precision bandgap reference circuit. SUMMARY
[0003] The technical problem to be solved by the present application is to provide a bandgap reference circuit to overcome the above-mentioned deficiencies in the prior art.
[0004] The technical solution for solving the above technical problem is as follows: a bandgap reference circuit, comprising a bandgap reference core circuit, a start-up circuit, a bias circuit and a process corner and temperature compensation circuit; the start-up circuit is electrically connected with the bandgap reference core circuit and the bias circuit respectively, and the bias circuit is electrically connected with the process corner and temperature compensation circuit; The bandgap reference core circuit is used for generating a zero-temperature-coefficient reference voltage Vref by adding positive and negative temperature coefficient voltages. The start-up circuit is used for providing a start-up signal for the bandgap reference core circuit. The bias circuit is used for providing bias for the start-up circuit and the process corner and temperature compensation circuit, and providing a comparison voltage Vcomp for the process corner and temperature compensation circuit. The process corner and temperature compensation circuit is used for generating a high-temperature compensation current or a low-temperature compensation current acting on the bandgap reference core circuit by comparing a reference signal with a comparison signal, and detecting the resistance value of the fast and slow process corner adjustment bandgap reference core circuit, so as to make the reference voltage rise or fall.
[0005] The beneficial effects of this invention are as follows: Based on the core of the bandgap reference circuit, this invention designs a startup circuit, a bias circuit, and a process angle and temperature compensation circuit; wherein: the startup circuit is connected to the core bandgap reference circuit; the startup circuit is connected to the bias circuit; the startup circuit provides a startup signal for the core bandgap reference circuit; the core bandgap reference circuit is connected to the bias circuit and the process angle and temperature compensation circuit; the core bandgap reference circuit generates a zero temperature coefficient reference voltage by adding positive and negative temperature coefficient voltages; the bias circuit is connected to the process angle and temperature compensation circuit; the bias circuit provides bias for the startup circuit, the process angle and temperature compensation circuit, and provides a comparison voltage for the process angle and temperature compensation circuit; the process angle and temperature compensation circuit generates high-temperature compensation current and low-temperature compensation current respectively through the comparison reference signal and the comparison signal, which act on the core bandgap reference circuit, and detects the fast and slow process angles to adjust the resistance value of the core bandgap reference circuit, thereby realizing the rise or fall of the reference voltage. This invention optimizes the bandgap reference voltage under different process angles and reduces the temperature drift characteristics of the bandgap reference voltage.
[0006] Based on the above technical solution, the present invention can be further improved as follows.
[0007] Furthermore, the core circuit of the bandgap reference includes transistors Q1 and Q2, resistors R1, R2, R3, and R4, PMOS transistors PM11 and PM12, and NMOS transistor NM11. The source of PM11 is electrically connected to the source of PM12 and connected to the startup circuit. The drain of PM11 is connected to the gate of NM11 and the collector of Q2. The gate of PM11 is electrically connected to the gate of PM12, the drain of PM12, and the collector of Q1 and connected to the startup circuit. The source of NM11 is connected to the base of Q1 and the base of Q2. The drain of NM11 is connected to the power supply VDD. The emitter of Q1 is electrically connected to one end of R1, and the other end of R1 is electrically connected to the emitter of Q2, one end of R3, and the bias circuit. The other end of R3 is connected in series with R2 and R4 and then grounded. The two ends of R3 and the two ends of R4 are respectively connected to the process corner and temperature compensation circuit.
[0008] Furthermore, the startup circuit includes PMOS transistors PM21, PM22, PM23, NMOS transistors NM21 and NMOS transistors NM22; The source of PM21 is electrically connected to the source of PM12 and the bias circuit; the drain of PM21 is electrically connected to the source of PM22; the drain of PM22 is electrically connected to the source of PM23; and the drain of PM23 is connected to the gate of PM23, the gate of PM22, the gate of PM21, the drain of NM21, and the gate of NM22. The drain of NM22 is electrically connected to the bandgap reference core circuit and the bias circuit; the source of NM22 is electrically connected to the source and the bias circuit of NM21; and the gate of NM21 is electrically connected to the bias circuit.
[0009] Furthermore, the bias circuit includes PMOS transistors PM31, PM32, PM33, NMOS transistors NM31, NMOS transistors NM32, and NMOS transistors NM33; The source of PM31 is electrically connected to the source of PM32 and is also electrically connected to the startup circuit, process corner and temperature compensation circuit. The gate of PM31 is electrically connected to the gate of PM32 and is also electrically connected to the startup circuit, bandgap reference core circuit and process corner and temperature compensation circuit. The drain of PM31 is electrically connected to the drain and gate of NM31, the source of NM31 is electrically connected to the source of PM33, and the drain of PM33 is electrically connected to the gate of PM33, the drain of NM33, and the bandgap reference core circuit. The drain of PM32 is electrically connected to the startup circuit, the drain of NM32, the gate of NM32, the gate of NM33, and the process corner and temperature compensation circuit. The source of NM32 is electrically connected to the source of NM33, the startup circuit, the process corner, and the temperature compensation circuit. The source of NM33 is grounded.
[0010] Furthermore, the process corner and temperature compensation circuit includes PMOS transistors PM41, PM42, PM43, PM44, PM45, PM46, PM47, PM48, PM49, PM410, PM411, PM412, PM413, PM414, NMOS transistors NM41, NM42, NM43, NM44, NM45, NM46, NM47, NM48, resistors R5, R6, R7, and R8. The source of PM414 is electrically connected to the sources of PM413, PM412, PM411, PM410, PM49, PM48, PM47, PM46 and PM45, and is also electrically connected to the bias circuit. The drain of PM414 is connected to the drain of NM48, the gate of NM48 is connected to the bias circuit and the gate of NM47; the source of NM48 is connected to the bias circuit, the drain of PM44, the drain of PM43, the source of NM47, the drain of PM42, and the drain of PM41. The drain of PM45 is connected to the drain of NM41, the gate of NM41, and the gate of NM42. The source of NM41 is connected to the source of NM43 and one end of R5. The other end of R5 is connected to the source of PM41. The source of NM42 is connected to one end of R6. The other end of R6 is connected to the source of PM42. The gate of PM45 is connected to the gate of PM46, the gate of PM410, the gate of PM411 and the bias circuit. The drain of PM46 is connected to the gate of NM43 and the drain of NM42. The drain of PM47 is connected to the drain of NM43, the gate of PM47, the gate of PM48 and the gate of PM49. The drain of PM49 is connected to the drain of NM47; the drain of PM410 is connected to the drain of NM44, the gate of NM44, and the gate of NM45; the source of NM44 is connected to one end of R7 and the source of NM46, and the other end of R7 is connected to the source of PM43; the drain of PM411 is connected to the gate of NM46 and the drain of NM45; the source of NM45 is connected to one end of R8, and the other end of R8 is connected to the source of PM44; the drain of NM46 is connected to the drain of PM412, the gate of PM412, the gate of PM413, and the gate of PM414; the drains of PM413 and PM48 are connected to VB.
[0011] The gates of PM41 and PM44 are connected to Vref, and the gates of PM42 and PM43 are connected to Vcomp.
[0012] Furthermore, the process corner and temperature compensation circuit also includes inverter G1, inverter G2, AND gate, NAND gate, NMOS transistor NM49 and NMOS transistor NM410; The input of G1 is connected to one input of NAND, the output of G1 is connected to one input of AND, the output of AND is connected to the gate of NM49, and the drain and source of NM49 are connected to the bandgap reference core circuit respectively. The input of G2 is connected to the other input of AND, the output of G2 is connected to the other input of NAND, the output of NAND is connected to the gate of NM410, and the drain and source of NM410 are connected to the bandgap reference core circuit respectively. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of the module structure of the present invention; Figure 2 This is the overall circuit diagram of the present invention; Figure 3 This is a schematic diagram of the temperature compensation waveform of the present invention; Figure 4 This is a schematic diagram of the process angle compensation waveform of the present invention; Figure 5This is a diagram of the bandgap reference voltage curve before compensation according to the present invention; Figure 6 This is a curve of the bandgap reference voltage after compensation according to the present invention. Detailed Implementation
[0014] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.
[0015] like Figures 1-6 As shown in Embodiment 1, a bandgap reference circuit includes a bandgap reference core circuit, a startup circuit, a bias circuit, and a process corner and temperature compensation circuit; the startup circuit is electrically connected to the bandgap reference core circuit and the bias circuit, respectively, and the bias circuit is electrically connected to the process corner and temperature compensation circuit. The core circuit of the bandgap reference is used to generate a zero-temperature-coefficient reference voltage Vref by adding positive and negative temperature-coefficient voltages. The startup circuit is used to provide a startup signal for the core circuit of the bandgap reference. The bias circuit is used to provide bias for the startup circuit, process corner and temperature compensation circuit, and to provide the comparison voltage Vcomp for the process corner and temperature compensation circuit; The process angle and temperature compensation circuit is used to generate high-temperature compensation current or low-temperature compensation current by comparing the reference signal and the comparison signal respectively, which is applied to the bandgap reference core circuit. It also detects the fast and slow process angles to adjust the resistance value of the bandgap reference core circuit, so that the reference voltage rises or falls.
[0016] This invention designs a startup circuit, a bias circuit, and a process corner and temperature compensation circuit based on the core of a bandgap reference circuit. Specifically: the startup circuit is connected to the core bandgap reference circuit; the startup circuit is connected to the bias circuit; the startup circuit provides a startup signal to the core bandgap reference circuit when the power supply voltage is applied, allowing it to exit other degenerate states and operate normally; the core bandgap reference circuit is connected to the bias circuit and the process corner and temperature compensation circuit; the core bandgap reference circuit generates a zero-temperature-coefficient reference voltage obtained by adding positive and negative temperature-coefficient voltages, i.e., a reference voltage signal independent of the first order of temperature, whose second-order effect produces a parabolic curve of the reference voltage versus temperature; the bias circuit is connected to the process corner and temperature compensation circuit; the bias circuit... The current is generated by the bandgap reference core circuit and is used to provide bias current for the startup circuit, process corner and temperature compensation circuit, and to provide comparison voltage Vcomp for the process corner and temperature compensation circuit. The process corner and temperature compensation circuit generates high temperature compensation current and low temperature compensation current through the comparison reference signal and the comparison signal, respectively, which are applied to the bandgap reference core circuit. It also detects the fast and slow process corners to adjust the resistance value of the bandgap reference core circuit, thereby realizing the rise or fall of the reference voltage, compensating for the second-order temperature effect of the temperature drift curve of the bandgap reference core circuit, and making its voltage approximately equal under different process corners, saving the cost of manual adjustment later. This invention optimizes the bandgap reference voltage under different process corners and reduces the temperature drift characteristics of the bandgap reference voltage.
[0017] Example 2 is a further improvement based on Example 1, and its details are as follows: The core circuit of the bandgap reference includes transistors Q1 and Q2, resistors R1, R2, R3, and R4, PMOS transistors PM11 and PM12, and NMOS transistor NM11. The source of PM11 is electrically connected to the source of PM12 and connected to the startup circuit. The drain of PM11 is connected to the gate of NM11 and the collector of Q2. The gate of PM11 is electrically connected to the gate of PM12, the drain of PM12, and the collector of Q1 and connected to the startup circuit. The source of NM11 is connected to the base of Q1 and the base of Q2. The drain of NM11 is connected to the power supply VDD. The emitter of Q1 is electrically connected to one end of R1, and the other end of R1 is electrically connected to the emitter of Q2, one end of R3, and the bias circuit. The other end of R3 is connected in series with R2 and R4 and then grounded. The two ends of R3 and the two ends of R4 are respectively connected to the process corner and temperature compensation circuit.
[0018] The core circuit of the bandgap reference consists of two transistors Q1 and Q2 with different multipliers, current mirror transistors PM11 and PM12, and resistors R1, R2, R3, and R4. The bases of the transistors are connected. Because the current mirrors control the two current values to be the same, a positive temperature coefficient voltage is generated between the transistors. A positive temperature coefficient current is generated by acting on resistor R1. After replication, a positive temperature coefficient voltage is generated by flowing through resistors R2, R3, and R4. This voltage depends only on the resistance ratio, the transistor multiplier ratio, and the thermal voltage, and is independent of the manufacturing process, so it can be used as a reference for generating comparison voltages. Adding this voltage VB to the negative temperature coefficient voltage VBE yields the bandgap reference voltage Vref.
[0019] Example 3 is a further improvement based on Example 2, and its details are as follows: The startup circuit includes PMOS transistors PM21, PM22, PM23, NMOS transistors NM21 and NM22; The source of PM21 is electrically connected to the source of PM12 and the bias circuit; the drain of PM21 is electrically connected to the source of PM22; the drain of PM22 is electrically connected to the source of PM23; and the drain of PM23 is connected to the gate of PM23, the gate of PM22, the gate of PM21, the drain of NM21, and the gate of NM22. The drain of NM22 is electrically connected to the bandgap reference core circuit (the drain of PM12) and the bias circuit; the source of NM22 is electrically connected to the source of NM21 and the bias circuit; the gate of NM21 is electrically connected to the bias circuit.
[0020] Startup Circuit: The startup circuit consists of a bias current source NM21, and PM21, PM22, PM23, and NM22 connected in a diode configuration. When the power supply voltage rises from zero, NM21 initially has no current. When the power supply voltage VDD is higher than VGSP+VGSN, NM22 turns on and pulls down the gate voltage of the current mirror transistor in the bandgap reference core. The bandgap reference core circuit starts up and controls NM21 to turn on and MN22 to turn off via the current mirror.
[0021] Example 4 is a further improvement on Example 3, and its details are as follows: The bias circuit includes PMOS transistors PM31, PM32, PM33, NMOS transistors NM31, NMOS transistors NM32, and NMOS transistors NM33; The source of PM31 is electrically connected to the source of PM32 and is also electrically connected to the startup circuit (the source of PM21) and the process corner and temperature compensation circuit. The gate of PM31 is electrically connected to the gate of PM32 and is also electrically connected to the startup circuit (the drain of NM22), the bandgap reference core circuit (the drain of PM12, the gate of PM12, and the collector of Q1) and the process corner and temperature compensation circuit. The drain of PM31 is electrically connected to the drain and gate of NM31, the source of NM31 is electrically connected to the source of PM33, and the drain of PM33 is electrically connected to the gate of PM33, the drain of NM33, and the bandgap reference core circuit (the other end of R1, one end of R3, and the emitter of Q2). The drain of PM32 is electrically connected to the startup circuit (gate of NM21), the drain of NM32, the gate of NM32, the gate of NM33, and the process corner and temperature compensation circuit. The source of NM32 is electrically connected to the source of NM33, the startup circuit (the source of NM21 and the source of NM22), and the process corner and temperature compensation circuit. The source of NM33 is grounded.
[0022] Bias Circuit: This circuit generates the NMOS bias voltage and the process corner comparison voltage. The NMOS bias voltage is obtained by replicating the positive temperature coefficient current of the bandgap reference core circuit; therefore, the current source for this bias voltage is a positive temperature coefficient current. The process corner compensation voltage is obtained by adding VB and VGS of the PMOS transistor PM33 connected in a diode configuration. The comparison voltage is generated by utilizing the threshold voltage VTH of the MOS transistor as it varies with different process corner deviations and temperatures. By designing the W / L of the MOSFET, VGS can be changed to make its value close to Vref.
[0023] Example 5 is a further improvement on Example 4, and its details are as follows: The process corner and temperature compensation circuit includes PMOS transistors PM41, PM42, PM43, PM44, PM45, PM46, PM47, PM48, PM49, PM410, PM411, PM412, PM413, PM414, NMOS transistors NM41, NM42, NM43, NM44, NM45, NM46, NM47, NM48, resistors R5, R6, R7, and R8. The source of PM414 is electrically connected to the sources of PM413, PM412, PM411, PM410, PM49, PM48, PM47, PM46 and PM45, and is also electrically connected to the bias circuit (the source of PM32). The drain of PM414 is connected to the drain of NM48. The gate of NM48 is connected to the bias circuit (the drain of NM32 and the drain of PM32) and the gate of NM47. The source of NM48 is connected to the bias circuit (the source of NM32), the drain of PM44, the drain of PM43, the source of NM47, the drain of PM42, and the drain of PM41. The drain of PM45 is connected to the drain of NM41, the gate of NM41, and the gate of NM42. The source of NM41 is connected to the source of NM43 and one end of R5. The other end of R5 is connected to the source of PM41. The source of NM42 is connected to one end of R6. The other end of R6 is connected to the source of PM42. The gate of PM45 is connected to the gate of PM46, the gate of PM410, the gate of PM411 and the bias circuit (the gate of PM32). The drain of PM46 is connected to the gate of NM43 and the drain of NM42. The drain of PM47 is connected to the drain of NM43, the gate of PM47, the gate of PM48 and the gate of PM49. The drain of PM49 is connected to the drain of NM47; the drain of PM410 is connected to the drain of NM44, the gate of NM44, and the gate of NM45; the source of NM44 is connected to one end of R7 and the source of NM46, and the other end of R7 is connected to the source of PM43; the drain of PM411 is connected to the gate of NM46 and the drain of NM45; the source of NM45 is connected to one end of R8, and the other end of R8 is connected to the source of PM44; the drain of NM46 is connected to the drain of PM412, the gate of PM412, the gate of PM413, and the gate of PM414; the drains of PM413 and PM48 are connected to VB.
[0024] The gates of PM41 and PM44 are connected to Vref, and the gates of PM42 and PM43 are connected to Vcomp.
[0025] Temperature compensation and process corner compensation circuit: This circuit can be divided into two mirrored sections. The structure is as follows: Input transistors PM41-PM44 are source followers (PMOS) used to isolate the compensation circuit and the bandgap reference core circuit, preventing error current from flowing into the reference core circuit. PMOS tail current transistors PM45 and PM46 replicate the current of the bandgap reference core circuit for bias. NMOS current mirrors NM41 and NM42 have the same gate voltage and current Id, and their source voltages are also approximately the same. When the input comparison voltage changes with temperature, to maintain the same source voltage, current is drawn from NMOS transistor NM43. This current is replicated and compensated to the VB terminal of the bandgap reference core circuit through a current mirror PM48 of appropriate proportion, thus adjusting the reference voltage Vref. The two mirrored modules are used to generate low-temperature compensation current and high-temperature compensation current, respectively. When the circuit process angle changes, the compensation current is large. The voltages Vx and VY of the branch connected to PM49 and the current source transistor NM47 flip, and then, after logic processing, control the switching of resistors R3 and R4 in the bandgap reference core circuit, thereby realizing voltage compensation for different process angles.
[0026] See attached diagram for the bandgap reference voltage curve before compensation. Figure 5 The different process angles have large deviations and the temperature drift curve has a large curvature; see the attached diagram for the compensated bandgap reference voltage curve. Figure 6 The voltage values and temperature drift at different process angles have been optimized.
[0027] Example 6 is a further improvement on Example 5, and its details are as follows: The process corner and temperature compensation circuit also includes inverter G1, inverter G2, AND gate, NAND gate, NMOS transistor NM49 and NMOS transistor NM410; The input of G1 is connected to one input of NAND, the output of G1 is connected to one input of AND, the output of AND is connected to the gate of NM49, and the drain and source of NM49 are connected to the bandgap reference core circuit (the two ends of R3). The input of G2 is connected to the other input of AND, the output of G2 is connected to the other input of NAND, the output of NAND is connected to the gate of NM410, and the drain and source of NM410 are connected to the bandgap reference core circuit (the two ends of R4).
[0028] After process angle and temperature compensation, the voltage value of the temperature drift curve is basically equal under different process angles, and the second-order temperature characteristics of the temperature drift curve are also significantly improved.
[0029] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A bandgap reference circuit, characterized in that, It includes a bandgap reference core circuit, a startup circuit, a bias circuit, and a process angle and temperature compensation circuit; the startup circuit is electrically connected to the bandgap reference core circuit and the bias circuit, and the bias circuit is electrically connected to the process angle and temperature compensation circuit. The bandgap reference core circuit is used to generate a zero temperature coefficient reference voltage Vref by adding positive and negative temperature coefficient voltages. The startup circuit is used to provide a startup signal for the bandgap reference core circuit; The bias circuit is used to provide bias for the startup circuit, the process corner and temperature compensation circuit, and to provide a comparison voltage Vcomp for the process corner and temperature compensation circuit. The process angle and temperature compensation circuit is used to generate a high-temperature compensation current or a low-temperature compensation current by comparing the reference signal and the comparison signal, respectively, and to apply them to the bandgap reference core circuit. It also detects the fast and slow process angles to adjust the resistance value of the bandgap reference core circuit, thereby causing the reference voltage to rise or fall.
2. The bandgap reference circuit according to claim 1, characterized in that, The core circuit of the bandgap reference includes transistors Q1 and Q2, resistors R1, R2, R3, and R4, PMOS transistors PM11 and PM12, and NMOS transistor NM11. The source of PM11 is electrically connected to the source of PM12 and connected to the startup circuit. The drain of PM11 is connected to the gate of NM11 and the collector of Q2. The gate of PM11, the gate of PM12, the drain of PM12, and the collector of Q1 are electrically connected to the startup circuit. The source of NM11 is connected to the base of Q1 and the base of Q2. The drain of NM11 is connected to the power supply VDD. The emitter of Q1 is electrically connected to one end of R1, and the other end of R1 is electrically connected to the emitter of Q2, one end of R3, and the bias circuit. The other end of R3 is connected in series with R2 and R4 and then grounded. The two ends of R3 and the two ends of R4 are respectively connected to the process angle and temperature compensation circuit.
3. The bandgap reference circuit according to claim 1, characterized in that, The startup circuit includes PMOS transistors PM21, PM22, PM23, NMOS transistors NM21 and NMOS transistors NM22; The source of PM21 is electrically connected to the source of PM12 and the bias circuit; the drain of PM21 is electrically connected to the source of PM22, the drain of PM22 is electrically connected to the source of PM23, and the drain of PM23 is connected to the gate of PM23, the gate of PM22, the gate of PM21, the drain of NM21, and the gate of NM22. The drain of NM22 is electrically connected to the bandgap reference core circuit and the bias circuit; the source of NM22 is electrically connected to the source of NM21 and the bias circuit; and the gate of NM21 is electrically connected to the bias circuit.
4. The bandgap reference circuit according to claim 1, characterized in that, The bias circuit includes PMOS transistors PM31, PM32, PM33, NMOS transistors NM31, NMOS transistors NM32, and NMOS transistors NM33; The source of PM31 is electrically connected to the source of PM32 and is also electrically connected to the startup circuit and the process corner and temperature compensation circuit. The gate of PM31 is electrically connected to the gate of PM32 and is also electrically connected to the startup circuit, the bandgap reference core circuit and the process corner and temperature compensation circuit. The drain of PM31 is electrically connected to the drain and gate of NM31, the source of NM31 is electrically connected to the source of PM33, and the drain of PM33 is electrically connected to the gate of PM33, the drain of NM33, and the bandgap reference core circuit. The drain of PM32 is electrically connected to the startup circuit, the drain of NM32, the gate of NM32, the gate of NM33, and the process corner and temperature compensation circuit. The source of NM32 is electrically connected to the source of NM33, the startup circuit, and the process corner and temperature compensation circuit, and the source of NM33 is grounded.
5. A bandgap reference circuit according to claim 1, characterized in that, The process angle and temperature compensation circuit includes PMOS transistors PM41, PM42, PM43, PM44, PM45, PM46, PM47, PM48, PM49, PM410, PM411, PM412, PM413, PM414, NMOS transistors NM41, NM42, NM43, NM44, NM45, NM46, NM47, NM48, resistors R5, R6, R7, and R8. The source of PM414 is electrically connected to the sources of PM413, PM412, PM411, PM410, PM49, PM48, PM47, PM46, and PM45, and is also electrically connected to the bias circuit. The drain of PM414 is connected to the drain of NM48, and the gate of NM48 is connected to the bias circuit and the gate of NM47; the source of NM48 is connected to the bias circuit, the drain of PM44, the drain of PM43, the source of NM47, the drain of PM42, and the drain of PM41. The drain of PM45 is connected to the drain of NM41, the gate of NM41, and the gate of NM42. The source of NM41 is connected to the source of NM43 and one end of R5, and the other end of R5 is connected to the source of PM41. The source of NM42 is connected to one end of R6, and the other end of R6 is connected to the source of PM42. The gate of PM45 is connected to the gate of PM46, the gate of PM410, the gate of PM411, and the bias circuit; the drain of PM46 is connected to the gate of NM43 and the drain of NM42; the drain of PM47 is connected to the drain of NM43, the gate of PM47, the gate of PM48, and the gate of PM49. The drain of PM49 is connected to the drain of NM47; the drain of PM410 is connected to the drain of NM44, the gate of NM44, and the gate of NM45; the source of NM44 is connected to one end of R7 and the source of NM46, and the other end of R7 is connected to the source of PM43; the drain of PM411 is connected to the gate of NM46 and the drain of NM45; the source of NM45 is connected to one end of R8, and the other end of R8 is connected to the source of PM44; the drain of NM46 is connected to the drain of PM412, the gate of PM412, the gate of PM413, and the gate of PM414; the drains of PM413 and PM48 are connected to VB. The gates of PM41 and PM44 are connected to Vref, and the gates of PM42 and PM43 are connected to Vcomp.
6. A bandgap reference circuit according to claim 5, characterized in that, The process angle and temperature compensation circuit also includes inverter G1, inverter G2, AND gate, NAND gate, NMOS transistor NM49 and NMOS transistor NM410; The input terminal of G1 is connected to one input terminal of NAND, the output terminal of G1 is connected to one input terminal of AND, the output terminal of AND is connected to the gate of NM49, and the drain and source of NM49 are respectively connected to the bandgap reference core circuit. The input terminal of G2 is connected to another input terminal of the AND, the output terminal of G2 is connected to another input terminal of the NAND, the output terminal of the NAND is connected to the gate of the NM410, and the drain and source of the NM410 are respectively connected to the bandgap reference core circuit.