Loop instruction execution method, integrated circuit, computer readable storage medium and computer program product

Abstract

The invention relates to a loop instruction execution method, an integrated circuit, a computer readable storage medium and a computer program product. The method comprises the steps that a target instruction set is obtained, the target instruction set comprises multiple parts of implicit branch instructions, and the multiple parts of implicit branch instructions are used for replacing explicit backward branch instructions to control starting, iteration and termination of a target loop; executing a multi-part implicit branch instruction, and starting a target loop and iteration based on an initial condition; adjusting the initial loop count value of the loop counter according to the loop type corresponding to the target loop, and updating the loop count value in real time in the iteration process of the target loop; under the condition that the reserved bit is triggered, comparing the current updated cycle count value with a termination condition; and terminating the target cycle under the condition that the current updated cycle count value meets a termination condition. By adopting the method, the problem of pipeline stagnation caused by backward branch instructions can be eliminated on the premise of not increasing the code volume, and the overall instruction execution efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and in particular to a method for executing loop instructions, integrated circuits, computer-readable storage media, and computer program products. Background Technology

[0002] In the pipelined processing stage of integrated circuits, which involves address fetching, decoding, execution, and write-back, the execution of backward branch instructions requires waiting for the branch judgment result, which causes the preceding pipeline stages such as address fetching and decoding to pause and become stagnant.

[0003] Currently, branch predictors can be deployed in integrated circuits to predict whether a branch will be executed, thereby reducing stalls in the pipeline processing stage. Alternatively, code or instruction set unrolling can also reduce the overhead caused by stalls. However, deploying branch predictors is typically complex and costly. Furthermore, the limited memory capacity available for storing instructions or code makes it difficult to cope with the doubling of size resulting from code or instruction set unrolling.

[0004] Therefore, there is an urgent need for a technical means to eliminate pipeline stalling caused by backward branch instructions without increasing code size. Summary of the Invention

[0005] Therefore, it is necessary to provide a loop instruction execution method, integrated circuit, computer-readable storage medium, and computer program product that can eliminate pipeline stalling caused by backward branch instructions without increasing code size, in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a loop instruction execution method, applied to an integrated circuit configured with a pipelined processing stage; the method includes:

[0007] Obtain a target instruction set, which includes multiple implicit branch instructions. These multiple implicit branch instructions replace the original explicit backward branch instructions in the target instruction set and control the start, iteration, and termination of the target loop corresponding to the explicit backward branch instructions. The multiple implicit branch instructions include a pre-instruction corresponding to the target loop and a reserved bit. The pre-instruction is used to store the loop boundary corresponding to the target loop. The loop boundary includes the start condition and termination condition of the target loop. The reserved bit is a single-bit instruction appended to the loop body termination instruction of the target loop or within the loop body of the target loop. The reserved bit is used to trigger the loop return or termination of the target loop.

[0008] Execute the multi-part implicit branch instructions, start the target loop based on the starting conditions, and iterate;

[0009] The initial loop count value of the loop counter is adjusted according to the loop type corresponding to the target loop, and the loop count value is updated in real time during the iteration process of the target loop;

[0010] If the reserved bit is triggered, compare the currently updated loop count value with the termination condition;

[0011] The target loop terminates if the currently updated loop count value satisfies the termination condition.

[0012] In one embodiment, the pre-instruction is further used to store the branch target corresponding to the target loop, and the branch target is used to store the starting code position where the loop body start instruction corresponding to the target loop is located;

[0013] After comparing the currently updated loop count value with the termination condition, the method further includes:

[0014] If the currently updated loop count value does not meet the termination condition, the program jumps back to the starting code position according to the branch target and continues to execute the iteration of the target loop.

[0015] In one embodiment, after acquiring the target instruction set, the method further includes:

[0016] Write the start and end conditions in the pre-instruction into a preset register;

[0017] The step of comparing the currently updated loop count value with the termination condition when the reserved bit is triggered, and terminating the target loop when the currently updated loop count value satisfies the termination condition, includes:

[0018] If the reserved bit is triggered, the termination condition stored in the preset register is read, and the termination condition is compared with the currently updated loop count value.

[0019] If the currently updated loop count value satisfies the termination condition, the target loop is terminated, and the start and termination conditions in the pre-instruction stored in the preset register are released.

[0020] In one embodiment, the preset register is physically separated from the arithmetic register of the array core in the integrated circuit;

[0021] The execution of the multi-part implicit branch instructions, and the initiation and iteration of the target loop based on the starting condition, includes:

[0022] The pre-processing instruction is written into the internal cache of the independent processing entity in the integrated circuit, and the independent processing entity in the integrated circuit is controlled to execute the multi-part implicit branch instruction, and the target loop is started and iterated based on the starting condition;

[0023] After initiating and iterating the target loop based on the stated starting conditions, the process further includes:

[0024] According to the predetermined data flow scheduling of the integrated circuit, the data required for the loop body operation instruction corresponding to the target loop is loaded into the register file of the array core, and the array core is controlled to execute the loop body operation instruction;

[0025] The execution progress of the target loop body by the independent processing entity is recorded in real time, and the execution progress of the loop body is synchronized with the execution progress of the loop body operation instructions by the array core.

[0026] In one embodiment, the target loop is determined by:

[0027] Obtain the target instruction set and determine the nested loop structure within the target instruction set;

[0028] Traverse each loop in the nested loop structure and use a loop depth counter to record the depth counter value corresponding to each loop.

[0029] The target loop is obtained by filtering from the nested loop structure based on the depth counter value.

[0030] In one embodiment, the step of filtering the target loop from the nested loop structure based on the depth counter value includes:

[0031] The inner loop in the nested loop structure is determined based on the depth counter value;

[0032] If an explicit backward branch instruction is detected in the inner loop, and the start and end conditions of the inner loop are definite or deducible, the inner loop is designated as the target loop.

[0033] In one embodiment, after determining the inner loop in the nested loop structure based on the depth counter value, the method further includes:

[0034] Count the number of instructions corresponding to the inner loop;

[0035] The priority of the inner loop is determined based on the comparison between the number of instructions and a preset instruction size threshold, wherein the instruction size threshold is a critical value determined based on the instruction cache capacity and pipeline characteristics of the integrated circuit.

[0036] Secondly, this application also provides an integrated circuit configured with a pipelined processing stage. The integrated circuit includes an independent processing entity, the independent processing entity storing a compiler program in its internal cache, and the independent processing entity implementing the loop instruction execution method described in any of the embodiments of the first aspect above when executing the compiler program.

[0037] Thirdly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a compiler program thereon, which, when executed by a processor, implements the loop instruction execution method described in any of the embodiments of the first aspect.

[0038] Fourthly, this application also provides a computer program product. The computer program product includes a compiler program, which, when executed by a processor, implements the loop instruction execution method described in any of the embodiments of the first aspect.

[0039] The aforementioned loop instruction execution method, integrated circuit, computer-readable storage medium, and computer program product, by adding multiple implicit branch instructions to the target instruction set to replace the original explicit backward branch instructions, control the start, iteration, and termination of the target loop using these multiple implicit branch instructions. During the iteration of the target loop, the triggering of reserved bits is monitored. If a reserved bit is triggered, a termination condition is used for termination judgment. If the updated loop count value meets the termination condition, the target loop is terminated. This can decouple loop control from the array core of the integrated circuit, completely eliminating pipeline stalls caused by backward branches. At the same time, the use of a single-bit reserved bit design can ensure that the overall code size of the target instruction set does not increase, adapting to the limited memory capacity of embedded systems. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart illustrating a loop instruction execution method in one embodiment;

[0042] Figure 2 This is a flowchart illustrating the preset register storage steps in one embodiment;

[0043] Figure 3 This is a flowchart illustrating the execution steps of a loop body in one embodiment;

[0044] Figure 4 This is a flowchart illustrating the target cyclical screening steps in one embodiment;

[0045] Figure 5 This is an algorithm structure diagram of an integrated circuit implementing a loop instruction execution method in one embodiment;

[0046] Figure 6 This is a schematic diagram of the target loop optimization operation in one embodiment;

[0047] Figure 7 This is a schematic diagram illustrating the execution of multipart implicit branch instructions in one embodiment. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0049] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the solutions, or any combination of multiple solutions. The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with relevant regulations.

[0050] In one exemplary embodiment, such as Figure 1 As shown, a loop instruction execution method is provided. This embodiment illustrates the application of this method to an integrated circuit configured with a pipelined processing stage. It is understood that this method can also be applied to hardware such as chips, robots, and compileable logic devices. In this embodiment, the method includes the following steps S102 to S110. Wherein:

[0051] Step S102: Obtain the target instruction set.

[0052] The target instruction set includes multi-part implicit branch instructions. These instructions replace the original explicit backward branch instructions in the target instruction set, controlling the start, iteration, and termination of the target loop corresponding to the explicit backward branch instructions. Each multi-part implicit branch instruction includes a pre-instruction and reserved bits. The pre-instruction stores the loop boundary, including the start and end conditions of the target loop. The reserved bits are single-bit instructions appended to the loop termination instruction or within the loop body of the target loop. These reserved bits trigger the loop's return or termination. In other words, the multi-part implicit branch instructions specifically control the loop's return or termination by replacing the explicit backward branch instructions with reserved bits.

[0053] For example, the integrated circuit can read the target instruction set to be executed. Optionally, in some implementations, the integrated circuit can evaluate the original instruction content of the target instruction set from multiple dimensions, identify nested loop objects in the instruction content, and filter out high-loss, easily optimized target loops among the nested loop objects. The loop boundary of the target loop is determined, and the start and end conditions of the loop boundary are stored in the pre-instruction. The single-bit flag bit in the single-bit instruction appended to the loop body termination instruction of the target loop or in the loop body of the target loop is stored in the reserved bits. Multiple implicit branch instructions are composed using the pre-instruction and the reserved bits. Multiple implicit branch instructions replace the original explicit backward branch instructions of the target instruction set, controlling the start, iteration, and termination of the target loop corresponding to the explicit backward branch instructions.

[0054] Step S104: Execute multi-part implicit branch instructions to start the target loop and iterate based on the initial conditions.

[0055] For example, the integrated circuit can be deployed with an independent loop execution control system. This system executes multi-part implicit branch instructions. Upon meeting initial conditions, the control target loop initiates and iterates according to its loop.

[0056] Step S106: Adjust the initial loop count value of the loop counter according to the loop type corresponding to the target loop, and update the loop count value in real time during the iteration process of the target loop.

[0057] For example, the integrated circuit can determine parameters such as the initial iteration value and the step size of each iteration for the target loop based on the loop type corresponding to the target loop. The initial loop count value of the loop counter is adjusted to the initial iteration value. During the iteration process of the target loop, after each iteration of the target loop is completed, the loop counter is controlled to increment or decrement the count value corresponding to the iteration step size. The incremented or decremented loop count value is then used to overwrite the loop count value before the iteration, serving as the updated loop count value in real time.

[0058] Step S108: If the reserved bit is triggered, compare the currently updated loop count value with the termination condition.

[0059] For example, the triggering condition for the reserved bit can be determined based on the instruction content corresponding to the reserved bit. For instance, the reserved bit can be triggered if the loop counter value, the number of iterations, or the result of the target loop operation meets the triggering condition. Alternatively, the reserved bit can be triggered when the compiler execution reaches the reserved bit. When the reserved bit is triggered, the currently updated loop counter value is compared with the condition value in the termination condition corresponding to the target loop.

[0060] Step S110: If the updated loop count value meets the termination condition, terminate the target loop.

[0061] For example, the integrated circuit can control the termination of the target loop when it determines that the currently updated loop count value meets the termination condition. Optionally, in some embodiments, after terminating the target loop, a loop execution completion signal can also be sent so that the subsequent integrated circuit can execute the subsequent instructions of the target instruction set in a timely manner.

[0062] In the above-described loop instruction execution method, multiple implicit branch instructions are added to the target instruction set to replace the original explicit backward branch instructions. The execution of these multiple implicit branch instructions controls the start, iteration, and termination of the target loop. During the iteration of the target loop, the triggering of the reserved bit is monitored. When the reserved bit is triggered, a termination condition is used to determine the termination. If the updated loop count value meets the termination condition, the target loop is terminated. This method can separate loop control from the array core of the integrated circuit, completely eliminating pipeline stalls caused by backward branches. At the same time, the use of a single-bit reserved bit design can ensure that the overall code size of the target instruction set does not increase, adapting to the limited memory capacity of embedded systems.

[0063] In an exemplary embodiment, the pre-instruction can also be used to store the branch target corresponding to the target loop. The branch target is used to store the starting code location where the loop body start instruction corresponding to the target loop is located. The pre-instruction and the branch target are bound at the instruction level and work together to achieve loop control.

[0064] The loop instruction execution method provided in this application may further include: after comparing the currently updated loop count value with the termination condition, it may also include: if the currently updated loop count value does not meet the termination condition, jumping back to the starting code position according to the branch target and continuing to execute the iteration of the target loop.

[0065] The starting code location may include, but is not limited to, uniquely identifying location information such as the memory address and instruction number corresponding to the loop body's starting instruction.

[0066] For example, if the currently updated loop counter value does not meet the termination condition, the integrated circuit can continue executing the iteration of the target loop by utilizing the Instruction Memory Dispatcher (IMD) to execute reserved bits: directly guiding the program back to the starting code location of the target loop according to the branch target, compiling from the starting code location, and continuing the execution of a new round of iteration of the target loop. The IMD can work in parallel with the array core of the integrated circuit that executes the loop body operation instructions of the target loop. The IMD can be deployed in a separate processing entity of the integrated circuit, which can be hardware running an independent loop execution control system for loop control of the target loop.

[0067] In this embodiment, when the loop count value does not meet the termination condition, the loop is looped back according to the branch target in the preceding instruction, and the loop body start instruction corresponding to the target loop is located at the starting code position to continue the iteration of the target loop. The reserved bit can be used to replace the original backward branch instruction to control the target loop loop, thereby avoiding the backward branch instruction from affecting the pipeline stall and improving the overall instruction execution efficiency.

[0068] In one exemplary embodiment, such as Figure 2 As shown, the loop instruction execution method provided in this application may further include the following steps S202 to S206. Wherein:

[0069] Step S202: Write the start condition and termination condition in the pre-instruction into the preset register.

[0070] Step S204: If the reserved bit is triggered, read the termination condition stored in the preset register and compare the termination condition with the currently updated loop count value.

[0071] Step S206: If the updated loop count value satisfies the termination condition, terminate the target loop and release the start and termination conditions in the pre-instruction stored in the preset register.

[0072] For example, during the initialization phase after acquiring the target instruction set, the integrated circuit can write the start and end conditions of the target loop from the pre-instructions into a dedicated preset register. Multi-part implicit branch instructions are executed, and the start instruction of the target loop is read from the preset register. The start instruction controls the start and iteration of the target loop. If a reserved bit is triggered, the end condition stored in the preset register is read and compared with the currently updated loop count value. If the currently updated loop count value satisfies the target loop's end condition, the target loop is terminated, and the start and end conditions from the pre-instructions stored in the preset register are released.

[0073] Optionally, in some implementations, the loop counter can be cleared after the target loop is terminated. After releasing the start and end conditions in the pre-defined instructions stored in the preset register and clearing the loop counter, a loop execution completion signal can be sent to the main scheduler of the integrated circuit, so that the main scheduler can guide the integrated circuit to execute subsequent instructions of the target instruction set according to the preset process.

[0074] In this embodiment, by writing the start and end conditions in the pre-instruction into a dedicated preset register, data conflicts can be avoided by isolating them from the data stored in other registers in the integrated circuit. Simultaneously, by releasing the storage resources of the preset register after terminating the target loop, the utilization rate of the preset register can be improved, facilitating the execution of other instructions in the subsequent target instruction set.

[0075] In one exemplary embodiment, such as Figure 3 As shown, the preset register is physically separated from the arithmetic register of the array core in the integrated circuit. The loop instruction execution method provided in this application may further include the following steps S302 to S306. Wherein:

[0076] Step S302: Write the pre-processing instruction into the internal cache of the independent processing entity in the integrated circuit, control the independent processing entity in the integrated circuit to execute multiple implicit branch instructions, start the target loop based on the starting condition and iterate.

[0077] Optionally, in some implementations, the address of the starting instruction of the target loop body in the pre-instruction, i.e., the branch target mentioned above, can be written into the internal cache of the independent processing entity in the integrated circuit to ensure that the independent processing entity can quickly call the branch target when the loop returns to its previous state. The independent processing entity in the integrated circuit is controlled to execute multiple implicit branch instructions, starting and iterating the target loop based on the starting conditions, as provided in the above embodiments.

[0078] Step S304: According to the predetermined data flow scheduling of the integrated circuit, the data required for the loop body operation instruction corresponding to the target loop is loaded into the register file of the array core, and the array core is controlled to execute the loop body operation instruction.

[0079] For example, the predetermined data flow schedule of the integrated circuit and the data required for the loop body operation instructions corresponding to the target loop can be determined based on the target instruction set. The data required for the loop body operation instructions is automatically loaded into the large register file of the array core according to the predetermined data flow schedule, without waiting for the array core to actively request data. The array core is then controlled to execute the loop body operation instructions. Since the loop control of the target loop is now executed by an independent processing entity, there are no backward branch instructions within the loop body of the target loop that the array core needs to execute, ensuring that the pipeline can execute continuously without stalls.

[0080] Step S306: Record the execution progress of the loop body of the target loop executed by the independent processing entity in real time, and control the execution progress of the loop body to be synchronized with the execution progress of the loop body operation instructions of the array core.

[0081] For example, the integrated circuit can utilize an independent processing entity to continuously monitor the execution status of the target loop's loop body, record the loop body execution progress in real time, and control the loop body execution progress to be synchronized with the progress of the array core in executing the loop body operation instructions, ensuring that the independent processing entity and the array core collaboratively process each iteration of the target loop.

[0082] In this embodiment, by assigning the loop control of the target loop to an independent processing entity for execution, assigning the loop operation in the target loop to the array core for execution, and controlling the processing progress of the independent processing entity and the array core to be synchronized, the loop control and loop operation can be separated, improving the utilization efficiency of the independent processing entity and the array core, while ensuring that the pipeline of the array core is uninterrupted.

[0083] In one exemplary embodiment, such as Figure 4 As shown, a method for determining a target loop is provided, including the following steps S402 to S406. Wherein:

[0084] Step S402: Obtain the target instruction set and determine the nested loop structure in the target instruction set.

[0085] Step S404: Traverse each loop in the nested loop structure and use the loop depth counter to record the depth counter value corresponding to each loop.

[0086] For example, the integrated circuit can acquire a target instruction set, perform static analysis on the target instruction set, and determine all nested loop structures in the target instruction set. An initial count value is initialized for the loop depth counter. During the traversal of each layer of loops in all nested loop structures, the loop depth counter records the depth count value corresponding to each layer. For example, the outermost loop in the nested loop structure can be marked as the initial count value. During subsequent traversals, the loop depth counter value is incremented or decremented for each layer nested inwards, thus forming the depth counter value corresponding to each layer of loops.

[0087] Step S406: Filter the nested loop structure to obtain the target loop based on the depth counter value.

[0088] For example, the integrated circuit can compare the depth counter values ​​of each layer's cycle. In the mode where the cycle depth counter increments, the cycle with the largest depth count value is selected as the target cycle. Alternatively, in the mode where the cycle depth counter decrements, the cycle with the smallest depth count value is selected as the target cycle.

[0089] Since the innermost loop is the part with the highest iteration frequency in the nested loop structure, its execution efficiency has the greatest impact on the overall computational efficiency. Therefore, this embodiment traverses all nested loop structures in the target instruction set and uses a loop depth counter to record the depth counter value corresponding to each loop. Based on the depth counter value, the innermost loop is selected from the nested loop structure as the target loop. This method can quickly find the innermost loop as the target loop, which helps to improve the execution efficiency of subsequent instructions.

[0090] In an exemplary embodiment, step S406 may include: determining the inner loop in the nested loop structure based on the depth counter value; and if an explicit backward branch instruction is detected in the inner loop, and the start and end conditions of the inner loop are definite or deducible, then the inner loop is taken as the target loop.

[0091] For example, the integrated circuit can determine the loop with the largest / smallest depth count value as the inner loop based on the above-mentioned incrementing or decrementing loop depth counter. Syntax analysis is used to identify whether there is an explicit backward branch instruction in the loop body instruction of the inner loop. If an explicit backward branch instruction is detected in the inner loop, the next step of evaluation is automatically triggered: searching whether the start and end conditions of the inner loop are deterministic or deducible. If both conditions are met simultaneously—that is, if there is an explicit backward branch instruction in the inner loop, and the start and end conditions of the inner loop are deterministic or deducible—the inner loop is selected as the target loop.

[0092] In this embodiment, the innermost loop, which has an explicit backward branch instruction and whose loop boundaries for the start and end conditions are clear or deducible, is identified as the target loop, which helps to improve the efficiency of instruction execution in the future.

[0093] In an exemplary embodiment, after determining the inner loop, the method may further include: counting the number of instructions corresponding to the inner loop; determining the priority of the inner loop based on the comparison result between the number of instructions and a preset instruction size threshold, wherein the instruction size threshold is a critical value determined based on the instruction cache capacity and pipeline characteristics of the integrated circuit.

[0094] For example, the integrated circuit can count the number of instructions corresponding to the inner loop. This number of instructions is compared to a preset instruction size threshold. If the number of instructions in the inner loop is less than the instruction size threshold, it is considered a compact small loop and prioritized for loop optimization; that is, the current inner loop is determined to have a higher priority. Subsequently, multiple implicit branch instructions corresponding to the inner loop can be generated first, or its corresponding multiple implicit branch instructions can be executed first.

[0095] In this embodiment, by judging the number of instructions in the inner loop and the preset instruction size threshold, the priority of the inner loop can be determined, which facilitates the subsequent priority processing of multiple implicit branch instructions of compact small loops.

[0096] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0097] Based on the same inventive concept, this application also provides an integrated circuit for implementing the aforementioned loop instruction execution method. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more integrated circuit embodiments provided below can be found in the limitations of the loop instruction execution method described above, and will not be repeated here.

[0098] In one exemplary embodiment, an integrated circuit is provided, configured with a pipelined processing stage, including an independent processing entity. The independent processing entity stores a compiler program in its internal cache. When the independent processing entity executes the compiler program, it can implement the loop instruction execution method described in the above embodiments.

[0099] For example, such as Figure 5 As shown, the integrated circuit can identify inner loops by using the depth counter values ​​recorded by the loop depth counter for each layer of loops, as described in the above embodiments, through an independent processing entity. If an explicit backward branch instruction is detected in the inner loop, and the start and end conditions of the inner loop are deterministic or deducible, the inner loop is used as the target loop for loop optimization. The loop boundary and branch target of the target loop are stored in a pre-instruction, and a single-bit instruction appended to the loop body termination instruction of the target loop or within the loop body of the target loop is stored in a reserved bit. The pre-instruction and reserved bit are used to form a multi-part implicit branch instruction corresponding to the target loop. The loop boundary of the target loop is stored in a dedicated preset register, and the loop counter is initialized. The multi-part implicit branch instruction is executed using the independent processing entity to control the start and iteration of the target loop. The loop count value is recorded during the target loop process using a dedicated loop counter. When the reserved bit is triggered, a termination judgment is performed: the loop count value is compared with the termination condition. When the loop count value meets the termination condition, the target loop is terminated. When the loop count does not meet the termination condition, jump to the starting code position of the target loop according to the branch target to perform the next iteration of the target loop.

[0100] Alternatively, in some implementations, such as Figure 6 As shown, loop optimization can be implemented using a loop optimizer. The integrated circuit can input the loop body instruction of the selected target loop (instr[loopN++]) into the loop optimizer, extract the start and end conditions of the target loop, and store them in the pre-instruction. The single-bit instruction controlling the termination or loop recurrence of the target loop is stored in the reserved bit lb. The reserved bit lb is added to the loop body instruction of the target loop for modification, forming the optimized loop body instruction.

[0101] Alternatively, in some implementations, such as Figure 7The diagram illustrates an independent processing entity executing multiple implicit branch instructions, primarily divided into an initialization phase, a loop execution phase, an iteration control phase, and a loop termination phase. In the initialization phase, initialization settings can be performed based on preceding instructions, such as scheduler control, initialization of loop boundaries, and initialization of a dedicated loop counter. In the loop execution phase, the independent processing entity executes the loop body. If a loop loop is in a state where the reserved bit is not triggered or is triggered but still in a loop state, the iteration control phase begins, where the scheduler processes the data required by the array core. When the reserved bit is triggered and the loop counter's count value meets the termination condition, the loop termination phase begins, and the loop exits.

[0102] Each module in the aforementioned integrated circuit can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0103] Those skilled in the art will understand that the structures shown in the accompanying drawings are merely block diagrams of some structures related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements.

[0104] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a compiler program, and the processor executes the compiler program to implement the steps in the above-described method embodiments.

[0105] In one exemplary embodiment, a computer-readable storage medium is provided that stores a compiler program thereon, which, when executed by a processor, implements the steps in the above-described method embodiments.

[0106] In one exemplary embodiment, a computer program product is provided, including a compiler program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0107] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a compiler program instructing related hardware. The compiler program can be stored in a non-volatile computer-readable storage medium. When executed, the compiler program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for executing loop instructions, characterized in that, Applied to an integrated circuit configured with a pipelined processing stage; the method includes: Obtain a target instruction set, which includes multiple implicit branch instructions. These multiple implicit branch instructions replace the original explicit backward branch instructions in the target instruction set and control the start, iteration, and termination of the target loop corresponding to the explicit backward branch instructions. The multiple implicit branch instructions include a pre-instruction corresponding to the target loop and a reserved bit. The pre-instruction is used to store the loop boundary corresponding to the target loop. The loop boundary includes the start condition and termination condition of the target loop. The reserved bit is a single-bit instruction appended to the loop body termination instruction of the target loop or within the loop body of the target loop. The reserved bit is used to trigger the loop return or termination of the target loop. Execute the multi-part implicit branch instructions, start the target loop based on the starting conditions, and iterate; The initial loop count value of the loop counter is adjusted according to the loop type corresponding to the target loop, and the loop count value is updated in real time during the iteration process of the target loop; If the reserved bit is triggered, compare the currently updated loop count value with the termination condition; The target loop terminates if the currently updated loop count value satisfies the termination condition.

2. The method according to claim 1, characterized in that, The pre-instruction is also used to store the branch target corresponding to the target loop, and the branch target is used to store the starting code position where the loop body start instruction corresponding to the target loop is located. After comparing the currently updated loop count value with the termination condition, the method further includes: If the currently updated loop count value does not meet the termination condition, the program jumps back to the starting code position according to the branch target and continues to execute the iteration of the target loop.

3. The method according to claim 1, characterized in that, After acquiring the target instruction set, the following is also included: Write the start and end conditions in the pre-instruction into a preset register; The step of comparing the currently updated loop count value with the termination condition when the reserved bit is triggered, and terminating the target loop when the currently updated loop count value satisfies the termination condition, includes: If the reserved bit is triggered, the termination condition stored in the preset register is read, and the termination condition is compared with the currently updated loop count value. If the currently updated loop count value satisfies the termination condition, the target loop is terminated, and the start and termination conditions in the pre-instruction stored in the preset register are released.

4. The method according to claim 3, characterized in that, The preset register is physically separated from the arithmetic register of the array core in the integrated circuit; The execution of the multi-part implicit branch instructions, and the initiation and iteration of the target loop based on the starting condition, includes: The pre-processing instruction is written into the internal cache of the independent processing entity in the integrated circuit, and the independent processing entity in the integrated circuit is controlled to execute the multi-part implicit branch instruction, and the target loop is started and iterated based on the starting condition; After initiating and iterating the target loop based on the stated starting conditions, the process further includes: According to the predetermined data flow scheduling of the integrated circuit, the data required for the loop body operation instruction corresponding to the target loop is loaded into the register file of the array core, and the array core is controlled to execute the loop body operation instruction; The execution progress of the target loop body by the independent processing entity is recorded in real time, and the execution progress of the loop body is synchronized with the execution progress of the loop body operation instructions by the array core.

5. The method according to claim 1, characterized in that, The methods for determining the target loop include: Obtain the target instruction set and determine the nested loop structure within the target instruction set; Traverse each loop in the nested loop structure and use a loop depth counter to record the depth counter value corresponding to each loop. The target loop is obtained by filtering from the nested loop structure based on the depth counter value.

6. The method according to claim 5, characterized in that, The step of filtering the target loop from the nested loop structure based on the depth counter value includes: The inner loop in the nested loop structure is determined based on the depth counter value; If an explicit backward branch instruction is detected in the inner loop, and the start and end conditions of the inner loop are definite or deducible, the inner loop is designated as the target loop.

7. The method according to claim 6, characterized in that, After determining the inner loop in the nested loop structure based on the depth counter value, the method further includes: Count the number of instructions corresponding to the inner loop; The priority of the inner loop is determined based on the comparison between the number of instructions and a preset instruction size threshold, wherein the instruction size threshold is a critical value determined based on the instruction cache capacity and pipeline characteristics of the integrated circuit.

8. An integrated circuit configured with a pipeline processing stage, characterized in that, It includes an independent processing entity, wherein the internal cache of the independent processing entity stores a compiler program, and when the independent processing entity executes the compiler program, it implements the steps of the method according to any one of claims 1 to 7.

9. A computer-readable storage medium storing a compiler program thereon, characterized in that, When the compiler is executed by the processor, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer program product, comprising a compiler program, characterized in that, When the compiler is executed by the processor, it implements the steps of the method according to any one of claims 1 to 7.

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