Field programmable gate array (FPGA) function level reliability prediction method, device, equipment and medium
By screening key configuration bits of the FPGA and injecting single-event upset faults into the simulation platform, sensitive configuration bits are identified, solving the problem of low reliability prediction efficiency in existing FPGA technologies. This achieves efficient and accurate reliability assessment and supports optimized design of FPGAs in radiated environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HARBIN INST OF TECH
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-10
AI Technical Summary
Existing technologies for testing the radiation resistance of FPGAs in radiation environments are complex and time-consuming, making it difficult to efficiently predict reliability.
By acquiring the set of configuration bits of the functional module under test in the FPGA, the set of key configuration bits is selected, and a single-event upset fault is injected into the simulation platform. The output consistency between the module under test and the reference module is compared to identify sensitive configuration bits, and reliability prediction is performed based on the target proportion.
It achieves efficient and accurate FPGA functional level reliability prediction in a simulation environment, provides a basis for reliability assessment in a radiation environment, and supports optimized design and protection measures.
Smart Images
Figure CN121835546A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of space environment effects technology, and more specifically, to a method, apparatus, device, and medium for predicting the functional level reliability of an FPGA. Background Technology
[0002] In recent years, Field-Programmable Gate Arrays (FPGAs) have been widely used in fields with high reliability requirements, such as aerospace and nuclear energy, due to their flexibility, reconfigurability, and powerful parallel processing capabilities. These applications often face complex and harsh radiation environments, where particle radiation can cause errors in the FPGA's internal logic, thereby affecting the normal operation of the entire system. Therefore, conducting reliability testing on the radiation resistance of FPGAs is a crucial step in ensuring their stable operation under radiation conditions.
[0003] Currently, testing the radiation resistance of FPGAs directly in actual radiation environments (such as radiation fields generated by particle accelerators) can accurately reflect their performance under radiation conditions, but this testing method has obvious limitations such as complex operation and long cycle. Summary of the Invention
[0004] The problem addressed by this invention is how to improve the reliability prediction efficiency of FPGAs.
[0005] To address the above problems, this invention provides a method for predicting the functional level reliability of an FPGA, comprising: Obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and filter out the set of key configuration bits from the set of configuration bits; The test module and the reference module are run synchronously in a preset simulation platform, and a single-event upset fault is injected into each key configuration bit in the key configuration bit set corresponding to the test module; wherein, the reference module represents the test module that has not been injected with the single-event upset fault. When the output of the function module under test does not meet the preset consistency condition with the output of the reference function module, the key configuration bit corresponding to the single-event flip fault is used as the sensitive configuration bit. Determine the target proportion of the sensitive configuration bit in the configuration bit set, and obtain the reliability prediction result corresponding to the functional module under test based on the target proportion.
[0006] Optionally, obtaining the set of configuration bits corresponding to the functional module under test in the FPGA, and filtering out the set of key configuration bits from the set of configuration bits, includes: Obtain the physical region of the functional module under test in the FPGA, and determine the configuration frame interval corresponding to the functional module under test in the configuration memory of the FPGA based on the physical region, and obtain the configuration bit set according to each configuration bit in the configuration frame interval; The tag type corresponding to each configuration bit in the configuration bit set is determined according to the preset tag file; wherein, the preset tag file includes the tag type corresponding to each configuration bit in the configuration memory, and the tag type includes critical configuration tags or non-critical configuration tags; The configuration bits in the configuration bit set whose tag type is the key configuration tag are taken as the key configuration bits to obtain the key configuration bit set.
[0007] Optionally, before injecting a single-event upset fault into each of the key configuration bits in the key configuration bit set corresponding to the functional module under test, the method further includes: Based on the mapping position of the key configuration bit in the preset tag file, the physical address of the key configuration bit in the configuration memory is determined; wherein, the physical address is used to indicate the target location for injecting the single-event flip fault in the simulation environment.
[0008] Optionally, before setting the critical configuration bit corresponding to the single-event upset fault injected as a sensitive configuration bit when the output of the function module under test and the output of the reference function module do not meet a preset consistency condition, the method further includes: The outputs of each output channel corresponding to the functional module under test and the reference functional module are obtained respectively, and the first output and the second output corresponding to each output channel are obtained. When the first output and the second output corresponding to the output channel are inconsistent, it indicates that the preset consistency condition is not met.
[0009] Optionally, after obtaining the first output and second output corresponding to each of the output channels, the method further includes: When the first output corresponding to the output channel is inconsistent with the second output, the output channel is regarded as a mismatched output channel, and the sensitive configuration bit is associated with the corresponding mismatched output channel to construct a sensitive configuration bit database.
[0010] Optionally, obtaining the reliability prediction result corresponding to the functional module under test based on the target proportion includes: Obtain the particle flux spectrum and single-particle flip section corresponding to the preset space radiation environment, and determine the single-particle flip rate of each configuration bit in the configuration bit set based on the particle flux spectrum and the single-particle flip section. Based on the single-particle flip rate and the target proportion, the predicted failure rate of the functional module under test is obtained when it operates under the preset space radiation environment, and the reliability prediction result is obtained based on the predicted failure rate.
[0011] Optionally, the predicted failure rate satisfies: ; in, This represents the predicted failure rate; This represents the single-particle flip rate; This indicates the total number of the sensitive configuration bits. This represents the total number of all configuration bits in the configuration bit set. and The ratio is equal to the target percentage.
[0012] In this invention, by acquiring the set of configuration bits corresponding to the functional module under test (DUT) in the FPGA and selecting a set of key configuration bits from this set, it is beneficial to ensure that subsequent simulations can focus on the configuration bits that play a crucial role in the functional implementation of the DUT, thereby effectively improving the reliability prediction efficiency of the DUT. Based on this, this invention synchronously runs the DUT with single-event upset (SEY) faults injected and the reference DUT without SEY faults injected in a preset simulation platform, providing a reliable reference for subsequent identification of sensitive configuration bits. Specifically, during simulation, this invention injects SEY faults one by one into each key configuration bit in the set of key configuration bits corresponding to the DUT, which facilitates systematic observation of the changes in the output of the DUT when each key configuration bit is affected by an SEY fault. Furthermore, when the output of the DUT does not meet the preset consistency condition with the output of the reference DUT, it indicates that its logic function is affected by an SEY fault in a key configuration bit. In this case, the key configuration bit injected with an SEY fault is taken as a sensitive configuration bit, ensuring the accuracy of sensitive configuration bit identification. In this invention, by pre-setting consistency conditions, a clear standard is established for determining whether the output of the functional module under test is normal, which helps to improve the objectivity and accuracy of sensitive configuration bit identification. Based on this, this invention can evaluate the reliability of the functional module under test based on the target proportion of sensitive configuration bits in the configuration bit set, thereby obtaining a reliability prediction result.
[0013] Thus, this invention eliminates the need to place the FPGA in an actual radiation environment for complex operations to obtain reliability test results. It enables efficient and accurate functional-level reliability prediction in a simulation environment, thereby helping designers understand the reliability status of the functional modules under test in the FPGA in the space radiation environment in advance, and providing a strong basis for the optimization design of the FPGA and the adoption of protective measures.
[0014] The present invention also provides an FPGA functional level reliability prediction device, comprising: A filtering module is used to obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and to filter out the set of key configuration bits from the set of configuration bits. The simulation module is used to synchronously run the functional module under test and the reference functional module in a preset simulation platform, and inject single-event upset faults into each key configuration bit in the key configuration bit set corresponding to the functional module under test; wherein, the reference functional module represents the functional module under test that has not been injected with the single-event upset fault. The identification module is used to identify the key configuration bit corresponding to the single-event flip fault injected into the reference function module as a sensitive configuration bit when the output of the function module under test does not meet the preset consistency condition. The prediction module is used to determine the target proportion of the sensitive configuration bits in the configuration bit set, and to obtain the reliability prediction result corresponding to the functional module under test based on the target proportion.
[0015] The FPGA functional level reliability prediction device and the FPGA functional level reliability prediction method provided by this invention have essentially the same advantages over the prior art, and will not be repeated here.
[0016] The present invention also provides an electronic device, including a memory and a processor; The memory is used to store computer programs; The processor is used to implement the FPGA functional level reliability prediction method as described above when executing the computer program.
[0017] The electronic device provided by this invention has essentially the same advantages as the FPGA functional level reliability prediction method compared to existing technologies, and will not be elaborated further here.
[0018] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the FPGA functional-level reliability prediction method as described above.
[0019] The advantages of the computer-readable storage medium provided by this invention and the FPGA functional level reliability prediction method compared to the prior art are basically the same, and will not be repeated here. Attached Figure Description
[0020] Figure 1 This is a flowchart illustrating the FPGA functional-level reliability prediction method according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the FPGA functional level reliability prediction device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0021] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.
[0022] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.
[0023] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; the term "optionally" means "optional embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this invention are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.
[0024] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".
[0025] like Figure 1 As shown in the figure, an FPGA functional level reliability prediction method provided by an embodiment of the present invention includes the following steps: S1: Obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and filter out the set of key configuration bits from the set of configuration bits.
[0026] Specifically, in this embodiment, FPGA (Field-Programmable Gate Array) refers to an integrated circuit that can be programmed to implement specific digital logic functions. The function under test (DUT) refers to the specific functional unit within the FPGA that requires reliability prediction, such as a spacecraft attitude control module. In this embodiment, the configuration bit set refers to a set of binary bits containing a series of configuration information that control the operation of the DUT; each configuration bit has a certain impact on the behavior of the function module. The critical configuration bit set is the set of configuration bits selected from the configuration bit set that plays a crucial role in the functional implementation of the DUT.
[0027] Optionally, obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and filter out the set of key configuration bits from the set of configuration bits, including: Obtain the physical region of the functional module under test in the FPGA, and determine the corresponding configuration frame interval of the functional module under test in the configuration memory of the FPGA based on the physical region. Obtain the configuration bit set according to each configuration bit in the configuration frame interval. The flag type corresponding to each configuration bit in the configuration bit set is determined according to the preset flag file; wherein, the preset flag file includes the flag type corresponding to each configuration bit in the configuration memory, and the flag type includes critical configuration flags or non-critical configuration flags; The configuration bits in the configuration bit set that are marked as critical configuration bits are selected as critical configuration bits, thus obtaining the critical configuration bit set.
[0028] Specifically, in this embodiment, the configuration memory is used to store the configuration information of the FPGA. The basic storage unit of the configuration memory is a configuration frame, and each configuration frame contains a certain number of configuration bits. The function under test (DUT) occupies a specific physical area on the FPGA chip, which can be obtained through chip layout information or related design documents, or by manual specification. For example, since there is a correspondence between the FPGA's configuration memory and the physical area, in this embodiment, two sets of coordinates can be selected in the device plane planning to constrain the physical area occupied by the DUT, thereby determining the configuration frame interval corresponding to the DUT in the configuration memory, and obtaining the configuration bit set based on each configuration bit in the configuration frame interval.
[0029] In one embodiment, the preset marker file includes marker types corresponding to each configuration bit in the configuration memory. The marker types include critical configuration markers or non-critical configuration markers. The preset marker file can be an EBD file, which can be generated using design tools after the FPGA implementation is complete. The EBD file provides the marker type corresponding to each configuration bit in ASCII format. The marker type is stored in character form. The character "1" represents a critical configuration marker, indicating that a single-event upset (SEE) of the configuration bit corresponding to that character may affect the functionality of the module under test. The character "0" represents a non-critical configuration marker, indicating that a SEE of the configuration bit corresponding to that character will not affect the functionality of the module under test. Due to the preset mapping relationship (linear correlation) between the physical address of the configuration memory and the EBD row number, the preset mapping relationship can be used to extract the EBD row set (32 characters per row) corresponding to the configuration frame region from the EBD file, thereby determining the marker type (i.e., character "1" or character "0") corresponding to each configuration bit in the configuration bit set. Based on this, the configuration bits in the configuration bit set whose marker type is critical configuration marker can be taken as critical configuration bits (i.e., the configuration bits corresponding to character "1"), thus obtaining the critical configuration bit set. This ensures an accurate correspondence between the configuration bit set and the functional modules, providing an accurate data foundation for subsequent analysis.
[0030] It should be understood that the configuration bits marked as critical configuration tags in this embodiment (i.e., critical configuration bits) are potentially sensitive configuration bits. Selecting such configuration bits from the configuration bit set based on their tag type to obtain the critical configuration bit set can effectively reduce the amount of data processing, allowing subsequent simulations to focus on configuration bits that play a crucial role in the functional implementation of the functional module, thereby effectively improving the reliability prediction efficiency of the functional module under test.
[0031] S2: Simultaneously run the function module under test and the reference function module in the preset simulation platform, and inject single-event upset faults into each key configuration bit in the key configuration bit set corresponding to the function module under test; wherein, the reference function module represents the function module under test that has not been injected with single-event upset faults.
[0032] Specifically, in this embodiment, the preset simulation platform refers to a software platform specifically designed to simulate the FPGA operating environment. The platform can simulate the operation of the functional module under test and the reference functional module. Based on this, this embodiment can instantiate a single-event upset (SED) fault injection engine (such as an existing SEM IP) and integrate it into the FPGA to achieve the function of injecting SED faults one by one into key configuration bits.
[0033] Optionally, before injecting single-event upset faults into each key configuration bit in the key configuration bit set corresponding to the functional module under test, the method further includes: Based on the mapping position of the key configuration bits in the preset tag file, determine the physical address of the key configuration bits in the configuration memory; wherein, the physical address is used to indicate the target location for injecting a single-event flip fault in the simulation environment.
[0034] Specifically, in this embodiment, the mapping position refers to the position of the character corresponding to the key configuration bit in the preset marker file, determined based on a preset mapping relationship. After identifying the key configuration bit, this embodiment can determine the physical address of the key configuration bit in the configuration memory according to the preset mapping relationship. Taking the preset marker file as an EBD file as an example, each line of the EBD file consists of 32 characters (0 or 1), corresponding to 32 bits of a configuration word. Assuming that each configuration frame in the configuration memory of this embodiment consists of 101 words, corresponding to 101 lines of the EBD file, the EBD line number and the character position within the line can be converted into a linear frame address, word address, and bit address B to obtain the physical address of the key configuration bit in the configuration memory. The physical address satisfies: ; Wherein, LA represents the linear frame address, WD represents the word address, and BT represents the bit address. Together, these three constitute the physical address of the critical configuration bits. Indicates the line number of the EBD file. This represents the remainder when the current line number is divided by 101. This indicates the mapping position of the character corresponding to the critical configuration bit in the EBD file. Thus, based on the mapping position of the critical configuration bit in the preset marker file, this embodiment can determine the physical address of the critical configuration bit in the configuration memory, providing an accurate and reliable target location reference for subsequently injecting single-event upset faults in the simulation environment.
[0035] In one embodiment, when the simulation platform synchronously runs the function module under test and the reference function module, a single-event upset fault can be injected into each key configuration bit in the key configuration bit set one by one using the injection engine. This simulates a fault situation where a high-energy particle collides with a key configuration bit, causing the logic value of the key configuration bit to flip (0 becomes 1 or 1 becomes 0). Optionally, in this embodiment, single-event upset faults can be injected sequentially according to the order of each key configuration bit in the key configuration bit set to avoid omissions.
[0036] It should be understood that in this implementation, only one key configuration bit is injected with a single event fault at a time. Before injecting a single event fault into the next key configuration bit, the single event fault of the previous key configuration bit needs to be removed.
[0037] S3: When the output of the function module under test does not meet the preset consistency conditions with the output of the reference function module, the key configuration bit of the corresponding injected single-event upset fault will be used as the sensitive configuration bit.
[0038] Specifically, in this embodiment, the sensitive configuration bit refers to the configuration bit that can affect the logic function of the module under test after a single-event upset (i.e., a change in logic value). The preset consistency condition in this embodiment refers to the reference benchmark for judging whether the output of the module under test is consistent with the output of the reference module, which can be preset according to requirements. In this embodiment, during the simulation of the operation of the module under test and the reference module in a preset simulation platform, single-event upset faults can be injected into key configuration bits one by one. After each single-event upset fault injection, the outputs of the module under test and the reference module can be synchronously acquired under the same input stimulus and the same clock sampling, and the sensitive configuration bit is identified based on the comparison result of the two outputs.
[0039] Optionally, before setting the critical configuration bit of the injected single-event upset fault as the sensitive configuration bit when the output of the function module under test and the output of the reference function module do not meet the preset consistency conditions, the method further includes: The outputs of each output channel corresponding to the functional module under test and the reference functional module are obtained respectively, and the first output and the second output corresponding to each output channel are obtained. When the first output and the second output corresponding to the output channel are inconsistent, it indicates that the preset consistency condition is not met.
[0040] Optionally, after obtaining the first and second outputs corresponding to each output channel, the method further includes: When the first output and the second output corresponding to the output channel are inconsistent, the output channel is regarded as a mismatched output channel, and the sensitive configuration bits are associated with the corresponding mismatched output channel to build a sensitive configuration bit database.
[0041] Specifically, in this embodiment, both the function module under test (DUT) and the reference function module include multiple output channels. After a single-event upset (SWE) fault injection, the outputs of each corresponding output channel can be acquired synchronously, resulting in a first output and a second output for each channel. Based on this, the consistency of the first and second outputs for each output channel can be compared. If the first and second outputs for a given output channel are inconsistent, it indicates that a preset consistency condition is not met. This embodiment uses output channel-level consistency judgment to identify whether the outputs of the DUT and the reference function module are consistent. This method helps to comprehensively capture abnormal output conditions of the DUT caused by SWEs, avoiding overlooking subtle differences that may affect the performance of the DUT. It also helps to more accurately determine sensitive configuration bits, thereby improving the accuracy of FPGA functional-level reliability prediction.
[0042] Furthermore, when the first output and the second output of an output channel are inconsistent, the output channel is designated as a mismatched output channel. For example, assuming the first output of a certain output channel is [1010, 1100, 0101…] and the second output is [1010, 1110, 0101…], each data bit can be compared one by one. Since the second data bit corresponding to the first output and the second output is different, it can be determined that the preset consistency condition is not met, and the output channel is designated as a mismatched output channel. In this embodiment, after comparing the first output and the second output of each output channel to obtain each mismatched output channel, the key configuration bit that causes the non-compliance condition can be designated as a sensitive configuration bit, and the sensitive configuration bit can be associated with each corresponding mismatched output channel for storage, thus constructing a sensitive configuration bit database. This sensitive configuration bit database can provide a reliable basis for fault analysis during subsequent actual use of the FPGA, facilitating rapid diagnosis of functional abnormalities caused by single-event upsets, thereby improving the efficiency of fault diagnosis in practical applications.
[0043] S4: Determine the target proportion of sensitive configuration bits in the configuration bit set, and obtain the reliability prediction result of the functional module under test based on the target proportion.
[0044] Specifically, the target percentage in this embodiment can be obtained as the ratio of the total number of sensitive configuration bits to the total number of configuration bits in the configuration bit set. For example, assuming there are 5000 configuration bits in the configuration bit set, and after the above steps, 10 sensitive configuration bits are identified, then the target percentage is 10 / 5000 = 0.002. Generally speaking, the lower the target percentage, the less likely the functional module under test is to malfunction due to single-event upset, and the higher its reliability; conversely, the higher the target percentage, the lower the reliability. Thus, the reliability prediction result of the functional module under test can be obtained.
[0045] Optionally, the reliability prediction results for the functional modules under test are obtained based on the target proportion, including: Obtain the particle flux spectrum and single-particle flip section corresponding to the preset space radiation environment, and determine the single-particle flip rate of each configuration bit in the configuration bit set based on the particle flux spectrum and single-particle flip section. Based on the single-event flip rate and the target proportion, the predicted failure rate of the functional module under test is obtained when it runs in a preset space radiation environment, and the reliability prediction result is obtained based on the predicted failure rate.
[0046] Specifically, the preset space radiation environment referred to in this embodiment represents the specific space region and its corresponding radiation conditions (such as the near-Earth orbit environment) that the FPGA actually needs to deploy, which can be determined according to the actual deployment requirements of the FPGA. The particle flux spectrum referred to in this embodiment represents the flux distribution of particles of different energies in the preset space radiation environment, i.e., the number of particles of different energies passing through a unit area per unit time, which can be obtained from publicly available data. The single-event flip cross section referred to in this embodiment is a physical quantity that measures the sensitivity of configuration bits to single-event flips. It represents the probability of a particle causing a single-event flip per unit area. This can be obtained through experiments with ground-based heavy ion or proton accelerators, obtaining the configuration bit flip cross section of the FPGA at different linear transmission energy values. Combined with the particle flux spectrum provided by the model corresponding to the preset space radiation environment (such as the CREME model), the average flip rate of the configuration bits in the FPGA configuration memory during operation in the preset space radiation environment can be predicted, thus obtaining the single-event flip rate. In this embodiment, the single-event flip rate satisfies: ; in, The single-particle flip rate represents the average number of flips of the configuration bit under a preset space radiation environment for one day; LET represents the energy deposited per unit path length by the incident particle as it passes through the configuration memory. Indicates a single-particle flip section; This represents the particle flux spectrum, which indicates the flux distribution of different particles. This represents the total number of all configuration bits in the configuration bit set; Optionally, the predicted failure rate satisfies: ; in, Indicates the predicted failure rate; Indicates the single-particle flip rate; Indicates the number of sensitive configuration bits. This indicates the total number of all configuration bits in the configuration memory. and The ratio is equal to the target percentage.
[0047] Specifically, in this embodiment, after determining the target proportion of the sensitive configuration bits in the configuration bit set and the single-event flip rate of the configuration bits, the predicted failure rate corresponding to the functional module under test can be obtained based on the product of the two. This rate represents the probability that the functional module under test will experience at least one functional failure after operating in a preset space radiation environment for one day. This embodiment determines the single-event flip rate of the configuration bits by combining the particle flux spectrum and single-event flip cross section of the preset space radiation environment, and then combines it with the target proportion to obtain the predicted failure rate, making the final reliability prediction more scientific, accurate, and in line with the actual application scenario. Considering the particle characteristics of the space radiation environment and the target proportion of the sensitive configuration bits, the failure risk of the functional module under test operating in this environment is comprehensively evaluated.
[0048] Optionally, after obtaining the single-event flip rate and sensitive configuration bit database, this embodiment can determine the injection probability of single-event flip faults based on the target proportion of sensitive configuration bits and the single-event flip rate. Random single-event flip faults can then be injected into sensitive configuration bits based on this injection probability, thereby achieving behavioral-level modeling of single-event flip faults. For example, assuming the single-event flip rate is 100 times per day and the target proportion is 0.1 (i.e., 10%), then the number of single-event flip events occurring in sensitive configuration bits per day is 10. The injection probability of single-event flip faults (i.e., 10 times per day) can be determined based on this. During simulation, random single-event flip faults can be injected into the functional module under test based on this injection probability, thereby conducting more realistic simulation tests on the functional module under test. This achieves decoupling modeling of the configuration bit flip sensitivity (i.e., target proportion) at the physical layer and the error propagation sensitivity (i.e., single-event flip rate) at the logical functional layer, thereby improving the comprehensiveness and reference value of reliability testing.
[0049] In this embodiment, by acquiring the set of configuration bits corresponding to the functional module under test (DUT) in the FPGA and selecting a set of key configuration bits from this set, it is beneficial to ensure that subsequent simulations can focus on the configuration bits that play a crucial role in the function of the DUT, thereby effectively improving the reliability prediction efficiency of the DUT. Based on this, this embodiment synchronously runs the DUT with single-event upset (SEY) faults injected and the reference DUT without SEY faults injected in a preset simulation platform, providing a reliable reference for subsequent identification of sensitive configuration bits. Specifically, during simulation, this embodiment injects SEY faults one by one into each key configuration bit in the set of key configuration bits corresponding to the DUT, which is beneficial for systematically observing the changes in the output of the DUT when each key configuration bit is affected by an SEY fault. Furthermore, when the output of the DUT does not meet the preset consistency condition with the output of the reference DUT, it indicates that its logic function is affected by the SEY fault in the key configuration bit. In this case, the key configuration bit injected with the SEY fault is taken as the sensitive configuration bit, ensuring the accuracy of sensitive configuration bit identification. In this embodiment, by pre-setting consistency conditions, a clear standard is established for determining whether the output of the functional module under test is normal, which helps to improve the objectivity and accuracy of sensitive configuration bit identification. Based on this, this embodiment can evaluate the reliability of the functional module under test based on the target proportion of sensitive configuration bits in the configuration bit set, thereby obtaining a reliability prediction result.
[0050] Thus, this embodiment eliminates the need to place the FPGA in an actual radiation environment for complex operations to obtain reliability test results. It enables efficient and accurate functional-level reliability prediction in a simulation environment, thereby helping designers understand the reliability status of the functional modules under test in the FPGA in the space radiation environment in advance, and providing a strong basis for the optimization design of the FPGA and the adoption of protective measures.
[0051] like Figure 2 As shown, an embodiment of the present invention provides an FPGA functional-level reliability prediction device 200, comprising: The filtering module 210 is used to obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and to filter out the set of key configuration bits from the set of configuration bits. The simulation module 220 is used to synchronously run the functional module under test and the reference functional module in a preset simulation platform, and inject single-event upset faults into each key configuration bit in the key configuration bit set corresponding to the functional module under test; wherein, the reference functional module represents the functional module under test that has not been injected with the single-event upset fault. The identification module 230 is used to identify the key configuration bit corresponding to the single-event flip fault injected into the function module as a sensitive configuration bit when the output of the function module under test and the output of the reference function module do not meet the preset consistency conditions. The prediction module 240 is used to determine the target proportion of the sensitive configuration bits in the configuration bit set, and obtain the reliability prediction result corresponding to the functional module under test based on the target proportion.
[0052] The FPGA functional level reliability prediction device and the FPGA functional level reliability prediction method provided in this embodiment can produce basically the same technical effects, and will not be described again here.
[0053] like Figure 3 As shown, an electronic device 300 provided in this embodiment of the invention includes a memory 310 and a processor 320; the memory 310 is used to store a computer program; the processor 320 is used to implement the FPGA functional level reliability prediction method as described above when the computer program is executed.
[0054] Alternatively, an electronic device 300 includes a memory 310 and a processor 320 coupled to the memory 310; the memory 310 is configured to store a computer program; and the processor 320 is configured to perform the following operations when the computer program is executed: Obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and filter out the set of key configuration bits from the set of configuration bits; The test module and the reference module are run synchronously in a preset simulation platform, and a single-event upset fault is injected into each key configuration bit in the key configuration bit set corresponding to the test module; wherein, the reference module represents the test module that has not been injected with the single-event upset fault. When the output of the function module under test does not meet the preset consistency condition with the output of the reference function module, the key configuration bit corresponding to the single-event flip fault is used as the sensitive configuration bit. Determine the target proportion of the sensitive configuration bit in the configuration bit set, and obtain the reliability prediction result corresponding to the functional module under test based on the target proportion.
[0055] The electronic device and the FPGA functional level reliability prediction method provided in this embodiment can produce basically the same technical effects, and will not be described again here.
[0056] This invention provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the FPGA functional-level reliability prediction method as described above.
[0057] Alternatively, a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to perform the following operations: Obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and filter out the set of key configuration bits from the set of configuration bits; The test module and the reference module are run synchronously in a preset simulation platform, and a single-event upset fault is injected into each key configuration bit in the key configuration bit set corresponding to the test module; wherein, the reference module represents the test module that has not been injected with the single-event upset fault. When the output of the function module under test does not meet the preset consistency condition with the output of the reference function module, the key configuration bit corresponding to the single-event flip fault is used as the sensitive configuration bit. Determine the target proportion of the sensitive configuration bit in the configuration bit set, and obtain the reliability prediction result corresponding to the functional module under test based on the target proportion.
[0058] The computer-readable storage medium provided in this embodiment and the FPGA functional level reliability prediction method can produce essentially the same technical effects, and will not be described again here.
[0059] The present invention will now be described an electronic device 300 that can serve as a server or client of the present invention, which is an example of a hardware device that can be applied to various aspects of the present invention. Electronic device 300 is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device 300 can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.
[0060] Electronic device 300 includes a computing unit that can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) or a computer program loaded from a storage unit into random access memory (RAM). The RAM may also store various programs and data required for device operation. The computing unit, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.
[0061] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. In this application, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention according to actual needs. Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units can be implemented in hardware or as software functional units.
[0062] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.
Claims
1. A method for predicting the functional level reliability of an FPGA, characterized in that, include: Obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and filter out the set of key configuration bits from the set of configuration bits; The test module and the reference module are run synchronously in a preset simulation platform, and a single-event upset fault is injected into each key configuration bit in the key configuration bit set corresponding to the test module; wherein, the reference module represents the test module that has not been injected with the single-event upset fault. When the output of the function module under test does not meet the preset consistency condition with the output of the reference function module, the key configuration bit corresponding to the single-event flip fault injected will be used as the sensitive configuration bit. Determine the target proportion of the sensitive configuration bit in the configuration bit set, and obtain the reliability prediction result corresponding to the functional module under test based on the target proportion.
2. The FPGA functional level reliability prediction method according to claim 1, characterized in that, The step of obtaining the set of configuration bits corresponding to the functional module under test in the FPGA, and filtering out the set of key configuration bits from the set of configuration bits, includes: Obtain the physical region of the functional module under test in the FPGA, and determine the configuration frame interval corresponding to the functional module under test in the configuration memory of the FPGA based on the physical region, and obtain the configuration bit set according to each configuration bit in the configuration frame interval; The tag type corresponding to each configuration bit in the configuration bit set is determined according to the preset tag file; wherein, the preset tag file includes the tag type corresponding to each configuration bit in the configuration memory, and the tag type includes critical configuration tags or non-critical configuration tags; The configuration bits in the configuration bit set whose tag type is the key configuration tag are taken as the key configuration bits to obtain the key configuration bit set.
3. The FPGA functional level reliability prediction method according to claim 2, characterized in that, Before injecting single-event upset faults into each key configuration bit in the key configuration bit set corresponding to the functional module under test, the method further includes: Based on the mapping position of the key configuration bit in the preset tag file, the physical address of the key configuration bit in the configuration memory is determined; wherein, the physical address is used to indicate the target location for injecting the single-event flip fault in the simulation environment.
4. The FPGA functional level reliability prediction method according to claim 1, characterized in that, Before setting the critical configuration bit corresponding to the single-event upset fault injected as a sensitive configuration bit when the output of the function module under test and the output of the reference function module do not meet the preset consistency condition, the method further includes: The outputs of each output channel corresponding to the functional module under test and the reference functional module are obtained respectively, and the first output and the second output corresponding to each output channel are obtained. When the first output and the second output corresponding to the output channel are inconsistent, it indicates that the preset consistency condition is not met.
5. The FPGA functional level reliability prediction method according to claim 4, characterized in that, After obtaining the first output and second output corresponding to each of the output channels, the method further includes: When the first output corresponding to the output channel is inconsistent with the second output, the output channel is regarded as a mismatched output channel, and the sensitive configuration bit is associated with the corresponding mismatched output channel to construct a sensitive configuration bit database.
6. The FPGA functional level reliability prediction method according to claim 1, characterized in that, The process of obtaining the reliability prediction result corresponding to the functional module under test based on the target proportion includes: Obtain the particle flux spectrum and single-particle flip section corresponding to the preset space radiation environment, and determine the single-particle flip rate of each configuration bit in the configuration bit set based on the particle flux spectrum and the single-particle flip section. Based on the single-particle flip rate and the target proportion, the predicted failure rate of the functional module under test is obtained when it operates under the preset space radiation environment, and the reliability prediction result is obtained based on the predicted failure rate.
7. The FPGA functional level reliability prediction method according to claim 6, characterized in that, The predicted failure rate satisfies: ； in, This represents the predicted failure rate; This represents the single-particle flip rate; This indicates the total number of the sensitive configuration bits. This represents the total number of all configuration bits in the configuration bit set. and The ratio is equal to the target percentage.
8. An FPGA functional-level reliability prediction device, characterized in that, include: A filtering module is used to obtain the set of configuration bits corresponding to the functional module under test in the FPGA, and to filter out the set of key configuration bits from the set of configuration bits. The simulation module is used to synchronously run the functional module under test and the reference functional module in a preset simulation platform, and inject single-event upset faults into each key configuration bit in the key configuration bit set corresponding to the functional module under test; wherein, the reference functional module represents the functional module under test that has not been injected with the single-event upset fault. The identification module is used to identify the key configuration bit corresponding to the single-event flip fault injected into the reference function module as a sensitive configuration bit when the output of the function module under test does not meet the preset consistency condition. The prediction module is used to determine the target proportion of the sensitive configuration bits in the configuration bit set, and to obtain the reliability prediction result corresponding to the functional module under test based on the target proportion.
9. An electronic device, characterized in that, Including memory and processor; The memory is used to store computer programs; The processor is configured to implement the FPGA functional-level reliability prediction method as described in any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the FPGA functional level reliability prediction method as described in any one of claims 1 to 7.