Electrothermal coupling rapid simulation method for multi-core particle packaging

Abstract

The invention discloses an electrothermal coupling rapid simulation method for multi-core-particle packaging, and the method comprises the steps: calculating corresponding thermal resistance and thermal capacity through solving equivalent thermal parameters of each layer of structure of Chiplet packaging, and building a steady-state and transient equivalent circuit for thermal simulation based on a thermoelectric equivalent relation; compared with a traditional numerical calculation method, the calculation amount is greatly reduced, the simulation speed is increased, and the defect that a traditional thermal resistance matrix or a thermal resistance network cannot conduct transient thermal simulation is overcome. According to the method, the coupling thermal resistance between the chips is considered at the same time, and the accuracy of the model is improved under the condition that the thermal coupling effect of the chips is remarkable. Besides, the method further achieves transient coupling rapid simulation of the equivalent circuit model and the chip power consumption model by building the chip power consumption model and finally through an iteration method, and obtains transient electric heating performance of the whole time period by calculating power consumption and temperature distribution at all moments, so that the performance of the electric heating coupling system is evaluated more accurately. And the scheduling and the path of the whole system are optimized.

Description

Technical Field

[0001] This invention relates to a rapid simulation method for electrothermal coupling in multi-chip package, belonging to the technical field of integrated circuit packaging. Background Technology

[0002] As chip feature sizes shrink, the manufacturing cost and design complexity of System-on-a-Chip (SoC) technology have been increasing in recent years. Chipplet technology is a chip design method that replaces the traditional monolithic SoC design with a design based on multiple chips and integrates them using advanced packaging processes. It features improved yield, breakthroughs in photomask limitations, and flexible chip architecture. However, as chip package sizes continue to shrink and power densities continue to increase, power consumption per unit volume of the chip continues to increase, and the internal temperature of the chip rises sharply. Chip heat dissipation has become one of the most important reliability challenges in advanced packaging; at the same time, with the continuous increase in power density, the electrothermal coupling effect in integrated circuits is also attracting increasing attention.

[0003] Electrothermal coupling simulation is an effective method for solving chip heat dissipation problems, improving chip efficiency and stability, and extending chip lifespan. Electrothermal coupling simulation is mainly divided into two categories: numerical methods and analytical methods. Numerical methods solve the heat conduction equation using the finite element method (FEM), finite volume method (FVM), and finite difference method (FDM), offering high accuracy but incurring huge computational costs. Analytical methods predict chip junction temperatures by establishing a thermal resistance topology network or thermal resistance matrix of the chip package structure. This significantly improves simulation speed at the cost of some accuracy, but its drawbacks include the ability to calculate only steady-state temperatures, not transient temperatures, failing to reflect the actual heating process of the chip, and neglecting the thermal coupling between chips, resulting in lower accuracy. Summary of the Invention

[0004] Purpose of the invention: To address the aforementioned existing technologies, this invention proposes a rapid simulation method for electrothermal coupling in multi-chip packaging, enabling steady-state thermal simulation of the packaging structure and simulating the transient temperature rise process of the chip, thereby reducing computational load and minimizing errors.

[0005] Technical solution: A rapid simulation method for electrothermal coupling in multi-core packaging, comprising the following steps:

[0006] S1: Treat each layer of the multi-core packaging structure as a homogeneous material and calculate the equivalent thermal conductivity, equivalent density and equivalent heat capacity.

[0007] S2: Construct an equivalent circuit model of thermal resistance and thermal capacitance;

[0008] S3: Based on S1 and S2, construct a chip power consumption model;

[0009] S4: Based on the power consumption model, perform electrothermal coupling simulation of multi-core packaging.

[0010] Furthermore, S1 specifically includes: the first core of the multi-core packaging structure... The layer structure in the layer plane If the thermal impedance in a certain direction is considered as a parallel connection of the thermal impedances of multiple sub-cubic blocks, and the thermal impedance of each sub-cubic block is considered as a series connection of the thermal impedances of various materials, then the... Layered structure in The equivalent thermal conductivity in the direction is:

[0011] (1)

[0012] in For the first Layered structure in Equivalent thermal conductivity in the direction, , and The first Layered structure in , , Length in the direction, For and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction; similarly, the first Layered structure in , The equivalent thermal conductivity in the direction is:

[0013] (2)

[0014] (3)

[0015] in, and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction; and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction;

[0016] Based on the volume ratio of different materials, the first The equivalent density and equivalent heat capacity of the layered structure are:

[0017] (4)

[0018] (5)

[0019] in For the first The equivalent density of the layered structure and The first Layer structure The density and volume of the material For the first The equivalent heat capacity of the layered structure, For the first Layer structure The heat capacity of the material.

[0020] Furthermore, S2 specifically includes: calculating the thermal resistance and thermal capacity of each layer of the structure along the heat flow path of each chip based on the equivalent thermal conductivity, equivalent density, and equivalent heat capacity of each layer in the multi-chip packaging model.

[0021] (6)

[0022] (7)

[0023] in It is a chip In the The thermal resistance of the layered structure It is a chip In the The cross-sectional area of ​​the heat flow path in the layered structure; It is a chip In the The heat capacity of the layered structure;

[0024] Based on the actual chip layout, the thermal resistance of each chip in the horizontal direction of each layer structure is calculated:

[0025] (8)

[0026] in It is a chip and chips In the The thermal resistance of the layered structure in the horizontal direction. It is a chip and chips Horizontal spacing, It is a chip and chips In the The cross-sectional area of ​​the heat flow path in the horizontal direction of the layered structure. for or ;

[0027] When the When the layer structure is the encapsulation surface, the convective thermal resistance to air also needs to be calculated:

[0028] (9)

[0029] in For the first The convective thermal resistance between the layered structure and the outside air. The convective heat transfer coefficient is... For chips In the The cross-sectional area of ​​the heat flow path on the surface of the layered structure;

[0030] Based on the thermoelectric equivalence relationship, the thermal resistance value is equivalent to the resistance value, the thermal capacity value is equivalent to the capacitance value, the chip power consumption is equivalent to the current source, and the chip temperature is equivalent to the node voltage. An equivalent circuit model is constructed based on the thermal resistance and thermal capacity topology relationship. The equivalent circuit model includes a steady-state equivalent circuit model and a transient equivalent circuit model.

[0031] Furthermore, in S3, the total power consumption of the chip is equal to the sum of the leakage current power consumption and the dynamic power consumption:

[0032] (10)

[0033] in This represents the total power consumption of the chip. For leakage current power consumption, For dynamic power consumption;

[0034] Leakage current power consumption is expressed as:

[0035] (11)

[0036] in The power supply voltage, Leakage current at standard temperature and voltage. This refers to the actual operating temperature of the integrated circuit. The bias voltage applied between the substrate and the source. These are constants related to circuit type, process, and design, derived by fitting actual power consumption data.

[0037] Dynamic power consumption is expressed as:

[0038] (12)

[0039] in It is an equivalent switched capacitor. This refers to the chip's operating frequency.

[0040] Furthermore, S4 specifically includes: based on the transient equivalent circuit model and the chip power consumption model, realizing the electrothermal coupling transient simulation of the multi-core packaging structure through an iterative method.

[0041] Furthermore, the steady-state equivalent circuit is composed of a thermal resistance network, which can be used to obtain the steady-state temperature distribution of the chip; the transient equivalent circuit is composed of a thermal resistance and thermal capacitance network, which can be used to obtain the transient temperature changes of the chip.

[0042] Furthermore, in S4, the initial power consumption of the chip is set at the beginning, and then the temperature distribution at the next moment is continuously calculated and the chip power consumption is updated. The iteration continues until convergence, and the curves of power consumption and temperature distribution over time are obtained, thereby obtaining the transient electrothermal performance over the entire time period.

[0043] Beneficial effects: The fast simulation method for electrothermal coupling of Chiplet packages proposed in this invention has the following significant advantages:

[0044] 1. This method constructs the thermal resistance and thermal capacitance equivalent circuit of the Chiplet package structure through analytical methods, which greatly reduces the amount of calculation and improves the simulation speed compared with traditional numerical calculation methods.

[0045] 2. This method characterizes the change of chip temperature over time by calculating heat capacity, which can perform transient thermal analysis compared with traditional thermal resistance matrix or thermal resistance topology network methods; at the same time, it considers the coupling thermal resistance between chips, which improves the accuracy of the model under the condition that the thermal coupling effect between chips is significant.

[0046] 3. This method can comprehensively consider circuit and thermal characteristics to realize transient simulation of chip electrothermal coupling, thereby more accurately evaluating the performance of electrothermal coupling system, optimizing the overall system scheduling and path, and improving system performance and efficiency. Attached Figure Description

[0047] Figure 1 This is a flowchart of the method of the present invention;

[0048] Figure 2 This is a side view of the Chiplet package structure according to an embodiment of the present invention;

[0049] Figure 3 This is a top view of the Chiplet packaging structure according to an embodiment of the present invention;

[0050] Figure 4 This is the steady-state model of the equivalent thermal resistance circuit of the Chiplet package according to an embodiment of the present invention;

[0051] Figure 5This is a transient model of the equivalent circuit of thermal resistance and thermal capacitance of the Chiplet package according to an embodiment of the present invention;

[0052] Figure 6 This is a flowchart of the electrothermal coupling process of the Chiplet package according to an embodiment of the present invention;

[0053] Figure 7 This is a diagram showing the electrothermal coupling result of the Chiplet package according to an embodiment of the present invention;

[0054] Figure reference numerals: 1-Copper heat sink layer, 2-Molding layer, 3-Chip layer, 4-Microbump layer, 5-Redistribution layer, 6-Microbump layer, 7-Substrate layer, 8-Bump layer. Detailed Implementation

[0055] The invention will now be further explained with reference to the accompanying drawings.

[0056] like Figure 1 As shown, the specific implementation scheme of the electrothermal coupling fast simulation method of the Chiplet package of the present invention is as follows:

[0057] S1: Treat each layer of the Chiplet package structure as a homogeneous material and calculate the equivalent thermal conductivity, equivalent density and equivalent heat capacity.

[0058] The first The layer structure in the layer plane If the thermal impedance in a certain direction is considered as a parallel connection of the thermal impedances of multiple sub-cubic blocks, and the thermal impedance of each sub-cubic block is considered as a series connection of the thermal impedances of various materials, then the... Layered structure in The equivalent thermal conductivity in the direction is:

[0059] (1)

[0060] in For the first Layered structure in Equivalent thermal conductivity in the direction, , and The first Layered structure in , , Length in the direction, and The first The first layer in each sub-cube of the layered structure Such materials in The length and thermal conductivity in the direction. Similarly, the first... Layered structure in , The equivalent thermal conductivity in the direction is:

[0061] (2)

[0062] (3)

[0063] in, and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction; and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction. direction and The directions are located on the same plane and are perpendicular to each other; direction and , The direction is perpendicular to the plane.

[0064] Based on the volume ratio of different materials, the first The equivalent density and equivalent heat capacity of the layered structure are:

[0065] (4)

[0066] (5)

[0067] in For the first The equivalent density of the layered structure and The first Layer structure The density and volume of the material For the first The equivalent heat capacity of the layered structure, For the first Layer structure The heat capacity of the material.

[0068] like Figure 2 and Figure 3 As shown, the Chiplet packaging structure used in this embodiment includes, from top to bottom, a copper heat sink layer 1, a molding layer 2, a chip layer 3, a microbump layer 4, a redistribution layer 5, a microbump layer 6, a substrate layer 7, and a bump layer 8. Chip layer 3 contains five chips, numbered sequentially from chip one to chip five. Chip one has a size of 43*55 mm. 3 Chip 2 to chip 5 measures 15*25 mm.3 .

[0069] like Figure 2 As shown, the microbump layer 4, redistribution layer 5, microbump layer 6 and substrate layer 7 in the packaging structure are all complex structures made of multiple materials, and the thermal resistance or thermal capacity cannot be directly solved. Therefore, the equivalent thermal conductivity, density and thermal capacity of each layer structure are calculated by equations (1) to (5).

[0070] S2: Construct an equivalent circuit model of thermal resistance and thermal capacitance.

[0071] Based on the equivalent thermal conductivity, equivalent density, and equivalent heat capacity of each layer in the Chiplet packaging model, calculate the thermal resistance and heat capacity of each layer along the heat flow path of each chip:

[0072] (6)

[0073] (7)

[0074] in It is a chip In the The thermal resistance of the layered structure It is a chip In the The cross-sectional area of ​​the heat flow path in the layered structure; It is a chip In the The heat capacity of the layered structure.

[0075] Based on the actual chip layout, the thermal resistance of each chip in the horizontal direction of each layer structure is calculated:

[0076] (8)

[0077] in It is a chip and chips In the The thermal resistance of the layered structure in the horizontal direction. It is a chip and chips Horizontal spacing, It is a chip and chips In the The cross-sectional area of ​​the heat flow path in the horizontal direction of the layered structure. for or .

[0078] In addition, when the When the layer structure is the encapsulation surface, its convective thermal resistance to air also needs to be calculated:

[0079] (9)

[0080] in For the first The convective thermal resistance between the layered structure and the outside air. The convective heat transfer coefficient is... For chips In the The cross-sectional area of ​​the heat flow path on the surface of the layered structure.

[0081] Based on the thermoelectric equivalence relationship, the thermal resistance value obtained above is equivalent to the resistance value, the thermal capacity value is equivalent to the capacitance value, the chip power consumption is equivalent to the current source, and the chip temperature is equivalent to the node voltage. An equivalent circuit model is then constructed based on the thermal resistance and thermal capacity topology relationship.

[0082] In the Chiplet packaging model example used in this embodiment, considering both the horizontal thermal conductivity of each packaging layer and its vertical distance to chip layer 3, only the horizontal thermal resistance of the copper heat sink layer 1, molding layer 2, and redistribution layer 5 is considered. For example... Figure 4 As shown, by solving the horizontal and vertical thermal resistances of each chip in each layer of the packaging structure, and based on the thermoelectric equivalence relationship, an equivalent circuit model for solving the steady-state temperature was constructed. Figure 5 As shown, by solving the heat capacity of each chip in each layer of the packaging structure and combining it with the steady-state circuit model, a transient equivalent circuit model for solving transient temperature was built.

[0083] like Figure 4 , Figure 5 As shown, the equivalent circuit model for steady-state and transient thermal simulation consists of resistors (thermal resistances) and has five vertical thermal paths, each numbered R from top to bottom. air(i)1 R sink(i) R EMC(i) R die(i) R bump(i)1 R RDL(i) R bump(i)2 R sub(i) R bump(i)3 R air(i)2 The thermal paths, in sequence, correspond to the top convection thermal resistance, heat sink layer conduction thermal resistance, molding compound layer conduction thermal resistance, chip conduction thermal resistance, Micro-bump1 conduction thermal resistance, RDL adapter board conduction thermal resistance, Micro-bump2 conduction thermal resistance, substrate layer conduction thermal resistance, solder bump conduction thermal resistance, and bottom convection thermal resistance. The thermal path number (i) ranges from 1 to 5, corresponding to the thermal conduction paths of one computing chip and four memory chips, respectively. This embodiment considers the horizontal coupling thermal resistance of the heat sink layer, the molding compound filling between chips, and the RDL layer, which are, in sequence, the top convection thermal resistance, the heat sink layer conduction ... Figure 4 , Figure 5R in sink(i)_(j) R EMC(i)_(j) R RDL(i)_(j) The thermal path numbers (i) and (j) range from 1 to 5, representing the horizontal coupling thermal resistance between chip (i) and chip (j). For example... Figure 5 As shown, the transient thermal simulation equivalent circuit model adds several capacitors (thermal capacitive capacitors) to the steady-state model. The capacitors on each thermal path are numbered C from top to bottom. sink(i) C ED(i) C bump(i)1 C RDL(i) C bump(i)2 C sub(i) C bump(i)3 The corresponding thermal capacities are, in order: heat sink layer, molding layer and chip layer, Micro-bump1, RDL adapter board, Micro-bump2, substrate layer and Solder bump. Figure 4 and Figure 5 The values ​​of each component in the equivalent circuit model are detailed in Table 1. Furthermore, since chips two through five are the same size and spatially symmetrical, the corresponding thermal resistance and thermal capacitance values ​​of chips two through five in the same layer structure are equal, as shown in copper heat sink layer 1: R sink2 =R sink3 =R sink4 =R sink5 R sink1_2 =R sink1_3 =R sink1_4 =R sink1_5 R sink2_3 =R sink4_5 C sink2 =C sink3 =C sink4 =C sink5 And so on.

[0084] Table 1. Values ​​of each component in the equivalent circuit

[0085] Devices numerical values Devices numerical values Devices numerical values Devices numerical values [R ari11 ]] 10.485Ω [R ari21 ]] 29.421Ω [R sink1_2 ]] 1.690Ω [C bump12 ]]> 16.094F [R sink1 ]]> 0.002Ω [R sink2 ]] 0.010Ω <![CDATA[R sink2_3 ]]> 1.901Ω <![CDATA[C sub1 ]]> 26.934F <![CDATA[R EMC1 ]]> 0.126Ω <![CDATA[R EMC2 ]]> 0.782Ω <![CDATA[R EMC1_2 ]]> 48.048Ω <![CDATA[C bump13 ]]> 17.457F <![CDATA[R die1 ]]> 0.005Ω <![CDATA[R die2 ]]> 0.030Ω <![CDATA[R EMC2_3 ]]> 400.400Ω <![CDATA[C sink2 ]]> 2.852F <![CDATA[R bump11 ]]> 0.030Ω <![CDATA[R bump21 ]]> 0.191Ω <![CDATA[R RDL1_2 ]]> 4.030Ω <![CDATA[C ED2 ]]> 1.140F <![CDATA[R RDL1 ]]> 0.793Ω <![CDATA[R RDL2 ]]> 5.000Ω <![CDATA[R RDL2_3 ]]> 4.554Ω <![CDATA[C bump21 ]]> 1.071F <![CDATA[R bump12 ]]> 0.012Ω <![CDATA[R bump22 ]]> 0.074Ω <![CDATA[C sink1 ]]> 15.937F <![CDATA[C RDL2 ]]> 2.144F <![CDATA[R sub1 ]]> 6.083Ω <![CDATA[R sub2 ]]> 27.930Ω <![CDATA[C ED1 ]]> 7.181F <![CDATA[C bump22 ]]> 2.552F <![CDATA[R bump13 ]]> 0.029Ω <![CDATA[R bump23 ]]> 0.100Ω <![CDATA[C bump11 ]]> 6.757F <![CDATA[C sub2 ]]> 5.942F <![CDATA[R air12 ]]> 15.517Ω <![CDATA[R air22 ]]> 50.099Ω <![CDATA[C RDL1 ]]> 13.520F <![CDATA[C bump23 ]]> 5.083F

[0086] S3: Build a chip power consumption model.

[0087] Based on the BSIM4 model (a circuit simulation model for semiconductor device modeling), the total power consumption of the chip equals the sum of leakage current power consumption and dynamic power consumption:

[0088] (10)

[0089] in This represents the total power consumption of the chip. For leakage current power consumption, This refers to dynamic power consumption.

[0090] Leakage current power consumption is expressed as:

[0091] (11)

[0092] in The power supply voltage, Leakage current at standard temperature and voltage. This refers to the actual operating temperature of the integrated circuit. The bias voltage applied between the substrate and the source. These are constants related to circuit type, process, and design, derived by fitting actual power consumption data.

[0093] Dynamic power consumption is expressed as:

[0094] (12)

[0095] in It is an equivalent switched capacitor. This refers to the chip's operating frequency.

[0096] In the Chiplet packaging model example used in this embodiment, the heat dissipation of chips two to five is considered as a constant value, and the electrothermal coupling effect of chip one is taken into account. The power consumption model parameters of chip one based on equations (10) to (12) are detailed in Table 2.

[0097] Table 2. Power consumption model parameters for chip one

[0098] parameter numerical values parameter numerical values parameter numerical values parameter numerical values parameter numerical values A <![CDATA[5.406*10 -4 ]]> α 1127 β 1670 γ 2224 B <![CDATA[6.597*10 -4 ]]> μ 5.69 <![CDATA[V dd ]]> 0.9~1.4V <![CDATA[I s ]]> 1.238A <![CDATA[C eff ]]> 5nF <![CDATA[f max ]]> 2.16GHz

[0099] in This is the chip's highest operating frequency.

[0100] S4: Simulation of electrothermal coupling in Chiplet package.

[0101] Based on the transient equivalent circuit model and chip power consumption model, an iterative method is used to simulate the transient electrothermal coupling of a Chiplet package. Figure 6 As shown, the initial power consumption of the chip is set at the beginning, and then the temperature distribution at the next moment is continuously calculated and the chip power consumption is updated. By iterating until convergence, the curves of power consumption and temperature distribution over time can be obtained, and the transient electrothermal performance over the entire time period can be obtained.

[0102] Figure 7 The figure shows the electrothermal coupling result of the Chiplet package in this embodiment. As the temperature of chip one increases, the heat generation power of chip one also increases significantly, which fully demonstrates the effectiveness and necessity of the electrothermal coupling of the Chiplet package in this invention.

[0103] The present invention provides a rapid simulation method for electrothermal coupling of chipplet packages. This method calculates the corresponding thermal resistance and thermal capacitance by solving the equivalent thermal parameters of each layer of the chipplet package structure, and constructs steady-state and transient equivalent circuits for thermal simulation based on thermoelectric equivalence relationships. The transient equivalent circuit, composed of a thermal resistance and thermal capacitance network, can simulate transient temperature changes in the chip, providing a more accurate representation of the chip junction temperature rise over time compared to traditional thermal resistance matrix methods. Furthermore, this method constructs a chip power consumption model and ultimately achieves transient coupling simulation of the equivalent circuit model and the chip power consumption model through an iterative method. This allows for a more accurate evaluation of the performance of the electrothermal coupling system, improving system performance and efficiency.

[0104] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A rapid simulation method for electrothermal coupling in multi-core packaging, characterized in that, Includes the following steps: S1: Treat each layer of the multi-core packaging structure as a homogeneous material and calculate the equivalent thermal conductivity, equivalent density and equivalent heat capacity. S2: Construct an equivalent circuit model of thermal resistance and thermal capacitance; S3: Based on S1 and S2, construct a chip power consumption model; S4: Based on the power consumption model, perform electrothermal coupling simulation of multi-core packaging.

2. The method according to claim 1, characterized in that, S1 specifically includes: the first part of the multi-core packaging structure The layer structure in the layer plane If the thermal impedance in a given direction is considered as a parallel connection of the thermal impedances of multiple sub-cubic blocks, and the thermal impedance of each sub-cubic block is considered as a series connection of the thermal impedances of various materials, then the... Layered structure in The equivalent thermal conductivity in the direction is: (1) in For the first Layered structure in Equivalent thermal conductivity in the direction, , and The first Layered structure in , , Length in the direction, For and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction; similarly, the first Layered structure in , The equivalent thermal conductivity in the direction is: (2) (3) in, and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction; and The first The first layer in each sub-cube of the layered structure Such materials in Length and thermal conductivity in the direction; Based on the volume ratio of different materials, the first The equivalent density and equivalent heat capacity of the layered structure are: (4) (5) in For the first The equivalent density of the layered structure and The first Layer structure The density and volume of the material For the first The equivalent heat capacity of the layered structure, For the first Layer structure The heat capacity of the material.

3. The method according to claim 1, characterized in that, Specifically, S2 includes: calculating the thermal resistance and thermal capacity of each layer of the structure along the heat flow path of each chip based on the equivalent thermal conductivity, equivalent density, and equivalent heat capacity of each layer in the multi-chip packaging model. (6) (7) in It is a chip In the The thermal resistance of the layered structure It is a chip In the The cross-sectional area of ​​the heat flow path in the layered structure; It is a chip In the The heat capacity of the layered structure; Based on the actual chip layout, the thermal resistance of each chip in the horizontal direction of each layer structure is calculated: (8) in It is a chip and chips In the The thermal resistance of the layered structure in the horizontal direction. It is a chip and chips Horizontal spacing, It is a chip and chips In the The cross-sectional area of ​​the heat flow path in the horizontal direction of the layered structure. for or ; When the When the layer structure is the encapsulation surface, the convective thermal resistance to air also needs to be calculated: (9) in For the first The convective thermal resistance between the layered structure and the outside air. The convective heat transfer coefficient is... For chips In the The cross-sectional area of ​​the heat flow path on the surface of the layered structure; Based on the thermoelectric equivalence relationship, the thermal resistance value is equivalent to the resistance value, the thermal capacity value is equivalent to the capacitance value, the chip power consumption is equivalent to the current source, and the chip temperature is equivalent to the node voltage. An equivalent circuit model is constructed based on the thermal resistance and thermal capacity topology relationship. The equivalent circuit model includes a steady-state equivalent circuit model and a transient equivalent circuit model.

4. The method according to claim 1, characterized in that, In S3, the total power consumption of the chip is equal to the sum of the leakage current power consumption and the dynamic power consumption: (10) in This represents the total power consumption of the chip. For leakage current power consumption, For dynamic power consumption; Leakage current power consumption is expressed as: (11) in The power supply voltage, Leakage current at standard temperature and voltage. This refers to the actual operating temperature of the integrated circuit. The bias voltage applied between the substrate and the source. These are constants related to circuit type, process, and design, derived by fitting actual power consumption data. Dynamic power consumption is expressed as: (12) in It is an equivalent switched capacitor. This refers to the chip's operating frequency.

5. The method according to claim 1, characterized in that, Specifically, S4 includes: based on the transient equivalent circuit model and the chip power consumption model, realizing the electrothermal coupling transient simulation of the multi-core packaging structure through an iterative method.

6. The method according to claim 3, characterized in that, The steady-state equivalent circuit is composed of a thermal resistance network, which can determine the steady-state temperature distribution of the chip; the transient equivalent circuit is composed of a thermal resistance and thermal capacitance network, which can determine the transient temperature changes of the chip.

7. The rapid simulation method for electrothermal coupling of Chiplet packages according to claim 5, characterized in that, In step S4, the initial power consumption of the chip is set at the beginning, and then the temperature distribution at the next moment is continuously calculated and the chip power consumption is updated. The process is iterated until convergence, and the curves of power consumption and temperature distribution over time are obtained, thereby obtaining the transient electrothermal performance over the entire time period.

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