PCB layout generation method and electronic equipment

Abstract

The invention provides a PCB layout generation method and electronic equipment. The method comprises the following steps: acquiring layout design parameters; generating a condition vector according to the layout design parameters; inputting the condition vector into a pre-trained diffusion model, and performing multi-round reverse denoising processing by the diffusion model based on the initialized noise image and the condition vector to obtain an initial PCB layout image; and verifying the initial PCB layout image, and generating a target PCB layout image according to a verification result. According to the method, the layout design parameters are acquired, the corresponding condition vectors are generated, and the pre-trained diffusion model is utilized to perform multi-round reverse de-noising processing on the initialized noise image, so that the initial PCB layout image meeting the design requirement is intelligently generated; and the final target PCB layout image is obtained by verifying and optimizing the initial image, so that the problem that the PCB layout scheme cannot be efficiently and automatically generated in the prior art is effectively solved.

Description

Technical Field

[0001] This application relates to the field of electrical design technology, and more specifically, to a PCB layout generation method and an electronic device. Background Technology

[0002] With the rapid development of high-performance computing and communication technologies, printed circuit board (PCB) design faces enormous challenges. On the one hand, signal rates are constantly increasing, such as PCIe 6.0 with a rate of up to 64 Gbps, which places extremely high demands on trace impedance and crosstalk suppression. On the other hand, device packaging is becoming increasingly dense, and power consumption and heat density are continuously rising, leading to prominent thermal management issues.

[0003] Currently, existing PCB design primarily relies on manual placement and routing, as well as rule-based automated tools. Manual placement and routing is time-consuming and labor-intensive, heavily dependent on human experience. Rule-based automated tools, on the other hand, lack the global perception and dynamic optimization capabilities to handle complex physical coupling relationships, thus limiting their optimization efficiency. Therefore, existing technologies cannot efficiently and automatically generate PCB layout solutions. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a PCB layout generation method and electronic device, thereby solving the problem that the prior art cannot efficiently and automatically generate PCB layout schemes.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a PCB layout generation method, the method comprising: Obtain layout design parameters; Generate a condition vector based on the layout design parameters; The conditional vector is input into the pre-trained diffusion model, which performs multiple rounds of reverse denoising based on the initialized noisy image and the conditional vector to obtain the initial PCB layout image. The initial PCB layout image is verified to obtain the verification result, and the target PCB layout image is generated based on the verification result.

[0006] As one possible implementation, the layout design parameters include circuit netlist, signal rate information, thermal constraints, plate physical constraints, and manufacturing process constraints. The step of generating a condition vector based on the layout design parameters includes: The layout design parameters are structured and encoded to obtain multiple feature vectors; The condition vector is generated based on the plurality of feature vectors.

[0007] As one possible implementation, the layout design parameters are structured and encoded to obtain multiple feature vectors, including: The circuit netlist is converted into a graph structure and the graph structure is encoded to obtain a graph embedding vector. The graph structure includes multiple nodes and edges, where nodes represent component pins and edges represent electrical connections between component pins. The signal rate information is normalized to obtain a frequency feature vector; The power consumption values ​​of each component are encoded to obtain a thermal constraint feature vector; The stacked structure in the physical constraints of the electrode plate is encoded according to the layer attributes to obtain the stacked structure embedding vector; The manufacturing process constraints are encoded to obtain a manufacturing process feature vector.

[0008] As one possible implementation, generating the condition vector based on the plurality of feature vectors includes: The graph embedding vector, the frequency feature vector, the thermal constraint feature vector, the stacked structure embedding vector, and the manufacturing process feature vector are concatenated in a preset order to obtain a concatenated vector; The concatenated vector is mapped to generate the conditional vector.

[0009] As one possible implementation, the initial PCB layout image is obtained by performing multiple rounds of reverse denoising processing based on the initial noise image and the conditional vector using the diffusion model, including: Step A: Use the initialized noisy image as the initial image to be denoised; Step B: Based on the time step corresponding to the current round, the current image to be denoised, and the conditional vector, predict the noise components in the current image to be denoised; Step C: Denoise the current image to be denoised based on the noise components in the current image to be denoised, and obtain a denoised image; Step D: Use the denoised image as the new current image to be denoised; Step E: Repeat steps B-D until a preset number of rounds are reached, and output the initial PCB layout image.

[0010] As one possible implementation, the training process of the diffusion model includes: Obtain training samples, which include multiple PCB layout image samples; The PCB layout image sample is input into an initial diffusion model, which performs multiple rounds of noise addition processing on the PCB layout image. For each round of generated noisy image sample, the predicted noise component added to the noisy image sample is predicted. A standard denoising loss is determined based on the predicted noise component and the actual noise component of the noisy image sample. The initial diffusion model is then optimized based on the standard denoising loss and a preset loss function to train the diffusion model. The preset loss function is shown in the following expression:

[0011] in, Indicates the preset loss function. Indicates the standard denoising loss. This represents the crosstalk level estimated based on the surrogate model. This represents the temperature rise estimated based on the thermal resistance network model. This represents the radiation intensity estimated based on the area of ​​the current loop. , , These represent the weights.

[0012] As one possible implementation, verifying the initial PCB layout image to obtain the verification result includes: The initial PCB layout image is input into a preset simulation engine to perform electromagnetic simulation and thermal simulation respectively, and the electromagnetic simulation results and thermal simulation results are obtained. The electromagnetic simulation results and the thermal simulation results are weighted and scored to obtain a comprehensive score; The comprehensive score is compared with a preset threshold. If the comprehensive score is greater than or equal to the preset threshold, the verification is deemed successful. If the comprehensive score is less than the preset threshold, the verification is deemed unsuccessful.

[0013] As one possible implementation, generating the target PCB layout image based on the verification result includes: If the verification passes, the initial PCB layout image will be used as the target PCB layout image. If the verification fails, the diffusion model is adjusted based on the electromagnetic simulation results, the thermal simulation results, and the preset loss function to obtain the adjusted diffusion model. The condition vector is then input into the adjusted diffusion model, which generates a new PCB layout image based on the condition vector. The new PCB layout image is then verified.

[0014] As one possible implementation, the method further includes: If the new PCB layout image fails verification, the process of generating and verifying the generated PCB layout image continues iteratively. If the generated PCB layout image still fails verification after reaching the maximum number of iterations, the PCB layout image with the highest comprehensive score among all the PCB layout images generated during the iteration process is taken as the target PCB layout image.

[0015] Secondly, embodiments of this application provide a PCB layout generation apparatus, the apparatus comprising: The acquisition module is used to obtain layout design parameters; The generation module is used to generate a condition vector based on the layout design parameters; The denoising module is used to input the conditional vector into the pre-trained diffusion model, and the diffusion model performs multiple rounds of reverse denoising based on the initialized noise image and the conditional vector to obtain the initial PCB layout image. The verification module is used to verify the initial PCB layout image, obtain the verification result, and generate the target PCB layout image based on the verification result.

[0016] As one possible implementation, the layout design parameters include circuit netlist, signal rate information, thermal constraints, electrode physical constraints, and manufacturing process constraints; the generation module is specifically used for: The layout design parameters are structured and encoded to obtain multiple feature vectors; The condition vector is generated based on the plurality of feature vectors.

[0017] As one possible implementation, the generation module is specifically used for: The circuit netlist is converted into a graph structure and the graph structure is encoded to obtain a graph embedding vector. The graph structure includes multiple nodes and edges, where nodes represent component pins and edges represent electrical connections between component pins. The signal rate information is normalized to obtain a frequency feature vector; The power consumption values ​​of each component are encoded to obtain a thermal constraint feature vector; The stacked structure in the physical constraints of the electrode plate is encoded according to the layer attributes to obtain the stacked structure embedding vector; The manufacturing process constraints are encoded to obtain a manufacturing process feature vector.

[0018] As one possible implementation, the generation module is specifically used for: The graph embedding vector, the frequency feature vector, the thermal constraint feature vector, the stacked structure embedding vector, and the manufacturing process feature vector are concatenated in a preset order to obtain a concatenated vector; The concatenated vector is mapped to generate the conditional vector.

[0019] As one possible implementation, the noise reduction module is specifically used for: Step A: Use the initialized noisy image as the initial image to be denoised; Step B: Based on the time step corresponding to the current round, the current image to be denoised, and the conditional vector, predict the noise components in the current image to be denoised; Step C: Denoise the current image to be denoised based on the noise components in the current image to be denoised, and obtain a denoised image; Step D: Use the denoised image as the new current image to be denoised; Step E: Repeat steps B-D until a preset number of rounds are reached, and output the initial PCB layout image.

[0020] As one possible implementation, the noise reduction module is further used for: Obtain training samples, which include multiple PCB layout image samples; The PCB layout image sample is input into an initial diffusion model, which performs multiple rounds of noise addition processing on the PCB layout image. For each round of generated noisy image sample, the predicted noise component added to the noisy image sample is predicted. A standard denoising loss is determined based on the predicted noise component and the actual noise component of the noisy image sample. The initial diffusion model is then optimized based on the standard denoising loss and a preset loss function to train the diffusion model. The preset loss function is shown in the following expression:

[0021] in, Indicates the preset loss function. Indicates the standard denoising loss. This represents the crosstalk level estimated based on the surrogate model. This represents the temperature rise estimated based on the thermal resistance network model. This represents the radiation intensity estimated based on the area of ​​the current loop. , , These represent the weights.

[0022] As one possible implementation, the verification module is specifically used for: The initial PCB layout image is input into a preset simulation engine to perform electromagnetic simulation and thermal simulation respectively, and the electromagnetic simulation results and thermal simulation results are obtained. The electromagnetic simulation results and the thermal simulation results are weighted and scored to obtain a comprehensive score; The comprehensive score is compared with a preset threshold. If the comprehensive score is greater than or equal to the preset threshold, the verification is deemed successful. If the comprehensive score is less than the preset threshold, the verification is deemed unsuccessful.

[0023] As one possible implementation, the verification module is specifically used for: If the verification passes, the initial PCB layout image will be used as the target PCB layout image. If the verification fails, the diffusion model is adjusted based on the electromagnetic simulation results, the thermal simulation results, and the preset loss function to obtain the adjusted diffusion model. The condition vector is then input into the adjusted diffusion model, which generates a new PCB layout image based on the condition vector. The new PCB layout image is then verified.

[0024] As one possible implementation, the verification module is further configured to: If the new PCB layout image fails verification, the process of generating and verifying the generated PCB layout image continues iteratively. If the generated PCB layout image still fails verification after reaching the maximum number of iterations, the PCB layout image with the highest comprehensive score among all the PCB layout images generated during the iteration process is taken as the target PCB layout image.

[0025] Thirdly, embodiments of this application provide an electronic device, including: a processor, a storage medium, and a bus. The storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the PCB layout generation method as described in any of the first aspects above.

[0026] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the PCB layout generation method as described in any of the first aspects above.

[0027] According to the PCB layout generation method and electronic device of this application, by acquiring layout design parameters and generating corresponding condition vectors, a pre-trained diffusion model is used to perform multi-round reverse denoising on the initialized noisy image, thereby intelligently generating an initial PCB layout image that meets the design requirements. Then, the final target PCB layout image is obtained by verifying and optimizing the initial image. In this way, the problems of time-consuming and laborious manual layout and routing, reliance on experience, and lack of global dynamic optimization capabilities of rule-based automated tools in the prior art are overcome. This achieves efficient and automated PCB layout generation, improves PCB layout design efficiency and optimization performance, and also ensures the feasibility and performance of the PCB layout design scheme under complex physical effects. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A flowchart illustrating a PCB layout generation method provided in an embodiment of this application is shown. Figure 2 A flowchart illustrating a condition vector generation method provided in an embodiment of this application is shown. Figure 3 A flowchart illustrating an initial PCB layout image generation method provided in an embodiment of this application is shown. Figure 4 A flowchart illustrating a verification method provided in an embodiment of this application is shown; Figure 5 This paper shows a schematic diagram of the structure of a PCB layout generation apparatus provided in an embodiment of this application; Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0031] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0032] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0033] Figure 1 A flowchart illustrating a PCB layout generation method provided in an embodiment of this application is shown. (Refer to...) Figure 1 As shown, the method specifically includes the following steps: S101. Obtain layout design parameters.

[0034] Optionally, layout design parameters include a circuit netlist, signal rate information, thermal constraints, plate physical constraints, and manufacturing process constraints. The circuit netlist uses a standard format, such as SPICE or XML, and contains identifiers, package types, pin definitions, and electrical connections between all electronic components. Signal rate information, for example, 28Gbps for a Peripheral Component Interconnect Express (PCIe) channel and 20Gbps for USB4, is used to identify critical high-speed networks and apply corresponding physical constraints during layout. Thermal constraints mainly include the power consumption (in watts) of each component and the maximum allowable temperature rise or junction temperature limit; for example, a Central Processing Unit (CPU) power consumption of 65W and a maximum allowable junction temperature of 95°C. Plate physical constraints include the number of PCB layers, stack-up structure, dielectric material parameters (such as dielectric constant and loss tangent), copper thickness, connector locations, and keep-away areas. Manufacturing process constraints are design manufacturability rules, including minimum line width, minimum line spacing, minimum via diameter, and escape routing capability of ball grid array (BGA) packages.

[0035] S102. Generate a condition vector based on the layout design parameters.

[0036] Optionally, the multi-source heterogeneous design parameters, such as circuit netlist, signal rate information, thermal constraints, board-level physical constraints, and manufacturing process constraints, are structurally encoded to obtain corresponding feature vectors. This includes converting the circuit netlist into a graph structure with component pins as nodes and electrical connections as edges, extracting graph embedding vectors through a graph neural network, normalizing the signal rate into a frequency feature vector within the [0,1] interval, classifying thermal sensitivity levels based on component power consumption and constructing thermal constraint feature vectors, parsing the layer attributes of the stack-up structure to generate stack-up structure embedding vectors, and mapping the design manufacturability rules into a high-resolution feasibility mask and extracting manufacturing process feature vectors through a lightweight convolutional network. Based on this, the above feature vectors are concatenated into a high-dimensional concatenated vector in a preset order, and the concatenated vector is input into a projective multilayer perceptron containing multiple fully connected layers and nonlinear activation functions. The concatenated vector is mapped into a fixed-dimensional unified condition vector. This condition vector serves as a compact representation integrating multi-dimensional constraints such as topology, electrical, thermal, structural, and process constraints, and is used to guide the diffusion model to generate compliant and high-performance PCB layout schemes.

[0037] S103. Input the conditional vector into the pre-trained diffusion model. The diffusion model performs multiple rounds of reverse denoising based on the initialized noise image and the conditional vector to obtain the initial PCB layout image.

[0038] Optionally, starting with an initialized pure Gaussian noise image, the noise image and conditional vector are input into a pre-trained diffusion model. The diffusion model's backbone network, combined with a cross-attention mechanism, predicts and subtracts noise components from the current image to be denoised in each iteration, thereby gradually removing random noise. As the number of iterations decreases, a PCB layout structure conforming to the design intent gradually emerges from the noise image, including details such as component positions and trace paths. After a preset number of iterations, such as 1000, the final output is an initial PCB layout image containing dual-channel semantic information.

[0039] S104. Verify the initial PCB layout image, obtain the verification result, and generate the target PCB layout image based on the verification result.

[0040] Optionally, the initial PCB layout image is parsed into a physical model recognizable by simulation tools, and electromagnetic and thermal simulations are performed on this physical model to obtain key performance indicators such as signal integrity, radiation intensity, and temperature distribution. Then, a comprehensive score is calculated based on a preset weighted scoring function, and the comprehensive score is compared with a preset threshold to determine whether the verification passes. If the verification passes, the initial PCB layout image is directly adopted as the final target PCB layout image; otherwise, the diffusion model is adjusted using simulation results, and the layout design is iteratively optimized until the target is met or the maximum number of iterations is reached. During this process, the layout with the highest comprehensive score can also be selected as the target PCB layout image to ensure that even under strict design requirements, a PCB layout solution that meets performance standards as much as possible can be provided.

[0041] Based on this, the PCB layout generation method according to the embodiments of this application obtains layout design parameters and generates corresponding condition vectors. It then uses a pre-trained diffusion model to perform multi-round reverse denoising on the initialized noisy image, thereby intelligently generating an initial PCB layout image that meets design requirements. Finally, the target PCB layout image is obtained through verification and optimization of this initial image. This overcomes the problems of time-consuming and labor-intensive manual layout and routing, reliance on experience, and the lack of global dynamic optimization capabilities in rule-based automated tools in existing technologies. It achieves efficient and automated PCB layout generation, improves PCB layout design efficiency and optimization performance, and also ensures the feasibility and performance of the PCB layout design scheme under complex physical effects.

[0042] Figure 2 A flowchart illustrating a condition vector generation method provided in an embodiment of this application is shown. (Refer to...) Figure 2 As shown, step S102 above generates a condition vector based on the layout design parameters, specifically including the following steps: S201. The layout design parameters are structured and encoded to obtain multiple feature vectors.

[0043] Optionally, the process of structured encoding of the circuit netlist includes: converting the circuit netlist into a graph structure and encoding the graph structure to obtain a graph embedding vector. The graph structure includes multiple nodes and edges, where nodes represent component pins and edges represent electrical connections between component pins.

[0044] For example, to enable the diffusion model to understand the circuit topology, the circuit netlist is further transformed into a graph structure, with each component pin as a graph node and the electrical connections between component pins as edges, forming an undirected graph. The node characteristics of the graph nodes include device type, package size, number of pins, and functional category (e.g., driver, receiver). Based on this, a graph embedding vector can be obtained by structured encoding the graph structure. This embedding vector, for example, is [1,0,0, 15.0, 15.0, 1024, 1], which represents a device type of processor and a package size of... mm, with 1024 pins, and its function is master control.

[0045] Optionally, the process of structured encoding of signal rate information includes: normalizing the signal rate information to obtain a frequency feature vector.

[0046] For example, to facilitate diffusion model processing, signal rate information can be quantized and mapped to frequency band labels, including "low frequency" (<1Gbps), "medium frequency" (1-10Gbps), "high frequency" (10-56Gbps), and "ultra-high frequency" (>56Gbps). Among them, high frequency and ultra-high frequency are given higher priority weights in the diffusion model to ensure that they receive key attention during the layout phase, such as prioritizing the allocation of independent reference planes and avoiding long-distance parallel traces.

[0047] Specifically, all signal rates are classified according to the frequency band labels defined above. Then, for each signal network, a scalar value reflecting its relative importance is calculated based on the frequency band to which its signal rate belongs. This scalar value is then normalized so that the final result falls within the [0,1] interval, thereby obtaining a frequency feature vector. This normalized frequency feature vector can effectively quantify the priority of different signal networks, ensuring that high-frequency and ultra-high-frequency networks receive higher attention and optimization measures during the layout design process.

[0048] Optionally, the process of structurally encoding the thermal constraint conditions includes: encoding the power consumption values ​​of each component to obtain a thermal constraint feature vector.

[0049] For example, based on the power consumption of each component, the components are divided into three thermal sensitivity levels: high, medium, and low. Specifically, if the power consumption of a component is greater than 50W, it is marked as a high heat source node; if the power consumption of a component is between 10W and 50W, it is marked as a medium heat source node; and if the power consumption of a component is less than 10W or it is a temperature-sensitive device, it is marked as a low heat source node. Further, according to the above classification rules, a corresponding thermal sensitivity value is assigned to each component in the circuit, and a thermal constraint feature vector with a length equal to the total number of components is constructed. The value of each element in this thermal constraint feature vector is, for example, 1.0, 0.5, or 0.1, corresponding to the high, medium, and low thermal sensitivity levels, respectively. This thermal constraint feature vector serves as the core numerical representation of thermal constraints and is used for subsequent multimodal fusion and layout guidance.

[0050] Optionally, a two-dimensional thermal weight matrix can be constructed based on thermal constraints. This two-dimensional thermal weight matrix is ​​aligned with the PCB layout space and is used to characterize the thermal sensitivity of different regions. During the training and inference of the diffusion model, thermal repulsion forces are applied between high-power components to prevent them from being too concentrated in space, thereby avoiding the formation of localized heat islands. In addition, in this embodiment, a thermal channel mask map with the same resolution as the layout image can be generated based on PCB mechanical structure and heat dissipation design information, such as fan positions and thermal pad areas. This identifies areas where high-power devices can be placed or where heat dissipation space needs to be reserved, further enhancing the spatial representation capability of thermal constraints.

[0051] Optionally, the process of structurally encoding the physical constraints of the electrode plates includes: encoding the stacked structure in the physical constraints of the electrode plates according to the layer attributes to obtain the stacked structure embedding vector.

[0052] For example, the PCB stack-up structure is analyzed, and key attributes of each layer are extracted sequentially, including layer type (e.g., signal layer, power layer, or ground layer), dielectric material (e.g., Flame Retardant 4 (FR-4), Rogers material), copper thickness, dielectric constant, and the layer's position in the stack, forming a structured sequence. Then, categorical fields in this structured sequence, such as layer type, material, and position, are converted into corresponding embedding vectors using a predefined lookup table, while numerical fields, such as thickness and dielectric constant, are directly normalized and treated as continuous features. Based on this, the embeddings of each field are concatenated and input into a small multilayer perceptron or through a learnable linear projection to generate a fixed-dimensional stack-up structure embedding vector. This embedding vector uniformly represents the electrical and physical characteristics of the entire PCB stack-up structure and is injected as conditional information into the subsequent diffusion model to ensure that the PCB layout generation scheme conforms to actual inter-layer routing rules and signal integrity requirements.

[0053] Optionally, the process of encoding manufacturing process constraints to obtain manufacturing process feature vectors includes: For example, based on design manufacturability rules, key process parameters are extracted, including minimum line width, minimum line spacing, minimum via diameter, pin spacing of BGA packages, and escape routing capabilities. These global or regional process constraints are then mapped onto a high-resolution two-dimensional grid map aligned with the PCB layout space, generating one or more feasibility mask layers. For instance, allowed escape channels are marked in dense BGA areas, and line width / spacing constraint areas are marked on specific layers. The mask layers are then downsampled or their spatial distribution features are extracted and compressed using a lightweight convolutional neural network to obtain a fixed-dimensional manufacturing process feature vector. This manufacturing process feature vector effectively characterizes the manufacturing feasibility boundaries of different regions and serves as a conditional input in multimodal fusion, ensuring that the routing and component layout generated by the subsequent diffusion model meet actual production requirements in terms of geometry and process.

[0054] S202. Generate a condition vector based on multiple feature vectors.

[0055] Optionally, the graph embedding vector, frequency feature vector, thermal constraint feature vector, stacked structure embedding vector, and manufacturing process feature vector are concatenated in a preset order to obtain a concatenated vector. The concatenated vector is then mapped to generate a condition vector.

[0056] For example, structured features from different design dimensions, including graph embedding vectors extracted by a netlist graph neural network, are incorporated. Normalized signal rate frequency eigenvector Thermally constrained feature vectors constructed based on power consumption levels Embedded vectors of layered structures that encode layered structures and material properties and manufacturing process feature vectors According to the preset order, such as [ , , , , The feature vector is concatenated along its feature dimension to form a high-dimensional concatenated vector. This concatenated vector is then input into a projective multilayer perceptron consisting of two or more fully connected layers. This multilayer perceptron contains nonlinear activation functions that compress and transform the concatenated vector into a fixed-dimensional, such as a 128-dimensional unified conditional vector, through nonlinear mapping. The condition vector As a compact representation of the global design intent, it is subsequently injected into the diffusion model through a cross-attention mechanism to achieve multi-constraint collaborative guidance of the layout generation process.

[0057] In addition, in this embodiment, the PCB layout strategy can be dynamically adjusted by combining the heat dissipation structure, such as the position information of the heat sink and fan, to ensure that sufficient air circulation space is reserved around the high-power devices.

[0058] Based on this, this application comprehensively considers multi-dimensional design parameters such as circuit netlist, signal rate information, thermal constraints, stack-up structure, and manufacturing process constraints, and transforms them into a unified condition vector, achieving comprehensive modeling and accurate expression of complex layout design problems. This not only enables the diffusion model to understand and handle the circuit's topology and electrical characteristics, but also fully considers the priority of different frequency signal networks, the heat dissipation requirements of components, and the actual limitations in the PCB manufacturing process. Therefore, this application can effectively improve the rationality and efficiency of layout design, ensure that high-frequency and high-power components are properly handled, avoid potential heat island effects, and guarantee signal integrity, ultimately generating a high-performance, highly manufacturable PCB layout solution.

[0059] Figure 3 A flowchart illustrating an initial PCB layout image generation method provided in an embodiment of this application is shown. (Refer to...) Figure 3 As shown, step S103 above involves multiple rounds of reverse denoising processing using a diffusion model based on the initialized noise image and conditional vectors to obtain the initial PCB layout image. Specifically, it includes the following steps: S301. Use the initialized noisy image as the initial image to be denoised.

[0060] For example, in the initial state, a pure Gaussian noise image with a size of 256×256 is generated. The noisy image Each pixel value in the image is independently sampled from a standard normal distribution and contains no structural information; it serves only as the starting point for the inverse generation process of the diffusion model. Furthermore, this noisy image... The first round, which is set to a preset number of rounds, such as 1000, is the initial image to be denoised, corresponding to the first time step, and is used for subsequent iterations of denoising.

[0061] S302. Based on the time step corresponding to the current round, the current image to be denoised, and the conditional vector, the noise component in the current image to be denoised is predicted.

[0062] For example, the noise component is used to represent how much noise should be removed from the current image to be denoised. In each denoising iteration, the current time step is... The image to be denoised and pre-generated condition vectors The inputs are fed into the U-Net backbone network of the diffusion model. The U-Net backbone network extracts image features through its encoder-decoder structure and uses a cross-attention mechanism to integrate the conditional vectors. The circuit topology, high-speed signals, thermal constraints, and other multi-dimensional design intentions are dynamically injected into the feature maps at each level, and the final output is a denoised image of the current object. Estimation of the noise components contained therein .

[0063] S303. Denoise the current image to be denoised based on the noise components in the current image to be denoised, and obtain the denoised image.

[0064] For example, based on a preset noise scheduling strategy, combined with predicted noise components... Current time step The scheduling parameters and potential random perturbations are used to denoise the current image to be denoised, and a clearer denoised image is calculated for the next time step. In other words, from the current image to be denoised... Subtract the noise component predicted by the model. And scale it up proportionally to restore an intermediate result that is closer to the real layout.

[0065] S304. Use the denoised image as the new current image to be denoised.

[0066] For example, after a denoising operation is completed, the resulting denoised image is updated as the input for the next iteration, i.e., the new current image to be denoised. At the same time, the time step decreases synchronously, preparing to enter the next round of more refined denoising stage, ensuring that the PCB layout generation process gradually converges from coarse to fine.

[0067] S305. Repeat steps S302-S304 until the preset number of rounds is reached, and output the initial PCB layout image.

[0068] For example, the time step is decreased round by round, and a total of 1000 iterations are performed. As the time step gradually approaches 0, noise in the image is continuously suppressed, and the layout structure, such as component positions and wiring paths, is optimized in the conditional vector. Under the guidance of [the system], the results gradually emerge. After 1000 iterations, the output denoised image becomes the initial PCB layout image. This initial PCB layout image contains dual-channel semantic information: one channel represents the component placement probability, and the other channel represents the routing possibility, which together constitute a complete initial PCB layout scheme.

[0069] Based on this, this application employs a diffusion model and conditional vectors for multi-round reverse denoising, effectively transforming high-dimensional, unstructured pure noise images into high-quality initial PCB layout images that conform to complex engineering constraints. Furthermore, each round of denoising incorporates multi-dimensional prior knowledge encoded by conditional vectors, including circuit topology, high-speed signal priority, thermal management requirements, layer stack-up structure, and manufacturing processes. A cross-attention mechanism dynamically guides the layout generation direction, automatically achieving length matching of critical signals, spatial isolation of high-power devices, reasonable reservation of routing channels, and implicit compliance with rules without manual intervention. Compared to traditional rule-driven or heuristic layout methods, this application significantly improves the physical compliance and electrical performance of the layout while drastically shortening the design cycle.

[0070] As one possible implementation, the training process of the diffusion model includes: acquiring training samples, which include multiple PCB layout image samples; inputting the PCB layout image samples into the initial diffusion model; performing multiple rounds of noise addition processing on the PCB layout images by the initial diffusion model; predicting the added noise component in the noisy image sample for each round; determining the standard denoising loss based on the predicted noise component and the actual noise component of the noisy image sample; and optimizing the initial diffusion model based on the standard denoising loss and the preset loss function to train the diffusion model.

[0071] Optionally, a large number of real PCB layout images are acquired as training samples. Each image contains component locations and routing information, and is paired with its corresponding layout design parameters to generate a conditional vector. During model training, a forward diffusion process is performed on each real layout image. That is, within a preset total number of steps, Gaussian noise is gradually added according to a noise scheduling strategy, such as a linear or cosine-increasing sequence, to obtain a series of noisy images. In each training iteration, a time step is randomly sampled, and the corresponding noisy image, time step embedding, and conditional vector are input into the initial diffusion model, which predicts the added noise components.

[0072] Furthermore, the mean square error between the predicted noise and the actual added noise is calculated as the standard denoising loss. At the same time, based on the denoising intermediate results output by the model, the surrogate loss term for physical perception is further calculated, including crosstalk level, temperature rise and radiation intensity, and combined according to weights to obtain the preset loss function shown in the following expression (1). On this basis, the loss function is minimized through backpropagation to optimize the model network parameters, and finally a conditional diffusion model that can generate physically compliant, multi-constraint collaborative optimization PCB layout schemes is trained.

[0073] The preset loss function is shown in the following expression (1): (1) in, Indicates the preset loss function. Indicates the standard denoising loss. This represents the crosstalk level estimated based on the surrogate model. This represents the temperature rise estimated based on the thermal resistance network model. This represents the radiation intensity estimated based on the area of ​​the current loop. , , These represent the weights.

[0074] Based on this, training the diffusion model using the above method enables it to learn the distribution of real PCB layout data while deeply integrating multi-dimensional engineering constraints such as circuit topology, high-speed signal integrity, thermal management, layer stack-up structure, and manufacturing process. This allows the model to directly output a highly compliant and high-performance initial layout scheme during the generation stage. Compared to traditional generation models that rely solely on standard denoising losses, this training method significantly improves the usability and pass rate of the generated layout, providing an intelligent generation engine for high-speed, high-density PCB design that combines automation efficiency with physical rationality.

[0075] Figure 4 A flowchart illustrating a verification method provided in an embodiment of this application is shown. (Refer to...) Figure 4 As shown, step S104 verifies the initial PCB layout image and obtains the verification result, specifically including the following steps: S401. Input the initial PCB layout image into the preset simulation engine to perform electromagnetic simulation and thermal simulation respectively, and obtain the electromagnetic simulation results and thermal simulation results.

[0076] Optionally, the generated initial PCB layout image is parsed into a physical model that can be recognized by simulation tools, including component locations, trace geometry, stack-up structure, and material parameters. This physical model is then imported into an electromagnetic simulation unit such as ANSYS HFSS or Keysight ADS, and the port excitation and frequency scan range are set, for example, 0–40 GHz. A full-wave three-dimensional electromagnetic field simulation is performed, extracting the S-parameters of key signal networks and further calculating signal integrity indices such as insertion loss, return loss, crosstalk, and near-field radiation peak. Simultaneously, the physical model is imported into a thermal simulation unit such as ANSYS Icepak or FloTHERM, configuring material thermal conductivity, convection boundary conditions, and the power consumption of each component as heat sources. Steady-state or transient thermal analysis is then performed to obtain the overall board temperature distribution, hotspot locations, and maximum temperature rise.

[0077] S402. Weight the electromagnetic simulation results and thermal simulation results to obtain a comprehensive score.

[0078] Optionally, after obtaining the electromagnetic and thermal simulation results, the various physical performance parameters are normalized and quantified according to a predefined weighted scoring function. Specifically, the measured signal integrity index, radiation intensity, and maximum temperature rise are each compared to their corresponding design target thresholds to form dimensionless performance ratios. These ratios are then weighted and scored using priority-based weighting coefficients to obtain a comprehensive score.

[0079] For example, the weighted scoring function is shown in the following expression (2): (2) in, This indicates the overall score. This represents the performance index value obtained from actual simulation of signal integrity. The design target value for signal integrity (the maximum allowable value or the expected value). This represents the radiation intensity value obtained from the actual simulation. This indicates the preset upper limit threshold for radiation intensity. This represents the actual temperature rise value obtained from the thermal simulation. Indicates the maximum allowable temperature rise in thermal design. , , These represent the weighting coefficients.

[0080] S403. Compare the overall score with the preset threshold. If the overall score is greater than or equal to the preset threshold, the verification is deemed successful. If the overall score is less than the preset threshold, the verification is deemed unsuccessful.

[0081] Optionally, the calculated comprehensive score is compared with a pre-set threshold, such as 1.0. If the comprehensive score is lower than the threshold value, the score is lowered. If the score is greater than or equal to the preset threshold of 1.0, it indicates that the layout scheme meets the design specifications in terms of signal integrity, radiation intensity, and thermal performance. Therefore, it is considered verified and the initial PCB layout image can be directly output as the final PCB layout scheme. However, if the overall score is... If the value is less than the preset threshold of 1.0, it indicates that at least one key indicator has exceeded the standard, and the verification is deemed unsuccessful. The feedback learning mechanism needs to be triggered, which involves combining the simulation results with the constructed loss function to fine-tune the diffusion model and returning to the generation stage for iterative optimization until the standard is met or the maximum number of iterations is reached.

[0082] Furthermore, the above steps generate a target PCB layout image based on the verification results, including: if the verification passes, the initial PCB layout image is used as the target PCB layout image; if the verification fails, the diffusion model is adjusted based on the electromagnetic simulation results, thermal simulation results, and a preset loss function to obtain an adjusted diffusion model; the condition vector is input into the adjusted diffusion model, and the adjusted diffusion model generates a new PCB layout image based on the condition vector, and the new PCB layout image is verified.

[0083] Optionally, if the verification result is passed, the initial PCB layout image is directly output as the final target PCB layout image. If the verification fails, a feedback optimization loop is entered. Specifically, the diffusion model is fine-tuned based on electromagnetic simulation results, thermal simulation results, and the constructed loss function. For example, an efficient parameter update strategy such as low-rank adaptation is preferred, adjusting only the low-rank increment matrix of the attention layer in the diffusion model to maintain training stability and reduce computational overhead. After the model adjustment is completed, the original conditional vector is re-input into the adjusted diffusion model, a complete reverse denoising process is performed, and a new PCB layout image is generated. This new PCB layout image is then sent to the physical simulation engine for a new round of electromagnetic and thermal verification.

[0084] Optionally, if the new PCB layout image fails verification, the process of generating a PCB layout image and verifying the generated PCB image is repeated iteratively. If the generated PCB layout image still fails verification after reaching the maximum number of iterations, the PCB layout image with the highest comprehensive score among all the PCB layout images generated during the iteration process is taken as the target PCB layout image.

[0085] For example, during the generation of the PCB layout image, if the newly generated PCB layout image fails the verification check, an iterative optimization process will be performed. This includes updating the model parameters based on simulation feedback from each iteration, repeatedly adjusting the diffusion model, regenerating the PCB layout image based on the adjusted model, and rigorously verifying the physical performance of the new layout. If, after a predetermined maximum number of iterations, such as three, a PCB layout image that meets all design specifications is still not obtained, the layout image with the highest comprehensive score from all iterations will be selected as the final target PCB layout image output. In this way, even under the most stringent engineering requirements, a feasible solution that meets the design goals and performance standards as much as possible can be provided, while maximizing the use of the design results accumulated throughout the iterative process.

[0086] Based on this, this application significantly improves the quality and reliability of the layout design through repeated simulation and optimization processes. Even when faced with complex and stringent design requirements, this application can ensure that the layout scheme closest to the ideal performance index is found within the maximum number of iterations. In addition, even if all preset conditions cannot be fully met within the limited number of iterations, selecting the layout with the highest comprehensive score as the final solution ensures the practicality of the generated PCB layout, greatly reducing generation risks and subsequent modification costs.

[0087] Based on the same inventive concept, this application also provides a PCB layout generation device corresponding to the PCB layout generation method. Since the principle of the PCB layout generation device in this application is similar to that of the PCB layout generation method described above, the implementation of the PCB layout generation device can refer to the implementation of the PCB layout generation method, and the repeated parts will not be described again.

[0088] Reference Figure 5 The diagram shown is a structural schematic of a PCB layout generation device provided in an embodiment of this application. The PCB layout generation device 500 includes: an acquisition module 501, a generation module 502, a noise reduction module 503, and a verification module 504, wherein: Module 501 is used to obtain layout design parameters; The generation module 502 is used to generate condition vectors based on layout design parameters; The denoising module 503 is used to input the conditional vector into the pre-trained diffusion model, and the diffusion model performs multiple rounds of reverse denoising based on the initialized noise image and the conditional vector to obtain the initial PCB layout image. The verification module 504 is used to verify the initial PCB layout image, obtain the verification result, and generate the target PCB layout image based on the verification result.

[0089] Based on this, the PCB layout generation apparatus according to the embodiments of this application acquires layout design parameters and generates corresponding condition vectors. It then uses a pre-trained diffusion model to perform multi-round reverse denoising on the initialized noisy image, thereby intelligently generating an initial PCB layout image that meets design requirements. Finally, the target PCB layout image is obtained through verification and optimization of this initial image. This overcomes the problems of time-consuming and labor-intensive manual layout and routing, reliance on experience, and the lack of global dynamic optimization capabilities in rule-based automated tools in the prior art. It achieves efficient and automated PCB layout generation, improves PCB layout design efficiency and optimization performance, and also ensures the feasibility and performance of the PCB layout design scheme under complex physical effects.

[0090] In one possible implementation, the layout design parameters include a circuit netlist, signal rate information, thermal constraints, plate physical constraints, and manufacturing process constraints; the aforementioned generation module 502 is specifically used for: The layout design parameters are structured and encoded to obtain multiple feature vectors; Generate a condition vector based on multiple feature vectors.

[0091] In one possible implementation, the generation module 502 is specifically used for: The circuit netlist is converted into a graph structure and the graph structure is encoded to obtain a graph embedding vector. The graph structure includes multiple nodes and edges. Nodes are used to represent component pins and edges are used to represent electrical connections between component pins. The signal rate information is normalized to obtain the frequency feature vector; The power consumption values ​​of each component are encoded to obtain a thermal constraint feature vector; The stacked structure in the physical constraints of the electrode plates is encoded according to the layer attributes to obtain the stacked structure embedding vector; The manufacturing process constraints are encoded to obtain the manufacturing process feature vector.

[0092] In one possible implementation, the generation module 502 is specifically used for: The graph embedding vector, frequency feature vector, thermal constraint feature vector, stacked structure embedding vector, and manufacturing process feature vector are concatenated in a preset order to obtain the concatenated vector. The concatenated vectors are mapped to generate conditional vectors.

[0093] In one possible implementation, the noise reduction module 503 is specifically used for: Step A: Use the initialized noisy image as the initial image to be denoised; Step B: Based on the time step corresponding to the current round, the current image to be denoised, and the conditional vector, predict the noise components in the current image to be denoised; Step C: Denoise the current image based on the noise components in the current image to be denoised, and obtain the denoised image; Step D: Use the denoised image as the new current image to be denoised; Step E: Repeat steps B through D until the preset number of rounds is reached, and output the initial PCB layout image.

[0094] In one possible implementation, the noise reduction module 503 is further configured to: Obtain training samples, which include multiple PCB layout image samples; PCB layout image samples are input into the initial diffusion model, which performs multiple rounds of noise addition processing on the PCB layout images. For each round of generated noisy image samples, the predicted noise component added to the noisy image samples is predicted. The standard denoising loss is determined based on the predicted noise component and the actual noise component of the noisy image samples. The initial diffusion model is then optimized based on the standard denoising loss and a preset loss function to train the diffusion model. The preset loss function is shown in the following expression:

[0095] in, Indicates the preset loss function. Indicates the standard denoising loss. This represents the crosstalk level estimated based on the surrogate model. This represents the temperature rise estimated based on the thermal resistance network model. This represents the radiation intensity estimated based on the area of ​​the current loop. , , These represent the weights.

[0096] In one possible implementation, the verification module 504 is specifically used for: The initial PCB layout image is input into the preset simulation engine to perform electromagnetic simulation and thermal simulation respectively, and the electromagnetic simulation results and thermal simulation results are obtained. The electromagnetic simulation results and thermal simulation results are weighted and scored to obtain a comprehensive score. The overall score is compared with a preset threshold. If the overall score is greater than or equal to the preset threshold, the verification is considered successful. If the overall score is less than the preset threshold, the verification is considered unsuccessful.

[0097] In one possible implementation, the verification module 504 is specifically used for: If the verification passes, the initial PCB layout image will be used as the target PCB layout image. If the verification fails, the diffusion model is adjusted based on the electromagnetic simulation results, thermal simulation results, and preset loss function to obtain the adjusted diffusion model. The condition vector is then input into the adjusted diffusion model, which generates a new PCB layout image based on the condition vector. The new PCB layout image is then verified.

[0098] In one possible implementation, the verification module 504 is further configured to: If the new PCB layout image fails verification, the process of generating and verifying the generated PCB layout image continues iteratively. If the generated PCB layout image still fails verification after reaching the maximum number of iterations, the PCB layout image with the highest comprehensive score among all the PCB layout images generated during the iteration process is taken as the target PCB layout image.

[0099] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0100] This application also provides an electronic device 600, such as... Figure 6 The diagram shown is a structural schematic of an electronic device 600 provided in an embodiment of this application, including: a processor 601, a memory 602, and optionally, a bus 603. The memory 602 stores machine-readable instructions executable by the processor 601. When the electronic device 600 is running, the processor 601 and the memory 602 communicate via the bus 603. When the machine-readable instructions are executed by the processor 601, the steps of the PCB layout generation method described in any of the preceding claims are performed.

[0101] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the PCB layout generation method as described in any of the preceding claims.

[0102] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0103] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0104] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A PCB layout generation method, characterized in that, include: Obtain layout design parameters; Generate a condition vector based on the layout design parameters; The conditional vector is input into the pre-trained diffusion model, which performs multiple rounds of reverse denoising based on the initialized noisy image and the conditional vector to obtain the initial PCB layout image. The initial PCB layout image is verified to obtain the verification result, and the target PCB layout image is generated based on the verification result.

2. The method according to claim 1, characterized in that, The layout design parameters include circuit netlist, signal rate information, thermal constraints, plate physical constraints, and manufacturing process constraints. The step of generating a condition vector based on the layout design parameters includes: The layout design parameters are structured and encoded to obtain multiple feature vectors; The condition vector is generated based on the plurality of feature vectors.

3. The method according to claim 2, characterized in that, The layout design parameters are structured and encoded to obtain multiple feature vectors, including: The circuit netlist is converted into a graph structure and the graph structure is encoded to obtain a graph embedding vector. The graph structure includes multiple nodes and edges, where nodes represent component pins and edges represent electrical connections between component pins. The signal rate information is normalized to obtain a frequency feature vector; The power consumption values ​​of each component are encoded to obtain a thermal constraint feature vector; The stacked structure in the physical constraints of the electrode plate is encoded according to the layer attributes to obtain the stacked structure embedding vector; The manufacturing process constraints are encoded to obtain a manufacturing process feature vector.

4. The method according to claim 3, characterized in that, The step of generating the condition vector based on the plurality of feature vectors includes: The graph embedding vector, the frequency feature vector, the thermal constraint feature vector, the stacked structure embedding vector, and the manufacturing process feature vector are concatenated in a preset order to obtain a concatenated vector; The concatenated vector is mapped to generate the conditional vector.

5. The method according to claim 1, characterized in that, The process of obtaining an initial PCB layout image by performing multiple rounds of reverse denoising based on the initial noise image and the conditional vector using the diffusion model includes: Step A: Use the initialized noisy image as the initial image to be denoised; Step B: Based on the time step corresponding to the current round, the current image to be denoised, and the conditional vector, predict the noise components in the current image to be denoised; Step C: Denoise the current image to be denoised based on the noise components in the current image to be denoised, and obtain a denoised image; Step D: Use the denoised image as the new current image to be denoised; Step E: Repeat steps B-D until a preset number of rounds are reached, and output the initial PCB layout image.

6. The method according to claim 1, characterized in that, The training process of the diffusion model includes: Obtain training samples, which include multiple PCB layout image samples; The PCB layout image sample is input into an initial diffusion model, which performs multiple rounds of noise addition processing on the PCB layout image. For each round of generated noisy image sample, the predicted noise component added to the noisy image sample is predicted. A standard denoising loss is determined based on the predicted noise component and the actual noise component of the noisy image sample. The initial diffusion model is then optimized based on the standard denoising loss and a preset loss function to train the diffusion model. The preset loss function is shown in the following expression: in, Indicates the preset loss function. Indicates the standard denoising loss. This represents the crosstalk level estimated based on the surrogate model. This represents the temperature rise estimated based on the thermal resistance network model. This represents the radiation intensity estimated based on the area of ​​the current loop. , , These represent the weights.

7. The method according to claim 1, characterized in that, The verification of the initial PCB layout image to obtain the verification result includes: The initial PCB layout image is input into a preset simulation engine to perform electromagnetic simulation and thermal simulation respectively, and the electromagnetic simulation results and thermal simulation results are obtained. The electromagnetic simulation results and the thermal simulation results are weighted and scored to obtain a comprehensive score; The comprehensive score is compared with a preset threshold. If the comprehensive score is greater than or equal to the preset threshold, the verification is deemed successful. If the comprehensive score is less than the preset threshold, the verification is deemed unsuccessful.

8. The method according to claim 7, characterized in that, The step of generating the target PCB layout image based on the verification result includes: If the verification passes, the initial PCB layout image will be used as the target PCB layout image. If the verification fails, the diffusion model is adjusted based on the electromagnetic simulation results, the thermal simulation results, and the preset loss function to obtain the adjusted diffusion model. The condition vector is then input into the adjusted diffusion model, which generates a new PCB layout image based on the condition vector. The new PCB layout image is then verified.

9. The method according to claim 8, characterized in that, The method further includes: If the new PCB layout image fails verification, the process of generating and verifying the generated PCB layout image continues iteratively. If the generated PCB layout image still fails verification after reaching the maximum number of iterations, the PCB layout image with the highest comprehensive score among all the PCB layout images generated during the iteration process is taken as the target PCB layout image.

10. An electronic device, characterized in that, include: A processor and a memory, the memory storing machine-readable instructions executable by the processor, which, when the electronic device is running, are executed by the processor to perform the steps of the PCB layout generation method as described in any one of claims 1 to 9.

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