Clock calibration circuit and clock calibration method
By using the clock delay module and the feedback mechanism of the phase offset processing and judgment module of the acquisition circuit, the problem of inaccurate data latching caused by coarse clock calibration is solved, and accurate calibration and stable data latching of the output clock signal are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-04-10
AI Technical Summary
In existing technologies, clock calibration methods result in relatively coarse adjustments, leading to inaccurate data latching.
A clock delay module is used to perform phase offset processing on the input clock signal. The signal is acquired through rising edge acquisition circuit and falling edge acquisition circuit. The phase offset value is determined by the judgment module and fed back to the clock delay module for adjustment to ensure accurate calibration of the output clock signal.
Precise calibration of the output clock signal was achieved, ensuring the accuracy of data latching.
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Figure CN121841322A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of computer, in particular to a clock calibration circuit and a clock calibration method. BACKGROUND
[0002] With the increase of communication frequency of single line protocol, the difficulty of latching data at both ends of communication is gradually increased. When the clock of latching data and the clock of sending data are the same frequency, the difficulty of latching data is greater. In the related art, the clock is calibrated to ensure that the data can be accurately latched. However, in the related art, the adjustment result of the clock calibration method is relatively rough, thereby affecting the accuracy of data latching. SUMMARY
[0003] In view of the above problems, the present application is proposed to provide a clock calibration circuit and a clock calibration method to overcome the above problems or at least partially solve the above problems.
[0004] In a first aspect, the present application provides a clock calibration circuit, comprising: a clock delay module, a rising edge acquisition circuit and a falling edge acquisition circuit connected with the clock delay module respectively, and a judgment module; the judgment module is connected with the rising edge acquisition circuit and the falling edge acquisition circuit respectively; The clock delay module is configured to obtain an input clock signal, perform phase offset processing on the input clock signal to obtain an output clock signal, and send the output clock signal and an acquisition signal to the rising edge acquisition circuit and the falling edge acquisition circuit; obtain a write enable and a phase offset signal sent by the judgment module, in response to the write enable, perform phase offset processing on the input clock again according to the phase offset signal to obtain an adjusted output clock signal, and send the adjusted output clock signal to the rising edge acquisition circuit and the falling edge acquisition circuit; The rising edge acquisition circuit is configured to obtain the acquisition signal according to the output clock signal. The falling edge acquisition circuit is configured to obtain the acquisition signal according to the output clock signal. The judgment module is configured to obtain the acquisition signal corresponding to the rising edge acquisition circuit, obtain the acquisition signal corresponding to the falling edge acquisition circuit, determine a phase offset value according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, and send the write enable and the phase offset signal corresponding to the phase offset value to the clock delay module.
[0005] Optionally, the clock delay module is configured to, after obtaining the input clock signal, perform phase offset processing on the input clock signal according to an initial phase offset value n to obtain an output clock signal; the output clock signal has n clock periods; and each clock period of the output clock signal is phase offset by 1 / n relative to each clock period of the input clock signal.
[0006] Optionally, the judging module is configured to determine a reference acquisition circuit and an adjustment acquisition circuit according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; the reference acquisition circuit is the rising edge acquisition circuit or the falling edge acquisition circuit; the adjustment acquisition circuit is the acquisition circuit that is not determined as the reference acquisition circuit among the rising edge acquisition circuit and the falling edge acquisition circuit; and compare the acquisition signal corresponding to the adjustment acquisition circuit with the acquisition signal corresponding to the reference acquisition circuit to determine a phase offset value.
[0007] Optionally, the judging module is configured to, if one of a first level state of the acquisition signal corresponding to the rising edge acquisition circuit and a first level state of the acquisition signal corresponding to the falling edge acquisition circuit is the same as a preset level state, determine the acquisition circuit with the same preset level state as the reference acquisition circuit.
[0008] Optionally, the judging module is configured to, if the first level state of the acquisition signal corresponding to the rising edge acquisition circuit and the first level state of the acquisition signal corresponding to the falling edge acquisition circuit are both the same as a preset level state, determine a first time at which the level state of the acquisition signal corresponding to the rising edge acquisition circuit first appears in a continuous same level state and a second time at which the level state of the acquisition signal corresponding to the falling edge acquisition circuit first appears in a continuous same level state; and determine the reference acquisition circuit according to the first time and the second time.
[0009] Optionally, the judging module is configured to, if the first time is greater than the second time, determine the rising edge acquisition circuit as the reference acquisition circuit; and if the first time is less than the second time, determine the falling edge acquisition circuit as the reference acquisition circuit.
[0010] Optionally, the judging module is configured to compare the level state of the acquisition signal corresponding to the adjustment acquisition circuit with the level state of the acquisition signal corresponding to the reference acquisition circuit; if there is a first level state that first appears in a continuous two-level state difference, determine a phase offset value according to the different level states.
[0011] Optionally, the judging module is configured to determine a serial number of the first level state in the different level states, and take the serial number as a phase offset value.
[0012] In a second aspect, an embodiment of the present application provides a clock calibration method, which is applied to a judging module of a clock calibration circuit as described in the first aspect above, and the method comprises: acquiring a collection signal corresponding to the rising edge collection circuit and a collection signal corresponding to the falling edge collection circuit; the rising edge collection circuit and the falling edge collection circuit acquire the collection signals according to an output clock signal respectively; the output clock signal is acquired from an input clock signal by the clock delay module; the input clock signal is subjected to phase shift processing to obtain the output clock signal; the collection signals are sent to the rising edge collection circuit and the falling edge collection circuit by the clock delay module; determining a phase shift value according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit; sending a phase shift signal corresponding to the write enable and the phase shift value to the clock delay module, so that the clock delay module responds to the write enable, subjects the input clock to phase shift processing again according to the phase shift signal, obtains an adjusted output clock signal, and sends the adjusted output clock signal to the rising edge collection circuit and the falling edge collection circuit.
[0013] Optionally, the output clock signal is obtained by subjecting the input clock signal to phase shift processing according to an initial phase shift value n; the output clock signal has a signal period number of n, and each clock period of the output clock signal is phase shifted by 1 / n with respect to each clock period of the input clock signal.
[0014] Optionally, the determination of the phase shift value according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit comprises: determining a reference collection circuit and an adjustment collection circuit according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit; the reference collection circuit is the rising edge collection circuit or the falling edge collection circuit; the adjustment collection circuit is the collection circuit which is not determined as the reference collection circuit among the rising edge collection circuit and the falling edge collection circuit; comparing the collection signal corresponding to the adjustment collection circuit with the collection signal corresponding to the reference collection circuit to determine the phase shift value.
[0015] Optionally, the determination of the reference collection circuit and the adjustment collection circuit according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit comprises: If one of the first level state of the acquisition signal corresponding to the rising edge acquisition circuit and the first level state of the acquisition signal corresponding to the falling edge acquisition circuit is the same as the preset level state, the acquisition circuit with the same preset level state is determined as the reference acquisition circuit, and the acquisition circuit not determined as the reference acquisition circuit is determined as the adjustment acquisition circuit.
[0016] Optionally, the determining the reference acquisition circuit and the adjustment acquisition circuit according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit comprises: If the first level state of the acquisition signal corresponding to the rising edge acquisition circuit and the first level state of the acquisition signal corresponding to the falling edge acquisition circuit are the same as the preset level state, the first time at which the level state of the acquisition signal corresponding to the rising edge acquisition circuit first appears continuous same level state and the second time at which the level state of the acquisition signal corresponding to the falling edge acquisition circuit first appears continuous same level state are determined. The reference acquisition circuit is determined according to the first time and the second time, and the acquisition circuit not determined as the reference acquisition circuit is determined as the adjustment acquisition circuit.
[0017] Optionally, the determining the reference acquisition circuit according to the first time and the second time comprises: If the first time is greater than the second time, the rising edge acquisition circuit is determined as the reference acquisition circuit. If the first time is less than the second time, the falling edge acquisition circuit is determined as the reference acquisition circuit.
[0018] Optionally, the determining the phase offset value by comparing the acquisition signal corresponding to the adjustment acquisition circuit with the acquisition signal corresponding to the reference acquisition circuit comprises: The level state of the acquisition signal corresponding to the adjustment acquisition circuit is compared with the level state of the acquisition signal corresponding to the reference acquisition circuit, and if there is first continuous two level states different from each other, the phase offset value is determined according to the different level states.
[0019] Optionally, the determining the phase offset value according to the different level states comprises: The serial number of the first level state in the different level states is determined, and the serial number is taken as the phase offset value.
[0020] The embodiments of the present application have the following advantages: In this embodiment of the invention, a clock delay module is used to acquire an input clock signal; perform phase offset processing on the input clock signal to obtain an output clock signal, and send the output clock signal and the acquisition signal to the rising edge acquisition circuit and the falling edge acquisition circuit; acquire the write enable and phase offset signals sent by the judgment module, respond to the write enable sent by the judgment module, perform phase offset processing on the input clock again according to the phase offset signal to obtain an adjusted output clock signal, and send the adjusted output clock signal to the rising edge acquisition circuit and the falling edge acquisition circuit; the rising edge acquisition circuit is used to acquire the acquisition signal according to the output clock signal; the falling edge acquisition circuit is used to acquire the acquisition signal according to the output clock signal; the judgment module is used to acquire the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; determine the phase offset value according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; and send the write enable and the phase offset signal corresponding to the phase offset value to the clock delay module. Thus, based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, the optimal phase offset value configuration is determined, thereby making the calibration result of the output clock signal more accurate and ensuring accurate data latching. Attached Figure Description
[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a structural block diagram of a clock calibration circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a clock phase offset provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a signal acquisition method provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another clock phase offset provided in an embodiment of the present invention; Figure 5 This is a flowchart of the steps of a clock calibration method provided in an embodiment of the present invention. Detailed Implementation
[0023] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the protection scope of the present application.
[0024] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in a "or" relationship.
[0025] In the related art, the adjustment result of the clock calibration method is relatively rough, which further affects the inaccurate data latching. In order to solve the technical problem, the embodiments of the present application disclose a clock calibration circuit, the core idea of which is that the clock delay module is used to obtain an input clock signal; the input clock signal is subjected to phase shift processing to obtain an output clock signal, and the output clock signal and a collection signal are sent to a rising edge collection circuit and a falling edge collection circuit; a write enable and a phase shift signal sent by a judgment module are obtained, the write enable sent by the judgment module is responded, the input clock is subjected to phase shift processing again according to the phase shift signal to obtain an adjusted output clock signal, and the adjusted output clock signal is sent to the rising edge collection circuit and the falling edge collection circuit; the rising edge collection circuit is used to obtain the collection signal according to the output clock signal; the falling edge collection circuit is used to obtain the collection signal according to the output clock signal; the judgment module is used to obtain the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit; the phase shift value is determined according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit; the phase shift signal corresponding to the phase shift value of the write enable is sent to the clock delay module. Thus, the configuration of the best phase shift value is determined according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit, and the calibration result of the output clock signal is more accurate, which ensures accurate data latching.
[0026] As shown in Figure 1 The structure block diagram of the clock calibration circuit provided by the embodiments of the present application is shown, which specifically includes: The clock calibration circuit includes: a clock delay module, a rising edge collection circuit, a falling edge collection circuit and a judgment module connected with the clock delay module respectively; and the judgment module is connected with the rising edge collection circuit and the falling edge collection circuit respectively.
[0027] The clock delay module is used for obtaining an input clock signal, performing phase offset processing on the input clock signal to obtain an output clock signal, and sending the output clock signal and a collection signal to the rising edge collection circuit and the falling edge collection circuit; obtaining a write enable and a phase offset signal sent by the judgment module, responding to the write enable sent by the judgment module, performing phase offset processing on the input clock again according to the phase offset signal to obtain an adjusted output clock signal, and sending the adjusted output clock signal to the rising edge collection circuit and the falling edge collection circuit; The rising edge collection circuit is used for obtaining the collection signal according to the output clock signal. The falling edge collection circuit is used for obtaining the collection signal according to the output clock signal. The judgment module is used for obtaining the collection signal corresponding to the rising edge collection circuit, obtaining the collection signal corresponding to the falling edge collection circuit, determining a phase offset value according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit, and sending a write enable and a phase offset signal corresponding to the phase offset value to the clock delay module.
[0028] In the application, the clock delay module can be connected with the rising edge collection circuit and the falling edge collection circuit, the clock delay module can send the output clock signal to the rising edge collection circuit and the falling edge collection circuit, and the clock delay module is connected with the rising edge collection circuit and the falling edge collection circuit through a bus, the bus adopts single-wire communication, and the single-wire communication can be communication of a high-speed same-frequency sampling single-wire protocol. The clock delay module can send the collection signal to the rising edge collection circuit and the falling edge collection circuit through the bus. The rising edge collection circuit and the falling edge collection circuit are connected with the judgment module respectively, and the judgment module is connected with the clock delay module simultaneously.
[0029] In the present application, the clock delay module can obtain the input clock signal sent by the host, the host being an electronic device in which the clock calibration circuit is deployed. After obtaining the input clock signal, the clock delay module can perform phase shift processing on the input clock signal after identifying the start bit signal, to obtain an output clock signal. Then the output clock signal is sent to the rising edge acquisition circuit and the falling edge acquisition circuit, and the acquisition signal can also be sent to the rising edge acquisition circuit and the falling edge acquisition circuit. After obtaining the output clock signal, the rising edge acquisition circuit and the falling edge acquisition circuit can acquire the acquisition signal according to the output clock signal. After sending the output clock signal, the clock delay module can send a calibration completion signal to the judgment module. After receiving the calibration completion signal, the judgment module can obtain the acquisition signals corresponding to the rising edge acquisition circuit and the falling edge acquisition circuit, and determine the phase shift value according to the acquisition signals corresponding to the rising edge acquisition circuit and the falling edge acquisition circuit, respectively. Then the judgment module sends a write enable and a phase shift signal corresponding to the determined phase shift value to the clock delay module. After receiving the write enable and the phase shift signal, the clock delay module can respond to the write enable, perform phase shift processing on the input clock again according to the phase shift signal, to obtain an adjusted output clock signal, and send the adjusted output clock signal to the rising edge acquisition circuit and the falling edge acquisition circuit. The rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal according to the adjusted output clock signal, and perform data latching according to the acquisition signal.
[0030] In the embodiment of the present application, the clock delay module can be used to obtain the input clock signal, and perform phase shift processing on the input clock signal according to the initial phase shift value n, to obtain the output clock signal. The number of signal periods of the output clock signal is n, and each clock period of the output clock signal is phase shifted by 1 / n with respect to each clock period of the input clock signal.
[0031] In the present application, the clock delay module can obtain the configuration parameter, which can include the initial phase shift value n, as shown in Figure 2 The clock phase shift diagram provided by the embodiment of the present application is shown. The clock delay module obtains the input clock signal, the clock period of the input clock signal is T, and the phase shift processing is performed on the input clock signal according to the initial phase shift value n, to obtain the output clock signal. The number of periods of the output clock signal is n, and each clock period of the output clock signal is (n+1 / n)T, so that each clock period of the output clock signal is superimposed with 1 / n T with respect to each clock period of the input clock signal. Thus, the phase shift processing is performed on the input clock signal according to the initial phase shift value, to obtain the output clock signal, and then the rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal according to the output clock signal, which ensures that the rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal more stably.
[0032] In the embodiment of the present application, the judging module is used to determine the reference collection circuit and the adjustment collection circuit according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit; the reference collection circuit is the rising edge collection circuit or the falling edge collection circuit; the adjustment collection circuit is the collection circuit which is not determined as the reference collection circuit among the rising edge collection circuit and the falling edge collection circuit; and the phase shift value is determined by comparing the collection signal corresponding to the adjustment collection circuit with the collection signal corresponding to the reference collection circuit.
[0033] In the present application, when the judging module determines the phase shift value according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit, the reference collection circuit and the adjustment collection circuit can be first determined from the rising edge collection circuit and the falling edge collection circuit according to the collection signal corresponding to the rising edge collection circuit and the collection signal corresponding to the falling edge collection circuit, and then the phase shift value is determined by comparing the collection signal corresponding to the adjustment collection circuit with the collection signal corresponding to the reference collection circuit. Thus, the reference collection circuit and the adjustment collection circuit are determined from the rising edge collection circuit and the falling edge collection circuit, and the best phase shift value is determined based on the collection signals of the reference collection circuit and the adjustment collection circuit, so that the subsequent phase shift of the input clock signal based on the phase shift value makes the calibration result of the clock more accurate.
[0034] In the embodiment of the present application, the judging module can be used to determine the reference collection circuit as the collection circuit with the same preset level state if one of the first level state of the collection signal corresponding to the rising edge collection circuit and the first level state of the collection signal corresponding to the falling edge collection circuit is the same as the preset level state.
[0035] In the present application, when the reference collection circuit is determined, the judging module can obtain the level state of the collection signal corresponding to the rising edge collection circuit and the level state of the collection signal corresponding to the falling edge collection circuit, and then compare each level state with the preset level state, and the preset level state is the first level state set in advance in the single-wire communication protocol. For example, the preset level state is low, and the first level state of the collection signal corresponding to the rising edge collection circuit is also low, and the first level state of the collection signal corresponding to the falling edge collection circuit is high, so that the rising edge collection circuit can be determined as the reference collection circuit and the falling edge collection circuit can be determined as the adjustment collection circuit. Thus, the reference collection circuit is determined according to the first level state of the rising edge collection circuit and the first level state of the falling edge collection circuit and the preset level state, and the best phase shift value is determined based on the collection signal of the reference collection circuit.
[0036] In this embodiment of the invention, the judgment module is used to determine, if the first level state of the acquisition signal corresponding to the rising edge acquisition circuit and the first level state of the acquisition signal corresponding to the falling edge acquisition circuit are both the same as the preset level state, a first time when the level state of the acquisition signal corresponding to the rising edge acquisition circuit first appears to be the same level state for the first time, and a second time when the level state of the acquisition signal corresponding to the falling edge acquisition circuit first appears to be the same level state for the first time; and to determine the reference acquisition circuit based on the first time and the second time.
[0037] For example, if the preset level state is high, the signal acquired by the rising edge acquisition circuit is: high, low, high, low, low, high, low... while the signal acquired by the falling edge acquisition circuit is: high, low, high, low, high, low, high, low, high, low, high... At this time, the first level state of the signal acquired by both the rising edge and falling edge acquisition circuits is the same as the preset level state. Then, the first time when consecutive identical level states first appear in the signal level states corresponding to the rising edge acquisition circuit is determined (i.e., the first time when the rising edge acquisition circuit has two consecutive low level states). The second time when consecutive identical level states first appear in the signal level states corresponding to the falling edge acquisition circuit is determined (i.e., the second time when the falling edge acquisition circuit has two consecutive high level states). Based on these two times, a reference acquisition circuit is determined. Thus, based on the first level states of the rising and falling edge acquisition circuits, the preset level state, and the time of the first consecutive identical level states, the reference acquisition circuit is determined, allowing subsequent determination of the optimal phase offset value using the acquired signal from the reference acquisition circuit as a standard.
[0038] In this invention, if a reference acquisition circuit cannot be determined according to the above method, a calibration error signal is output, indicating that the clock of one of the acquisition circuits is abnormal and communication is stopped.
[0039] In this embodiment of the invention, the determination module can be used to determine the rising edge acquisition circuit as the reference acquisition circuit if the first time is greater than the second time; and to determine the falling edge acquisition circuit as the reference acquisition circuit if the first time is less than the second time.
[0040] In this invention, if the first level state of the rising edge acquisition circuit and the first level state of the falling edge acquisition circuit are both the same as the first level state in the single-wire protocol, then the acquisition circuit that exhibits the latest two consecutive identical level states is used as the reference acquisition module. Thus, the reference acquisition circuit is determined based on the time of the first occurrence of consecutive identical level states, and subsequently, the optimal phase offset value is determined using the acquisition signal from the reference acquisition circuit as a standard.
[0041] like Figure 3As shown, a diagram for collecting signals is shown. The first row of signals is an input clock signal, the second row of signals is a collected signal, and the third row of signals is an output clock signal obtained by phase offsetting the input clock signal according to an initial phase offset value. Because the output clock signal is offset by 1 / nT in each clock cycle, the collected signals obtained by the rising edge collection circuit and the falling edge collection circuit are offset, and the positions of the collected signals are all moved backward. When the offset continues to increase, the collected signals obtained by the rising edge collection circuit and the falling edge collection circuit in the same cycle start to differ. In the example shown in the figure, 1100100110 indicates that the collected signal obtained by the rising edge collection circuit is high, low, high, low, high, and low, and the collected signal obtained by the falling edge collection circuit is high, low, low, high, and low. It also indicates that in the first clock cycle, the collected signal obtained by the rising edge collection circuit is the same as the collected signal obtained by the falling edge collection circuit, and both are high. In the third clock cycle, the collected signal obtained by the rising edge collection circuit is high, and the collected signal obtained by the falling edge collection circuit is low.
[0042] In the embodiment of the present application, the judging module is configured to compare the level state of the collected signal of the adjusting collection circuit with the level state of the collected signal of the reference collection circuit, and if there is a first continuously appearing level state different from the two level states, determine the phase offset value according to the different level state.
[0043] In the present application, after the reference collection circuit and the adjusting collection circuit are determined, the collected signals of the adjusting collection circuit and the reference collection circuit can be compared one by one. For example, if the reference collection circuit is a falling edge collection circuit, the adjusting collection circuit is a rising edge collection circuit, the first collected signal of the rising edge collection circuit is compared with the first collected signal of the falling edge collection circuit, the second collected signal of the rising edge collection circuit is compared with the second collected signal of the falling edge collection circuit, and so on. If there is a first continuously appearing level state different from the two or more level states in the reference collection circuit, the phase offset value can be determined according to the determined different level state. The different level state is the first continuously appearing level state different from the two level states. Thus, the adjustment is set according to the continuously appearing two level states different from each other, so as to avoid the influence of communication noise.
[0044] In the present application, if the first continuously appearing level state different from the two level states is not determined according to the above method, an abnormal calibration signal is output, indicating that the clock of a certain collection circuit is abnormal, and the communication is stopped.
[0045] In the embodiment of the present application, the judging module is configured to determine the serial number of the first level state in the different level states, and take the serial number as the phase offset value.
[0046] For example, if the level state of the acquisition signal of the adjustment acquisition circuit is different from the level state of the acquisition signal of the reference acquisition circuit for the first time in the fifth continuous level state, the serial number 5 can be determined, and 5 can be taken as the phase offset value. Thus, the optimal phase offset value is determined according to the serial number of the first level state in the different level states.
[0047] As shown in Figure 4 Fig. 2 shows another schematic diagram of the clock phase offset provided by the embodiment of the present application. The clock period of the input clock signal is T, and the adjusted output clock signal is obtained after the input clock is subjected to the phase offset processing again according to the phase offset signal corresponding to the determined phase offset value, and the period of the adjusted output clock signal is x / nT, wherein x is the determined phase offset value, and n is the initial phase offset value.
[0048] In the present application, the clock calibration of the acquisition signal can be performed by the clock calibration circuit for the communication devices at both ends of the single-wire protocol. For example, after the host sends the calibration data to the slave, the slave also sends the calibration data to the host for calibration after completing the calibration, so that the full-duplex single-wire protocol calibration can be realized.
[0049] In the embodiment of the present application, the clock delay module is configured to acquire an input clock signal, perform phase offset processing on the input clock signal to obtain an output clock signal, and send the output clock signal and an acquisition signal to the rising edge acquisition circuit and the falling edge acquisition circuit; acquire a write enable and a phase offset signal sent by the judgment module, respond to the write enable sent by the judgment module, perform phase offset processing on the input clock again according to the phase offset signal to obtain an adjusted output clock signal, and send the adjusted output clock signal to the rising edge acquisition circuit and the falling edge acquisition circuit; the rising edge acquisition circuit is configured to acquire the acquisition signal according to the output clock signal; the falling edge acquisition circuit is configured to acquire the acquisition signal according to the output clock signal; the judgment module is configured to acquire the acquisition signal corresponding to the rising edge acquisition circuit and acquire the acquisition signal corresponding to the falling edge acquisition circuit; determine a phase offset value according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; and send the write enable and the phase offset signal corresponding to the phase offset value to the clock delay module. Thus, the optimal phase offset value configuration is determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, and the calibration result of the output clock signal is more accurate, so that accurate data latching can be ensured.
[0050] As shown in Figure 5 Fig. 3 shows a step flowchart of a clock calibration method provided by the embodiment of the present application. The method is applied to the judgment module of the clock calibration circuit as described above, and the method comprises the following steps: In step 501, the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit are acquired; the rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal according to the output clock signal respectively; the output clock signal is acquired by the clock delay module from the input clock signal; the input clock signal is phase-shifted to obtain the output clock signal; the acquisition signal is sent by the clock delay module to the rising edge acquisition circuit and the falling edge acquisition circuit; In step 502, the phase shift value is determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit. In step 503, the phase shift signal corresponding to the write enable and the phase shift value is sent to the clock delay module, so that the clock delay module responds to the write enable, and the input clock is phase-shifted again according to the phase shift signal to obtain the adjusted output clock signal, and the adjusted output clock signal is sent to the rising edge acquisition circuit and the falling edge acquisition circuit.
[0051] In an embodiment, the output clock signal is obtained by phase-shifting the input clock signal by an initial phase shift value n; the number of signal periods of the output clock signal is n, and each clock period of the output clock signal is phase-shifted by 1 / n relative to each clock period of the input clock signal. Thus, the input clock signal is phase-shifted according to the initial phase shift value to obtain the output clock signal, and then the rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal according to the output clock signal, which ensures that the rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal more stably.
[0052] In an embodiment, the phase shift value is determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, comprising: The reference acquisition circuit and the adjustment acquisition circuit are determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; the reference acquisition circuit is the rising edge acquisition circuit or the falling edge acquisition circuit; the adjustment acquisition circuit is the acquisition circuit in the rising edge acquisition circuit and the falling edge acquisition circuit that is not determined as the reference acquisition circuit; The acquisition signal corresponding to the adjustment acquisition circuit is compared with the acquisition signal corresponding to the reference acquisition circuit to determine the phase shift value. Thus, the reference acquisition circuit and the adjustment acquisition circuit are determined in the rising edge acquisition circuit and the falling edge acquisition circuit, and the best phase shift value is determined based on the acquisition signals of the reference acquisition circuit and the adjustment acquisition circuit, and then the input clock signal is phase-shifted based on the phase shift value, so that the clock calibration result is more accurate.
[0053] In an embodiment, the reference acquisition circuit and the adjustment acquisition circuit are determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, comprising: If one of the first level state of the acquisition signal corresponding to the rising edge acquisition circuit and the first level state of the acquisition signal corresponding to the falling edge acquisition circuit is the same as the preset level state, the acquisition circuit with the same preset level state is determined as the reference acquisition circuit, and the acquisition circuit not determined as the reference acquisition circuit is determined as the adjustment acquisition circuit. Thus, the reference acquisition circuit is determined according to the first level state of the rising edge acquisition circuit, the first level state of the falling edge acquisition circuit and the preset level state, and the optimal phase offset value is determined subsequently based on the acquisition signal of the reference acquisition circuit.
[0054] In an embodiment, the reference acquisition circuit and the adjustment acquisition circuit are determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, comprising: If the first level state of the acquisition signal corresponding to the rising edge acquisition circuit and the first level state of the acquisition signal corresponding to the falling edge acquisition circuit are both the same as the preset level state, the first time when the level state of the acquisition signal corresponding to the rising edge acquisition circuit first appears continuous same level state and the second time when the level state of the acquisition signal corresponding to the falling edge acquisition circuit first appears continuous same level state are determined. The reference acquisition circuit is determined according to the first time and the second time, and the acquisition circuit not determined as the reference acquisition circuit is determined as the adjustment acquisition circuit. Thus, the reference acquisition circuit is determined according to the first level state of the rising edge acquisition circuit, the first level state of the falling edge acquisition circuit, the preset level state and the time when the level state first appears continuous same level state, and the optimal phase offset value is determined subsequently based on the acquisition signal of the reference acquisition circuit.
[0055] In an embodiment, the reference acquisition circuit is determined according to the first time and the second time, comprising: If the first time is greater than the second time, the rising edge acquisition circuit is determined as the reference acquisition circuit. If the first time is less than the second time, the falling edge acquisition circuit is determined as the reference acquisition circuit. Thus, the reference acquisition circuit is determined based on the time when the level state first appears continuous same level state, and the optimal phase offset value is determined subsequently based on the acquisition signal of the reference acquisition circuit.
[0056] In an embodiment, the comparing the acquisition signal corresponding to the adjustment acquisition circuit with the acquisition signal corresponding to the reference acquisition circuit to determine the phase offset value comprises: comparing the level state of the acquisition signal corresponding to the adjustment acquisition circuit with the level state of the acquisition signal corresponding to the reference acquisition circuit, if there is a first level state with different level states in succession, determining the phase offset value according to the different level states. Thus, the setting adjustment of the two level states in succession is adopted to avoid the influence of communication noise.
[0057] In an embodiment, the determining the phase offset value according to the different level states comprises: determining the serial number of the first level state in the different level states, and taking the serial number as the phase offset value. Thus, the best phase offset value is determined through the serial number of the first level state in the different level states.
[0058] In the embodiment of the application, the acquisition signal corresponding to the rising edge acquisition circuit is acquired, and the acquisition signal corresponding to the falling edge acquisition circuit is acquired; the rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal according to the output clock signal respectively; the output clock signal is acquired by the clock delay module from the input clock signal; the input clock signal is subjected to phase offset processing to obtain; the acquisition signal is sent to the rising edge acquisition circuit and the falling edge acquisition circuit by the clock delay module; the phase offset value is determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; the phase offset signal corresponding to the write enable and the phase offset value is sent to the clock delay module, so that the clock delay module responds to the write enable sent by the judgment module, and the input clock is subjected to phase offset processing again according to the phase offset signal to obtain the adjusted output clock signal, and the adjusted output clock signal is sent to the rising edge acquisition circuit and the falling edge acquisition circuit. Thus, the best phase offset value configuration is determined according to the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, and the calibration result of the output clock signal is more accurate, and accurate data latching is ensured.
[0059] It should be noted that, for the method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the application are not limited to the action order described, because according to the embodiments of the application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the application.
[0060] The various embodiments described in this specification are intended to be illustrative only and in no way limit the scope of the application. One skilled in the art will readily recognize from the disclosure herein, possible alternative techniques within the scope of the application. Accordingly, the embodiments described in this specification are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.
[0061] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects all generally referred to herein as a "circuit" or "module." Furthermore, the present application can take the form of a computer program product on a computer-readable storage medium having computer program code embodied in the medium.
[0062] The embodiments of the present application are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing unit or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 means for performing each of the one or more functions specified in the flowchart illustrations and / or block diagrams.
[0063] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 means for performing each of the one or more functions specified in the flowchart illustrations and / or block diagrams.
[0064] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 means for performing each of the one or more functions specified in the flowchart illustrations and / or block diagrams.
[0065] While the preferred embodiments of the application have been described above, it should be understood that many modifications and adaptations will occur to those skilled in the art upon reading the foregoing description. Accordingly, the appended claims are intended to cover all such modifications and adaptations as fall within the scope of the preferred embodiments of the application.
[0066] Finally, it should be noted that, in the description above, relative terms such as first and second, etc. are used merely to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
[0067] The above provides a clock calibration circuit and a clock calibration method, and the principles and implementation manners of the application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the application and its core idea. Meanwhile, for those skilled in the art, the specific implementation manners and application scope can be changed according to the idea of the application. In summary, the content of the description should not be understood as a limitation of the application.
Claims
1. A clock calibration circuit, characterized in that, The clock calibration circuit includes: a clock delay module, a rising edge acquisition circuit, a falling edge acquisition circuit, and a judgment module, all connected to the clock delay module; the judgment module is connected to both the rising edge acquisition circuit and the falling edge acquisition circuit. The clock delay module is used to acquire an input clock signal; perform phase offset processing on the input clock signal to obtain an output clock signal, and send the output clock signal and the acquisition signal to the rising edge acquisition circuit and the falling edge acquisition circuit; acquire the write enable and phase offset signals sent by the judgment module, respond to the write enable, perform phase offset processing on the input clock again according to the phase offset signal to obtain an adjusted output clock signal, and send the adjusted output clock signal to the rising edge acquisition circuit and the falling edge acquisition circuit; The rising edge acquisition circuit is used to acquire the acquisition signal according to the output clock signal; The falling edge acquisition circuit is used to acquire the acquisition signal according to the output clock signal; The judgment module is used to acquire the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; determine the phase offset value based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; and send the write enable and the phase offset signal corresponding to the phase offset value to the clock delay module.
2. The clock calibration circuit according to claim 1, characterized in that, The clock delay module is used to acquire the input clock signal and then perform phase offset processing on the input clock signal according to the initial phase offset value n to obtain the output clock signal. The output clock signal has n signal periods, and each clock period of the output clock signal is phase-shifted by 1 / n relative to each clock period of the input clock signal.
3. The clock calibration circuit according to claim 1, characterized in that, The judgment module is used to determine the reference acquisition circuit and the adjustment acquisition circuit based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit. The reference acquisition circuit is either the rising edge acquisition circuit or the falling edge acquisition circuit; the adjustment acquisition circuit is the acquisition circuit that is not determined to be the reference acquisition circuit between the rising edge acquisition circuit and the falling edge acquisition circuit. The phase offset value is determined by comparing the acquisition signal corresponding to the adjustment acquisition circuit with the acquisition signal corresponding to the reference acquisition circuit.
4. The clock calibration circuit according to claim 3, characterized in that, The judgment module is used to determine the acquisition circuit that has the same preset level state as the reference acquisition circuit if either the first level state of the acquisition signal corresponding to the rising edge acquisition circuit or the first level state of the acquisition signal corresponding to the falling edge acquisition circuit is the same as the preset level state.
5. The clock calibration circuit according to claim 3, characterized in that, The judgment module is used to determine the first time when the level state of the acquisition signal corresponding to the rising edge acquisition circuit first appears to be the same as the first time when the level state of the acquisition signal corresponding to the falling edge acquisition circuit first appears to be the same as the preset level state, and the second time when the level state of the acquisition signal corresponding to the falling edge acquisition circuit first appears to be the same as the preset level state. The reference acquisition circuit is determined based on the first time and the second time.
6. The clock calibration circuit according to claim 5, characterized in that, The determination module is configured to determine the rising edge acquisition circuit as the reference acquisition circuit if the first time is greater than the second time, and to determine the falling edge acquisition circuit as the reference acquisition circuit if the first time is less than the second time.
7. The clock calibration circuit according to claim 3, characterized in that, The judgment module is used to compare the level state of the acquisition signal corresponding to the adjustment acquisition circuit with the level state of the acquisition signal corresponding to the reference acquisition circuit. If there is a first occurrence of two consecutive level states with different levels, then the phase offset value is determined based on the different level states.
8. The clock calibration circuit according to claim 7, characterized in that, The judgment module is used to determine the sequence number of the first level state among the different level states, and use the sequence number as the phase offset value.
9. A clock calibration method, characterized in that, The method is applied to the judgment module of the clock calibration circuit as described in any one of claims 1-8, and the method includes: The system acquires the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit; the rising edge acquisition circuit and the falling edge acquisition circuit acquire the acquisition signal according to the output clock signal; the output clock signal is obtained by the clock delay module from the input clock signal; the input clock signal is obtained by performing phase shift processing on the input clock signal; the acquisition signal is sent by the clock delay module to the rising edge acquisition circuit and the falling edge acquisition circuit. The phase offset value is determined based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit. The clock delay module sends the write enable and the phase offset signal corresponding to the phase offset value to the clock delay module so that the clock delay module responds to the write enable, performs phase offset processing on the input clock again according to the phase offset signal, obtains the adjusted output clock signal, and sends the adjusted output clock signal to the rising edge acquisition circuit and the falling edge acquisition circuit.
10. The clock calibration method according to claim 9, characterized in that, The output clock signal is obtained by phase shifting the input clock signal according to the initial phase shift value n; the number of signal periods of the output clock signal is n, and each clock period of the output clock signal is phase-shifted by 1 / n relative to each clock period of the input clock signal.
11. The clock calibration method according to claim 9, characterized in that, Determining the phase offset value based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit includes: Based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit, a reference acquisition circuit and an adjustment acquisition circuit are determined; the reference acquisition circuit is either the rising edge acquisition circuit or the falling edge acquisition circuit; the adjustment acquisition circuit is the acquisition circuit that is not determined to be the reference acquisition circuit among the rising edge acquisition circuit and the falling edge acquisition circuit. The phase offset value is determined by comparing the acquisition signal corresponding to the adjustment acquisition circuit with the acquisition signal corresponding to the reference acquisition circuit.
12. The clock calibration method according to claim 11, characterized in that, The step of determining the reference acquisition circuit and the adjustment acquisition circuit based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit includes: If either the first level state of the acquisition signal corresponding to the rising edge acquisition circuit or the first level state of the acquisition signal corresponding to the falling edge acquisition circuit is the same as a preset level state, then the acquisition circuit that is the same as the preset level state is determined as the reference acquisition circuit, and the acquisition circuit that is not determined as the reference acquisition circuit is determined as the adjustment acquisition circuit.
13. The clock calibration method according to claim 11, characterized in that, The step of determining the reference acquisition circuit and the adjustment acquisition circuit based on the acquisition signal corresponding to the rising edge acquisition circuit and the acquisition signal corresponding to the falling edge acquisition circuit includes: If the first level state of the acquisition signal corresponding to the rising edge acquisition circuit and the first level state of the acquisition signal corresponding to the falling edge acquisition circuit are both the same as the preset level state, then the first time when the level state of the acquisition signal corresponding to the rising edge acquisition circuit first appears to be the same level state for the first time, and the second time when the level state of the acquisition signal corresponding to the falling edge acquisition circuit first appears to be the same level state for the first time. The reference acquisition circuit is determined based on the first time and the second time, and the acquisition circuits that are not determined as the reference acquisition circuits are determined as adjustment acquisition circuits.
14. The clock calibration method according to claim 13, characterized in that, The step of determining the reference acquisition circuit based on the first time and the second time includes: If the first time is greater than the second time, then the rising edge acquisition circuit is determined as the reference acquisition circuit; If the first time is less than the second time, then the falling edge acquisition circuit is determined as the reference acquisition circuit.
15. The clock calibration method according to claim 11, characterized in that, The step of comparing the acquisition signal corresponding to the adjustment acquisition circuit with the acquisition signal corresponding to the reference acquisition circuit to determine the phase offset value includes: The level of the acquisition signal corresponding to the adjustment acquisition circuit is compared with the level of the acquisition signal corresponding to the reference acquisition circuit. If two consecutive level states are different for the first time, the phase offset value is determined based on the different level states.
16. The clock calibration method according to claim 15, characterized in that, Determining the phase offset value based on the different level states includes: Determine the sequence number of the first level state among the different level states, and use the sequence number as the phase offset value.