Power clock synchronization signal link planning method
By employing a tree-like growth and hierarchical planning method in the power SDH transmission system to transmit clock signals step by step, the high error rate and timing loop problems in clock link planning are solved, thereby improving the synchronization accuracy and reliability of the power network.
Patent Information
- Application Number
- CN202512034303.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-10
AI Technical Summary
The existing clock link planning in power systems suffers from a high error rate and is prone to forming timing loops, which affects clock synchronization accuracy and network communication reliability, especially in complex power SDH transmission networks.
By adopting a tree-growing, hierarchical planning approach, clock signals are transmitted step by step from the core layer in the power SDH transmission system. By setting up primary and backup clock sources through extremely long links in the core layer and injecting clock signals into the aggregation and access layers step by step, signal backhaul is avoided, forming a tree-like structure to reduce timing loops.
It reduces the error rate of clock link organization, improves the reliability of clock signal transmission and simplifies network organization, and ensures high precision and reliable communication in power transmission networks.
Smart Images
Figure CN121841528A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the field of power clock frequency synchronization signal link planning, and particularly relates to a power clock synchronization signal link planning method. BACKGROUND
[0002] With the rapid development of smart grid, the requirements for clock synchronization accuracy and reliability of the power system have reached an unprecedented height. New generation substations, digital transmission lines, distributed energy grid connection, power distribution network automation and power internet of things and other key businesses all rely on high-precision synchronization signals (such as IRIG-B, PTP, 1PPS+TOD, etc.) for time alignment to ensure the correct execution of protection control, data sampling, fault location and other functions; SDH devices, dispatching switching devices and other devices need to be synchronized in frequency to ensure the normal operation of transmission devices and dispatching switching devices.
[0003] Currently, the construction of the clock synchronization network in the power system mainly relies on cesium clocks or satellite signals (Beidou) as the master clock source, and the synchronization signals are transmitted downward through hierarchical cascading of ground links (SDH transmission network). The typical architecture is that a region deploys a primary master clock and a primary backup clock in the dispatching center or hub station to receive cesium clock signals or Beidou satellite signals; the subordinate dispatching center or hub station deploys a secondary master clock and a backup clock and receives the synchronization signals from the upper level clock through the SDH transmission network. The SDH network in the region transmits the clock signals to the next level slave clock and transmits the upper level clock signals to all SDH devices for synchronization, as shown in FIG. 1. Figure 1
[0004] The clock link organization of the power SDH network includes the primary clock link and the backup clock link, and the link organization of the entire network should not form a timing loop (the arrows are connected at the head and tail). However, since the clock links of most networks are manually organized, and the planning is arbitrary, it is difficult to avoid forming a loop in some areas, as shown in FIG. 2. Figure 2 After the loop is formed, the SDH clock in the region self-oscillates, the clock synchronization accuracy is reduced to the minimum, and the communication reliability of the transmission network is seriously affected.
[0005] At the same time, in the region with a complex structure of the power SDH transmission network, the organization of the related clock links is also more complex and prone to errors. SUMMARY
[0006] The technical problem to be solved by the application is how to reduce the error rate of the clock link organization. The application provides a power clock synchronization signal link planning method based on tree growth and hierarchical planning.
[0007] To achieve the above purpose, the application is implemented as follows. A method for planning power clock synchronization signal links includes the following steps: Step 1: Identify the core layer in the topology of the power SDH transmission system that needs to be planned, and find the longest chain in the core layer, denoted as the first-layer link L1. There is only one first-layer link. Set a primary clock and a backup clock at both ends of the first-layer link. The primary clock and the backup clock inject clock signals into the first-layer link L1. Plan the primary and backup clock links for each SDH node according to the direction of the first-layer link L1. Step 2: Find the interconnecting links in Layer 1 link L1, and denote them as Layer 2 link L. 2n If the Layer 2 link L 2n If there are ≥2 SDH nodes in the layer, then the data can be simultaneously transmitted from the layer 1 link L1 to the layer 2 link L2 interconnected with it. 2n Two nodes inject the primary clock link, and then in the Layer 2 link L... 2n The backup clock is planned in the middle, and the backup clock link does not inject signals into the upper layer link L1; if the layer 2 link L 2n If there is one SDH node, then simultaneously from the Layer 1 link L1 to the Layer 2 link L2 interconnected with it... 2n Inject the Layer 2 primary clock link and Layer 2 backup clock link into the SDH node; and so on, traversing all Layer 2 links L. 2n ; Step 3: In Layer 2 link L 2n Find the link that is interconnected with it, and denote it as a Layer 3 link L. 3n If the three-layer link L 3n If there are ≥2 SDH nodes in the link, then from link L 2n Simultaneously, it connects to the three-layer link L. 3n Two nodes inject the primary clock link, and then in the Layer 3 link L... 3n The backup clock is planned in the middle, and the backup clock link does not go up to the next layer 2 link L. 2n Inject signal; if the three-layer link L 3n If there is one SDH node in the layer 2 link L, then... 2n Simultaneously, it connects to the three-layer link L. 3n In the middle SDH node, a Layer 3 primary clock link and a Layer 3 backup clock link are injected, and so on, traversing all Layer 3 links L. 3n ; Step 4: Following this pattern, in layer i link L... in Find the link that is interconnected with it in the i+1 layer, and denote it as the link L in the i+1 layer. （i+1）n If there are ≥2 SDH nodes in the i+1 layer link, then from the i-th layer link L in Simultaneously, it connects to the i+1 layer link L. （i+1）nThe two nodes inject a main clock link, and then inject a clock signal to the i+1 layer link L （i+1）n The standby clock link does not inject a signal to the upper layer link; if the SDH node in the i+1 layer link is one, a clock signal is injected to the i layer link L in The i+1 layer link L （i+1）n The SDH node injects the i+1 layer main clock link and the i+1 layer standby clock link, and so on, and traverses all the i layer links L in .
[0008] The method further comprises a fifth step: if there are p layer links L pn and q layer links L qn interconnected with the next layer link, the next layer link is named as u layer, u = min(p, q) + 1, and the L un link respectively takes a clock signal from the p layer link L pn and the q layer link L qn .
[0009] Compared with the prior art, the method has the following beneficial effects: the method provides a power clock synchronization signal link planning method, combines the power SDH transmission network structure, combines the original hierarchical topology, and gradually transmits the clock signal from the core layer to the aggregation layer and the access layer, specifically, a very long chain is preferentially found in the core layer, the two ends of the chain are main and standby clock sources, and the main clock link and the standby clock link are planned in the chain. Then the clock signal is injected from the very long chain to other links in the core layer, the aggregation layer and the access layer, and the main and standby clock links are sequentially organized. In this way, all links have clock signals. Since the method only transmits the clock from the trunk to the branch like a tree branch, the signal cannot be transmitted back from the branch to the trunk, so the probability of forming a timing loop can be greatly reduced. After the planar mesh network structure is split into a link structure and the clock link is organized, the network complexity is reduced, and the link organization is easier. At the same time, the core layer of the power transmission network generally has a reliable optical cable operating environment, and the method preferentially relies on the core layer link of the power transmission network to transmit the clock to the branch, which can improve the clock signal transmission reliability. BRIEF DESCRIPTION OF DRAWINGS
[0010] Figure 1 is a typical architecture diagram in the prior art; Figure 2 is a schematic diagram of forming a loop in part of the existing architecture; Figure 3 is a schematic diagram of forming a loop in part of the existing architecture; DETAILED DESCRIPTION
[0011] The application will be described in the embodiments with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.
[0012] In the description of the application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.
[0013] As shown in Figure 3 , a power clock synchronization signal link planning method is used for power SDH transmission system (or other transmission systems requiring clock synchronization) clock synchronization signal link planning, including the following steps: Step 1: Find the core layer in the power SDH transmission system topology requiring planning, and find the extremely long chain in the core layer, mark it as a layer link L1, and there is only one layer link L1, and a primary clock and a backup clock are arranged at both ends of the layer link L1, the primary clock and the backup clock inject clock signals into the layer link L1, and the primary and backup clock links of each SDH node are planned according to the direction of the layer link L1, as shown in Figure 3 The red solid line and the red dashed line are the layer primary clock link and the layer backup clock link, respectively.
[0014] Step 2: Find the links interconnected with the layer link L1 in the layer link L1, mark them as two-layer links L 2n , and it should be noted that there can be multiple two-layer links, and n represents the nth two-layer link; if the number of SDH nodes in the two-layer link L 2n is greater than or equal to 2, the primary clock link is injected from the layer link L1 into the two nodes interconnected with the two-layer link L 2n , marked as a blue solid line, and marked as a two-layer primary clock link; and then the backup clock is planned in the two-layer link L 2n , marked as a two-layer backup clock link, and the backup clock link does not inject signals into the layer link L1 of the upper layer. If the number of SDH nodes in the two-layer link L 2n is 1, the two-layer primary clock link and the two-layer backup clock link (blue solid line and blue dashed line, respectively) are injected from the layer link L1 into the SDH node interconnected with the two-layer link L 2n . In this way, all two-layer links L2n .
[0015] Step three: find out the link connected with it in the second layer link L 2n , noted as the third layer link L 3n , it is to be noted that there can be multiple third layer links, n represents the nth third layer link; if the SDH nodes in the third layer link L 3n are ≥ 2, then inject the primary clock link (marked as green solid line) from the link L 2n to the two nodes in the third layer link L 3n connected with it, noted as the third layer primary clock link; and then plan the backup clock in the third layer link L 3n , noted as the third layer backup clock link, the backup clock link does not inject signals to the second layer link L 2n of the upper layer; if the SDH nodes in the third layer link L 3n are 1, then inject the third layer primary clock link and the third layer backup clock link (green solid line and green dotted line respectively) from the second layer link L 2n to the SDH node in the third layer link L 3n connected with it, and so on, traverse all the third layer links L 3n .
[0016] Step four: in this way, find out the link connected with it in the i layer link L in , noted as the i+1 layer link L （i+1）n , if the SDH nodes in the i+1 layer link are ≥ 2, then inject the primary clock link from the i layer link L in to the two nodes in the i+1 layer link L （i+1）n connected with it, noted as the i+1 layer primary clock link; and then plan the backup clock in the i+1 layer link L （i+1）n , noted as the i+1 layer backup clock link, the backup clock link does not inject signals to the link of the upper layer. If the SDH nodes in the i+1 layer link are 1, then inject the i+1 layer primary clock link and the i+1 layer backup clock link from the i layer link L in to the SDH node in the i+1 layer L （i+1）n connected with it, and so on, traverse all the i layer links L in .
[0017] Step five: if the p layer link L pn and the q layer link L qn are connected with the next layer link at the same time, then the next layer link is named as the u layer, u = min (p, q) + 1, the link L un takes the clock signal from the p layer link L pn and the q layer link L qn at the same time. The specific steps are the same as step 4.
[0018] The principle adopted by the present application is: Combined with the power SDH transmission network structure, the clock signal is transmitted from the core layer to the convergence layer and the access layer in stages, specifically, a very long chain is found in the core layer, the two ends of the chain are the main and standby clock sources, and the main clock link and the standby clock link are planned in the chain. Then the clock signal is injected from the very long chain to other links in the core layer, convergence layer and access layer, and the main and standby clock links are organized in turn, and so on until all the links have clock signals. Since this method only transmits clock from the trunk to the branch like a branch, the signal will not be transmitted back from the branch to the trunk, so the probability of forming a timing loop can be greatly reduced. After the planar mesh network structure is split into link structure and then the clock link is organized, the network complexity is reduced, and it is easier to organize the link. At the same time, the core layer of the power transmission network generally has a reliable optical cable operating environment, and the present application relies on the core layer link of the power transmission network to transmit the clock to the branch, which can improve the reliability of clock signal transmission.
[0019] The above only describes the preferred embodiments of the present application, and it should be pointed out that for those skilled in the art, without departing from the overall concept of the present application, a number of changes and improvements can be made, which should also be considered as the protection scope of the present application.
Claims
1. A method for planning power clock synchronization signal links, characterized in that, Includes the following steps: Step 1: Identify the core layer in the topology of the power SDH transmission system that needs to be planned, and find the longest chain in the core layer, denoted as the first-layer link L1. There is only one first-layer link. Set a primary clock and a backup clock at both ends of the first-layer link. The primary clock and the backup clock inject clock signals into the first-layer link L1. Plan the primary and backup clock links for each SDH node according to the direction of the first-layer link L1. Step 2: Find the interconnecting links in Layer 1 link L1, and denote them as Layer 2 link L. 2n If the Layer 2 link L 2n If there are ≥2 SDH nodes in the layer, then the data can be simultaneously transmitted from the layer 1 link L1 to the layer 2 link L2 interconnected with it. 2n Two nodes inject the primary clock link, and then in the Layer 2 link L... 2n The backup clock is planned in the middle, and the backup clock link does not inject signals into the upper layer link L1; if the layer 2 link L 2n If there is one SDH node, then simultaneously from the Layer 1 link L1 to the Layer 2 link L2 interconnected with it... 2n Inject the Layer 2 primary clock link and Layer 2 backup clock link into the SDH node; and so on, traversing all Layer 2 links L. 2n ; Step 3: In Layer 2 link L 2n Find the link that is interconnected with it, and denote it as a Layer 3 link L. 3n If the three-layer link L 3n If there are ≥2 SDH nodes in the link, then from link L 2n Simultaneously, it connects to the three-layer link L. 3n Two nodes inject the primary clock link, and then in the Layer 3 link L... 3n The backup clock is planned in the middle, and the backup clock link does not go up to the next layer 2 link L. 2n Inject signal; if the three-layer link L 3n If there is one SDH node in the layer 2 link L, then... 2n Simultaneously, it connects to the three-layer link L. 3n In the middle SDH node, a Layer 3 primary clock link and a Layer 3 backup clock link are injected, and so on, traversing all Layer 3 links L. 3n ; Step 4: Following this pattern, in layer i link L... in Find the link that is interconnected with it in the i+1 layer, and denote it as the link L in the i+1 layer. （i+1）n If there are ≥2 SDH nodes in the i+1 layer link, then from the i-th layer link L in Simultaneously, it connects to the i+1 layer link L. （i+1）n Two nodes are injected with the primary clock link, and then in the i+1 layer link L... （i+1）n A backup clock is planned in the middle, and the backup clock link does not inject signals into the upper layer link; If there is only one SDH node in the i+1 layer link, then from the i-th layer link L in Simultaneously, it connects to the i+1 layer L. （i+1）n In the middle SDH node, inject the primary clock link and the backup clock link of layer i+1, and so on, traversing all layer i links L. in .
2. The power clock synchronization signal link planning method according to claim 1, characterized in that: It also includes step five: if there is a p-layer link L pn and q-layer link L qn Simultaneously, it interconnects with the next layer link, then the next layer link is named layer u, u = min(p, q) + 1, L un The links are respectively from the p layer link L pn and q-layer link L qn Simultaneously, the clock signal is acquired.