Circuit board typesetting method and device, electronic equipment, storage medium and product

Abstract

The invention discloses a circuit board typesetting method and device, electronic equipment, a storage medium and a product. The method comprises the following steps: acquiring electrical constraint information of a device unit; determining a geometric cutting boundary of the device unit according to the electrical constraint information, wherein the geometric cutting boundary is a boundary of an area allowing slotting in the device unit; and determining the arrangement positions of the plurality of device units on the circuit board substrate by taking the plurality of device units as arrangement objects, the geometric cutting boundary as a constraint condition and the maximization of the material utilization rate of the circuit board substrate as an optimization target. According to the scheme provided by the invention, the arrangement distance between the device units can be reduced, and the material utilization rate of the circuit board substrate is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, and in particular to a circuit board layout method and device, electronic equipment, storage medium and product. BACKGROUND

[0002] Flexible circuit boards have the advantages of high wiring density, light weight, and thin thickness, and can be applied to devices for producing various electronic products. In the production and processing process of the devices, the flexible circuit boards usually need to be cut.

[0003] In related technologies, the device is usually irregularly shaped. If the arrangement position of the device on the flexible circuit board is unreasonable, the base material waste will be increased, and the material utilization rate of the circuit board substrate will be reduced. Therefore, how to arrange the device on the flexible circuit board to reduce the waste material and improve the material utilization rate has become a problem that needs to be solved by the technical personnel in the field. SUMMARY

[0004] The present application provides a circuit board layout method and device, electronic equipment, storage medium and product, which can reduce the arrangement distance between device units and improve the material utilization rate of the circuit board substrate.

[0005] In a first aspect, the present application provides a circuit board layout method, which comprises: obtaining electrical constraint information of a device unit; determining a geometric cutting boundary of the device unit according to the electrical constraint information, the geometric cutting boundary being a boundary of a region allowed to be slotted in the device unit; taking a plurality of device units as arrangement objects, taking the geometric cutting boundary as a constraint condition, and taking the maximum material utilization rate of a circuit board substrate as an optimization target, to determine the arrangement position of the plurality of device units on the circuit board substrate.

[0006] In the embodiments of the present application, the geometric cutting boundary of the device unit is determined according to the electrical constraint information of the device unit, so that when the device unit is arranged on the circuit board substrate, the device unit can be appropriately cut according to the requirements, and then for the device unit with irregular shape, the arrangement distance between device units can be reduced, and the material utilization rate of the circuit board substrate can be improved.

[0007] In some embodiments, determining the geometric cutting boundary of the device unit according to the electrical constraint information comprises: obtaining point cloud coordinates of a plurality of point clouds on the device unit; and constructing the geometric cutting boundary according to the point cloud coordinates corresponding to the plurality of point clouds and the electrical constraint information.

[0008] By geometrizing the electrical constraint of the device unit, the uncertainty in the FPC circuit board substrate arrangement process is reduced, the conflict risk that needs to be verified subsequently is pre-emptively resolved into a geometric constraint, the number of modifications of the FPC layout is reduced, and the efficiency of the FPC layout is improved.

[0009] In some embodiments, the geometric clipping boundary is constructed according to the point cloud coordinates corresponding to the plurality of point clouds and the electrical constraint information, including: in a case where it is determined according to the point cloud coordinates of the first point cloud that the first point cloud is a geometric mutation point, determining a first boundary point according to the point cloud coordinates corresponding to the first point cloud, wherein the first point cloud is any one of the plurality of point clouds, the geometric mutation point is a point cloud whose change value of geometric attribute is greater than a change threshold compared to adjacent point clouds, and the change threshold is determined by the change values of the geometric attributes corresponding to the plurality of point clouds; in a case where it is determined according to the point cloud coordinates corresponding to the first point cloud that the first point cloud is a regular point, determining the first boundary point according to the electrical constraint information and the point cloud coordinates of the first point cloud; and determining the geometric clipping boundary according to a region boundary formed by the first boundary point and a second boundary point.

[0010] Through the fine classification processing of the point cloud of the device unit, the coordination between the electrical constraint and the geometric boundary of the device unit can be realized, so as to maximize the effective area of the FPC circuit board substrate that can be used for close arrangement and improve the material utilization rate of the FPC circuit board substrate under the premise of ensuring the manufacturability of the device unit.

[0011] In some embodiments, the electrical constraint information includes a connector position, a wire width, and a preset safety distance; and the second boundary point is determined according to the electrical constraint information and the point cloud coordinates of the first point cloud, including: determining the number of wires according to the relative positional relationship between the point cloud coordinates of the first point cloud and the connector position; determining the wire arrangement requirement width according to the wire width and the number of wires; and determining the second boundary point according to the wire arrangement requirement width and the safety distance.

[0012] By dynamically calculating the wire arrangement requirement width point by point, fine adaptive clipping of the device unit is realized, and the effective area of the FPC circuit board substrate that can be arranged is maximized and the material utilization rate of the substrate is improved under the premise of ensuring electrical safety.

[0013] In some embodiments, the geometric clipping boundary includes a first clipping boundary and a second clipping boundary arranged oppositely, and the second boundary point is determined according to the wire arrangement requirement width and the safety distance, including: determining the second boundary point on the first clipping boundary according to the sum of the wire arrangement requirement width and the safety distance; and determining the second boundary point on the second clipping boundary according to the difference between the wire arrangement requirement width and the safety distance.

[0014] By differentially applying the sum of the wire arrangement requirement width and the safety distance and the difference between the wire arrangement requirement width and the safety distance, non-uniform and adaptive clipping of the device unit is realized, so as to maximize the effective area of the FPC circuit board substrate for arranging the device unit and improve the material utilization rate of the substrate on the basis of ensuring electrical safety.

[0015] In some embodiments, the geometric clipping boundary is determined according to a region boundary formed by the first boundary points and the second boundary points, including: obtaining a first boundary point sequence composed of the first boundary points and a second boundary point sequence composed of the second boundary points; fitting the first boundary point sequence and the second boundary point sequence to generate a region boundary line; and determining the geometric clipping boundary according to the region boundary line.

[0016] By fitting the boundary points to generate the geometric clipping boundary, and then clipping the device units based on the geometric clipping boundary, the material utilization rate of the arranged FPC circuit board substrate can be improved.

[0017] In some embodiments, a plurality of device units are arranged as arrangement objects, the geometric clipping boundary is used as a constraint condition, and the material utilization rate of the circuit board substrate is maximized as an optimization target to determine the arrangement position of the plurality of device units on the circuit board substrate, including: in the case that there are arranged device units on the circuit board substrate, using the point cloud coordinates of the arranged device units as tree nodes to construct a search tree; performing neighborhood search on the search tree to determine a target arrangement position interval of a to-be-arranged device unit on the circuit board substrate; searching for a target arrangement position that maximizes the material utilization rate of the circuit board substrate in the target arrangement position interval, taking the arrangement position of the to-be-arranged device unit as a variable and taking the geometric clipping boundary as a constraint condition; and determining the arrangement position of the to-be-arranged device unit on the circuit board substrate according to the target arrangement position.

[0018] By constructing a spatial index, neighborhood search, and a local fine optimization arrangement framework, the complex global arrangement problem is decomposed into a locally optimized sub-problem that can be efficiently solved, the arrangement density is greatly improved on the premise of ensuring the solution quality, and thus the material utilization rate of the circuit board substrate is directly improved.

[0019] In some embodiments, the neighborhood search is performed on the search tree to determine a target arrangement position interval of a to-be-arranged device unit on the circuit board substrate, including: taking the centroid of the to-be-arranged device unit as the center and taking a region determined by the size of the to-be-arranged device unit as a search range, performing neighborhood search on the search tree to determine a conflict device unit whose point cloud coordinates are located in the search range, and obtaining a conflict device set; and determining the target arrangement position interval of the to-be-arranged device unit on the circuit board substrate according to the relative position between the conflict device unit and the initial arrangement position of the to-be-arranged device unit on the circuit board substrate.

[0020] By adaptive range conflict detection and interval positioning based on conflict geometric relationship, the available space of the to-be-arranged device unit is accurately circled, a high-quality initial solution interval is provided for subsequent high-density embedding, and thus the substrate material utilization rate is directly improved.

[0021] In some embodiments, the target arrangement position interval of the device unit to be arranged on the circuit board substrate is determined according to the relative position between the conflicting device unit and the initial arrangement position of the device unit to be arranged on the circuit board substrate, including: determining the initial arrangement position interval according to the relative position between the conflicting device unit and the device unit to be arranged; iteratively updating the initial arrangement position interval according to the interval length corresponding to the initial arrangement position interval, until the interval length corresponding to the initial arrangement position interval is within a target length range, to obtain the target arrangement position interval, wherein the lower limit of the target length range is a first length threshold, and the upper limit of the target length range is a second length threshold.

[0022] By iteratively approaching the critical position through interval iteration, the available space of the device unit to be arranged is positioned with high precision, so that the device unit can be placed at a limit position that is just not interfered with other device units and the gap is compressed to the minimum value allowed by the process, thereby improving the utilization rate of the circuit board substrate material.

[0023] In some embodiments, the target arrangement position interval includes an arrangement position upper limit value and an arrangement position lower limit value, and the initial arrangement position interval is iteratively updated according to the interval length corresponding to the initial arrangement position interval, until the interval length corresponding to the initial arrangement position interval is within a target length range, to obtain the target arrangement position interval, including: determining the midpoint position of the initial arrangement position interval according to the arrangement position upper limit value and the arrangement position lower limit value; in the case that the interval length is less than the first length threshold, updating the arrangement position upper limit value based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, to obtain the target arrangement position interval; in the case that the interval length is greater than the second length threshold, updating the arrangement position lower limit value based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, to obtain the target arrangement position interval.

[0024] By iteratively approaching the critical position through bisection method, the available space of the device unit to be arranged is positioned with high precision, so that the gap between the device units is compressed to the minimum value allowed by the process, thereby improving the material utilization rate of the circuit board substrate.

[0025] In some embodiments, the target arrangement position of the device unit to be arranged is taken as a variable, and a geometric clipping boundary is taken as a constraint condition, a target arrangement position that maximizes the material utilization rate of the circuit board substrate is searched for in a target arrangement position interval, including: moving the device unit to be arranged according to a preset rotation angle and / or movement direction within the target arrangement position interval and under the constraint condition of the geometric clipping boundary to obtain a set of arrangement positions corresponding to the device unit to be arranged, wherein the set of arrangement positions includes a plurality of first arrangement positions; the material utilization rate of the device unit to be arranged at each first arrangement position is calculated respectively; at least one second arrangement position is determined from the plurality of first arrangement positions according to the material utilization rate, wherein the second arrangement position is an arrangement position with a material utilization rate greater than a preset material utilization rate threshold; the at least one second arrangement position is subjected to Gaussian mixture fitting to obtain an optimized set of arrangement positions; and a position search is performed in the optimized set of arrangement positions to obtain the target arrangement position of the device unit to be arranged on the circuit board substrate.

[0026] By sampling screening and intelligent search guided by a probability model, efficient approximation of a globally optimal arrangement position is realized, a more compact arrangement scheme is found under limited computing resources, and thus the material utilization rate of the circuit board substrate is improved.

[0027] In some embodiments, the position search is performed in the optimized set of arrangement positions to obtain the target arrangement position of the device unit to be arranged on the circuit board substrate, including: obtaining a probability density distribution function corresponding to the optimized set of arrangement positions; fusing the probability density distribution function with a Gaussian process as a surrogate model to obtain a weighted acquisition function; and performing iterative search on the arrangement positions in the optimized set of arrangement positions by using the weighted acquisition function to determine the target arrangement position of the device unit to be arranged on the circuit board substrate.

[0028] By efficient global optimization guided by a probability model, focusing and rapid convergence of an optimal arrangement position are realized, a more compact arrangement scheme is found under limited computing resources, and thus the material utilization rate of the circuit board substrate is improved.

[0029] In a second aspect, the present application further provides a circuit board layout device, including: an information acquisition module configured to acquire electrical constraint information of device units; a boundary determination module configured to determine geometric clipping boundaries of the device units according to the electrical constraint information, the geometric clipping boundaries being boundaries of regions allowed to be slotted in the device units; and a position determination module configured to determine arrangement positions of a plurality of device units on a circuit board substrate, taking the plurality of device units as arrangement objects, taking the geometric clipping boundaries as constraint conditions, and taking maximization of a material utilization rate of the circuit board substrate as an optimization target.

[0030] In a third aspect, the present application provides an electronic device, comprising a processor and a memory storing a program or instructions, wherein the processor executes the program or instructions to implement the circuit board layout method according to the first aspect.

[0031] In a fourth aspect, the present application provides a machine readable storage medium, wherein the machine readable storage medium stores computer program instructions, and the computer program instructions are executed by a processor to implement the circuit board layout method according to the first aspect.

[0032] In a fifth aspect, the present application provides a computer program product, wherein the instructions in the computer program product are executed by a processor of an electronic device to make the electronic device execute the circuit board layout method according to the first aspect.

[0033] The above description is only a summary of the technical solutions of the present application. In order to enable one skilled in the art to better understand the technical means of the present application and to implement the same according to the contents of the description, and in order to make the above and other purposes, characteristics and advantages of the present application more apparent and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0034] The features, advantages, and technical effects of the exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0035] Figure 1 A schematic diagram of an FPC unit according to an embodiment of the present application; Figure 2 A flowchart of a circuit board layout method according to an embodiment of the present application; Figure 3 A structural schematic diagram of an FPC circuit board substrate according to an embodiment of the present application; Figure 4 A flowchart of a method for determining a geometric clipping boundary according to an embodiment of the present application; Figure 5 A clipping boundary schematic diagram of a device unit according to an embodiment of the present application; Figure 6 A flowchart of a method for determining a geometric clipping boundary according to an embodiment of the present application; Figure 7 A flowchart of a method for determining a second boundary point according to an embodiment of the present application; Figure 8 A flowchart of a method for determining a second boundary point according to an embodiment of the present application; Figure 9 A flowchart of a method for determining a geometric clipping boundary according to an embodiment of the present application; Figure 10 A flowchart of a method for determining an arrangement position according to an embodiment of the present application; Figure 11 Flow chart of a domain search method of a search tree according to an embodiment of the present application; Figure 12 Flow chart of a method for determining a target arrangement position interval according to an embodiment of the present application; Figure 13 Flow chart of a method for determining a target arrangement position interval according to an embodiment of the present application; Figure 14 Flow chart of a method for determining a target arrangement position according to an embodiment of the present application; Figure 15 Flow chart of a method for determining a target arrangement position according to an embodiment of the present application; Figure 16 Flow chart of a method for determining a target arrangement position according to an embodiment of the present application; Figure 17 Flow chart of a method for determining a target arrangement position according to an embodiment of the present application; Figure 18 Schematic diagram of a fault data injection device according to another embodiment of the present application; Figure 19 Schematic diagram of an electronic device according to yet another embodiment of the present application.

[0036] In the drawings, the drawings are not necessarily drawn according to the actual proportions. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs; the terms used herein are only for the purpose of describing specific embodiments of the present application, and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.

[0039] In the description of the embodiments of the present application, the technical terms "first", "second" and the like are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality of" is more than two, unless otherwise explicitly and specifically limited.

[0040] In the embodiments of the present application, the phrase "embodiments" means that the specific features, structures or properties described in conjunction with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase at various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in the embodiments of the present application can be combined with other embodiments.

[0041] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0042] In the description of the embodiments of the present application, the term "a plurality of" refers to more than two (including two), and similarly, "a plurality of groups" refers to more than two groups (including two groups), and "a plurality of pieces" refers to more than two pieces (including two pieces).

[0043] In the description of the embodiments of the present application, the term "determine" can cover a variety of actions. For example, "determine" can include calculating, computing, processing, deriving, investigating, looking up (for example, looking up in a table, a database, or another data structure), ascertaining, and the like. In addition, "determine" can include receiving (for example, receiving information), accessing (for example, accessing data in a memory), and the like. In addition, "determine" can include resolving, selecting, choosing, establishing, and the like. The specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances by those of ordinary skill in the art.

[0044] Flexible Printed Circuit (FPC) has the advantages of lightness, thinness, bendability, etc., and is widely used in consumer electronics, automotive electronics, medical devices and other fields, especially in lithium power battery pack connection components.

[0045] The manufacturing process of FPC generally includes: the end customer completes the circuit design and outputs the Gerber file; the FPC board factory performs layout and slotting design; substrate cutting, lamination, gold plating, surface treatment; shipment to SMT (Surface Mounted Technology, surface mounting technology) production line to mount components. Layout and slotting design is the key link to determine the substrate utilization rate and manufacturing cost. After receiving the Gerber file, the FPC board factory needs to arrange dozens to hundreds of the same FPC units in two-dimensional geometry on a fixed size of copper clad plate, and plan the slotting position in each FPC unit to maximize material utilization and reduce mold cutting times.

[0046] Currently, the layout and slotting design of the FPC board factory still highly depends on the manual experience of the layout engineer, and the difference between the layout strategies of different engineers makes the standard deviation of material utilization rate as high as 15%-20%, causing material waste and imbalance between material utilization and cost control. Moreover, the manual layout method cannot provide real-time feedback on material utilization, and the layout engineer needs to repeatedly adjust the layout scheme, resulting in a long circuit design cycle, which is extended by more than 30% on average.

[0047] In addition, when the FPC board factory performs layout and slotting on the FPC unit, it usually only focuses on the compact arrangement of the geometric profile of the FPC unit, without considering the electrical wiring safety requirements of the FPC unit, such as the minimum line width, safety distance, and fan-shaped wiring area requirements inside the FPC unit, and without considering the geometric arrangement constraints of the FPC unit, such as the position of slotting in the FPC unit and mechanical strength. This way, the slotting position of the FPC unit invades the wiring channel, resulting in the failure of subsequent electrical verification of the FPC unit, which requires rework to modify the layout, increasing the iteration cycle of FPC layout, affecting the delivery cycle, and increasing the research and development cost.

[0048] In addition, the profile of the FPC unit is usually a non-regular polygon, for example, Figure 1 A schematic diagram of the FPC unit corresponding to the device unit to be cut is shown, which can be a mounted component generated after the FPC unit is subjected to substrate cutting, lamination, gold plating, surface treatment, etc. The device unit has an irregular shape, for example, in Figure 1 The device unit has a convex portion Q protruding relative to the reference line L. If a traditional brute force arrangement algorithm is used, the time complexity is as high as O(n²), which cannot be solved within a reasonable time; while heuristic algorithms are prone to local optimization and are difficult to stably approach the global highest utilization rate. Moreover, high-precision material utilization rate evaluation (e.g., determination of slotting position, avoidance of micro-hole area, etc.) has high computational cost, and the traditional layout method needs to be iterated multiple times, while the time consumed by a single design is relatively long, which cannot meet the demand for response timeliness of the production end.

[0049] In summary, how to realize the collaborative optimization of the layout of FPC units and the electrical routing space at the FPC manufacturing end, while taking into account the irregular pattern arrangement efficiency and the global optimization speed, has become a technical problem to be solved in the field.

[0050] To solve the problems in the prior art, the embodiments of the present application provide a circuit board layout method and device, electronic equipment, storage medium and product. In the embodiments of the present application, the mapping relationship between the electrical safety control of the device unit and the geometric cutting boundary is constructed, and the electrical constraints such as the wiring width and the safety distance between the wirings are converted into quantifiable geometric boundary conditions to solve the conflict between the electrical wiring safety and the geometric slotting optimization in FPC layout. In the embodiments of the present application, a mixed optimization strategy of center alignment, K-dimensional tree neighborhood search and bisection method criticality judgment is used to reduce the computational complexity and improve the real-time performance and stability of the device unit arrangement. In addition, in the embodiments of the present application, a multi-fidelity proxy model and a Bayesian optimization framework are introduced to solve the problems of high computational cost and low optimization efficiency of the traditional FPC material utilization rate evaluation method.

[0051] The following describes a circuit board layout method provided by the embodiments of the present application.

[0052] In some embodiments, Figure 2 A flowchart of a circuit board layout method is shown, which can be applied to an FPC layout system, which can include a computing device capable of arranging device units on an FPC substrate and displaying the material utilization rate of the arranged FPC substrate. As Figure 2 shown, the method can include the following steps S201 to S203: Step S201, obtaining electrical constraint information of the device unit.

[0053] In step S201, the device unit is an FPC unit that needs to be cut on the circuit board substrate of the FPC, and in the embodiments of the present application, the shape and size of the device unit cut on the same FPC circuit board substrate are the same.

[0054] In step S201, the electrical constraint information of the device unit is used to represent the safety requirement of wiring in the device unit, and the electrical constraint information can include but is not limited to the wiring direction of wiring in the device unit, the minimum line width of wiring, the safety distance, etc.

[0055] In step S201, the electrical constraint information of the device unit can be pre-set, meaning that the wiring information required for the safe operation of the device unit has been planned before cutting the device unit from the FPC circuit board substrate. Before laying out and cutting the circuit board substrate, the layout engineer can input the electrical constraint information of the device unit into the PFC layout system, so that the PFC layout system can lay out and cut the device unit on the FPC circuit board substrate according to the electrical constraint information.

[0056] It is worth noting that obtaining electrical constraint information through step S201 and constraining the layout and cutting of device units based on this electrical constraint information can improve the electrical safety of device units.

[0057] Step S202: Determine the geometric trimming boundary of the device unit based on the electrical constraint information.

[0058] In step S202, to improve material utilization, grooves need to be cut into the device units to minimize the spacing between irregularly shaped device units. The geometric cutting boundary of the device unit is the boundary of the area within the device unit where grooves are allowed. For example, as... Figure 3 The schematic diagram of the FPC circuit board substrate shown depicts four device units S arranged on the substrate. A slot is formed on the outline of device unit S2, and the connector of device unit S1 extends into the slot of device unit S2 (e.g., ...). Figure 3 (As shown in the dashed box in the figure), the boundary of the area in device unit S2 that can be slotted is the geometric cutting boundary.

[0059] In step S202, the geometric cutting boundary of the device unit is determined based on the electrical constraint information. The arrangement of multiple device units is then optimized based on the geometric cutting boundary to reduce the spacing between adjacent device units while meeting the electrical requirements of the device units, thereby improving the material utilization rate of the FPC circuit board substrate.

[0060] Step S203: Using multiple device units as the arrangement objects, geometric cutting boundaries as constraints, and maximizing the material utilization rate of the circuit board substrate as the optimization objective, determine the arrangement positions of multiple device units on the circuit board substrate.

[0061] In step S203, the FPC layout system can use a hybrid algorithm to arrange the device units on the FPC circuit board substrate to improve the material utilization rate of the FPC circuit board substrate. Among them, the FPC layout system can use the neighborhood search of K-dimensional tree to quickly determine the spatial station of each device unit on the FPC circuit board substrate, and then use the bisection method to accurately determine the critical distance between the two adjacent device units, and finally use the Bayesian optimization algorithm to improve the global optimization speed, so as to improve the efficiency of FPC layout. Further, after determining the arrangement position of the plurality of device units on the FPC circuit board substrate, as shown in Figure 3 , the device units can be cut based on the arrangement position.

[0062] Based on the above steps S201 to S203, it can be known that in the embodiments of the present application, the geometric cutting boundary of the device unit is determined according to the electrical constraint information of the device unit, so that when the device unit is arranged on the circuit board substrate, the device unit can be appropriately cut according to the demand, and then for the device unit with irregular shape, the arrangement distance between the device units can be reduced, and the material utilization rate of the circuit board substrate can be improved.

[0063] The specific implementation process of the method provided by the embodiments of the present application is introduced as follows.

[0064] In some embodiments, the determination of the geometric cutting boundary can use the method as shown in Figure 4 , which includes the following steps S401 to S402: Step S401, obtaining the point cloud coordinates of a plurality of point clouds on the device unit; Step S402, constructing a geometric cutting boundary according to the point cloud coordinates corresponding to the plurality of point clouds and the electrical constraint information.

[0065] In step S401, the design information of the device unit is usually provided by the end customer in a standardized electronic file format, for example, a Gerber file, which contains vector graphic data of the circuit layer, the solder mask layer and the outline layer. By analyzing the vector graphic data, the point cloud data of the device unit can be obtained, which includes the point cloud coordinates of each point cloud.

[0066] An exemplary Figure 5 cutting boundary diagram of the device unit is shown, in which Figure 5 the left side is the tail of the device unit, and the right side is the head of the device unit. The connectors are concentrated in the head, and the wires converge like a fan to the tail. Among them, the closer to the head, the more connectors pass through, and the greater the wiring demand; the closer to the tail, the fewer connectors pass through, and the smaller the wiring demand.

[0067] In step S402, the trimmable boundary includes a first trimmable boundary and a second trimmable boundary arranged oppositely, for example, in Figure 5 In the above embodiment, the first trimmable boundary can be an upper trimmable boundary L1, and the second trimmable boundary can be a lower trimmable boundary L2. The first trimmable boundary and the second trimmable boundary not only include the original contour of the device unit, but also include the slot contour of the slot dug in the device unit. For example, in Figure 5 In the above embodiment, L3 and L4 are the depths of the slots dug on the sides of L1 and L2 of the device unit, respectively.

[0068] After the point cloud coordinates of the point cloud are determined, the FPC layout system can determine the routing space requirement of the device unit by the number and position of the connectors from the tail to the head by using a bidirectional boundary propagation calculation method, realize reverse propagation calculation of the routing space requirement, and ensure the connectivity of the device unit and improve the material utilization rate of the FPC circuit board substrate.

[0069] By steps S401 to S402, the electrical constraints of the device unit are geometricized, which can reduce the uncertainty in the FPC circuit board substrate layout process, pre-resolve the conflict risk that needs to be verified subsequently into geometric constraints, reduce the number of FPC layout modifications, and improve the efficiency of FPC layout.

[0070] In some embodiments, the specific determination method of the geometric trimmable boundary can be as shown in Figure 6 The method includes steps S601 to S603 as follows: In step S601, in a case where the first point cloud is determined as a geometric mutation point according to the point cloud coordinates of the first point cloud, a first boundary point is determined according to the point cloud coordinates corresponding to the first point cloud; In step S602, in a case where the first point cloud is determined as a regular point according to the point cloud coordinates corresponding to the first point cloud, a second boundary point is determined according to the electrical constraint information and the point cloud coordinates of the first point cloud; In step S603, a geometric trimmable boundary is determined according to the region boundary formed by the first boundary point and the second boundary point.

[0071] In steps S601 to S603, the first point cloud is any one of the plurality of point clouds, and the geometric mutation point is a point cloud whose geometric attribute change value is greater than a change threshold value compared with adjacent point clouds, where the geometric attribute can include but is not limited to curvature, slope, height, deflection, etc. The change threshold value is determined by the geometric attribute change values corresponding to the plurality of point clouds, for example, the change threshold value can be the average of the geometric attribute change values corresponding to the plurality of point clouds. In the embodiments of the present application, the geometric mutation point includes an outer convex point or an inner concave point, and the outer convex point is a point cloud of a convex region in the device unit, for example, Figure 5P1 point in the outer convex point, wherein the outer convex point is a key part for subsequent nesting complementation with other device units, and excessive cutting will destroy the shape advantage, thus, in the embodiment of the present application, the outer convex point is a non-cuttable point cloud. The inner concave point is a point cloud of an inner concave region in the device unit, for example, Figure 5 P2 point in the inner concave point, wherein the inner concave point is a potential space for accommodating the protrusion of other devices (for example, a connector), and accurate reservation can improve the arrangement density, thus, in the embodiment of the present application, the inner concave point is also a non-cuttable point cloud. The regular point is a point cloud in the device unit outside the convex region and the inner concave region, for example, a point cloud in a region determined by L3 or L4 in Figure 5 the embodiment of the present application, both the convex region and the inner concave region are non-cuttable regions.

[0072] As can be seen from the above steps S601 to S603, through the fine classification processing of the point cloud of the device unit, the coordination between the electrical constraint and the geometric boundary of the device unit can be realized, so as to maximize the effective area of the FPC circuit board substrate that can be used for close arrangement and improve the material utilization rate of the FPC circuit board substrate under the premise of ensuring the manufacturability of the device unit.

[0073] In some embodiments, the second boundary point can be determined by the method as shown in Figure 7 , as shown in Figure 7 , the method comprises the following steps S701 to S703: Step S701, determining the number of wires according to the relative position relationship between the point cloud coordinates of the first point cloud and the connector position; Step S702, determining the wire demand width according to the wire width and the number of wires; Step S703, determining the second boundary point according to the wire demand width and the safety distance.

[0074] In steps S701 to S703, the electrical constraint information includes the connector position, the wire width and the preset safety distance.

[0075] In step S701, the FPC layout system can use the reverse accumulation method from the tail to the head to determine the number of wires, for example, traversing the point cloud from the tail to the head of the device unit, and adding the number of wires led out by the connector to the wire number count corresponding to all points after the current point every time a connector position is passed, so that the number of wires at the head of the device unit is larger, the width of the wire demand is also higher, and correspondingly, the cuttable region at the head of the device unit is smaller.

[0076] In step S702, if the wire width is small, even if the number of wires is large, the corresponding wiring demand width is small, and the corresponding cuttable area is large; if the wire width is large, even if the number of wires is small, the corresponding wiring demand width is small, and the corresponding cuttable area is large. As can be seen, the wiring demand width is affected by both the wire width and the number of wires, and therefore, in the embodiment of the present application, the FPC layout system can determine the wiring demand width according to the product of the wire width and the number of wires.

[0077] In step S703, after the wiring demand width and the safety distance are determined, the safety distance is used as a constraint to prevent interference between wires or damage caused by grooving, so that the cut device unit still meets the electrical specifications.

[0078] In steps S701 to S702, the wiring demand width is dynamically calculated point by point, which realizes fine adaptive cutting of the device unit. On the premise of ensuring electrical safety, the effective area of the FPC circuit board substrate that can be arranged is maximized, and the utilization rate of the substrate material is improved.

[0079] In some embodiments, the specific determination method of the second boundary point can be as shown in Figure 8 . Step S801: determining the second boundary point on the first cutting boundary according to the sum of the wiring demand width and the safety distance; Step S802: determining the second boundary point on the second cutting boundary according to the difference between the wiring demand width and the safety distance.

[0080] In the embodiment of the present application, a segmented function of decreasing wiring space is constructed to determine the demarcation point on the cutting boundary, according to the structure characteristic that the positive and negative electrodes of the FPC are distributed apart. The input parameters of the segmented function include: the point cloud coordinates , the coordinate value of the boundary point on the cutting boundary , the point cloud type ( = , indicating an outward convex point; = , indicating an inward concave point; = , indicating a regular point), the coordinates of the connector , the connector set K, the ( , indicating that the x coordinate of the point cloud is greater than the x coordinate of the connector; =0, indicating that the x coordinate of the point cloud is not greater than the x coordinate of the connector), the number of wires N corresponding to the connector, the wire width d corresponding to the connector, and the safety distance S required by the design.

[0081] For the first clipping boundary, its corresponding piecewise function is as follows: =1 For the second clipping boundary, its corresponding piecewise function is as follows: =1 In the above piecewise function, represents the trace demand width; is the x coordinate of the i-th point cloud, is the y coordinate of the i-th point cloud.

[0082] In the above steps S801 to S802, by differentially applying the sum of the trace demand width and the safety distance, and the difference between the trace demand width and the safety distance, non-uniform and adaptive clipping of the device unit is realized, thereby maximizing the effective area of the FPC circuit board substrate for arranging the device unit on the basis of ensuring electrical safety, and improving the utilization rate of the substrate material.

[0083] In some embodiments, after the first boundary point and the second boundary point are determined, the FPC layout system can determine the clipping boundary (i.e., the geometric clipping boundary) of the FPC circuit board substrate based on the first boundary point and the second boundary point, as shown in Figure 9 The process includes the following steps S901 to S903: Step S901, obtaining a first boundary point sequence composed of the first boundary points and a second boundary point sequence composed of the second boundary points; Step S902, fitting the first boundary point sequence and the second boundary point sequence to generate a region boundary line; Step S903, determining the geometric clipping boundary according to the region boundary line.

[0084] In step S901, the first boundary points are the point clouds of the non-trimmed region in the device unit, and the second boundary points are the point clouds of the trimmed region in the device unit. In the embodiments of the present application, the first boundary point sequence not only contains all the point clouds that are prohibited from being trimmed in the device unit, but also reflects the relative position relationship between the point clouds. That is, in the embodiments of the present application, the point clouds can be sorted according to their positions on the device unit, and the first boundary point sequence can be obtained. The second boundary point sequence contains all the point clouds that can be trimmed in the device unit. Similarly, the second boundary point sequence also reflects the relative position relationship between the point clouds.

[0085] In steps S902 and S903, the FPC layout system can use an existing data fitting method to fit the boundary points in the first boundary point sequence and the second boundary point sequence, so as to obtain a region boundary line. The region boundary line is an envelope line that can fit the actual occupied space of the device unit. The envelope line is the geometric trimming boundary of the device unit.

[0086] In the above steps S901 to S903, the geometric trimming boundary is generated by sorting and fitting the boundary points, and then the device unit is trimmed based on the geometric trimming boundary, which can improve the material utilization rate of the arranged FPC circuit board substrate.

[0087] In some embodiments, after the geometric trimming boundary is determined, the FPC layout system determines the arrangement position of the plurality of device units on the circuit board substrate, taking the plurality of device units as the arrangement objects, taking the geometric trimming boundary as the constraint condition, and taking the maximization of the material utilization rate of the circuit board substrate as the optimization target. Specifically, the process can include steps S1001 to S1004 as shown in Figure 10 Step S1001, in the case where there are arranged device units on the circuit board substrate, taking the point cloud coordinates of the arranged device units as tree nodes to construct a search tree; Step S1002, performing neighborhood search on the search tree to determine the target arrangement position interval of the device unit to be arranged on the circuit board substrate; Step S1003, taking the arrangement position of the device unit to be arranged as a variable, taking the geometric trimming boundary as a constraint condition, searching for the target arrangement position that maximizes the material utilization rate of the circuit board substrate in the target arrangement position interval; Step S1004, determining the arrangement position of the device unit to be arranged on the circuit board substrate according to the target arrangement position.

[0088] ​In step S1001, a search tree is constructed with the point cloud coordinates of the arranged device units as tree nodes, which can be a K-dimensional tree (i.e., KDTREE). It is worth noting that in the conventional method, when detecting the collision relationship between the device units to be arranged and the arranged device units, the distance between the two device units usually needs to be calculated one by one, and the time complexity is (n is the number of arranged device units). When n is large, the calculation overhead also increases sharply, so that the algorithm must use rough heuristic rules, resulting in loose arrangement results. In the embodiment of the present application, KDTREE is used to search the collision relationship between two device units, which uses the neighbor search algorithm, so that the search complexity can be reduced to , which improves the accuracy of collision detection.

[0089] In step S1002, the search tree is used to quickly search for the arranged device units within the device units to be arranged, so that according to the occupation situation of these adjacent device units, one or more target arrangement position intervals that may have space can be deduced, thereby reducing the search interval of the arrangement position of the device units and improving the arrangement efficiency of the device units.

[0090] In step S1003, the arrangement position of the device unit to be arranged is taken as a continuous variable, and the geometric clipping boundary is taken as a collision constraint. In the target arrangement position interval determined in step S1002, the specific coordinates that maximize the material utilization rate are searched through a mathematical optimization method (for example, bisection method approximation, gradient descent, etc.).

[0091] In step S1003, the continuous variable optimization can accurately fill the device unit to be arranged into the deepest part of the available space until the limit allowed by the geometric clipping boundary. This way makes the gap between the device units compressed to the minimum value allowed by the process, thereby maximizing the number of device units per unit area of the FPC circuit board substrate and improving the material utilization rate of the FPC circuit board substrate.

[0092] In step S1004, after the target arrangement position is determined, the device unit to be arranged is arranged at the target arrangement position on the FPC circuit board substrate, and the next iteration is triggered. Through successive iterations, the device unit arrangement on the entire FPC circuit board substrate can gradually approach the global optimum.

[0093] In the above steps S1001 to S1004, by constructing a space index, neighborhood search and local fine optimization arrangement framework, the complex global arrangement problem is decomposed into local optimization sub-problems that can be efficiently solved, which greatly improves the arrangement density under the premise of ensuring the solution quality, thereby directly improving the material utilization rate of the circuit board substrate.

[0094] In some embodiments, the domain search process of the search tree can be as shown in Figure 11 The process includes the following steps S1101 to S1102: Step S1101, taking the centroid of the device unit to be arranged as the center, and taking the region determined by the size of the device unit to be arranged as the search range, performing neighborhood search on the search tree to determine the conflict device units whose point cloud coordinates are located in the search range, and obtaining a conflict device set; Step S1102, determining the target arrangement position interval of the device unit to be arranged on the circuit board substrate according to the relative position between the conflict device unit and the initial arrangement position of the device unit to be arranged on the circuit board substrate.

[0095] In step S1101, taking the centroid of the device unit to be arranged as the center, and dynamically determining the search range by the maximum circumscribed rectangle of the device unit to be arranged, performing neighborhood search on the constructed KDTREE to find all arranged device units whose point cloud coordinates fall within the search range, thereby forming a conflict device set.

[0096] Notably, in step S1101, the search range is dynamically bound with the size of the device unit to be arranged, which can make all adjacent units that are likely to have position conflicts with the device unit to be arranged be included in the conflict device set, thereby reducing the missed detection rate of conflict device units.

[0097] In step S1102, the target arrangement position interval of the device unit to be arranged is determined through geometric reasoning according to the relative position relationship (e.g., azimuth angle, distance, overlap degree, etc.) between the conflict device unit and the device unit to be arranged on the circuit board substrate. For example, if there is a conflict device unit A on the left side of the device unit to be arranged and a conflict device unit B on the right side, it can be inferred that the device unit to be arranged can only move left and right within the gap between the conflict device unit A and the conflict device unit B; if there is a conflict device unit C above the device unit to be arranged, it can be inferred that the device unit to be arranged may need to find a sinking space below the conflict device unit C.

[0098] Steps S1101 and S1102 realize accurate delineation of the available space of the device unit to be arranged through adaptive range conflict detection and interval positioning based on conflict geometric relationship, provide a high-quality initial solution interval for subsequent high-density embedding, and thus directly improve the substrate material utilization rate.

[0099] In some embodiments, the target arrangement position interval can be determined using Figure 12 as shown in steps S1201 to S1202: Step S1201: Determine the initial layout position range based on the relative positions between the conflicting device unit and the device unit to be arranged; Step S1202: Based on the interval length corresponding to the initial arrangement position interval, iteratively update the initial arrangement position interval until the interval length corresponding to the initial arrangement position interval is within the target length range, and obtain the target arrangement position interval.

[0100] In step S1201, the FPC layout system initially determines a continuous interval where there may be available space based on the geometric relationship between the conflicting device unit and the device unit to be arranged, and determines the position of the device unit to be arranged within the continuous interval.

[0101] In step S1202, the lower limit of the target length range is a first length threshold, and the upper limit of the target length range is a second length threshold. The target layout position interval includes the upper limit and lower limit of the layout position. In this step, the FPC layout system uses the interval length as a criterion and repeatedly narrows the search interval using methods such as bisection, golden section, and direct trial and error until the interval length falls within the preset target length range. If the interval length is too long, i.e., the interval length is greater than the upper limit of the target length range, it will lead to computational waste and slow convergence speed; if the interval length is too short, i.e., the interval length is less than the lower limit of the target length range, the positioning accuracy may be insufficient and cannot meet the manufacturing accuracy of the device unit. In this embodiment, limiting the interval length to the target length range can not only reduce computational waste and ensure convergence speed, but also ensure positioning accuracy and meet the manufacturing accuracy of the device unit.

[0102] Steps S1201 and S1202 approach the critical position through interval iterative shrinkage, achieving high-precision positioning of the available space for the device units to be arranged. This allows the device units to be placed at the limit position where they do not interfere with other device units and the gap is compressed to the minimum value allowed by the process, thereby improving the utilization rate of the circuit board substrate material.

[0103] In some embodiments, the FPC typesetting system can determine the target layout position range through a bisection iterative approximation method, such as... Figure 13 As shown, the process includes the following steps S1301 to S1303: Step S1301: Determine the midpoint of the initial layout position interval based on the upper limit and lower limit of the layout position. Step S1302: If the interval length is less than the first length threshold, update the upper limit of the arrangement position based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, and obtain the target arrangement position interval. Step S1303: If the interval length is greater than the second length threshold, update the lower limit of the arrangement position based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, and obtain the target arrangement position interval.

[0104] In step S1301, the midpoint of the current arrangement position interval is taken as the candidate position for this iteration. The midpoint is a representative position within the initial arrangement position interval. By detecting whether the midpoint collides with the already arranged device unit, the bias of the feasible region is quickly determined.

[0105] In steps S1302 to S1303, based on the comparison between the interval length of the initial arrangement position interval and the preset length thresholds (i.e., the first length threshold and the second length threshold), it is determined how to update the interval boundary of the initial arrangement position interval until the interval length falls within the target length range.

[0106] When the interval length is less than the first length threshold, it means that the initial layout position interval is already fine enough, but may not have reached the critical point. At this time, the upper limit value of the layout position is updated based on the midpoint position. For example, the upper limit value of the layout position is adjusted to the midpoint position to further move closer to the critical direction, ensuring that the final target layout position interval meets the accuracy requirements and includes the critical point.

[0107] When the interval length is greater than the second length threshold, it means that the initial layout position interval is too large and needs to be further narrowed. At this time, the lower limit of the layout position is updated based on the midpoint position. For example, the lower limit of the layout position is adjusted to the midpoint position to gradually reduce the range.

[0108] Steps S1301 to S1303 use a binary search method to iteratively approximate the critical position, achieving high-precision positioning of the available space for the device units to be arranged, thereby compressing the gap between device units to the minimum value allowed by the process and improving the material utilization rate of the circuit board substrate.

[0109] For example, Figure 14 A flowchart illustrating the determination of the target layout position of the device units to be arranged is shown, such as... Figure 14 As shown, the process includes the following steps S1401 to S1409: Step S1401: The FPC layout system acquires the point cloud data of the device cells; In step S1402, the FPC layout system sets the initial parameters required for the operation of each algorithm, including but not limited to electrical constraint parameters (e.g., wire width, safety distance, connector position, number of wires, etc.), process parameters (e.g., minimum manufacturing spacing, substrate size, etc.), and algorithm control parameters (e.g., first length threshold, second length threshold, maximum number of iterations, etc.). Step S1403: Invoke the wiring trimming design algorithm to map the electrical constraint information to the geometric trimming boundary; Step S1404: Determine the relative position of the cutting boundary in the device cell based on the geometric cutting boundary; Step S1405: Collision detection is performed using a combination of KDTREE and bisection methods, with the upper and lower clipping boundaries as constraints. Step S1406: After collision detection at the candidate arrangement position, the outline containing the candidate arrangement position and the already arranged device unit is determined as the critical polygon boundary of the current iteration. Step S1407: Perform bounding box calculation based on the critical polygon boundary to obtain the substrate area occupied by the device unit under the current arrangement scheme. Step S1408: Determine the area utilization rate of the circuit board substrate based on the ratio of the substrate area to the total area of ​​the circuit board substrate. Step S1409: Determine whether the current layout scheme needs to be retained based on the area utilization rate. For example, if the area utilization rate is greater than the preset utilization rate threshold, arrange the device units to be arranged on the circuit board substrate according to the current layout scheme.

[0110] In some embodiments, after determining the geometric trimming boundary and the target layout position range, the FPC layout system uses the layout position of the device units to be arranged as a variable and the geometric trimming boundary as a constraint to search for the target layout position within the target layout position range that maximizes the material utilization of the circuit board substrate. Specifically, such as... Figure 15 As shown, the process includes the following steps S1501 to S1505: Step S1501: Within the target arrangement position range, using the geometric cutting boundary as a constraint, move the device unit to be arranged according to the preset rotation angle and / or movement direction to obtain the arrangement position set corresponding to the device unit to be arranged. Step S1502: Calculate the material utilization rate of the device unit to be arranged at each first arrangement position; Step S1503: Determine at least one second arrangement position from multiple initial arrangement positions based on material utilization rate; Step S1504: Perform Gaussian mixture fitting on at least one second arrangement position to obtain the optimized arrangement position set; Step S1505: Perform a position search in the optimized layout position set to obtain the target layout position of the device unit to be arranged on the circuit board substrate.

[0111] In step S1501, the arrangement position set includes a plurality of first arrangement positions. Within the target arrangement position interval, the first arrangement positions are generated by moving the device unit to be arranged according to a preset rotation angle and / or movement direction, with the geometric clipping boundary as a constraint. Compared with the traditional single-point search (for example, gradient descent), the diversity of rotation and movement is introduced to realize the exploration of multiple possible poses of the target arrangement position interval, cover a wider solution space, provide rich candidate samples for subsequent screening, and increase the opportunity to find a high-usage arrangement.

[0112] In step S1502, the material utilization of the device unit to be arranged at each first arrangement position is calculated, that is, the area utilization of the overall substrate after the current unit is placed, to provide a quantitative basis for subsequent screening and to retain arrangement schemes with higher utilization.

[0113] In step S1503, the second arrangement position is an arrangement position with a material utilization greater than a preset material utilization threshold. According to the material utilization, the second arrangement position with a utilization greater than a preset threshold (such as 80% of the historical optimal value) is selected from the plurality of first arrangement positions. Through threshold screening, a large number of low-quality candidate points are eliminated, and the computing resources are concentrated in the potential area.

[0114] In step S1504, the selected second arrangement position is fitted with a Gaussian mixture model to obtain a plurality of Gaussian distributions, each distribution corresponding to a high-potential sub-region, and an optimized arrangement position set is formed.

[0115] In step S1505, a fine search (such as local optimization or bisection approximation) is performed in the optimized position set (i.e., the region with high probability density) generated by the Gaussian mixture model, and the target arrangement position of the device unit to be arranged is finally determined.

[0116] Steps S1501 to S1505 realize efficient approximation of the global optimal arrangement position through sampling screening and intelligent search guided by a probability model, find a more compact arrangement scheme under limited computing resources, and thus improve the material utilization of the circuit board substrate.

[0117] It should be noted that in a complex, non-convex design space, the optimal solution is usually not a single isolated point, but is distributed in some high-potential sub-regions. The default assumption (such as the output obeying a Gaussian distribution) of the traditional Bayesian optimization is difficult to describe such a complex multimodal structure. Based on this, in the embodiments of the present application, a Bayesian optimization and Gaussian fitting framework is used to improve the search speed of the target arrangement position.

[0118] In some embodiments, Figure 16A search process of the target arrangement position based on a Bayesian optimization and a Gaussian fitting framework is shown, and the process includes the following steps S1601 to S1603. In step S1601, a probability density distribution function corresponding to the optimized arrangement position set is obtained. In step S1602, the probability density distribution function is fused with a Gaussian process to obtain a weighted acquisition function, with the Gaussian process as a surrogate model. In step S1603, the arrangement positions in the optimized arrangement position set are iteratively searched through the weighted acquisition function, and the target arrangement position of the device unit to be arranged on the circuit board substrate is determined.

[0119] In step S1601, the sample points with the top K% (K=10-20) performance are selected, and the positions of the sample points in the design space are regarded as a data point set. Then, the probability density is estimated by using the following formula: In the above formula, is the probability density estimation value; K is the number of Gaussian components, is the mixing weight, =1; is the mean vector; is the covariance matrix.

[0120] In step S1602, a Gaussian process (GP) is used as a surrogate model to simulate the unknown mapping relationship between the arrangement position and the material utilization rate. The probability density distribution function is fused with the Gaussian process to obtain a weighted acquisition function.

[0121] In step S1603, the optimized arrangement position set (i.e., the region with high probability density) is iteratively searched through the weighted acquisition function. In each iteration, the position that maximizes the weighted acquisition function is selected as the next evaluation point. High-precision utilization rate calculation (or actual collision detection) is performed at the position. The new result is added to the observation data set, and the Gaussian process model is updated. The process is repeated until convergence or the maximum number of iterations is reached, and finally the target arrangement position is determined.

[0122] It should be noted that in the embodiments of the present application, the Gaussian fitting can automatically discover and model multiple potential high-performance regions in the design space (each Gaussian component represents a region). The distribution fitted in this way naturally presents right bias or multimodal characteristics, that is, most of the high-performance samples are concentrated in several specific regions, rather than uniform or normal distribution. This provides strong, data-driven prior knowledge for subsequent Bayesian optimization, making the search more directional.

[0123] The efficient global optimization guided by the probability model in steps S1601 to S1603 realizes focusing and fast convergence of the optimal arrangement position, finds a more compact arrangement scheme under limited computing resources, and thus improves the material utilization rate of the circuit board substrate.

[0124] Exemplarily, Figure 17 A flowchart for determining a target arrangement position of a device unit to be arranged is shown as Figure 17 As shown, the process includes the following steps S1701 to S1710: In step S1701, the FPC layout system acquires point cloud data of the device unit. In step S1702, the FPC layout system determines the number of sample points in the initial sampling stage according to the problem dimension (for example, position coordinates, rotation angle). In step S1703, Latin hypercube sampling method and the number of sample points are used for uniform sampling. In step S1704, the top K% of the current evaluated sample points with higher utilization rate are fitted by Gaussian mixture model to obtain multiple Gaussian distributions. In step S1705, the artificial experience of the domain expert (for example, the device unit is preferentially arranged at the edge of the substrate, and the connector side faces the open area) is converted into deterministic or probabilistic prior samples, and injected into the observation point set. In step S1706, a proxy model is constructed using all the current observation points and their true utilization rate values. In step S1707, a weighted acquisition function is constructed according to the proxy model and prior knowledge. In step S1708, the weighted acquisition function is solved by an optimization algorithm (for example, a multi-start local search algorithm) to obtain the next arrangement position (i.e., the next sample point) that needs to be evaluated in reality. In step S1709, the next sample point and its true utilization rate value are added to the historical observation data set. In step S1710, the updated observation point set is used to retrain the Gaussian process proxy model, update the predicted mean and uncertainty, and terminate until the termination condition is met, for example, the number of iterations reaches a preset iteration threshold, the maximum value of the acquisition function is lower than a preset threshold, the utilization rate improvement amplitude is less than a tolerance value for multiple times, etc.

[0125] Thus far, the explanation and description of the method provided by the embodiments of the present application are completed.

[0126] It can be known from the above that, in view of the problems of low material utilization rate, insufficient design efficiency, and high optimization cost in the related art flexible circuit board layout, an embodiment of the present application proposes an intelligent layout method based on multi-constraint collaborative optimization. The method solves the complex conflict and calculation bottleneck in irregular polygon device arrangement by fusing electrical constraint modeling, geometric topology analysis, and efficient optimization algorithm, and improves the material utilization rate of the FPC circuit board substrate.

[0127] In the embodiment of the present application, a hybrid optimization strategy of center alignment, KDTREE neighborhood search, and dichotomy criticality determination is adopted. The centroid coordinate normalization reduces the search dimension of the rotation angle; secondly, the K-dimensional tree index structure is constructed to realize the fast search of the device unit neighborhood; finally, the dichotomy is used to iteratively search the conflict area, and the area overlap rate is used to determine the arrangement critical state. The method reduces the traditional brute force O(n2) calculation complexity to O(n log n), significantly improving the real-time performance and stability of large-scale device arrangement.

[0128] To solve the problems of high calculation cost and low optimization efficiency of the traditional evaluation method, in the embodiment of the present application, a multi-fidelity proxy model and a Bayesian optimization framework are also introduced to improve the execution efficiency of the layout algorithm.

[0129] It should be understood that, although each step in the flowchart involved in each embodiment as described above is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps.

[0130] In one embodiment, Figure 18 A schematic diagram of a circuit board layout device is shown, which is Figure 18 It can be known that the device 1800 includes an information acquisition module 1801, a boundary determination module 1802, and a position determination module 1803.

[0131] The information acquisition module 1801 is configured to acquire electrical constraint information of the device unit; The boundary determination module 1802 is configured to determine a geometric clipping boundary of the device unit according to the electrical constraint information, the geometric clipping boundary being a boundary of an area allowed to be slotted in the device unit; The position determination module 1803 is configured to determine the arrangement positions of the plurality of device units on the circuit board substrate, with the plurality of device units as arrangement objects, with the geometric clipping boundary as a constraint condition, and with the material utilization rate of the circuit board substrate being maximized as an optimization target.

[0132] In some embodiments, the boundary determination module comprises a point cloud acquisition module and a first boundary determination module. The point cloud acquisition module is configured to acquire point cloud coordinates of a plurality of point clouds on the device unit. The first boundary determination module is configured to construct the geometric clipping boundary according to the point cloud coordinates of the plurality of point clouds and the electrical constraint information.

[0133] In some embodiments, the first boundary determination module comprises a first determination module, a second determination module, and a third determination module. The first determination module is configured to determine a first boundary point according to the point cloud coordinates of a first point cloud, in a case where the first point cloud is determined to be a geometric mutation point according to the point cloud coordinates of the first point cloud. The first point cloud is any one of the plurality of point clouds. The geometric mutation point is a point cloud with a geometric attribute change value greater than a change threshold value compared to adjacent point clouds. The change threshold value is determined by the geometric attribute change values of the plurality of point clouds. The second determination module is configured to determine a second boundary point according to the electrical constraint information and the point cloud coordinates of the first point cloud, in a case where the first point cloud is determined to be a regular point according to the point cloud coordinates of the first point cloud. The third determination module is configured to determine the geometric clipping boundary according to a region boundary formed by the first boundary point and the second boundary point.

[0134] In some embodiments, the electrical constraint information comprises a connector position, a wire width, and a preset safety distance. The second determination module comprises a quantity determination module and a fourth determination module. The quantity determination module is configured to determine the number of wires according to the relative positional relationship between the point cloud coordinates of the first point cloud and the connector position. The fourth determination module is configured to determine a wire routing requirement width according to the wire width and the number of wires, and to determine the second boundary point according to the wire routing requirement width and the safety distance.

[0135] In some embodiments, the geometric clipping boundary comprises a first clipping boundary and a second clipping boundary arranged oppositely. The fourth determination module is specifically configured to determine the second boundary point on the first clipping boundary according to the sum of the wire routing requirement width and the safety distance, and to determine the second boundary point on the second clipping boundary according to the difference between the wire routing requirement width and the safety distance.

[0136] In some embodiments, the position determining module comprises a tree construction module, an interval determining module, a position searching module, and a first position determining module. The tree construction module is configured to, in the case that there are arranged device units on the circuit board substrate, construct a search tree with point cloud coordinates of the arranged device units as tree nodes. The interval determining module is configured to perform neighborhood search on the search tree to determine a target arrangement position interval of the device unit to be arranged on the circuit board substrate. The position searching module is configured to search for a target arrangement position that maximizes material utilization of the circuit board substrate in the target arrangement position interval, with the arrangement position of the device unit to be arranged as a variable and with a geometric clipping boundary as a constraint condition. The first position determining module is configured to determine the arrangement position of the device unit to be arranged on the circuit board substrate according to the target arrangement position.

[0137] In some embodiments, the interval determining module comprises a neighborhood search module and a first interval determining module. The neighborhood search module is configured to perform neighborhood search on the search tree with the centroid of the device unit to be arranged as the center and with a region determined by the size of the device unit to be arranged as a search range, to determine conflict device units whose point cloud coordinates are within the search range, and to obtain a conflict device set. The first interval determining module is configured to determine the target arrangement position interval of the device unit to be arranged on the circuit board substrate according to the relative positions between the conflict device units and the initial arrangement position of the device unit to be arranged on the circuit board substrate.

[0138] In some embodiments, the third determining module is specifically configured to obtain a first boundary point sequence composed of the first boundary points and a second boundary point sequence composed of the second boundary points; fit the first boundary point sequence and the second boundary point sequence to generate a region boundary line; and determine the geometric clipping boundary according to the region boundary line.

[0139] In some embodiments, the first interval determining module comprises a second interval determining module and a third interval determining module. The second interval determining module is configured to determine the initial arrangement position interval according to the relative positions between the conflict device units and the device unit to be arranged. The third interval determining module is configured to iteratively update the initial arrangement position interval according to an interval length corresponding to the initial arrangement position interval until the interval length corresponding to the initial arrangement position interval is within a target length range, to obtain the target arrangement position interval, wherein a lower limit value of the target length range is a first length threshold and an upper limit value of the target length range is a second length threshold.

[0140] In some embodiments, the target arrangement position interval includes an arrangement position upper limit value and an arrangement position lower limit value, and the third interval determination module is specifically configured to determine a midpoint position of the initial arrangement position interval according to the arrangement position upper limit value and the arrangement position lower limit value; in a case where the interval length is less than the first length threshold, the arrangement position upper limit value is updated based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, to obtain the target arrangement position interval; in a case where the interval length is greater than the second length threshold, the arrangement position lower limit value is updated based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, to obtain the target arrangement position interval.

[0141] In some embodiments, the position search module includes a set determination module, a utilization calculation module, a second position determination module, a set optimization module, and a third position determination module. The set determination module is configured to move the device unit to be arranged according to a preset rotation angle and / or movement direction, with a geometric clipping boundary as a constraint condition, to obtain an arrangement position set corresponding to the device unit to be arranged, wherein the arrangement position set includes a plurality of first arrangement positions. The utilization calculation module is configured to calculate the material utilization of the device unit to be arranged at each first arrangement position. The second position determination module is configured to determine at least one second arrangement position from the plurality of initial arrangement position sets according to the material utilization, wherein the second arrangement position is an arrangement position with a material utilization greater than a preset material utilization threshold. The set optimization module is configured to perform Gaussian mixture fitting on the at least one second arrangement position to obtain an optimized arrangement position set. The third position determination module is configured to perform position search in the optimized arrangement position set to obtain the target arrangement position of the device unit to be arranged on the circuit board substrate.

[0142] In some embodiments, the third position determination module is specifically configured to obtain a probability density distribution function corresponding to the optimized arrangement position set, fuse the probability density distribution function with a Gaussian process as a proxy model to obtain a weighted acquisition function, and perform iterative search on the arrangement positions in the optimized arrangement position set through the weighted acquisition function to determine the target arrangement position of the device unit to be arranged on the circuit board substrate.

[0143] Figure 19 A structural schematic diagram of an electronic device according to an embodiment of the present application is shown.

[0144] As shown in Figure 19 , the electronic device can implement an exemplary hardware architecture of the electronic device according to the circuit board layout method in the embodiments of the present application.

[0145] The electronic device can include a processor 1901 and a memory 1902 storing computer program instructions.

[0146] In particular, the processor 1901 described above can include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement one or more embodiments of the present application.

[0147] The memory 1902 can include a mass storage for data or instructions. By way of example and not limitation, the memory 1902 can include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a Universal Serial Bus (USB) drive or a combination of two or more of these. The memory 1902 can include removable or non-removable (or fixed) media, where appropriate. The memory 1902 can be internal or external to the integrated gateway disaster recovery device, as appropriate. In particular embodiments, the memory 1902 is non-volatile, solid-state memory. In particular embodiments, the memory 1902 can include read-only memory (ROM), random-access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory device, electrical, optical, or other physical / tangible memory storage device. Accordingly, in one or more particular embodiments, the memory 1902 includes one or more tangible (non-transitory) computer-readable storage media specifically configured to store software, wherein the software is operable when executed to carry out operations described with reference to the circuit board layout method according to the present application.

[0148] The processor 1901 implements the circuit board layout method in the above-described embodiments by reading and executing the computer program instructions stored in the memory 1902.

[0149] In one example, the electronic device can further include a communication interface 1903 and a bus 1904. As shown, the processor 1901, the memory 1902, and the communication interface 1903 are connected through the bus 1904 and complete communication with each other. Figure 19

[0150] The communication interface 1903 is mainly used to realize the communication between the modules, devices, units and / or equipment in the embodiments of the present application.

[0151] ​Bus 1904 includes a hardware, software, or both that couples components of electronic device to each other. As an example and not by way of limitation, bus can include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand (IB) interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or another suitable bus or a combination of two or more of these. Where appropriate, bus 1904 can include one or more buses. Although this application describes and shows a particular bus, this application contemplates any suitable bus or interconnect.

[0152] In one embodiment, the application further provides a machine readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the above-described circuit board layout method.

[0153] In one embodiment, the application further provides a computer program product, instructions in the computer program product, when executed by a processor of an electronic device, cause the electronic device to perform the above-described circuit board layout method.

[0154] It is important to note that the application is not limited to the specific configurations and processes described above and illustrated in the drawings. Detailed descriptions of known methods are omitted for the sake of brevity. In the above-described embodiments, several specific steps are described and shown as examples. However, the method processes of the application are not limited to the specific steps described and shown, and one skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the application.

[0155] The functions indicated in the structural block diagram above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, and the like. When implemented in software, the elements of the present application are program or code segments that are used to perform the required tasks. The program or code segments can be stored in a machine-readable medium, or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. The "machine-readable medium" can include any medium that can store or transfer information. Examples of the machine-readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable ROM (EROM), a floppy diskette, a CD-ROM, an optical disk, a hard disk, a fiber optic medium, a radio frequency (RF) link, and the like. The code segments can be downloaded via a computer network, such as the Internet, an intranet, and the like.

[0156] It is also noted that the exemplary embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiments, or in an order different from the embodiments, or several steps can be performed simultaneously.

[0157] The above describes aspects of the present application with reference to flowcharts and / or block diagrams of a circuit board layout method, device, electronic equipment, storage medium and product according to embodiments of the present application. It should be understood that each block in the flowchart and / or block diagram, and the combination of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus enable the implementation of the functions / acts specified in one or more blocks of the flowchart and / or block diagram. The processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It should also be understood that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can also be implemented by special-purpose hardware to perform the specified functions or acts, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0158] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some or all of the technical features can be replaced equivalently. These modifications or replacements do not change the essence of the corresponding technical solutions, which should be covered in the scope of the present application. In particular, the technical features mentioned in each embodiment can be combined in any way as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method of routing a circuit board, characterized by, The method comprises the following steps: obtaining electrical constraint information of a device unit; determining a geometric clipping boundary of the device unit according to the electrical constraint information, the geometric clipping boundary being a boundary of an area in the device unit that is allowed to be slotted; determining arrangement positions of a plurality of device units on a circuit board substrate, taking the geometric clipping boundary as a constraint condition and maximizing material utilization of the circuit board substrate as an optimization target.

2. The method of claim 1, wherein, The method of determining the geometric clipping boundary of the device unit according to the electrical constraint information comprises the following steps: obtaining point cloud coordinates of a plurality of point clouds on the device unit; constructing the geometric clipping boundary according to the point cloud coordinates corresponding to the plurality of point clouds and the electrical constraint information.

3. The method of claim 2, wherein, The method of constructing the geometric clipping boundary according to the point cloud coordinates corresponding to the plurality of point clouds and the electrical constraint information comprises the following steps: in a case where it is determined according to the point cloud coordinates of a first point cloud that the first point cloud is a geometric mutation point, determining a first boundary point according to the point cloud coordinates corresponding to the first point cloud, wherein the first point cloud is any one of the plurality of point clouds, the geometric mutation point is a point cloud whose geometric attribute change value is greater than a change threshold value compared with adjacent point clouds, and the change threshold value is determined by the geometric attribute change values corresponding to the plurality of point clouds; in a case where it is determined according to the point cloud coordinates of the first point cloud that the first point cloud is a regular point, determining a second boundary point according to the electrical constraint information and the point cloud coordinates of the first point cloud; determining the geometric clipping boundary according to the area boundary formed by the first boundary point and the second boundary point.

4. The method of claim 3, wherein, The electrical constraint information comprises connector positions, wire widths and a preset safety distance; the method of determining the second boundary point according to the electrical constraint information and the point cloud coordinates of the first point cloud comprises the following steps: determining the number of wires according to the relative positional relationship between the point cloud coordinates of the first point cloud and the connector positions; determining a wire routing requirement width according to the wire width and the number of wires; determining the second boundary point according to the wire routing requirement width and the safety distance.

5. The method of claim 4, wherein, The geometric clipping boundary comprises a first clipping boundary and a second clipping boundary arranged oppositely; the method of determining the second boundary point according to the wire routing requirement width and the safety distance comprises the following steps: determining the second boundary point on the first clipping boundary according to the sum of the wire routing requirement width and the safety distance; determining the second boundary point on the second clipping boundary according to the difference between the wire routing requirement width and the safety distance.

6. The method of claim 3, wherein, The method of determining the geometric clipping boundary according to the area boundary formed by the first boundary point and the second boundary point comprises the following steps: obtaining a first boundary point sequence composed of the first boundary point and a second boundary point sequence composed of the second boundary point; fitting the first boundary point sequence and the second boundary point sequence to generate an area boundary line; determining the geometric clipping boundary according to the area boundary line.

7. The method according to any one of claims 1 to 6, characterized in that, The arrangement position of the device unit on the circuit board substrate is determined by taking the plurality of device units as arrangement objects, taking the geometric clipping boundary as a constraint condition, and maximizing the material utilization rate of the circuit board substrate as an optimization target, and the method comprises the steps of: In the case that there are arranged device units on the circuit board substrate, taking the point cloud coordinates of the arranged device units as tree nodes, a search tree is constructed; The search tree is subjected to neighborhood search to determine the target arrangement position interval of the to-be-arranged device unit on the circuit board substrate; The arrangement position of the to-be-arranged device unit is taken as a variable, and the geometric clipping boundary is taken as a constraint condition, and the target arrangement position of the circuit board substrate that maximizes the material utilization rate is searched in the target arrangement position interval; The arrangement position of the to-be-arranged device unit on the circuit board substrate is determined according to the target arrangement position.

8. The method of claim 7, wherein, The search tree is subjected to neighborhood search to determine the target arrangement position interval of the to-be-arranged device unit on the circuit board substrate, and the method comprises the steps of: The centroid of the to-be-arranged device unit is taken as the center, and the region determined by the size of the to-be-arranged device unit is taken as the search range, the search tree is subjected to neighborhood search, the conflict device units whose point cloud coordinates are located in the search range are determined to obtain a conflict device set; According to the relative position between the conflict device units and the initial arrangement position of the to-be-arranged device unit on the circuit board substrate, the target arrangement position interval of the to-be-arranged device unit on the circuit board substrate is determined.

9. The method of claim 8, wherein, According to the relative position between the conflict device units and the initial arrangement position of the to-be-arranged device unit on the circuit board substrate, the target arrangement position interval of the to-be-arranged device unit on the circuit board substrate is determined, and the method comprises the steps of: According to the relative position between the conflict device units and the to-be-arranged device unit, an initial arrangement position interval is determined; According to the interval length corresponding to the initial arrangement position interval, the initial arrangement position interval is iteratively updated until the interval length corresponding to the initial arrangement position interval is within a target length range, and the target arrangement position interval is obtained, wherein the lower limit value of the target length range is a first length threshold, and the upper limit value of the target length range is a second length threshold.

10. The method of claim 9, wherein, The target arrangement position interval comprises an arrangement position upper limit value and an arrangement position lower limit value, and the initial arrangement position interval is iteratively updated according to the interval length corresponding to the initial arrangement position interval until the interval length corresponding to the initial arrangement position interval is within a target length range, and the target arrangement position interval is obtained, and the method comprises the steps of: The midpoint position of the initial arrangement position interval is determined according to the arrangement position upper limit value and the arrangement position lower limit value; In the case that the interval length is less than the first length threshold, the arrangement position upper limit value is updated based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, and the target arrangement position interval is obtained; In a case where the interval length is greater than the second length threshold, the lower limit value of the arrangement position is updated based on the midpoint position until the interval length corresponding to the initial arrangement position interval is within the target length range, to obtain the target arrangement position interval.

11. The method of claim 8, wherein, The searching, as the arrangement position of the device unit to be arranged is a variable and the geometric clipping boundary is a constraint condition, for a target arrangement position in the target arrangement position interval, includes: In the target arrangement position interval, moving the device unit to be arranged according to a preset rotation angle and / or movement direction, with the geometric clipping boundary as a constraint condition, to obtain an arrangement position set corresponding to the device unit to be arranged, wherein the arrangement position set includes a plurality of first arrangement positions; Calculating a material utilization rate of the device unit to be arranged at each first arrangement position; Determining at least one second arrangement position from a plurality of initial arrangement position sets according to the material utilization rate, wherein the second arrangement position is an arrangement position with a material utilization rate greater than a preset material utilization rate threshold; Performing Gaussian mixture fitting on at least one second arrangement position to obtain an optimized arrangement position set; Searching for a position in the optimized arrangement position set to obtain a target arrangement position of the device unit to be arranged on the circuit board substrate.

12. The method of claim 11, wherein, The searching for a position in the optimized arrangement position set to obtain a target arrangement position of the device unit to be arranged on the circuit board substrate includes: Obtaining a probability density distribution function corresponding to the optimized arrangement position set; Fusing the probability density distribution function and a Gaussian process as a proxy model to obtain a weighted acquisition function; Iteratively searching for an arrangement position in the optimized arrangement position set through the weighted acquisition function to determine a target arrangement position of the device unit to be arranged on the circuit board substrate.

13. A circuit board layout device, characterized by comprising: It includes: An information acquisition module configured to acquire electrical constraint information of a device unit; A boundary determination module configured to determine a geometric clipping boundary of the device unit according to the electrical constraint information, the geometric clipping boundary being a boundary of a region in the device unit that allows slotting; A position determination module configured to determine arrangement positions of a plurality of device units on a circuit board substrate, with the plurality of device units as arrangement objects, the geometric clipping boundary as a constraint condition, and maximization of material utilization rate of the circuit board substrate as an optimization target.

14. An electronic device, comprising: The device includes a processor and a memory storing program instructions; the processor executes the program instructions to implement the circuit board layout method of any one of claims 1 to 12.

15. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores program instructions, and the program instructions are executed by the processor to implement the circuit board layout method of any one of claims 1 to 12.

16. A computer program product, characterised in that, The instructions in the computer program product, when executed by a processor of an electronic device, cause the electronic device to perform the circuit board layout method as claimed in any one of claims 1 to 12.

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