Current regulative diode chip terminal structure, chip and manufacturing method thereof

Abstract

The invention discloses a current regulative diode chip terminal structure, a chip and a manufacturing method of the current regulative diode chip terminal structure, and belongs to the technical field of semiconductor power devices. The terminal structure is located at the edge of an N-silicon epitaxial layer and comprises a cell-terminal transition region and a terminal region. The transition region is provided with a P region, a P + region and an N + region in the P region, and a first polycrystalline silicon layer located on the surface passivation oxide layer, and the P region and the P + region and the N + region are connected through front metal. The terminal region is provided with a P region connected with the transition region, a P + region in the P region and a thicker field oxide layer; the front metal is connected with the P + region through a contact hole, and the metal is connected with the transition region metal. The invention further discloses a current regulative diode chip comprising the terminal structure and a manufacturing method of the current regulative diode chip. According to the scheme, smooth transition and effective modulation of the electric field are realized through optimized design of the transition region and the selectable terminal field plate in combination with accurate and controllable process parameters, and the breakdown voltage and reliability of the chip are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, specifically to a constant current diode chip terminal structure, chip, and its fabrication method. Background Technology

[0002] A constant current diode (CRD) is a semiconductor diode that outputs a constant current regardless of voltage changes within a certain voltage range. It is mainly used in LED lighting, semiconductor protection and biasing, reference current sources, battery charging, instrumentation and measurement, timing circuits and waveform generation, and other scenarios or fields.

[0003] Several solutions exist for achieving constant current in existing technologies. One solution uses a JFET (Jet Field-Effect Transistor) to achieve constant current. This method results in a simple diode manufacturing process and a constant current resistor with a positive temperature coefficient (TTC) characteristic, where the resistance increases with temperature. This allows for automatic current shunting and easier circuit protection. However, it suffers from weak current regulation under voltage fluctuations, large current fluctuations, and poor stability and consistency. Another solution is a Zener diode solution, which achieves constant current by stabilizing the voltage. Chips manufactured using this method have a constant current resistor with a negative temperature coefficient (TTC) characteristic, where the resistance decreases with temperature, resulting in higher current, increased heat generation, and even higher temperatures. This creates a positive temperature-current excitation, leading to poor circuit stability and reliability. Summary of the Invention

[0004] Technical problems to be solved The purpose of this invention is to overcome the shortcomings of the prior art and provide a constant current diode chip terminal structure, chip and its manufacturing method.

[0005] Technical solution To achieve the above objectives, the present invention provides the following technical solution: a constant current diode chip termination structure, disposed on one side of an N-silicon epitaxial layer on a heavily N+ doped silicon substrate, the termination structure comprising a cell-terminal transition region and a termination region; The cell-terminal transition region includes: The P-region is located within the N-silicon epitaxial layer; A surface passivated silicon oxide insulating dielectric film covering the N-silicon epitaxial layer; The first doped polycrystalline silicon layer is located on the surface passivated silicon oxide insulating dielectric film; An interlayer insulating dielectric film covering the first doped polycrystalline silicon layer; In addition, the front negative electrode metal penetrates the interlayer insulating dielectric film and the surface passivated silicon oxide insulating dielectric film through the first contact hole, and is electrically connected to the P+ region, N+ region and the first doped polysilicon layer in the P region. Optionally, the transition region may be partially replaced on the terminal region side with a field-silicon oxide insulating dielectric layer instead of the surface passivated silicon oxide insulating dielectric film. The terminal area includes: The P region located within the N-silicon epitaxial layer and connected to the transition region P region, and the P+ region connected to the P+ region within the transition region p region; A field oxide insulating dielectric film covering the N-silicon epitaxial layer has a thickness greater than that of the surface passivation silicon oxide insulating dielectric film. The front negative electrode metal covering the field silicon oxide insulating dielectric film and the interlayer insulating dielectric film is electrically connected to the P+ region in the terminal region P region through the second contact hole. The front negative electrode metal of the transition region is connected to the front negative electrode metal of the terminal region; A final passivation film formed of silicon oxide and silicon nitride is covered on the front negative electrode metal, and the back positive electrode metal is covered under the heavily N+ doped silicon substrate.

[0006] The terminal area mentioned above also includes: The second doped polycrystalline silicon field plate is located on the field oxide insulating dielectric film; The negative electrode metal on the front side of the terminal area is electrically connected to both the P+ region and the second doped polysilicon field plate through the second contact hole.

[0007] The resistivity of the N-silicon epitaxial layer is 0.1-20.0 Ω·cm, and the thickness is 2.0-60.0 μm.

[0008] The doping concentration of the P-region in the transition region and the terminal region mentioned above is 1E15-1E19 atoms / cm³, and the junction depth is 2.0-6.0 μm.

[0009] The P+ region has a doping concentration of 1E17-1E20 atoms / cm³ and a junction depth of 0.2-3.0 μm; the N+ region has a doping concentration of 1E18-1E22 atoms / cm³ and a junction depth of 0.1-2.0 μm.

[0010] A constant current diode chip, comprising: The aforementioned terminal structure; A constant current cell region connected to the transition region of the terminal structure includes a P region periodically arranged on the upper part of the N-silicon epitaxial layer, a P+ region and an N+ region located in each P region, a constant current N region located above the P region, and a doped polysilicon field plate located above the adjacent P region. The front negative electrode metal short-circuits the P+ region, the N+ region and the doped polysilicon field plate.

[0011] A method for fabricating a constant current diode chip termination structure, characterized by comprising the following steps: Provide an N+ doped silicon substrate and grow an N-silicon epitaxial layer on it with a resistivity of 0.1-20.0 Ω·cm and a thickness of 2.0-60.0 μm; Through the first ion implantation and propulsion, a P-region consisting of a cell region, a transition region, and a terminal region is formed within the N-silicon epitaxial layer. The doping concentration of the P-region is 1E15-1E19 atoms / cm³, and the junction depth is 2.0-6.0 μm. A constant-current N region is formed above the P region of the cell region and the transition region through a second ion implantation and propulsion. Through a third ion implantation and propulsion, P+ and N+ regions are formed in the P-regions of the cell region, transition region, and terminal region, respectively; wherein, the process is controlled so that the doping concentration of the P+ region is 1E17-1E20 atoms / cm³ and the junction depth is 0.2-3.0 μm, and the doping concentration of the N+ region is 1E18-1E22 atoms / cm³ and the junction depth is 0.1-2.0 μm; A surface passivated silicon oxide insulating dielectric film is grown on the N-silicon epitaxial layer, and a thicker field silicon oxide insulating dielectric film is grown in the region corresponding to the terminal region. A doped polysilicon layer is deposited and patterned to form a first doped polysilicon layer on the surface of the transition region, and optionally a second doped polysilicon field plate is formed on the field oxide of the terminal region. Deposit interlayer insulating dielectric film; The interlayer insulating dielectric film and the underlying silicon oxide layer are etched to form contact holes that expose the P+ region, N+ region, first doped polysilicon layer and optionally second doped polysilicon field plate, respectively. A front-side metal layer is deposited and patterned to form a front-side negative electrode metal, which fills the contact holes and electrically connects all exposed areas. A back positive electrode metal is formed on the back side of the heavily N+ doped silicon substrate.

[0012] The resistivity of the heavily N+ doped silicon substrate is 0.001-0.010 Ω·cm.

[0013] The doping concentration of the constant current N region is 1E14-1E18 atoms / cm³, and the junction depth is 0.1-2.0 μm.

[0014] A constant current device comprising the aforementioned constant current diode chip, Beneficial effects: Compared with existing technologies, the proposed constant current diode chip terminal structure, chip, and fabrication method have the following advantages: Superior terminal performance: By setting up a cell-terminal transition region with a specific structure and using a combination of thick field oxygen and optional polycrystalline silicon field plates in the terminal region, a smooth, step-like attenuation of the electric field from the active region to the chip edge is achieved, effectively suppressing electric field spikes and significantly improving the chip's avalanche breakdown voltage and long-term reliability.

[0015] High process integration and good consistency: The fabrication method proposed in this invention employs a set of integrated process steps and precisely controlled process parameters (such as doping concentration and junction depth in each region) to simultaneously form the cell region, transition region, and termination region. This not only simplifies the process but, more importantly, ensures a high degree of consistency in the doping profile and interface characteristics of different regions (especially on both sides of the transition region), thereby ensuring the continuity and predictability of electric field expansion, which is the foundation for achieving high-performance termination.

[0016] Flexible Design: The optional polycrystalline silicon field plate in the terminal area provides design flexibility. Basic field oxide terminals or enhanced field plate terminals can be selected based on the target withstand voltage level, optimizing performance and cost.

[0017] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0018] Figure 1 Formation of field-insulating silicon dioxide dielectric film under the first and second terminal structures Figure 2 The formation of the P-region and the constant current N-region under the first and second terminal structures Figure 3 The first terminal structure involves the formation of a passivated silicon oxide insulating dielectric film and doped polycrystalline silicon on the lower surface. Figure 4 The formation of P+ and N+ regions under the first terminal structure Figure 5 The formation of the interlayer insulating dielectric film and contact holes in the first type of terminal structure Figure 6 Formation of the front negative electrode metal under the first terminal structure Figure 7 The formation of the final passivation film and the back positive electrode metal under the first terminal structure Figure 8 The second type of terminal structure involves the formation of a passivated silicon oxide insulating dielectric film and doped polycrystalline silicon on the lower surface. Figure 9 The second type of terminal structure forms the P+ and N+ regions. Figure 10The formation of the interlayer insulating dielectric film and contact holes in the second type of terminal structure Figure 11 Formation of the front negative electrode metal under the second terminal structure Figure 12 The formation of the final passivation film and the back positive electrode metal under the second terminal structure Figure 13 Formation of field-insulating silicon dioxide dielectric film under the third and fourth terminal structures Figure 14 The third and fourth terminal structures form the P-region and the constant current N-region. Figure 15 The third type of terminal structure involves the formation of a passivated silicon oxide insulating dielectric film and doped polysilicon. Figure 16 The formation of P+ and N+ regions under the third terminal structure Figure 17 The formation of the interlayer insulating dielectric film and contact holes in the third type of terminal structure Figure 18 Formation of the front negative electrode metal under the third terminal structure Figure 19 The formation of the final passivation film and the back positive electrode metal under the third terminal structure Figure 20 The fourth type of terminal structure involves the formation of a passivated silicon oxide insulating dielectric film and doped polycrystalline silicon on the lower surface. Figure 21 The formation of P+ and N+ regions under the fourth terminal structure Figure 22 The formation of the interlayer insulating dielectric film and contact holes in the fourth type of terminal structure Figure 23 Formation of the front negative electrode metal under the fourth terminal structure Figure 24 The formation of the final passivation film and the back positive electrode metal under the fourth terminal structure Figure 25 The first type of terminal structure is a planar design (with a polycrystalline field plate terminal). Figure 26 The second type of terminal structure is a planar design (without a polycrystalline field plate terminal). Figure 27 The third type of terminal structure planar design (transition zone with field oxygen + polycrystalline field plate terminal) Figure 28 The fourth type of terminal structure is a planar design (with field oxygen in the transition zone + without polycrystalline field plate terminal). Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This invention provides a constant current diode chip fabricated on a heavily N+ doped silicon substrate 1. An N-silicon epitaxial layer 2 is formed on the substrate 1. The chip mainly includes three functional regions in the horizontal direction: a cell region for realizing constant current function, a cell-terminal transition region for electric field transition, and a termination region for withstanding high voltage.

[0021] Detailed description of cell-terminal transition region and terminal region structure The core improvement of this invention lies in the coordinated design of the transition area and the terminal area.

[0022] Within the cell-terminal transition region, a P-region 4 is formed in the N-silicon epitaxial layer 2, and this P-region 4 is connected to the structure at the end of the cell region. The P-region 4 contains a P+ region 9 and an N+ region 8. A surface passivated silicon oxide insulating dielectric film 6 covers the surface of the N-silicon epitaxial layer 2. A section of doped polysilicon 7 is formed on top of this dielectric film 6. An interlayer insulating dielectric film 10 covers the doped polysilicon 7. The front-side negative electrode metal 12 is electrically connected to the P+ region 9, the N+ region 8, and the doped polysilicon 7 through contact holes 11 penetrating the interlayer insulating dielectric film 10 and the surface passivated silicon oxide insulating dielectric film 6.

[0023] Within the terminal region, a P-region 4 is formed in the N-silicon epitaxial layer 2, which is connected to the P-region 4 of the transition region, and a P+ region 9 is provided inside it. A field silicon oxide insulating dielectric film 3 with a thickness significantly greater than that of the surface passivation silicon oxide insulating dielectric film 6 is formed on the surface of the terminal region. For example... Figure 2 As shown, in one embodiment, the terminal region only contains the field-insulating silicon dioxide dielectric film 3, and the front negative electrode metal 12 is directly connected to the P+ region 9 through the contact hole 11. Figure 3 As shown, in another preferred embodiment, a doped polysilicon field plate 7 is also disposed on the field oxide insulating dielectric film 3 in the terminal region. In this case, the front negative electrode metal 12 is connected to both the P+ region 9 and the doped polysilicon field plate 7 through the contact hole 11.

[0024] It should be noted that the front negative electrode metal 12 of the transition region and the terminal region is connected as a whole and is ultimately covered by the final passivation film 13. A back positive electrode metal 14 is provided on the back of the chip.

[0025] The implementation of this invention is described below with reference to the process steps. Key steps correspond to the accompanying drawings, and specific process parameter ranges are introduced to reflect process control: Step 1: Substrate Preparation and Epitaxy: A heavily doped N+ silicon substrate 1 with a resistivity of 0.001-0.010 Ω·cm is provided. An N-silicon epitaxial layer 2 is grown on this substrate 1 using an epitaxial process. The resistivity of the N-silicon epitaxial layer 2 is controlled between 0.1-20.0 Ω·cm, and the thickness is controlled between 2.0-60.0 μm, with the specific values ​​determined based on the target breakdown voltage and constant current.

[0026] Step 2: Formation of the P-region: The P-region 4 pattern, comprising the cell region, transition region, and terminal region, is defined using photolithography. Subsequently, boron (B) ion implantation is performed. The implantation dose and energy are designed to meet the requirements of a junction depth of 2.0-6.0 μm and a doping concentration of 1E15-1E19 atoms / cm³ for subsequent propagation of P-region 4. High-temperature annealing is then performed after implantation to activate impurities and achieve the desired junction depth.

[0027] Step 3: Forming the constant current N-region: Define the cell region and transition region where the constant current N-region 5 needs to be formed using photolithography. Perform phosphorus (P) or arsenic (As) ion implantation, followed by annealing to form an N-type region with a doping concentration of 1E14-1E18 atoms / cm³ and a junction depth of 0.1-2.0 μm, i.e., the constant current N-region 5.

[0028] Step 4: Formation of P+ and N+ regions: Ohmic contact regions are formed through two independent photolithography and ion implantation steps. First, a high-dose boron implantation is performed to form P+ region 9, with a doping concentration controlled at 1E17-1E20 atoms / cm³ and a junction depth of 0.2-3.0 μm. Subsequently, a higher-dose phosphorus or arsenic implantation is performed to form N+ region 8, with a doping concentration controlled at 1E18-1E22 atoms / cm³ and a junction depth of 0.1-2.0 μm. Both implantations can be activated by simultaneous annealing.

[0029] Step 5: Growth of the oxide layer and formation of polycrystalline silicon: A layer of silicon dioxide is thermally grown as a surface passivation silicon dioxide insulating dielectric film 6, typically tens of nanometers thick. In the terminal region, a thicker field silicon dioxide insulating dielectric film 3 can be grown using techniques such as local oxidation (LOCOS), reaching thicknesses of hundreds of nanometers to over one micrometer. Then, a doped polycrystalline silicon layer is formed by low-pressure chemical vapor deposition (LPCVD), and patterned using photolithography and dry etching to form the doped polycrystalline silicon 7 patterns required for the cell region and transition region, as well as the optional doped polycrystalline silicon field plate 7 pattern for the terminal region.

[0030] Step 6: Forming the interlayer dielectric and contact holes: Silicon nitride, silicon oxide, or a composite layer thereof are formed as the interlayer insulating dielectric film 10 by chemical vapor deposition such as PECVD. Subsequently, contact holes 11 are etched in the interlayer insulating dielectric film 10 and the underlying oxide layer by photolithography and a dry / wet combined etching process, exposing the surfaces of the P+ regions 9, N+ regions 8, and doped polysilicon 7 that need to be interconnected.

[0031] Step 7: Front-side metallization and passivation: An aluminum-based alloy, such as an AlSiCu layer, is formed using physical vapor deposition, such as sputtering, and a patterned front-side negative electrode metal 12 is formed by photolithography and etching. This metal fills the contact holes 11, achieving reliable ohmic contact and electrical interconnection. Subsequently, silicon nitride or other dielectrics are deposited as the final passivation film 13 using methods such as PECVD, and windows are created by photolithography to expose the bonding areas.

[0032] Step 8: Backside metallization: After thinning and cleaning the backside of the silicon wafer, multiple layers of metals such as titanium, nickel, and silver are formed by evaporation or sputtering to form the backside positive electrode metal 14.

[0033] Technical Effects Description This invention achieves the following synergistic effects through the integrated structural design and manufacturing method described above: the doped polysilicon 7 in the transition region is electrically connected to the field plate in the cell region, effectively guiding the electric field lines at the cell edges. The thick field oxygen 3 in the terminal region bears the main voltage drop, while the optional polysilicon field plate 7 further optimizes the electric field distribution on the field oxygen surface, preventing premature breakdown. Crucially, through the precisely controlled ion implantation and annealing processes in steps two to four, the P-region 4, P+ region 9, N+ region 8, and constant current N-region 5 in the cell region, transition region, and terminal region have a design-controllable and consistent doping distribution. This consistency ensures that when reverse voltage is applied to the device, the lateral expansion of the depletion region from the high-electric-field cell region to the terminal region is a smooth transition, eliminating electric field concentration points caused by abrupt doping changes. Thus, both structural design and process implementation jointly guarantee the high withstand voltage and high reliability of the terminal.

[0034] It should be noted that in this document, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "fixed," "installed," "connected," and "linked" should be interpreted broadly. For example, "installed" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a mechanical connection or an electrical connection; "linked" can be a direct connection, an indirect connection through an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A constant current diode chip termination structure, characterized in that, The terminal structure, which is disposed on one side of an N-silicon epitaxial layer on a heavily N+ doped silicon substrate, includes a cell-terminal transition region and a terminal region. The cell-terminal transition region includes: The P-region is located within the N-silicon epitaxial layer; A surface passivated silicon oxide insulating dielectric film covering the N-silicon epitaxial layer; The first doped polycrystalline silicon layer is located on the surface passivated silicon oxide insulating dielectric film; An interlayer insulating dielectric film covering the first doped polycrystalline silicon layer; In addition, the front negative electrode metal penetrates the interlayer insulating dielectric film and the surface passivated silicon oxide insulating dielectric film through the first contact hole, and is electrically connected to the P+ region, N+ region and the first doped polysilicon layer in the P region. Optionally, the transition region may be partially replaced on the terminal region side with a field-silicon oxide insulating dielectric layer instead of the surface passivated silicon oxide insulating dielectric film. The terminal area includes: The P region located within the N-silicon epitaxial layer and connected to the transition region P region, and the P+ region connected to the P+ region within the transition region p region; A field oxide insulating dielectric film covering the N-silicon epitaxial layer has a thickness greater than that of the surface passivation silicon oxide insulating dielectric film. The front negative electrode metal covering the field silicon oxide insulating dielectric film and the interlayer insulating dielectric film is electrically connected to the P+ region in the terminal region P region through the second contact hole. The front negative electrode metal of the transition region is connected to the front negative electrode metal of the terminal region; A final passivation film formed of silicon oxide and silicon nitride is covered on the front negative electrode metal, and the back positive electrode metal is covered under the heavily N+ doped silicon substrate.

2. The constant current diode chip termination structure according to claim 1, characterized in that, The terminal area also includes: The second doped polycrystalline silicon field plate is located on the field oxide insulating dielectric film; The negative electrode metal on the front side of the terminal area is electrically connected to both the P+ region and the second doped polysilicon field plate through the second contact hole.

3. The constant current diode chip termination structure according to claim 1, characterized in that, The resistivity of the N-silicon epitaxial layer is 0.1-20.0 Ω·cm, and the thickness is 2.0-60.0 μm.

4. The constant current diode chip termination structure according to claim 1, characterized in that, The P-region doping concentration in the transition and terminal regions is 1E15-1E19 atoms / cm³, and the junction depth is 2.0-6.0 μm.

5. The constant current diode chip termination structure according to claim 1, characterized in that, The P+ region has a doping concentration of 1E17-1E20 atoms / cm³ and a junction depth of 0.2-3.0 μm; the N+ region has a doping concentration of 1E18-1E22 atoms / cm³ and a junction depth of 0.1-2.0 μm.

6. A constant current diode chip, characterized in that, include: The terminal structure as described in any one of claims 1 to 5; A constant current cell region connected to the transition region of the terminal structure includes a P region periodically arranged on the upper part of the N-silicon epitaxial layer, a P+ region and an N+ region located in each P region, a constant current N region located above the P region, and a doped polysilicon field plate located above the adjacent P region. The front negative electrode metal short-circuits the P+ region, the N+ region and the doped polysilicon field plate.

7. A method for fabricating a constant current diode chip termination structure as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Provide an N+ doped silicon substrate and grow an N-silicon epitaxial layer on it with a resistivity of 0.1-20.0 Ω·cm and a thickness of 2.0-60.0 μm; Through the first ion implantation and propulsion, a P-region consisting of a cell region, a transition region, and a terminal region is formed within the N-silicon epitaxial layer. The doping concentration of the P-region is 1E15-1E19 atoms / cm³, and the junction depth is 2.0-6.0 μm. A constant-current N region is formed above the P region of the cell region and the transition region through a second ion implantation and propulsion. Through a third ion implantation and propulsion, P+ and N+ regions are formed in the P-regions of the cell region, transition region, and terminal region, respectively; wherein, the process is controlled so that the doping concentration of the P+ region is 1E17-1E20 atoms / cm³ and the junction depth is 0.2-3.0 μm, and the doping concentration of the N+ region is 1E18-1E22 atoms / cm³ and the junction depth is 0.1-2.0 μm; A surface passivated silicon oxide insulating dielectric film is grown on the N-silicon epitaxial layer, and a thicker field silicon oxide insulating dielectric film is grown in the region corresponding to the terminal region. A doped polysilicon layer is deposited and patterned to form a first doped polysilicon layer on the surface of the transition region, and optionally a second doped polysilicon field plate is formed on the field oxide of the terminal region. Deposit interlayer insulating dielectric film; The interlayer insulating dielectric film and the underlying silicon oxide layer are etched to form contact holes that expose the P+ region, N+ region, first doped polysilicon layer and optionally second doped polysilicon field plate, respectively. A front-side metal layer is deposited and patterned to form a front-side negative electrode metal, which fills the contact holes and electrically connects all exposed areas. A back positive electrode metal is formed on the back side of the heavily N+ doped silicon substrate.

8. The manufacturing method according to claim 7, characterized in that, The resistivity of the heavily N+ doped silicon substrate is 0.001-0.010 Ω·cm.

9. The manufacturing method according to claim 7, characterized in that, The doping concentration of the constant current N-region is 1E14-1E18 atoms / cm³, and the junction depth is 0.1-2.0 μm.

10. A constant current device, characterized in that, It includes the constant current diode chip as described in claim 6.

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