Silicon NPN type planar high-frequency high-power transistor and manufacturing method thereof

Abstract

The invention discloses a silicon NPN type planar high-frequency high-power transistor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The transistor comprises a silicon substrate, a silicon epitaxial layer formed on the silicon substrate, a base region formed in the silicon epitaxial layer, an emitter region formed in the base region, an oxide layer covering the surface of a device, and a base electrode and an emitter electrode formed on the oxide layer, the pattern structures of the emitter region and the emitter are both multi-emitter interdigital structures taking the vertical center line of the chip as a symmetry axis, and the emitter is connected with the emitter region through a lead contact hole; the pattern structure of the base electrode is a cross-penetrating structure which is distributed with the multi-emitter interdigital structure in a staggered manner, and the base electrode is connected with the base region through a lead contact hole; the transistor does not include a field limiting ring. According to the invention, the contradiction of mutual restriction among the power capacity, the breakdown voltage and the frequency characteristic in the high-frequency high-power transistor is solved, the process is simplified, and the yield of mass production is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and particularly relates to a silicon NPN type planar high-frequency high-power transistor and a manufacturing method thereof. BACKGROUND

[0002] The bipolar transistor (BJT, hereinafter referred to as transistor) is one of the earliest and most important solid-state devices with amplification function. It was invented by a research team at Bell Laboratories in 1947, and the first junction bipolar transistor was demonstrated in 1951. Since then, with the continuous deepening of theory, transistors have been expanded in the aspects of high frequency, high reverse voltage, high power and switching characteristics.

[0003] Generally speaking, the characteristic frequency f T of a transistor is greater than 30 MHZ, and the collector dissipation power P CM is greater than 1 W, which is called a high-frequency high-power transistor. Compared with ordinary transistors, high-frequency high-power transistors have higher working frequency and larger output power, and are widely used in the fields of wireless communication, radar, navigation, broadcast television and the like, and are the core components of various electronic systems.

[0004] Silicon epitaxial planar process technology is a mainstream technology in current semiconductor device production. However, there is an inherent and mutually restrictive contradictory relationship between the key parameters of the frequency characteristics, power capacity and breakdown voltage of the transistor: 1. The core of power capacity optimization is to maximize the current-carrying capacity per unit chip area, to expand the current-carrying area and reduce the on-state loss. The effective methods are to increase the width of a single emitter, increase the number of emitter strips, and increase the total length of the emitter, etc. At the same time, the thickness of the front metal layer can be increased, the metal line width can be increased, and the current distribution uniformity can be optimized. However, when the size of the emitter is increased to improve the power, the parasitic capacitance is also increased, and the carrier transit path is lengthened, which directly leads to a decrease in frequency characteristics. At the same time, under large current, the base region expansion effect is easy to occur, which affects the frequency characteristics, so that the actual frequency is lower than the theoretical frequency.

[0005] 2. With the increase of working frequency, the collector edge effect of the emitter current will be intensified. In order to weaken the collector edge effect, a smaller unit length current capacity of the emitter should be selected, and the total length of the emitter should be increased to meet the required I CM . At the same time, reducing the base width of the high-frequency transistor with low frequency can improve the characteristic frequency, but if it is too small, the base width modulation effect will be very significant, the linearity of the transistor output curve will be poor, and the breakdown value will decrease. Narrow emitter strips will cause the peak value of the collector junction edge electric field to rise, which will reduce the breakdown value.

[0006] 3. In order to improve the breakdown voltage, the conventional technical means is to introduce a field limiting ring (FLR) structure, and multiple field limiting rings can improve the breakdown characteristics and power redundancy of the transistor. For example, the scheme disclosed in CN221960978U improves the breakdown voltage by setting a field limiting ring, and optimizes the frequency by adjusting the aspect ratio of the emitter. However, if the size and layout are unreasonable, it will affect the frequency characteristics to some extent. At the same time, the introduction of the field limiting ring will bring new problems: first, the field limiting ring will occupy additional chip area, reducing the integration density of the chip and increasing the unit cost; second, the introduction of the field limiting ring increases the process steps of photolithography and ion implantation, increases the process complexity and manufacturing cost, and challenges the yield of mass production; finally, the introduction of the field limiting ring may adversely affect the high-frequency characteristics of the device.

[0007] Therefore, there is an urgent need in the art for an innovative high-frequency high-power transistor structure that can achieve high power, high breakdown voltage and high frequency without relying on field limiting rings, and has a simple process suitable for mass production. SUMMARY

[0008] The purpose of the present application is to overcome the problems existing in the prior art and provide a silicon NPN type planar high-frequency high-power transistor and a manufacturing method thereof.

[0009] The purpose of the present application is achieved by the following technical solutions: In a first aspect, a silicon NPN type planar high-frequency high-power transistor is provided, comprising a silicon substrate, a silicon epitaxial layer formed on the silicon substrate, a base region formed in the silicon epitaxial layer, an emitter region formed in the base region, an oxide layer covering the surface of the device, and a base and an emitter formed on the oxide layer. The pattern structure of the emitter region and the emitter is a multi-emitter interdigital structure with the chip vertical center line as the symmetry axis, and the emitter is connected to the emitter region through a lead contact hole; The pattern structure of the base is an interpenetrating structure staggered with the multi-emitter interdigital structure, and is connected to the base region through a lead contact hole; The transistor does not contain a field limiting ring.

[0010] In some embodiments, the emitter region includes a main emitter region located at the center of the chip and a long strip-shaped emitter strip symmetrically arranged around the main emitter region.

[0011] In some embodiments, the metal electrode lead edges of the emitter and the base adopt a circular arc structure.

[0012] In some embodiments, the silicon substrate is an N+ silicon substrate, the silicon epitaxial layer is an N- silicon epitaxial layer, the base region is a P base region, and the emitter region is an N+ emitter region.

[0013] In some embodiments, the effective area of the emission zone is 0.31mm 2 , the width of the emission strip is 0.06mm, and the perimeter of the emission zone is 7.4mm.

[0014] In some embodiments, the collector of the transistor dissipates power ≥7.5W, the breakdown voltage is >150V, and the characteristic frequency is >50MHz.

[0015] In a second aspect, a method for manufacturing the silicon NPN type planar high-frequency high-power transistor of the first aspect is provided, comprising the following steps: S1. Providing an N+ silicon substrate and growing an N-silicon epitaxial layer; S2. Forming a P-base region in the N-silicon epitaxial layer by photolithography and ion implantation; S3. Forming an N+ emission zone of a multi-emitter interdigital structure symmetrical to the vertical center line of the chip in the P-base region by photolithography and ion implantation; S4. Growing an oxide layer on the surface of the silicon wafer and etching a base lead contact hole and an emitter lead contact hole; S5. Depositing a metal layer on the front surface of the chip and forming a base and an emitter by etching, wherein the pattern structure of the emitter is the same as the N+ emission zone and is correspondingly arranged above the N+ emission zone; and the pattern structure of the base is a cross-interleaved structure interleaved with the multi-emitter interdigital structure; S6. Depositing a passivation layer on the front surface of the chip and etching a bonding area.

[0016] It should be further explained that the technical features of the above-mentioned option embodiments can be combined or replaced with each other to form new technical solutions without conflict.

[0017] Compared with the prior art, the present application has the following advantages: 1. The pattern structure of the emission zone and the emitter of the present application is a multi-emitter interdigital structure symmetrical to the vertical center line of the chip, and the pattern structure of the base is a cross-interleaved contact plane structure interleaved with the multi-emitter interdigital structure. The use of the center-symmetrical multi-emitter interdigital parallel and cross-interleaved base contact structure increases the effective area of the emission zone, and at the same time, the current is symmetrically injected from the center to both sides, the current distribution and heat distribution are extremely uniform, and the large-current requirement is met. The overall vertical center line symmetrical structure is adopted, the current is uniformly diffused, the heat path is symmetrically optimized, the effective active area of the chip is more fully utilized, and the chip heat dissipation is improved. Compared with the ordinary layout structure, the power capacity of the transistor can be increased by 20%~40%.

[0018] 2. The application does not use field limiting ring structure, ensures the key parameters, reduces the overall size of the chip, and improves the integration density per unit area of the chip; since the manufacturing link of the field limiting ring is completely eliminated, at least one photolithography and ion implantation process step is reduced, the process complexity and manufacturing cost are significantly reduced, and at the same time, due to the reduction of process steps, the process implementation is strong, which brings a significant improvement in yield.

[0019] 3. The application realizes the high-performance indexes of collector dissipation power≥7.5W, breakdown voltage>150V, and characteristic frequency>50MHz on a single device by the unique vertical center-symmetric interdigital structure and the field-free ring design, successfully solves the traditional contradiction between high power, high voltage resistance and high frequency characteristics.

[0020] 4. The bonding area is independent, which is convenient for wire bonding operation in later assembly; at the same time, the metal electrode lead edges of the emitter and the base are in arc structure, which improves the breakdown performance. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a sectional view of a silicon NPN type planar high-frequency high-power transistor of the application; Figure 2 is a schematic diagram of a multi-emitter interdigital parallel and cross-emitter base contact structure of the application; Figure 3 is a flow chart of a manufacturing method of a silicon NPN type planar high-frequency high-power transistor of the application; Figure 4 is a schematic diagram of a multi-emitter interdigital structure of the application; Figure 5 is a schematic diagram of a metal electrode lead edge structure of the application; Figure 6 is a schematic diagram of the design of the base and the emitter.

[0022] In the figure: 1-N+ silicon substrate; 2-N-silicon epitaxial layer; 3-P base region; 4-N+ emitter region; 5-base; 6-emitter; 7-oxide layer; 8-base lead contact hole; 9-emitter lead contact hole; 10-collector. DETAILED DESCRIPTION

[0023] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of, rather than all of, the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the protection scope of the present application.

[0024] It should be noted that the defects of the above prior art solutions are the results obtained by the inventors after practice and careful study. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of the present application to the above problems should be the contributions made by the inventors to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.

[0025] To solve the technical problems pointed out in the background art, the embodiments provided by the present application are as follows: In an exemplary embodiment, a silicon NPN type planar high-frequency high-power transistor is provided, comprising an N+ silicon substrate 1, an N-silicon epitaxial layer 2 formed on the N+ silicon substrate 1, a P base region 3 formed in the N-silicon epitaxial layer 2, an N+ emitter region 4 formed in the P base region 3, an oxide layer 7 covering the surface of the device, and a base 5 and an emitter 6 formed on the oxide layer 7. The pattern structure of the N+ emitter region 4 and the emitter 6 is a multi-emitter interdigital structure with the chip vertical center line as the symmetry axis, and the emitter 6 is connected to the N+ emitter region 4 through an emitter lead contact hole 9. The pattern structure of the base 5 is a cross structure distributed alternately with the multi-emitter interdigital structure, and is connected to the base region 5 through a base lead contact hole 8. The transistor does not contain a field limiting ring.

[0026] As Figure 2As shown, in this embodiment, the P-base region 3 is a rectangular planar structure of a certain thickness. The N+ emitter region 4 is a central-symmetrical strip structure, including a main emitter region located at the center of the chip and long strip-shaped emitter strips symmetrically arranged around the main emitter region. Specifically, the core of the present application is to adopt a parallel layout of a central main emitter and multiple emitter sub-strips. In the prior art, a large-area, square-shaped emitter region is simply designed, and current is injected from the entire upper surface metal. However, due to the existence of the lateral resistance (base resistance) of the semiconductor material, the current will preferentially flow into the base region from the edge of the emitter region, which is called “edge effect” or “current clustering effect”. The current density of the central region of the emitter region is extremely low and almost does not participate in work, becoming a “dead zone”. This huge central region occupies the chip area, but contributes very little current, while introducing a huge parasitic capacitance, which seriously degrades the frequency characteristics. The multiple-finger structure of the present application divides a large emitter region into multiple parallel, slender “finger”-shaped small emitter regions (i.e., “interdigital fingers”) and connects them in parallel. The effective working area of each slender emitter strip is almost completely concentrated in the two long edges of the strip. The central region is very narrow, and the “dead zone” occupies a very small proportion. For a given total area of the emitter region, by dividing it into multiple thin strips, the total length of the “effective edge” of the emitter junction (i.e., the total perimeter) is greatly increased, so that the useful current of the transistor is increased.

[0027] The working principle of the transistor is that the base-collector PN junction is reversely biased V CE , the base-emitter PN junction is forward biased V BE , the collector 10 is at a high potential, the base 5 is at a 0.7V on-voltage, and the emitter 6 is at a low potential or grounded. The emitter 6 is located in the center of the chip layout and is in the form of a long strip, which is the core injection area of the electron carriers. The current flows from the central emitter and is symmetrically injected into the P-base region 3 on both sides. This structure makes the direction of electron injection symmetrical and the path length substantially uniform, avoiding the current bias flow problem of unilateral layout.

[0028] At the same time, the base 5 is symmetrically distributed around the emitter 6 on both sides, and the symmetrical injection of the base current is realized through uniform wiring. After the base 5 current is introduced, it is symmetrically divided into two parts and injected into the base region 5 on both sides of the emitter 6, uniformly and symmetrically injecting hole carriers and forming a symmetrical base region electric field. The structure of the present application maximizes the effective area of the emitter 6, effectively reduces the current density, avoids local overheating of the device, effectively controls the junction temperature, and improves the power dissipation capability; the direction of electron injection is symmetrical, the path length is uniform, the current density of each region is uniform, and the total current carrying capacity is effectively improved.

[0029] Further, the metal electrode lead edge of the emitter 6 and the base 5 adopts a circular arc structure, increasing the radius of curvature at this point. The circular arc surface forces the charge to be more evenly distributed, avoiding excessive concentration at a point. The circular arc transition provides a gentle "exit" or "entrance" for the electric field lines, allowing the electric field lines to bend and diverge smoothly, rather than being forced to squeeze, twist and concentrate at sharp corners. At the same time, the circular arc edge can reduce the local electric field peak to a level close to the average electric field, thereby significantly delaying or preventing avalanche breakdown at this point. The effect of improving the breakdown performance is achieved.

[0030] In this embodiment, the effective area of the emitter region is 0.31mm 2 , the width of the emitter bar is 0.06mm, the perimeter of the emitter region is 7.4mm, the collector dissipation power of the transistor is ≥7.5W, the breakdown voltage is >150V, and the characteristic frequency is >50MHz.

[0031] In another exemplary embodiment, as shown in Figure 3 , a manufacturing method of a silicon NPN type planar high-frequency high-power transistor is provided, comprising the following steps: S1. Providing an N+ silicon substrate 1 and growing an N-silicon epitaxial layer 2; S2. Forming a P-base region 3 in the N-silicon epitaxial layer 2 by lithography and ion implantation; S3. Forming an N+ emitter region 4 of a multi-emitter interdigital structure with the chip vertical center line as the symmetry axis in the P-base region 3 by lithography and ion implantation; the N+ emitter region 4 is a center-symmetric strip structure. The middle is the main emitter region, and the periphery is a long strip-shaped emitter bar, as shown in Figure 4 .

[0032] S4. Growing an oxide layer 7 on the surface of the silicon wafer and etching a base lead contact hole 8 and an emitter lead contact hole 9, while the metal electrode lead edge of the emitter 6 and the base 5 adopts a circular arc structure, as shown in Figure 5 , to improve the breakdown performance; S5. Depositing a metal layer on the front surface of the chip and forming a base 5 and an emitter 6 by etching, as shown in Figure 6 , wherein the pattern structure of the emitter 6 is the same as that of the N+ emitter region 4 and is correspondingly arranged above the N+ emitter region 4; the pattern structure of the base 5 is a cross-penetrating structure interlaced with the multi-emitter interdigital structure; S6. Depositing a passivation layer on the front surface of the chip and etching a bonding area.

[0033] The above detailed description of the application is not intended to limit the application to the specific embodiments described, but is intended to cover all alternatives that fall within the scope of the application.

Claims

1. A silicon NPN planar high-frequency high-power transistor, comprising a silicon substrate, a silicon epitaxial layer formed on the silicon substrate, a base region formed within the silicon epitaxial layer, an emitter region formed within the base region, an oxide layer covering the device surface, and a base and an emitter formed on the oxide layer, characterized in that, The emitter region and emitter are both multi-emitter interdigitated structures with the vertical center line of the chip as the axis of symmetry. The emitter is connected to the emitter region through a lead contact hole. The base has a patterned structure that is interlaced with the multi-emitter interdigitated structure and is connected to the base region through lead contact holes. The transistor does not contain a field-limiting ring.

2. The silicon NPN planar high-frequency high-power transistor according to claim 1, characterized in that, The emission area includes a main emission area located at the center of the chip and elongated emission strips symmetrically arranged around the main emission area.

3. The silicon NPN planar high-frequency high-power transistor according to claim 1, characterized in that, The edges of the metal electrode leads of the emitter and base are rounded.

4. A silicon NPN planar high-frequency high-power transistor according to claim 1, characterized in that, The silicon substrate is an N+ silicon substrate, the silicon epitaxial layer is an N- silicon epitaxial layer, the base region is a P-base region, and the emitter region is an N+ emitter region.

5. A silicon NPN planar high-frequency high-power transistor according to claim 2, characterized in that, The effective area of ​​the launch zone is 0.31 mm. 2 The width of the launch bar is 0.06 mm, and the perimeter of the launch area is 7.4 mm.

6. A silicon NPN planar high-frequency high-power transistor according to claim 2, characterized in that, The transistor has a collector power dissipation ≥7.5W, a breakdown voltage >150V, and a characteristic frequency >50MHz.

7. A method for fabricating a silicon NPN planar high-frequency high-power transistor as described in any one of claims 1-6, characterized in that, Includes the following steps: S1. Provide an N+ silicon substrate and perform N- silicon epitaxial layer growth; S2. A P-based region is formed within the N-silicon epitaxial layer by photolithography and ion implantation; S3. An N+ emitter region with a multi-emitter interdigitated structure and a symmetry axis of the chip's vertical centerline is formed in the P-base region by photolithography and ion implantation; S4. An oxide layer is grown on the surface of the silicon wafer, and base lead contact holes and emitter lead contact holes are etched out; S5. A metal layer is deposited on the front side of the chip, and the base and emitter are formed by etching. The emitter pattern structure is the same as that of the N+ emitter region and is correspondingly disposed above the N+ emitter region. The base pattern structure is a forked structure that is interspersed with the multi-emitter interdigitated structure. S6. Deposit a passivation layer on the front side of the chip and etch out the bonding area.

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