Light-emitting chip and preparation method thereof

Abstract

The embodiment of the invention discloses a light-emitting chip and a preparation method thereof, through bonding connection of a first connection structure of a light-emitting structure part and a second connection structure of a circuit structure part, electrical connection of a driving circuit of a circuit layer and a light-emitting unit is realized, and electrical interconnection of the light-emitting structure part and the circuit structure part is realized; through bonding connection between the first dielectric layer and the second dielectric layer, mechanical connection between the light-emitting structure part and the circuit structure part is realized, and the firmness of the overall structure of the light-emitting chip is ensured. Moreover, by arranging the first dielectric layer and the second dielectric layer, diffusion of at least part of conductive materials of the first connection structure and the second connection structure can be blocked, electrical failure caused by diffusion of the conductive materials in the first connection structure and the second connection structure is reduced, and the yield and reliability of the light-emitting chip are further improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a light-emitting chip and its fabrication method. Background Technology

[0002] Compared with traditional LEDs, micro LEDs have outstanding advantages such as high resolution, high contrast, low power consumption, and long lifespan, and are gradually being used in micro-display fields such as AR, VR glasses, and head-mounted displays.

[0003] Smaller screen sizes and smaller pixel pitches (<10µm) are important technological directions in the AR / VR display field. Traditional bump flip-chip bonding solutions are difficult to meet the requirements of high-density interconnection. Therefore, the use of hybrid bonding solutions is a key technology application direction in this field.

[0004] However, the light-emitting chips obtained by using the hybrid bonding method in the existing technology have the problem of conductive material diffusion, which causes chip failure and affects yield and reliability. Summary of the Invention

[0005] This invention provides a light-emitting chip and its fabrication method to reduce the diffusion of conductive materials in the light-emitting chip and improve the yield and reliability of the light-emitting chip.

[0006] According to one aspect of the present invention, a light-emitting chip is provided, comprising: a light-emitting structure portion and a circuit structure portion;

[0007] The light-emitting structure includes at least one light-emitting unit, a first connecting structure, and a first dielectric layer. The first connecting structure is electrically connected to the light-emitting unit. The first dielectric layer is located on one side of the light-emitting unit, and the first connecting structure passes through the first dielectric layer.

[0008] The circuit structure includes a circuit layer, a second connection structure, and a second dielectric layer. The second dielectric layer is located on one side of the circuit layer. The second connection structure passes through the second dielectric layer and is electrically connected to the circuit layer. The second connection structure is bonded to the first connection structure, and the first dielectric layer is bonded to the second dielectric layer.

[0009] The first dielectric layer and / or the second dielectric layer are used to block at least a portion of the conductive material of the connection structure from diffusing; the connection structure includes at least one of the first connection structure and the second connection structure.

[0010] Optionally, the connection structure is located in the through hole. The connection structure includes a diffusion barrier layer and a connecting post. The diffusion barrier layer is located on the sidewall of the through hole and surrounds the connecting post to prevent the conductive material of the connecting post from diffusing out of the through hole.

[0011] Optionally, the connection structure also includes an adhesive layer and a seed layer, which are located between the diffusion barrier layer and the connecting post. The seed layer is located between the adhesive layer and the connecting post, the adhesive layer surrounds the seed layer, and the seed layer surrounds the connecting post. The material of the seed layer is the same as that of the connecting post.

[0012] Optionally, the light-emitting unit includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked together; the first connection structure includes a first connection portion and a second connection portion, the first connection portion being disposed in a first through hole, the second connection portion being disposed in a second through hole, the first connection portion being electrically connected to the first semiconductor layer, the second connection portion being electrically connected to the second semiconductor layer, and the first connection portion and the second connection portion passing through the first dielectric layer respectively;

[0013] The light-emitting structure also includes a first conductive connection layer, which is located between the first semiconductor layer and the first connection portion and electrically connects the first semiconductor layer and the first connection portion respectively, for blocking at least a portion of the conductive material of the first connection portion from diffusing;

[0014] And / or, the diffusion barrier layer of the second connection portion is also located at the bottom of the second via, and the connecting post of the second connection portion is electrically connected to the second semiconductor layer through the diffusion barrier layer at the bottom of the second via.

[0015] Optionally, the light-emitting structure further includes a third dielectric layer, which is located between the light-emitting unit and the first dielectric layer, and covers the sidewall of the light-emitting unit;

[0016] The first through-hole and the second through-hole penetrate the first dielectric layer and the third dielectric layer, respectively;

[0017] The first connecting part and the second connecting part respectively include a first diffusion barrier layer and a first connecting post. The first diffusion barrier layer surrounds the first connecting post and is used to block the conductive material of the first connecting post from diffusing to the third dielectric layer and the light-emitting unit.

[0018] Optionally, the third dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, with the second sub-dielectric layer located between the first sub-dielectric layer and the first dielectric layer;

[0019] The light-emitting structure also includes a sidewall reflective layer, which is located at least between the first sub-dielectric layer and the second sub-dielectric layer on the sidewall of the light-emitting unit.

[0020] Optionally, the circuit structure may further include a fourth dielectric layer and a second conductive connection layer;

[0021] The fourth dielectric layer is located between the circuit layer and the second dielectric layer, and the second connection structure passes through the second dielectric layer and the fourth dielectric layer respectively;

[0022] The second conductive connection layer is located between the second connection structure and the circuit layer, and is electrically connected to the second connection structure and the circuit layer respectively;

[0023] The second conductive connection layer is used to block at least a portion of the conductive material of the second connection structure from diffusing.

[0024] Optionally, the surface of the first connection structure near the circuit structure portion is flush with the surface of the first dielectric layer near the circuit structure portion; and / or,

[0025] The surface of the second connecting structure near the light-emitting structure is flush with the surface of the second dielectric layer near the light-emitting structure.

[0026] Optionally, the first dielectric layer and the second dielectric layer are made of the same material; and / or, the first connection structure is made of the same material as the second connection structure.

[0027] Optionally, the material of the first dielectric layer includes at least one of SiN and SiCN; and / or, the material of the second dielectric layer includes at least one of SiN and SiCN.

[0028] According to another aspect of the present invention, a method for fabricating a light-emitting chip is provided, comprising:

[0029] A light-emitting structure is formed; wherein the light-emitting structure includes at least one light-emitting unit, a first connecting structure and a first dielectric layer, the first connecting structure being electrically connected to the light-emitting unit; the first dielectric layer is located on one side of the light-emitting unit, and the first connecting structure passes through the first dielectric layer;

[0030] A circuit structure is formed; wherein the circuit structure includes a circuit layer, a second connection structure and a second dielectric layer, the second connection structure passes through the second dielectric layer and is electrically connected to the circuit layer;

[0031] The light-emitting structure and the circuit structure are bonded together to achieve the bonding connection between the first connection structure and the second connection structure, and the bonding connection between the first dielectric layer and the second dielectric layer.

[0032] The first dielectric layer and / or the second dielectric layer are used to block at least a portion of the conductive material of the connection structure from diffusing; the connection structure includes at least one of the first connection structure and the second connection structure.

[0033] Optionally, a light-emitting structure is formed, including:

[0034] A first dielectric layer is prepared on the side of the third dielectric layer of the first intermediate structure away from the first substrate to form a second intermediate structure; wherein, the first intermediate structure includes a first substrate, at least one light-emitting unit on one side of the first substrate, and a third dielectric layer covering the light-emitting unit, and the light-emitting unit includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked together.

[0035] The second intermediate structure is patterned to form a first via and a second via; the first via is located on the side of the first semiconductor layer away from the first substrate, and the second via is located on the side of the second semiconductor layer away from the first substrate; the first via and the second via penetrate the first dielectric layer and the third dielectric layer, respectively.

[0036] A first connecting portion is formed in a first through hole, and a second connecting portion is formed in a second through hole; the first connecting structure includes a first connecting portion and a second connecting portion.

[0037] Optionally, before forming the second intermediate structure, the method further includes: [The method is described in the original text, but the provided excerpt ends here.]

[0038] A first conductive interconnect layer is prepared on the side of the epitaxial wafer away from the first substrate to form an epitaxial structure layer;

[0039] The epitaxial structure layer is patterned to form multiple light-emitting units;

[0040] A third dielectric layer is formed on the side of the light-emitting unit away from the first substrate, forming a first intermediate structure;

[0041] When the second intermediate structure is patterned to form the first through-hole, the etching stops at the first conductive connection layer.

[0042] Optionally, the circuit structure includes:

[0043] A second dielectric layer is fabricated on the side of the fourth dielectric layer of the third intermediate structure away from the second substrate to form the fourth intermediate structure; wherein, the third intermediate structure includes a second substrate, a circuit layer and a fourth dielectric layer, and the fourth dielectric layer is located on the side of the circuit layer away from the second substrate;

[0044] The fourth intermediate structure is patterned to form a third through-hole and a fourth through-hole; the third through-hole and the fourth through-hole penetrate the second dielectric layer and the fourth dielectric layer, respectively.

[0045] A third connecting portion is formed in the third through hole, and a fourth connecting portion is formed in the fourth through hole;

[0046] The second connection structure includes a third connection part and a fourth connection part.

[0047] Optionally, the second dielectric layer is fabricated on the side of the fourth dielectric layer of the third intermediate structure away from the second substrate. Before forming the fourth intermediate structure, the method further includes:

[0048] A second conductive interconnect layer is fabricated on the side of the backplane wafer away from the second substrate from the circuit layer.

[0049] A fourth dielectric layer is formed on the side of the second conductive interconnect layer away from the second substrate to form a third intermediate structure;

[0050] In the process of patterning the fourth intermediate structure to form the third and fourth through holes, the etching stops at the second conductive connection layer.

[0051] The light-emitting chip and its fabrication method according to embodiments of the present invention achieve electrical connection between the driving circuit of the circuit layer and the light-emitting unit by bonding the first connection structure of the light-emitting structure portion and the second connection structure of the circuit structure portion, thus realizing the electrical interconnection between the light-emitting structure portion and the circuit structure portion; and achieve mechanical connection between the light-emitting structure portion and the circuit structure portion by bonding the first dielectric layer and the second dielectric layer, thereby ensuring the robustness of the overall structure of the light-emitting chip. Furthermore, by providing the first dielectric layer and the second dielectric layer, at least a portion of the conductive material diffusion in the first connection structure and the second connection structure can be blocked, reducing electrical failures caused by the diffusion of conductive material in the first connection structure and the second connection structure, thereby improving the yield and reliability of the light-emitting chip.

[0052] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the structure of a light-emitting chip provided in an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of the structure of another light-emitting chip provided in an embodiment of the present invention;

[0057] Figure 4 This is a flowchart of a method for fabricating a light-emitting chip according to an embodiment of the present invention;

[0058] Figure 5 This is a flowchart of another method for preparing a light-emitting chip provided in an embodiment of the present invention;

[0059] Figure 6 This is a schematic diagram of the formed epitaxial structure layer;

[0060] Figure 7This is a schematic diagram of the structure after multiple light-emitting units are formed;

[0061] Figure 8 This is a structural diagram of the first intermediate structure;

[0062] Figure 9 This is a schematic diagram of the structure after the formation of the first sub-dielectric layer;

[0063] Figure 10 This is a schematic diagram of the structure after a via is formed on the first sub-dielectric layer;

[0064] Figure 11 This is a schematic diagram of the structure after the formation of the second ohmic contact layer;

[0065] Figure 12 This is a schematic diagram of the structure after the sidewall reflective layer is formed;

[0066] Figure 13 This is a schematic diagram of the structure after the second intermediate structure has been graphically represented;

[0067] Figure 14 This is a schematic diagram of the structure after the first connecting part and the second connecting part are formed;

[0068] Figure 15 This is a flowchart of another method for preparing a light-emitting chip provided in an embodiment of the present invention;

[0069] Figure 16 This is a schematic diagram of the structure after the second conductive connection layer is formed;

[0070] Figure 17 This is a structural diagram of the third intermediate structure;

[0071] Figure 18 This is a structural diagram of the fourth intermediate structure;

[0072] Figure 19 This is a schematic diagram of the structure after the third and fourth through holes are formed;

[0073] Figure 20 This is a structural diagram showing the formation of the third and fourth connecting parts;

[0074] Figure 21 This is a schematic diagram of the structure after the light-emitting structure and the circuit structure are bonded together.

[0075] Figure 22 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention. Detailed Implementation

[0076] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0077] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0078] This invention provides a light-emitting chip. Figure 1 This is a schematic diagram of the structure of a light-emitting chip provided in an embodiment of the present invention, for reference. Figure 1 The light-emitting chip includes: a light-emitting structure portion 100 and a circuit structure portion 200; the light-emitting structure portion 100 includes at least one light-emitting unit 110, a first connection structure 120 and a first dielectric layer 130, the first connection structure 120 being electrically connected to the light-emitting unit 110; the first dielectric layer 130 is located on one side of the light-emitting unit 110, and the first connection structure 120 passes through the first dielectric layer 130; the circuit structure portion 200 includes a circuit layer 210, a second connection structure 220 and a second dielectric layer 230, the second dielectric layer 230 being located on one side of the circuit layer 210, the second connection structure 220 passing through the second dielectric layer 230 and being electrically connected to the circuit layer 210; the second connection structure 220 is bonded to the first connection structure 120, and the first dielectric layer 130 is bonded to the second dielectric layer 230; wherein, the first dielectric layer 130 and / or the second dielectric layer 230 are used to block at least a portion of the conductive material of the connection structure from diffusing; the connection structure includes at least one of the first connection structure 120 and the second connection structure 220.

[0079] The light-emitting unit 110 can be an organic light-emitting unit 110 or an inorganic light-emitting unit 110, such as a Micro-LED. In some embodiments, the light-emitting unit 110 includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked together. The first connection structure 120 is a conductive connection structure; for example, the first connection structure 120 includes a metallic material, such as copper. The first dielectric layer 130 is an insulating dielectric layer, located on one side of the light-emitting unit 110, and the first connection structure 120 passes through the first dielectric layer 130, thus facilitating electrical connection between the first connection structure 120 and the second connection structure 220 in the circuit structure section 200.

[0080] The circuit structure section 200 includes a circuit layer 210, which includes at least one driving circuit 211 for driving a corresponding light-emitting unit 110. Each driving circuit can correspond to at least one light-emitting unit 110 and is electrically connected to a first connecting structure 120 via a second connecting structure 220, thus achieving an electrical connection between the driving circuit 211, the second connecting structure 220, the first connecting structure 120, and the light-emitting unit 110, i.e., an electrical connection between the driving circuit 211 and the corresponding light-emitting unit 110. The second connecting structure 220 is a conductive connection structure; for example, it includes a metallic material, such as copper. The circuit structure section 200 also includes a second dielectric layer 230, which is an insulating dielectric layer located on one side of the circuit layer 210. The second connecting structure 220 passes through the second dielectric layer 230, facilitating the connection between the second connecting structure 220 and the first connecting structure 120.

[0081] In this embodiment of the invention, in addition to insulation, the first dielectric layer 130 and the second dielectric layer 230 also serve to block the diffusion of at least a portion of the conductive material in the connection structure. For example, they block the diffusion of copper in the connection structure, the diffusion of conductive material during the fabrication of the light-emitting chip, and the diffusion of conductive material during use after fabrication. This reduces or prevents the diffusion of conductive material from the first connection structure 120 or the second connection structure 220 to the light-emitting structure portion 100 or the circuit structure portion 200 outside the connection structure, thereby improving the yield and reliability of the light-emitting chip. The first dielectric layer 130 and the second dielectric layer 230 comprise highly dense materials. For example, the material of the first dielectric layer 130 includes at least one of SiN and SiCN, and / or the material of the second dielectric layer 230 includes at least one of SiN and SiCN. Specifically, SiN and SiCN films are very dense, almost pinhole-free, and provide a continuous physical barrier. SiN and SiCN have very low chemical reactivity with copper, forming a stable interface. This not only prevents copper from diffusing outwards and contaminating the chip structure, but also prevents external impurities (such as moisture) from diffusing inwards and eroding the copper wires and connection structures. In this embodiment, the light-emitting structure 100 and the circuit structure 200 are bonded together. Specifically, the second connection structure 220 is bonded to the first connection structure 120, thereby achieving electrical connection between the driving circuit of the circuit layer 210 and the light-emitting unit 110, and realizing electrical interconnection between the light-emitting structure 100 and the circuit structure 200. The first dielectric layer 130 is bonded to the second dielectric layer 230, thus achieving mechanical connection between the light-emitting structure 100 and the circuit structure 200, ensuring the robustness of the overall structure of the light-emitting chip. The light-emitting structure 100 and the circuit structure 200 can be bonded using a hybrid bonding method.

[0082] In this embodiment, the light-emitting chip achieves electrical connection between the driving circuit of the circuit layer and the light-emitting unit through a first connection structure of the light-emitting structure and a second connection structure of the circuit structure, thus realizing electrical interconnection between the light-emitting structure and the circuit structure. A mechanical connection between the light-emitting structure and the circuit structure is achieved through a first dielectric layer and a second dielectric layer, ensuring the robustness of the overall structure of the light-emitting chip. Furthermore, by providing the first and second dielectric layers, at least a portion of the conductive material in the first and second connection structures can be prevented from diffusing, reducing electrical failures caused by the diffusion of conductive material in the first and second connection structures, thereby improving the yield and reliability of the light-emitting chip.

[0083] Figure 2 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention, for reference. Figure 2Optionally, the connection structure is located in the through hole. The connection structure includes a diffusion barrier layer and a connecting post. The diffusion barrier layer is located on the sidewall of the through hole and surrounds the connecting post to prevent the conductive material of the connecting post from diffusing out of the through hole.

[0084] like Figure 2 As shown, the first connection structure 120 includes a first diffusion barrier layer 121 and a first connection post 122, and the second connection structure 220 includes a second diffusion barrier layer 221 and a second connection post 222.

[0085] The diffusion barrier layer covers the side of the connecting post (the first diffusion barrier layer 121 covers the side of the first connecting post 122, and the second diffusion barrier layer 221 covers the side of the second connecting post 222), thereby preventing the conductive material of the connecting post from diffusing from the sidewall of the through hole to the outside of the through hole, reducing electrical failure caused by the diffusion of the conductive material of the connecting post. Optionally, the material of the diffusion barrier layer includes TaN, and the material of the connecting post includes Cu.

[0086] Continue to refer to Figure 2 Optionally, the connection structure also includes an adhesive layer and a seed layer, which are located between the diffusion barrier layer and the connecting post. The seed layer is located between the adhesive layer and the connecting post, the adhesive layer surrounds the seed layer, and the seed layer surrounds the connecting post. The material of the seed layer is the same as that of the connecting post.

[0087] like Figure 2 As shown, the first connection structure 120 includes a first adhesion layer 123 and a first seed layer 124, and the second connection structure 220 includes a second adhesion layer 223 and a second seed layer 224.

[0088] Specifically, the adhesive layer can be made of an adhesive material, such as Ta. By placing the adhesive layer between the diffusion barrier layer and the connecting post (the first adhesive layer 123 is disposed between the first diffusion barrier layer 121 and the first connecting post 122, and the second adhesive layer 223 is disposed between the second diffusion barrier layer 221 and the second connecting post 222), the adhesive layer can create a tighter connection between the diffusion barrier layer and the connecting post. By configuring the connection structure from the inside out, including the connecting post, seed layer, adhesive layer, and diffusion barrier layer (the first seed layer 124 is located between the first connecting post 122 and the first adhesive layer 123, and the second seed layer 224 is located between the second connecting post 222 and the second adhesive layer 223), the diffusion barrier layer, being the outermost layer of the connection structure, prevents the conductive material of the connecting post from diffusing into the dielectric layer, which could lead to leakage and device failure. Optionally, the resistivity of the diffusion barrier layer is higher than that of the adhesive layer, which helps to reduce parasitic capacitance and electrical coupling between adjacent connecting posts.

[0089] The conductivity of the adhesion layer can be higher than that of the diffusion barrier layer but lower than that of the connecting pillars. The adhesion layer improves the adhesion between the diffusion barrier layer and the seed layer, and provides a good surface for the crystal growth of the seed layer, promoting the formation of a high-quality, low-resistance seed layer film. The adhesion layer can also serve as part of the conductive pathway in the connecting structure. The seed layer, acting as a template for the crystal growth of the electroplated connecting pillars, provides global conductivity, enabling uniform distribution of the electroplating current.

[0090] Optionally, the sum of the thicknesses of the diffusion barrier layer, the adhesion layer, and the seed layer is less than the thickness of the connecting post, where the thickness refers to the horizontal dimension. This ensures that the first connecting structure 120 and the second connecting structure 220 can be effectively electrically connected through the connecting post.

[0091] Figure 3 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention, for reference. Figure 3 Optionally, the light-emitting unit 110 includes a first semiconductor layer 111, a light-emitting layer 112, and a second semiconductor layer 113 stacked together; the first connection structure 120 includes a first connection portion 124 and a second connection portion 125, the first connection portion 124 being disposed in a first through hole, the second connection portion 125 being disposed in a second through hole, the first connection portion 124 being electrically connected to the first semiconductor layer 111, and the second connection portion 125 being electrically connected to the second semiconductor layer 113, the first connection portion 124 and the second connection portion 125 respectively passing through the first dielectric layer 130; the light-emitting structure portion 100 further includes a first conductive connection layer 140, the first conductive connection layer 140 being located between the first semiconductor layer 111 and the first connection portion 124, and electrically connecting the first semiconductor layer 111 and the first connection portion 124 respectively, for blocking at least part of the conductive material of the first connection portion 124 from diffusing.

[0092] In this configuration, the first semiconductor layer 111 is an N-type semiconductor layer, and the second semiconductor layer 113 is a P-type semiconductor layer; or the first semiconductor layer 111 is a P-type semiconductor layer, and the second semiconductor layer 113 is an N-type semiconductor layer. The N-type semiconductor layer may include n-GaN, and the P-type semiconductor layer may include p-GaN. The light-emitting layer 112 may be a quantum well layer, optionally a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.

[0093] In this embodiment, the first connection structure 120 includes a first connection portion 124 and a second connection portion 125. The first connection portion 124 is connected to the first semiconductor layer 111, and the second connection portion 125 is connected to the second semiconductor layer 113. The first connection portion 124 and the second connection portion 125 are insulated from each other. The first connection portion 124 is disposed in a first through hole, and the second connection portion 125 is disposed in a second through hole. Each light-emitting unit 110 is connected to one first connection portion 124, and each second connection portion 125 is connected to at least one second semiconductor layer 113 of the light-emitting unit 110. In some embodiments, the second semiconductor layer 113 of each light-emitting unit 110 is connected to one second connection portion 125; in other embodiments, to save space, the second semiconductor layers 113 of at least two light-emitting units 110 are connected to the same second connection portion 125. In this case, the second semiconductor layers 113 of different light-emitting units 110 are interconnected.

[0094] The first connecting portion 124 and the second connecting portion 125 can be connected to different second connecting structures 220 in the circuit structure portion 200. Optionally, the second connecting structure 220 includes a third connecting portion 224 and a fourth connecting portion 225. The third connecting portion 224 and the fourth connecting portion 225 are insulated from each other. The first connecting portion 124 is bonded to the third connecting portion 224, and the second connecting portion 125 is bonded to the fourth connecting portion 225.

[0095] refer to Figure 3 In this embodiment, the light-emitting structure 100 further includes a first conductive connection layer 140. A first conductive connection layer 140 is disposed between the first semiconductor layer 111 of each light-emitting unit 110 and the corresponding first connection portion 124, electrically connecting the first semiconductor layer 111 and the first connection portion 124. The first conductive connection layer 140 can block the diffusion of at least a portion of the conductive material in the first connection portion 124, for example, preventing the material of the connecting pillars in the first connection portion 124 from diffusing to the light-emitting unit 110 or other structural layers in the light-emitting chip, further reducing electrical failures of the light-emitting chip and improving its yield and reliability. The first conductive connection layer 140 can also act as a light reflector, reflecting light emitted from the light-emitting unit 110 to the outside of the light-emitting chip, thereby increasing the light output of the light-emitting chip. Furthermore, the first conductive connection layer 140 can also serve as an etching stop layer during the formation of the first via, preventing over-etching during the formation of the first via from damaging the light-emitting unit 110. Optionally, the material of the first conductive interconnect layer 140 is TiN.

[0096] Continue to refer to Figure 3Optionally, the light-emitting unit 110 further includes a first ohmic contact layer 152, which is located between the first semiconductor layer 111 and the first conductive connection layer 140. Optionally, the material of the first ohmic contact layer 152 is a transparent metal oxide, such as indium tin oxide. In some embodiments, the light-emitting unit 110 further includes a reflective metal layer 151, which is located between the first ohmic contact layer 152 and the first conductive connection layer 140. The reflective metal layer 151 can reflect the light emitted by the light-emitting unit 110 to the outside of the light-emitting chip, increasing the light output of the light-emitting chip. Optionally, the material of the reflective metal layer 151 is aluminum, copper, or gold.

[0097] In some embodiments, the diffusion barrier layer of the second connection portion 125 is also located at the bottom of the second through hole, and the connecting post of the second connection portion 125 is electrically connected to the second semiconductor layer 113 through the diffusion barrier layer at the bottom of the second through hole.

[0098] Optionally, the adhesion layer and seed layer are also located at the bottom of the second via. The adhesion layer and seed layer at the bottom of the second via are located between the diffusion barrier layer and the connecting post, with the seed layer located between the adhesion layer and the connecting post. In this way, the second semiconductor layer 113 is connected to the first connecting post 122 through the diffusion barrier layer, the adhesion layer, and the seed layer. By providing a diffusion barrier layer at the bottom of the second via, the conductive material of the second connecting post 222 can be prevented from diffusing outward from the bottom of the second via, further reducing electrical failures caused by the outward diffusion of the conductive material of the connecting post, and further improving the yield and reliability of the light-emitting chip.

[0099] refer to Figure 3 Optionally, the light-emitting chip also includes a second ohmic contact layer 192, which is located between the second connection portion 125 and the second semiconductor layer 113, so that the second connection portion 125 and the second semiconductor layer 113 form a more effective electrical connection through the second ohmic contact layer 192.

[0100] Continue to refer to Figure 3 Optionally, the light-emitting structure 100 further includes a third dielectric layer 160, which is located between the light-emitting unit 110 and the first dielectric layer 130, and covers the sidewall of the light-emitting unit 110; the first through hole and the second through hole respectively penetrate the first dielectric layer 130 and the third dielectric layer 160; the first connecting part 124 and the second connecting part 125 respectively include a first diffusion barrier layer 121 and a first connecting post 122, the first diffusion barrier layer 121 surrounds the first connecting post 122, and the first diffusion barrier layer 121 is used to block the conductive material of the first connecting post 122 from diffusing to the third dielectric layer 160 and the light-emitting unit 110.

[0101] The third dielectric layer 160 is an insulating dielectric layer, and its material differs from that of the first dielectric layer 130. Optionally, the material of the third dielectric layer 160 may include SiO2. In some embodiments, the first dielectric layer 130 is more compact than the third dielectric layer 160, allowing the first dielectric layer 130 to prevent the conductive material of the first connecting post 122 from entering the third dielectric layer 160, thereby avoiding electrical failure caused by a change in the dielectric constant of the material in the third dielectric layer 160.

[0102] In some embodiments, for conductive materials whose diffusion needs to be blocked, the diffusion coefficient of the first dielectric layer 130 is lower than that of the third dielectric layer 160. For example, if the conductive material whose diffusion needs to be blocked is copper, then the copper diffusion coefficient of the first dielectric layer 130 is lower than that of the third dielectric layer 160, thereby enabling the first dielectric layer 130 to block copper diffusion, preventing copper from entering the third dielectric layer 160 through the first dielectric layer 130, and avoiding electrical failure caused by copper diffusion to the third dielectric layer 160.

[0103] In this embodiment, the first connecting part 124 is disposed in the first through hole, and the second connecting part 125 is disposed in the second through hole. The first through hole and the second through hole respectively penetrate the first dielectric layer 130 and the third dielectric layer 160. The first connecting part 124 and the second connecting part 125 respectively include a first diffusion barrier layer 121 and a first connecting post 122. The first diffusion barrier layer 121 can prevent the conductive material of the first connecting post 122 from diffusing to the third dielectric layer 160 and the light-emitting unit 110, thereby preventing the light-emitting structure part 100 from failing due to the diffusion of the conductive material of the first connecting post 122.

[0104] Optionally, the thickness of the first dielectric layer 130 is lower than the thickness of the third dielectric layer 160. This setting ensures that the thickness of the light-emitting chip will not be too large after the first dielectric layer 130 is added to the light-emitting chip, thereby achieving miniaturization of the light-emitting chip.

[0105] Continue to refer to Figure 3 Optionally, the third dielectric layer 160 includes a first sub-dielectric layer 161 and a second sub-dielectric layer 162, with the second sub-dielectric layer 162 located between the first sub-dielectric layer 161 and the first dielectric layer 130; the light-emitting structure 100 also includes a sidewall reflective layer 170, with the sidewall reflective layer 170 located at least between the first sub-dielectric layer 161 and the second sub-dielectric layer 162 on the sidewall of the light-emitting unit 110.

[0106] Optionally, the first sub-dielectric layer 161 and the second sub-dielectric layer 162 are made of the same material. During the fabrication of the light-emitting chip, after the light-emitting unit 110 is formed, the first sub-dielectric layer 161 is formed on the light-emitting unit 110. Then, a sidewall reflective layer 170 is formed on the side of the first sub-dielectric layer 161 away from the light-emitting unit 110. The sidewall reflective layer 170 can be made of a metallic material and can be used to reflect the light emitted from the light-emitting unit 110 to the outside of the light-emitting unit 110 or the light-emitting chip, thereby increasing the light output of the light-emitting chip. In some embodiments, the sidewall reflective layer 170 includes a main body 171, a first overlapping portion 172, and a second overlapping portion 173. The main body 171 is located between the first sub-dielectric layer 161 and the second sub-dielectric layer 162 on the sidewall of the light-emitting unit 110. The first overlapping portion 172 overlaps with the main body 171 on the side of the first dielectric layer 130 away from the light-emitting unit 110. The second overlapping portion 173 overlaps with the main body 171 on the side of the light-emitting unit 110.

[0107] In some embodiments, the sidewall reflective layer 170 can be prepared in the same process step as the second ohmic contact layer 192, and the materials of the sidewall reflective layer 170 and the second ohmic contact layer 192 can be the same.

[0108] Continue to refer to Figure 3 Optionally, the circuit structure portion 200 further includes a fourth dielectric layer 240 and a second conductive connection layer 250; the fourth dielectric layer 240 is located between the circuit layer 210 and the second dielectric layer 230, and the second connection structure 220 passes through the second dielectric layer 230 and the fourth dielectric layer 240 respectively; the second conductive connection layer 250 is located between the second connection structure 220 and the circuit layer 210, and electrically connects the second connection structure 220 and the circuit layer 210 respectively; the second conductive connection layer 250 is used to block at least a portion of the conductive material of the second connection structure 220 from diffusing.

[0109] The fourth dielectric layer 240 is an insulating dielectric layer, and its material differs from that of the second dielectric layer 230. Optionally, the material of the fourth dielectric layer 240 includes SiO2. In some embodiments, the second dielectric layer 230 is more compact than the fourth dielectric layer 240, allowing the second dielectric layer 230 to prevent the conductive material of the first connecting post 122 from entering the fourth dielectric layer 240, thereby preventing electrical failure caused by a change in the dielectric constant of the fourth dielectric layer 240 material. Optionally, the circuit structure portion 200 may further include a metal layer 260 for enhancing connection conductivity, the material of which includes Ti and / or Al.

[0110] In some embodiments, for conductive materials whose diffusion needs to be blocked, the diffusion coefficient of the second dielectric layer 230 is lower than that of the fourth dielectric layer 240. For example, if the conductive material whose diffusion needs to be blocked is copper, then the copper diffusion coefficient of the second dielectric layer 230 is lower than that of the fourth dielectric layer 240, thereby enabling the second dielectric layer 230 to block copper diffusion. This prevents copper from passing through the second dielectric layer 230 into the fourth dielectric layer 240, avoiding electrical failure caused by copper diffusion into the fourth dielectric layer 240.

[0111] Optionally, the second connection structure 220 includes a third connection portion 224 and a fourth connection portion 225. The third connection portion 224 is disposed in the third through hole, and the fourth connection portion 225 is disposed in the fourth through hole. The third through hole and the fourth through hole respectively penetrate the second dielectric layer 230 and the fourth dielectric layer 240. The third connection portion 224 and the fourth connection portion 225 respectively include a second diffusion barrier layer 221 and a second connecting post 222. The second diffusion barrier layer 221 can prevent the conductive material of the second connecting post 222 from diffusing to the fourth dielectric layer 240, thereby preventing the circuit structure portion 200 from failing due to the diffusion of the conductive material of the first connecting post 122.

[0112] Optionally, the thickness of the second dielectric layer 230 is lower than the thickness of the fourth dielectric layer 240. This setting ensures that the thickness of the light-emitting chip will not be too large after the second dielectric layer 230 is added to the light-emitting chip, thereby achieving miniaturization of the light-emitting chip.

[0113] Continue to refer to Figures 1-3 The surface of the first connecting structure 120 near the circuit structure portion 200 is flush with the surface of the first dielectric layer 130 near the circuit structure portion 200; and / or, the surface of the second connecting structure 220 near the light-emitting structure portion 100 is flush with the surface of the second dielectric layer 230 near the light-emitting structure portion 100. This arrangement ensures good surface flatness for the bonding between the light-emitting structure portion 100 and the circuit structure portion 200, allowing for effective bonding of the first connecting structure 120 and the second connecting structure 220, as well as effective bonding of the first dielectric layer 130 and the second dielectric layer 230. This ensures that there are no gaps between the light-emitting structure portion 100 and the circuit structure portion 200 after bonding, guaranteeing the reliability of the bonding between them.

[0114] In some embodiments, the first dielectric layer 130 and the second dielectric layer 230 are made of the same material. This allows for a more reliable connection at the bonding interface when the first dielectric layer 130 and the second dielectric layer 230 are bonded together, ensuring the robustness and reliability of the light-emitting chip structure.

[0115] In some embodiments, the first connection structure 120 and the second connection structure 220 are made of the same material. This allows for a more reliable connection at the bonding interface when the first connection structure 120 and the second connection structure 220 are bonded together, resulting in a more reliable electrical connection and thus ensuring the light-emitting effect of the light-emitting chip.

[0116] This invention also provides a method for fabricating a light-emitting chip. Figure 4 This is a flowchart of a method for fabricating a light-emitting chip according to an embodiment of the present invention, see reference. Figure 4 The method for fabricating this light-emitting chip includes:

[0117] S310, Forming a light-emitting structure; wherein the light-emitting structure includes at least one light-emitting unit, a first connecting structure and a first dielectric layer, the first connecting structure being electrically connected to the light-emitting unit; the first dielectric layer being located on one side of the light-emitting unit, and the first connecting structure passing through the first dielectric layer.

[0118] S320. Forming a circuit structure portion; wherein the circuit structure portion includes a circuit layer, a second connection structure, and a second dielectric layer, the second connection structure passing through the second dielectric layer, and the second connection structure being electrically connected to the circuit layer.

[0119] S330. The light-emitting structure and the circuit structure are bonded together to achieve the bonding connection between the first connection structure and the second connection structure, and the bonding connection between the first dielectric layer and the second dielectric layer.

[0120] The first dielectric layer and / or the second dielectric layer are used to block at least a portion of the conductive material of the connection structure from diffusing; the connection structure includes at least one of the first connection structure and the second connection structure.

[0121] The method for preparing the light-emitting chip according to the embodiments of the present invention is used to prepare the light-emitting chip of any of the above embodiments of the present invention, and has the beneficial effects of the light-emitting chip of any of the embodiments of the present invention, which will not be repeated here.

[0122] Figure 5 This is a flowchart of another method for fabricating a light-emitting chip provided in an embodiment of the present invention, see reference. Figure 5 The method for fabricating this light-emitting chip includes:

[0123] S410. A first dielectric layer is prepared on the side of the third dielectric layer of the first intermediate structure away from the first substrate to form a second intermediate structure; wherein, the first intermediate structure includes a first substrate, at least one light-emitting unit on one side of the first substrate, and a third dielectric layer covering the light-emitting unit, and the light-emitting unit includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked together.

[0124] The first intermediate structure is the structure formed before the light-emitting structure is formed during the fabrication of the light-emitting chip. Optionally, the first intermediate structure is formed before S410, and the process of forming the first intermediate structure includes S401, S402 and S403.

[0125] S401. A first conductive connection layer is prepared on the side of the epitaxial wafer away from the first substrate to form an epitaxial structure layer.

[0126] Figure 6 This is a schematic diagram of the formed epitaxial structure layer, for reference. Figure 6 Optionally, the epitaxial structure layer includes a first substrate 180, a second semiconductor layer 113, a light-emitting layer 112, and a first semiconductor layer 111 stacked on one side of the first substrate 180. A first conductive connection layer 140 is located on the side of the first semiconductor layer 111 away from the first substrate 180. Optionally, the epitaxial structure layer further includes a first ohmic contact layer 152 and a reflective metal layer 151, wherein both the first ohmic contact layer 152 and the reflective metal layer 151 are located between the first conductive connection layer 140 and the first semiconductor layer 111, and the reflective metal layer 151 is located between the first conductive connection layer 140 and the first ohmic contact layer 152.

[0127] S402. Pattern the epitaxial structure layer to form multiple light-emitting units.

[0128] Figure 7 This is a schematic diagram of the structure after multiple light-emitting units have been formed. (Refer to...) Figure 6 and Figure 7 Optional, for Figure 6 The epitaxial structure layer shown is formed using photolithography and etching processes. Figure 7 Multiple light-emitting units 110 are shown. When patterning the epitaxial structure layer, it is possible to... Figure 6 The first conductive connection layer 140, reflective metal layer 151, first ohmic contact layer 152, first semiconductor layer 111, and light-emitting layer 112 of the epitaxial structure layer shown are patterned, and the first conductive connection layer 140, reflective metal layer 151, first ohmic contact layer 152, first semiconductor layer 111, and light-emitting layer 112, excluding the light-emitting units 110, are removed. The second semiconductor layer 113 may not be patterned, or a portion of its thickness may be patterned to ensure that the first semiconductor layers 111 of each light-emitting unit 110 can be interconnected.

[0129] S403. A third dielectric layer is formed on the side of the light-emitting unit away from the first substrate, forming a first intermediate structure.

[0130] Figure 8 This is a structural diagram of the first intermediate structure, for reference. Figure 8The third dielectric layer 160 can be formed by deposition, and it serves to passivate and protect the light-emitting unit 110. (Reference) Figure 8 The third dielectric layer 160 may include a first sub-dielectric layer 161 and a second sub-dielectric layer 162, wherein the first sub-dielectric layer 161 is formed before the second sub-dielectric layer 162. Figure 9 This is a schematic diagram of the structure after the formation of the first sub-dielectric layer. Optionally, after forming multiple light-emitting units 110, a first sub-dielectric layer 161 is formed on the side of the multiple light-emitting units 110 away from the first substrate 180. The first sub-dielectric layer 161 can serve as a passivation and protection for the light-emitting units 110. Subsequently, the first sub-dielectric layer 161 is patterned, for example, by using photolithography and etching processes to form vias for fabricating the second ohmic contact layer 192 in the first sub-dielectric layer 161. Figure 10 This is a schematic diagram of the structure after a via is formed on the first sub-dielectric layer. Then, the second ohmic contact layer 192 is formed in the via during the fabrication of the second ohmic contact layer 192. Figure 11 This is a schematic diagram of the structure after the formation of the second ohmic contact layer. The sidewall reflective layer 170 can be formed simultaneously with or after the formation of the second ohmic contact layer 192. Figure 12 This is a schematic diagram of the structure after the sidewall reflective layer has been formed. (See reference) Figure 12 The sidewall reflective layer 170 is located on one side of the first sub-dielectric layer 161 on the sidewall of the light-emitting unit 110. Optionally, the sidewall reflective layer 170 further includes a first overlap portion 172 located on the surface of the first sub-dielectric layer 161 away from the light-emitting unit 110, and a second overlap portion 173 between adjacent light-emitting units 110. The second ohmic contact layer 192 and the sidewall reflective layer 170 can be formed using a lift-off process or a photolithography etching process. Figure 12 The structure shown forms a second sub-dielectric layer 162 on the side away from the first substrate 180, forming... Figure 8 The second sub-dielectric layer 162 of the first intermediate structure shown can be formed by a deposition process. Optionally, after forming the second sub-dielectric layer 162, the surface of the second sub-dielectric layer 162 away from the first substrate 180 is planarized. Then, a first dielectric layer 130 is formed on the side of the third dielectric layer 160 of the first intermediate structure away from the first substrate 180 to form the second intermediate structure.

[0131] S420. The second intermediate structure is patterned to form a first via and a second via. The first via is located on the side of the first semiconductor layer away from the first substrate, and the second via is located on the side of the second semiconductor layer away from the first substrate. The first via and the second via penetrate the first dielectric layer and the third dielectric layer, respectively.

[0132] Figure 13This is a graphical representation of the second intermediate structure. (See reference) Figure 13 The second intermediate structure is patterned to form a first via L1 and a second via L2. When forming the first via L1, etching stops at the first conductive connection layer 140. The first conductive connection layer 140 serves as an etching stop layer for forming the first via, preventing damage to the light-emitting unit 110 caused by over-etching when forming the first via L1.

[0133] S430, A first connecting portion is formed in a first through hole, and a second connecting portion is formed in a second through hole; the first connecting structure includes a first connecting portion and a second connecting portion.

[0134] Figure 14 This is a structural diagram showing the structure after the first connecting part and the second connecting part are formed, combined with... Figure 13 and Figure 14 When a first connection portion 124 is formed in the first through-hole L1 and a second connection portion 125 is formed in the second through-hole L2, the materials of the first connection portion 124 and the second connection portion 125 may be formed on the side of the first dielectric layer 130 away from the substrate. During this process, the first dielectric layer 130 can prevent the conductive materials of the first connection portion 124 and the second connection portion 125 from diffusing to the third dielectric layer 160 and the light-emitting unit 110. In this step, a planarization process can be performed to remove the conductive materials of the first connection portion 124 and the second connection portion 125 on the side of the first dielectric layer 130 away from the first substrate 180. The planarization process stops at the first dielectric layer 130, that is, after the planarization process, the side of the first dielectric layer 130 away from the first substrate 180 does not contain conductive materials.

[0135] Optionally, a TaN / Ta / Cu electroplated Cu seed layer is deposited in the first and second vias, wherein TaN serves as a Cu diffusion barrier layer, Ta as an adhesion layer, and Cu as the electroplating seed layer. Subsequently, a Cu metal filler layer is electroplated, and a planarization process is used to remove the metal outside the vias, thus achieving metal filling of the first and second vias.

[0136] S440. Forming a circuit structure portion; wherein the circuit structure portion includes a circuit layer, a second connection structure, and a second dielectric layer, the second connection structure passes through the second dielectric layer and is electrically connected to the circuit layer; the second connection structure is bonded to the first connection structure, and the first dielectric layer is bonded to the second dielectric layer.

[0137] S450. The light-emitting structure and the circuit structure are bonded together to achieve the bonding connection between the first connection structure and the second connection structure, and the bonding connection between the first dielectric layer and the second dielectric layer.

[0138] Figure 15 This is a flowchart of another method for fabricating a light-emitting chip provided in an embodiment of the present invention, see reference. Figure 15 The method for fabricating this light-emitting chip includes:

[0139] S510, Forming a light-emitting structure; wherein the light-emitting structure includes at least one light-emitting unit, a first connecting structure and a first dielectric layer, the first connecting structure being electrically connected to the light-emitting unit; the first dielectric layer being located on one side of the light-emitting unit, and the first connecting structure passing through the first dielectric layer.

[0140] S520. A second dielectric layer is prepared on the side of the fourth dielectric layer of the third intermediate structure away from the second substrate to form a fourth intermediate structure; wherein, the third intermediate structure includes a second substrate, a circuit layer and a fourth dielectric layer, and the fourth dielectric layer is located on the side of the circuit layer away from the second substrate.

[0141] The third intermediate structure is the structure formed before the circuit structure is formed during the fabrication of the light-emitting chip. Optionally, the third intermediate structure is formed before S510, and the process of forming the third intermediate structure includes S501 and S502.

[0142] S501. A second conductive interconnect layer is prepared on the side of the backplane wafer away from the second substrate, where the circuit layer is located.

[0143] Figure 16 This is a schematic diagram of the structure after the second conductive interconnect layer is formed. (Refer to...) Figure 16 The backplane wafer may include a second substrate 270 and a circuit layer 210 on one side of the second substrate 270, with a second conductive connection layer 250 formed on the side of the circuit layer 210 away from the second substrate 270. Optionally, before forming the second conductive connection layer 250, a redistribution layer may be formed on the side of the circuit layer 210 of the backplane wafer away from the second substrate 270, such that the driving circuit of the circuit layer 210 can be electrically connected to the light-emitting unit 110 of the light-emitting structure 100. Optionally, a metal layer 260 for enhancing the conductivity of the connection may be formed between the redistribution layer and the second conductive connection layer 250, the material of which may include Ti or Al.

[0144] S502, a fourth dielectric layer is formed on the side of the second conductive connection layer away from the second substrate to form a third intermediate structure.

[0145] Figure 17 This is a structural diagram of the third intermediate structure, for reference. Figure 17 The fourth dielectric layer 240 can be formed by deposition, and then a planarization process can be used to planarize the side of the fourth dielectric layer 240 away from the second substrate 270.

[0146] Figure 18 This is a structural diagram of the fourth intermediate structure. (See reference) Figure 17 and Figure 18After forming the third intermediate structure, a second dielectric layer 230 is prepared on the side of the fourth dielectric layer 240 of the third intermediate structure away from the second substrate 270 to form the fourth intermediate structure. The second dielectric layer 230 can be formed by deposition.

[0147] S530. The fourth intermediate structure is patterned to form a third through hole and a fourth through hole; the third through hole and the fourth through hole penetrate the second dielectric layer and the fourth dielectric layer, respectively.

[0148] Figure 19 This is a schematic diagram of the structure after the formation of the third and fourth vias. The fourth intermediate structure is graphically represented. During the formation of the third via L3 and the fourth via L4, etching stops at the second conductive interconnect layer 250. The second conductive interconnect layer 250 serves as an etching stop layer for the formation of the third via L3 and the fourth via L4, preventing over-etching that could damage the circuit layer 210.

[0149] S540. A third connecting portion is formed in the third through hole, and a fourth connecting portion is formed in the fourth through hole.

[0150] The second connection structure 220 includes a third connection portion 224 and a fourth connection portion 225. Figure 20 This is a structural diagram forming the third and fourth connecting parts. (Combined with...) Figure 19 and Figure 20 When a third connection portion 224 is formed in the third via L3 and a fourth connection portion 225 is formed in the fourth via L4, the materials of the third connection portion 224 and the fourth connection portion 225 may be formed on the side of the second dielectric layer 230 away from the second substrate 270. During this process, the second dielectric layer 230 can prevent the conductive materials of the third connection portion 224 and the fourth connection portion 225 from diffusing to the fourth dielectric layer 240 and the circuit layer 210. In this step, a planarization process can be performed to remove the conductive materials of the third connection portion 224 and the fourth connection portion 225 on the side of the second dielectric layer 230 away from the second substrate 270. The planarization process stops at the second dielectric layer 230; that is, after the planarization process, the side of the second dielectric layer 230 away from the second substrate 270 does not contain conductive material.

[0151] Optionally, a TaN / Ta / Cu electroplated Cu seed layer is deposited in the third and fourth vias, where TaN serves as a Cu diffusion barrier layer, Ta as an adhesion layer, and Cu as the electroplating seed layer. Subsequently, a Cu metal filler layer is electroplated, and a planarization process is used to remove the metal outside the vias, thus achieving metal filling of the third and fourth vias.

[0152] S550, The light-emitting structure and the circuit structure are bonded together to achieve the bonding connection between the first connection structure and the second connection structure, and the bonding connection between the first dielectric layer and the second dielectric layer.

[0153] Figure 21 This is a schematic diagram of the structure after the light-emitting structure 100 and the circuit structure 200 are bonded together. The light-emitting structure 100 and the circuit structure 200 are bonded using a hybrid bonding method. Afterwards, the first substrate 180 of the light-emitting structure 100 can be thinned or removed to obtain... Figure 3 The light-emitting chip shown.

[0154] Figure 22 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention, for reference. Figure 22 Optionally, the light-emitting chip also includes an arc-shaped lens structure 300, with a lens structure 300 corresponding to the light-emitting side of each light-emitting unit 110 to improve light-emitting efficiency.

[0155] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0156] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A light-emitting chip, characterized in that, include: Light-emitting structure and circuit structure; The light-emitting structure includes at least one light-emitting unit, a first connection structure, and a first dielectric layer, wherein the first connection structure is electrically connected to the light-emitting unit. The first dielectric layer is located on one side of the light-emitting unit, and the first connection structure passes through the first dielectric layer; The circuit structure includes a circuit layer, a second connection structure, and a second dielectric layer. The second dielectric layer is located on one side of the circuit layer, the second connection structure passes through the second dielectric layer, and the second connection structure is electrically connected to the circuit layer. The second connection structure is bonded to the first connection structure, and the first dielectric layer is bonded to the second dielectric layer; Wherein, the first dielectric layer and / or the second dielectric layer are used to block at least a portion of the conductive material of the connection structure from diffusing; the connection structure includes at least one of the first connection structure and the second connection structure.

2. The light-emitting chip according to claim 1, characterized in that, The connection structure is located in the through hole. The connection structure includes a diffusion barrier layer and a connecting post. The diffusion barrier layer is located on the sidewall of the through hole and surrounds the connecting post, and is used to prevent the conductive material of the connecting post from diffusing out of the through hole.

3. The light-emitting chip according to claim 2, characterized in that, The connection structure further includes an adhesion layer and a seed layer, the adhesion layer and the seed layer being located between the diffusion barrier layer and the connecting post, the seed layer being located between the adhesion layer and the connecting post, the adhesion layer surrounding the seed layer, the seed layer surrounding the connecting post, and the material of the seed layer being the same as the material of the connecting post.

4. The light-emitting chip according to claim 2, characterized in that, The light-emitting unit includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked together; the first connection structure includes a first connection portion and a second connection portion, the first connection portion being disposed in a first through hole, the second connection portion being disposed in a second through hole, the first connection portion being electrically connected to the first semiconductor layer, the second connection portion being electrically connected to the second semiconductor layer, and the first connection portion and the second connection portion respectively passing through the first dielectric layer; The light-emitting structure further includes a first conductive connection layer, which is located between the first semiconductor layer and the first connection portion and electrically connects the first semiconductor layer and the first connection portion respectively, for blocking at least a portion of the conductive material of the first connection portion from diffusing. And / or, the diffusion barrier layer of the second connection portion is also located at the bottom of the second via, and the connecting post of the second connection portion is electrically connected to the second semiconductor layer through the diffusion barrier layer at the bottom of the second via.

5. The light-emitting chip according to claim 4, characterized in that, The light-emitting structure further includes a third dielectric layer, which is located between the light-emitting unit and the first dielectric layer, and the third dielectric layer covers the sidewall of the light-emitting unit; The first through-hole and the second through-hole respectively penetrate the first dielectric layer and the third dielectric layer; The first connecting portion and the second connecting portion each include a first diffusion barrier layer and a first connecting post. The first diffusion barrier layer surrounds the first connecting post and is used to prevent the conductive material of the first connecting post from diffusing to the third dielectric layer and the light-emitting unit.

6. The light-emitting chip according to claim 5, characterized in that, The third dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, wherein the second sub-dielectric layer is located between the first sub-dielectric layer and the first dielectric layer; The light-emitting structure further includes a sidewall reflective layer, which is located at least between the first sub-dielectric layer and the second sub-dielectric layer of the sidewall of the light-emitting unit.

7. The light-emitting chip according to claim 2, characterized in that, The circuit structure also includes a fourth dielectric layer and a second conductive connection layer. The fourth dielectric layer is located between the circuit layer and the second dielectric layer, and the second connection structure passes through the second dielectric layer and the fourth dielectric layer respectively; The second conductive connection layer is located between the second connection structure and the circuit layer, and is electrically connected to the second connection structure and the circuit layer respectively; The second conductive connection layer is used to block at least a portion of the conductive material of the second connection structure from diffusing.

8. The light-emitting chip according to claim 1, characterized in that, The surface of the first connection structure near the circuit structure portion is flush with the surface of the first dielectric layer near the circuit structure portion; and / or... The surface of the second connecting structure near the light-emitting structure is flush with the surface of the second dielectric layer near the light-emitting structure.

9. The light-emitting chip according to claim 1, characterized in that, The first dielectric layer and the second dielectric layer are made of the same material; and / or, the first connection structure is made of the same material as the second connection structure.

10. The light-emitting chip according to claim 1, characterized in that, The material of the first dielectric layer includes at least one of SiN and SiCN; and / or, the material of the second dielectric layer includes at least one of SiN and SiCN.

11. A method for fabricating a light-emitting chip, characterized in that, include: A light-emitting structure is formed; wherein the light-emitting structure includes at least one light-emitting unit, a first connecting structure and a first dielectric layer, the first connecting structure being electrically connected to the light-emitting unit; the first dielectric layer is located on one side of the light-emitting unit, and the first connecting structure passes through the first dielectric layer; A circuit structure is formed; wherein the circuit structure includes a circuit layer, a second connection structure, and a second dielectric layer, the second connection structure passes through the second dielectric layer, and the second connection structure is electrically connected to the circuit layer; The light-emitting structure is bonded to the circuit structure to achieve the bonding connection between the first connection structure and the second connection structure, and the bonding connection between the first dielectric layer and the second dielectric layer. Wherein, the first dielectric layer and / or the second dielectric layer are used to block at least a portion of the conductive material of the connection structure from diffusing; the connection structure includes at least one of the first connection structure and the second connection structure.

12. The method for preparing a light-emitting chip according to claim 11, characterized in that, The formation of the light-emitting structure includes: The first dielectric layer is prepared on the side of the third dielectric layer of the first intermediate structure away from the first substrate to form a second intermediate structure; wherein, the first intermediate structure includes a first substrate, at least one light-emitting unit on one side of the first substrate, and the third dielectric layer covering the light-emitting unit, and the light-emitting unit includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked together. The second intermediate structure is patterned to form a first via and a second via; the first via is located on the side of the first semiconductor layer away from the first substrate, and the second via is located on the side of the second semiconductor layer away from the first substrate; the first via and the second via penetrate the first dielectric layer and the third dielectric layer, respectively. A first connecting portion is formed in the first through hole, and a second connecting portion is formed in the second through hole; The first connection structure includes a first connection portion and a second connection portion.

13. The method for preparing a light-emitting chip according to claim 12, characterized in that, Before forming the second intermediate structure by fabricating the first dielectric layer on the side of the third dielectric layer of the first intermediate structure away from the first substrate, the method further includes: A first conductive interconnect layer is prepared on the side of the epitaxial wafer away from the first substrate to form an epitaxial structure layer; The epitaxial structure layer is patterned to form multiple light-emitting units; A third dielectric layer is formed on the side of the light-emitting unit away from the first substrate, forming the first intermediate structure; When the second intermediate structure is patterned to form the first through-hole, the etching stops at the first conductive connection layer.

14. The method for preparing a light-emitting chip according to claim 11, characterized in that, The circuit structure portion includes: The second dielectric layer is fabricated on the side of the fourth dielectric layer of the third intermediate structure away from the second substrate to form the fourth intermediate structure; wherein, the third intermediate structure includes a second substrate, a circuit layer and a fourth dielectric layer, and the fourth dielectric layer is located on the side of the circuit layer away from the second substrate; The fourth intermediate structure is patterned to form a third through hole and a fourth through hole; the third through hole and the fourth through hole respectively penetrate the second dielectric layer and the fourth dielectric layer; A third connecting portion is formed in the third through hole, and a fourth connecting portion is formed in the fourth through hole; The second connection structure includes a third connection part and a fourth connection part.

15. The method for preparing a light-emitting chip according to claim 14, characterized in that, Before forming the fourth dielectric layer of the third intermediate structure on the side away from the second substrate, the method further includes: A second conductive interconnect layer is prepared on the side of the circuit layer of the backplane wafer away from the second substrate; The fourth dielectric layer is formed on the side of the second conductive connection layer away from the second substrate to form the third intermediate structure; When the fourth intermediate structure is patterned to form the third and fourth through holes, the etching stops at the second conductive connection layer.

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