Microstructured IC chip

Abstract

The invention relates to an IC chip having an IC substrate (100), at least one IC functional layer (110) on the substrate, and an etched hole (130) which penetrates the IC functional layer from an outer side (111) to the substrate. The core of the invention is that a metal seal (120) is arranged between the region of the IC functional layer and the etched hole.

Description

TECHNICAL FIELD

[0001] The invention is based on an IC chip having an IC substrate and at least one IC functional layer. In the IC functional layer there is at least one etched hole of arbitrary geometry. BACKGROUND

[0002] IC chips are usually composed of a series of different functional layers, for example silicon oxide or silicon nitride. The choice of material and the way in which the IC functional layer is produced, as well as the material lying beneath it, all influence the crystal properties of the functional layer. The IC functional layer has a changed crystal structure due to variations in the intrinsic lattice constant. These distortions are partially relieved by crystal defects, but intrinsic stresses always remain in the layer. This intrinsic stress can in addition be changed by the influence of temperature or the application of additional functional layers in subsequent production processes. The intrinsic stress of the IC functional layer can be relieved when the layer is subsequently structured over a large area and uniformly. If the IC functional layer is structured locally, the structuring can act as a weak point or defect, thereby uncontrolledly reducing the layer tension. Defects, delaminations and cracks can thereby arise, which can also spread to deeper layers and cause irreparable damage to the component. SUMMARY

[0003] The task of the invention is to integrate a sealed and mechanically or crystallographically decoupled structure in the IC functional layer in order to prevent the spreading of defects, delaminations or cracks around the locally structured region.

[0004] The invention is based on an IC chip having an IC substrate and at least one functional layer. In the functional layer there is at least one etched hole of arbitrary geometry.

[0005] The core of the invention is that the functional layer has a metal-filled structure which acts as a seal, in particular a sealing ring, and protects the locally structured region from the formation of defects, delaminations and cracks. The metal sealing ring can also have additional functions and for example act as an electrical contact between the IC chip and a MEMS chip, which is connected to the IC chip by a bonding process, or as a particle barrier.

[0006] The core of the invention is a metal sealing ring which acts as a vertical barrier preventing the spreading of defects caused by layer stresses in the IC functional layer. Etched holes of arbitrary size, shape and position can thereby be produced. In addition, the metal sealing ring can also have other functions such as electrical contacts or particle barriers.

[0007] The present invention advantageously allows for the prevention of defects, delamination, and cracks originating from locally structured areas, or the reduction of layer stress, by means of a metal-filled structure (metal sealing ring). If such defects are to form in the structured area, they only diffuse to the sealing ring and are prevented or reduced there. The metal sealing ring is particularly advantageous when the coating undergoes further manufacturing processes (thereby inducing layer stress again by means of temperature or additional functional layers).

[0008] In an advantageous configuration of the invention, the metal sealing ring is located on the topmost layer of the IC chip and is electrically connected to the relevant potential of the IC chip. Therefore, electrical contacts can be created on the surface, for example, for the ground potential of the IC chip.

[0009] In an advantageous configuration of the invention, the metal sealing ring does not terminate flush with the IC functional layer, but rather has an elevated topography. If the IC chip is bonded to a MEMS chip with a cavity via a bonding process, the metal sealing ring can be advantageously utilized to locally adjust a defined distance between the surface of the MEMS chip and the surface of the metal sealing ring.

[0010] For example, this distance can be minimized to create regions within the cavity where gas exchange can occur, but particles larger than the distance between the sealing ring and the surface of the MEMS chip cannot be exchanged. If the etched hole surrounded by the metal sealing ring is used, for example, as an access port for a trench extending through the substrate of the IC chip (which extends through the substrate of the IC chip, allowing gas to enter the cavity and subsequently being sealed by laser melting), the metal sealing ring with its elevated terrain can additionally serve as a narrow section between the IC chip and the MEMS chip. This allows gas exchange between the external atmosphere and the cavity of the MEMS chip before sealing the trench and prevents particles from intruding into the MEMS chip, except through the etched hole, via the metal sealing ring. Attached Figure Description

[0011] Figure 1 a and Figure 1 b The IC chip according to the invention in the first and second embodiments is schematically shown, the IC chip having a metal sealing ring surrounding an etched hole.

[0012] Figure 2a and 2b The IC chip according to the invention in the third and fourth embodiments is schematically shown, the IC chip having a metal sealing ring that contacts a conductive layer located below it.

[0013] Figure 3 An IC chip according to the invention in the fifth embodiment is schematically shown, the IC chip including a metal sealing ring with a flange.

[0014] Figures 4a to 4d The IC chip according to the invention is illustrated schematically in other embodiments, the IC chip having a metal sealing ring that penetrates completely or partially through a multilayer IC functional layer system in different ways. Detailed Implementation

[0015] Figure 1 a and Figure 1 b The IC chip according to the invention in the first and second embodiments is schematically shown, the IC chip having a metal sealing ring surrounding an etched hole. Figure 1 a A top view and a cross-sectional view of the IC chip according to the invention in the first embodiment are schematically shown. The IC chip is shown having a substrate 100, at least one IC functional layer 110, and a rectangular etched hole 130. The etched hole is directly surrounded by a portion of the IC functional layer and indirectly surrounded by a similarly rectangular metal sealing ring 120.

[0016] Figure 1 b The IC chip according to the invention in the second embodiment is schematically shown in top and cross-sectional views. An IC chip having a substrate 100, at least one IC functional layer 110, and a rectangular etched hole 130 is shown. The etched hole is directly surrounded by a metal sealing ring 120, which is also rectangular.

[0017] The IC chip is, for example, an application-specific integrated circuit (ASIC). The layer system (including metal layers) of this integrated circuit is not shown in detail here, but rather summarized within the IC functional layers and the IC chip itself. As shown here, the etched holes can have rectangular or square outlines, but can also take any other possible shape. Metal sealing rings can completely or partially surround the etched holes in any shape and are, for example, filled with aluminum.

[0018] Figure 2a and Figure 2b The IC chip in the third and fourth embodiments of the present invention is schematically shown. The chip has a metal sealing ring that contacts a conductive layer disposed on the lower side.

[0019] Figure 2a A top view and a cross-sectional view of an IC chip according to the invention in a third embodiment are schematically shown. An IC chip having a substrate 100, at least one IC functional layer 110, and a rectangular etched hole 130 is shown. The etched hole is directly surrounded by a portion of the IC functional layer and indirectly surrounded by a rectangular metal sealing ring 120. The metal sealing ring is disposed in the outer IC functional layer. The sealing ring has conductive contacts on its underside that contact the conductive layer 140 located below. Electrical contact with the conductive layer 140 can be achieved from the outside through the outer contact surface 121 of the metal sealing ring 120.

[0020] Figure 2b A top view and a cross-sectional view of the IC chip according to the invention in the fourth embodiment are schematically shown. The etched hole 130 is directly surrounded by a metal sealing ring 120. The metal sealing ring 120 has conductive contacts on its underside that contact the conductive layer 140 located below.

[0021] Figure 3 An IC chip according to the invention in a fifth embodiment is schematically shown, the IC chip including a metal sealing ring with a flange. An IC chip having a substrate 100, at least one IC functional layer 110, and a rectangular etched hole 130 is shown. The etched hole 130 is directly surrounded by the metal sealing ring 120. The metal sealing ring 120 does not terminate flush with the uppermost IC functional layer 110 of the IC chip, but has a raised topographical position, i.e., a flange 122, compared to it. The metal sealing ring can be used to adjust the distance between the surface 201 of the MEMS chip 200 and the outer contact surface 121 on the upper side of the flange 122 of the metal sealing ring 120 if the IC chip is bonded to a MEMS chip 200 having a cavity.

[0022] For example, this distance can be minimized to create regions within the cavity where gas exchange can occur, but particles larger than the distance between the sealing ring and the surface of the MEMS chip cannot be exchanged. If the etched holes surrounded by the metal sealing ring are used, for example, as entry holes for trenches extending through the substrate of the IC chip and subsequently for laser sealing, the elevated metal sealing ring can serve as an additional function as a narrow section within the MEMS chip. This allows gas exchange between the external atmosphere and the cavity of the MEMS chip during laser sealing and prevents particles from intruding into the MEMS chip beyond the etched holes through the metal sealing ring.

[0023] Figures 4a to 4d The illustration schematically shows an IC chip according to the invention in another embodiment, the IC chip having a metal sealing ring that penetrates completely or partially through a multilayer IC functional layer system in different ways. Here, the IC chip has an IC functional layer system 150 consisting of multiple IC functional layers, and the metal sealing ring 120 may penetrate one, more, or all of the functional layers.

[0024] Figure 4a A cross-sectional view schematically illustrates an IC chip according to the present invention, which includes a substrate 100, an IC functional layer system 150 consisting of multiple IC functional layers, and etched vias 130. The etched vias are directly surrounded by a portion of the IC functional layer system and indirectly surrounded by a metal sealing ring 120. The metal seal penetrates the entire IC functional layer system to the substrate.

[0025] Figure 4bA schematic cross-sectional view is shown with Figure 4a Similarly, in the IC chip according to the present invention, the metal seal 120 only partially penetrates the IC layer system 150. Therefore, the metal sealing ring does not extend to the substrate 100.

[0026] Figure 4c A cross-sectional view schematically illustrates an IC chip according to the present invention, which has a substrate 100, an IC functional layer system 150 consisting of multiple IC functional layers, and etched vias 130. The etched vias are directly surrounded by a metal sealing ring 120. The metal seal extends through the entire IC functional layer system to the substrate.

[0027] Figure 4d A schematic cross-sectional view is shown with Figure 4c Similarly, in the IC chip according to the present invention, the metal seal 120 only partially defines the IC layer system 150 and the etched hole 130. Therefore, the metal sealing ring does not extend to the substrate 100, and a portion of the IC layer system is directly adjacent to the etched hole.

[0028] Other configurations may additionally include raised terrain for the metal seals, such as... Figure 3 The surface shown is in the form of a flange or includes, for example, a flange. Figure 2a and Figure 2b The conductive contacts are shown.

[0029] List of reference signs 100 IC chips 110 IC Functional Layer 111 Outer side 120 Metal Seals 121 External contact surface of metal seal 122 flange 130 Etched Hole 140 conductive layer A 150+ layer IC functional system 200 MEMS chips Surface of 201 MEMS chip

Claims

1. An IC chip having: IC substrate (100). At least one IC functional layer (110) on the substrate. An etched hole (130) penetrates the IC functional layer from the outside (111) to the substrate. Its features are, A metal seal (120) is arranged between the region of the IC functional layer and the etched hole.

2. The IC chip according to claim 1, characterized in that, The metal seal (120) surrounds the etched hole (130) as a sealing ring.

3. The IC chip according to claim 1 or 2, characterized in that, The metal seal (120) directly defines the etched hole (130).

4. The IC chip according to any one of claims 1 to 3, characterized in that, The metal seal (120) extends from the outer side (111) to the base (100).

5. The IC chip according to any one of claims 1 to 4, characterized in that, The metal seal (120) is electrically connected to the potential of the IC chip, especially the ground potential.

6. The IC chip according to any one of claims 1 to 5, characterized in that, The metal seal (120) has a flange (121) that extends beyond the outer side (111) of the IC functional layer (110).

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