Online upgrading method and device, electronic equipment, storage medium and program product

Abstract

The invention provides an online upgrading method and device, electronic equipment, a storage medium and a program product. The method comprises the steps that a first pin is set to be in a first level state, the first level state is the same as the state of a signal needing to be kept output when the programmable control device is upgraded, or operation exists between the first level state and the state of the signal output by the programmable control device, and the first level state is a high level; sending the upgrading file to the programmable control device, and obtaining state information of a state machine in the programmable control device; when the state information indicates that the programmable control device is upgraded, the first pin is set to be in a second level state, and the second level state is opposite to the output state needing to be kept when the programmable control device is upgraded. And the reliability of online upgrading of the programmable control device is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an online upgrade method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] With the widespread application of embedded systems in high-reliability fields such as industrial control, communication equipment and automotive electronics, the requirements for the reliability and continuity of equipment operation are increasing. In particular, as a core control unit, the Complex Programmable Logic Device (CPLD) needs to be upgraded while the equipment is running normally.

[0003] In related technologies, during CPLD upgrades, the controller can send an upgrade file to the CPLD via a communication bus, and the CPLD can perform the upgrade operation based on the received upgrade file.

[0004] However, during the CPLD upgrade process, the state transition of the state machine in the CPLD may cause the critical signals output by the CPLD to change instantaneously, which may lead to equipment interruption and other situations, resulting in low reliability of CPLD online upgrade. Summary of the Invention

[0005] This application provides an online upgrade method, apparatus, electronic device, storage medium, and program product to solve the technical problem of low reliability in CPLD online upgrades.

[0006] Firstly, this application provides an online upgrade method, including:

[0007] Set the first pin to a first level state. The first level state is the same as the signal state that needs to be maintained when the programmable controller is upgraded. The first level state and the signal state output by the programmable controller are ORed. The first level state is high.

[0008] Send upgrade files to the programmable controller and obtain the state information of the state machine in the programmable controller;

[0009] When the status information indicates that the programmable controller has completed the upgrade, the first pin is set to the second level state, which is the opposite of the output state that the programmable controller needs to maintain during the upgrade.

[0010] In this embodiment, by setting the first pin connecting the controller to the CPLD to the same first-level state as the signal state required to be maintained during CPLD upgrade, and performing an OR operation between this first-level state and the signal state output by the CPLD, an upgrade file is sent to the CPLD and the state information of its internal state machine is obtained. When the state information indicates that the upgrade is complete, the first pin is set to a second-level state opposite to the required maintained output state. In the above method, the electronic device can establish a reliable signal protection path during CPLD logic reconstruction by introducing a signal maintenance mechanism based on OR logic. When the first pin is set to the first level state, the circuit characteristics of OR logic ensure that the key signals output by the CPLD are forcibly maintained at an effective level, effectively avoiding signal jumps or interruptions caused by state machine reset. This ensures the continuous and stable operation of the controlled device during the upgrade process. Furthermore, by monitoring the operating status of the state machine, the timing of signal holding is precisely controlled. When the state machine is detected to have entered a stable operating state, the signal holding is released in a timely manner, and control is returned to the internal logic of the CPLD. This method not only ensures the stability of key signals during the upgrade process but also ensures that the system can quickly restore normal control logic after the upgrade is completed. In addition, this method uses a general-purpose GPIO interface combined with basic logic circuits, eliminating the need for complex dedicated hardware. It has the advantages of simple implementation and low cost, and can be flexibly applied to various embedded control systems, providing a reliable solution for online upgrades of CPLDs. While improving the reliability of online upgrades of CPLDs, it also enhances the stability and operational stability of the device.

[0011] Optionally, in the method described above, the first pin is a general-purpose input / output interface; setting the first pin to a first level state includes:

[0012] Obtain the current operating status, which is used to determine whether to upgrade the programmable controller;

[0013] When the operating status indicator is upgrading the programmable controller, the level state of the general-purpose input / output interface pins is set to the first level state.

[0014] In this embodiment of the application, by obtaining the current running status as the upgrade trigger condition, intelligent control of the upgrade process is realized, avoiding manual intervention and improving the accuracy of determining the upgrade timing.

[0015] Optionally, in the method described above, the upgrade file includes multiple data packets; sending the upgrade file to the programmable controller includes:

[0016] Send upgrade instructions to the programmable controller;

[0017] Receive the response message corresponding to the upgrade instruction sent by the programmable controller, and when the response message indicates that the programmable controller can be upgraded, send multiple data packets to the programmable controller in sequence.

[0018] In this embodiment of the application, by establishing a handshake protocol between upgrade instructions and response messages, data conflicts and transmission errors are effectively avoided, thereby improving the reliability and integrity of the upgrade process.

[0019] Optionally, the method described above is used to obtain the state information of the state machine in the programmable controller, including:

[0020] Determine the first duration, which is the duration required for the programmable controller to perform an upgrade based on the upgrade file;

[0021] After the first duration, the state information of the state machine in the programmable controller is obtained.

[0022] In this embodiment of the application, the accuracy and timeliness of status acquisition are ensured by setting the time required for CPLD upgrade and performing status monitoring.

[0023] Optionally, in the method described above, when the status information indicates that the programmable controller has completed the upgrade, setting the first pin to the second level state includes:

[0024] When the state machine is in the target state and the target state has been maintained for a second duration, the state information is determined to instruct the programmable controller to complete the upgrade.

[0025] Set the first pin to the second level state.

[0026] In this embodiment, by combining the dual judgment conditions of the target state and duration of the state machine, misjudgment caused by instantaneous state stability is effectively avoided, thereby improving the reliability of CPLD online upgrade.

[0027] Optionally, as described above, when the programmable controller is upgraded, it is necessary to keep the output signal state at a high level. When the programmable controller is upgraded, the output signal state of the programmable controller is ORed with the first level state to make the output signal state of the CPLD at a high level.

[0028] In this embodiment, by clearly defining that the CPLD upgrade requires maintaining a high-level output and the first level as high, the safety of the upgrade process is improved by ensuring that the key signals always remain at a high level, regardless of how the state machine in the CPLD jumps.

[0029] Optionally, in the method described above, the controller and the programmable controller are also connected via a second pin. After sending the upgrade file to the programmable controller, the method further includes:

[0030] Detect the third level state of the second pin;

[0031] Based on the third level state, the status information is obtained. When the third level state is high, the status information indicates that the programmable controller has completed the upgrade.

[0032] In this embodiment, by introducing a second pin as an independent upgrade completion status feedback channel, a dual status confirmation mechanism is established, which improves the accuracy and reliability of upgrade completion judgment and provides additional security for high-reliability application scenarios.

[0033] Secondly, this application provides an online upgrade device, comprising:

[0034] The first setting module is used to set the first pin to a first level state. The first level state is the same as the signal state that needs to be maintained when the programmable controller is upgraded. The first level state and the signal state output by the programmable controller are ORed. The first level state is a high level.

[0035] The processing module is used to send upgrade files to the programmable controller and obtain the state information of the state machine in the programmable controller.

[0036] The second setting module is used to set the first pin to a second level state when the status information indicates that the programmable controller has completed the upgrade. The second level state is the opposite of the output state that the programmable controller needs to maintain during the upgrade.

[0037] Optionally, in the device described above, the first pin is a general-purpose input / output interface; setting the first pin to a first level state, the first setting module is specifically used for:

[0038] Obtain the current operating status, which is used to determine whether to upgrade the programmable controller;

[0039] When the operating status indicator is upgrading the programmable controller, the level state of the general-purpose input / output interface pins is set to the first level state.

[0040] Optionally, in the apparatus described above, the upgrade file includes multiple data packets; the processing module is specifically used to send the upgrade file to the programmable controller for:

[0041] Send upgrade instructions to the programmable controller;

[0042] Receive the response message corresponding to the upgrade instruction sent by the programmable controller, and when the response message indicates that the programmable controller can be upgraded, send multiple data packets to the programmable controller in sequence.

[0043] Optionally, in the apparatus described above, the state information of the state machine in the programmable controller is obtained, and the processing module is specifically used for:

[0044] Determine the first duration, which is the duration required for the programmable controller to perform an upgrade based on the upgrade file;

[0045] After the first duration, the state information of the state machine in the programmable controller is obtained.

[0046] Optionally, in the device described above, when the status information indicates that the programmable controller has completed the upgrade, the first pin is set to a second level state, and the second setting module is specifically used for:

[0047] When the state machine is in the target state and the target state has been maintained for a second duration, the state information is determined to instruct the CPLD to complete the upgrade.

[0048] Set the first pin to the second level state.

[0049] Optionally, in the device described above, when the programmable controller is upgraded, it is necessary to maintain the output signal state at a high level. When the programmable controller is upgraded, the output signal state of the programmable controller is ORed with the first level state to make the output signal state of the programmable controller at a high level.

[0050] Optionally, in the device described above, the controller and the programmable controller are also connected via a second pin. After sending an upgrade file to the programmable controller, the device further includes a detection module, which is also used for:

[0051] Detect the third level state of the second pin;

[0052] Based on the third level state, the status information is obtained. When the third level state is high, the status information indicates that the programmable controller has completed the upgrade.

[0053] Thirdly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0054] The memory stores instructions that the computer executes;

[0055] The processor executes computer-executable instructions stored in memory to implement the method described in the first aspect.

[0056] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, are used to implement the method described in the first aspect.

[0057] The computer-readable storage medium provided in this application embodiment can execute the technical solutions in the above method embodiments, and its beneficial effects are similar, so they will not be described again here.

[0058] Fifthly, this application provides a computer program product, including a computer program, which, when executed by a computer, is used to implement the method of the first aspect.

[0059] The computer program product provided in this application embodiment can execute the technical solutions in the above method embodiments, and its beneficial effects are similar, so they will not be described again here.

[0060] The online upgrade method, apparatus, electronic device, storage medium, and program product provided in this application set the first pin of the controller connected to the CPLD to the same first level state as the signal state that needs to be maintained during the CPLD upgrade, and perform an OR operation between the first level state and the signal state output by the CPLD, and send an upgrade file to the CPLD and obtain the state information of its internal state machine. When the state information indicates that the upgrade is complete, the first pin is set to a second level state that is opposite to the output state that needs to be maintained. In the above method, the electronic device can introduce a signal holding mechanism based on OR logic. When the first pin is set to the first level state, the circuit characteristics of OR logic can ensure that the key signals output by the CPLD are forcibly maintained at the effective level, effectively avoiding signal jumps or interruptions caused by state machine reset, and ensuring the continuous and stable operation of the controlled device during the upgrade process. Furthermore, by monitoring the operating status of the state machine, the timing of releasing the signal holding is precisely controlled. When the state machine is detected to have entered a stable working state, the signal holding is released in a timely manner, and the control is returned to the internal logic of the CPLD. This method not only ensures the stability of key signals during the upgrade process, but also ensures that the system can quickly restore normal control logic after the upgrade is completed. In addition, this method is implemented using a general GPIO interface combined with basic logic circuits, without the need for complex dedicated hardware. It has the advantages of simple implementation and low cost, and can be flexibly applied to various embedded control systems, providing a reliable solution for online upgrades of CPLDs. On the basis of improving the reliability of online upgrades of CPLDs, it also improves the stability and operational stability of the device. Attached Figure Description

[0061] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0062] Figure 1 This is a schematic diagram of the system architecture provided for an embodiment of this application;

[0063] Figure 2A flowchart illustrating an online upgrade method provided in an embodiment of this application;

[0064] Figure 3 A schematic diagram of the hardware connection structure for online upgrades provided in this application embodiment;

[0065] Figure 4 This is a schematic diagram of a method for monitoring the state of a state machine provided in an embodiment of this application;

[0066] Figure 5 A flowchart illustrating another online upgrade method provided in this application embodiment;

[0067] Figure 6 A schematic diagram of a timing control diagram provided in an embodiment of this application;

[0068] Figure 7 This is a schematic diagram of the structure of an online upgrade device provided in an embodiment of this application;

[0069] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0070] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0071] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0072] With the increasing reliability requirements of embedded systems in industrial control, communication equipment, and automotive electronics, more stringent demands are being placed on ensuring business continuity during the online upgrade process of complex programmable logic devices (CPLDs). The limitations of traditional communication bus-based upgrade schemes are becoming increasingly apparent. Traditional CPLD online upgrade schemes are characterized by: reliance solely on communication bus transmission, lack of signal protection mechanisms, and susceptibility to state machine transitions during the upgrade process, often leading to system interruptions and insufficient reliability. This places higher demands on the online maintenance capabilities of high-reliability embedded systems, as interruptions to critical signals can trigger system malfunctions, while manual intervention can affect the level of system automation.

[0073] In related technologies, during CPLD upgrades, the controller can send an upgrade file to the CPLD via a communication bus, and the CPLD can perform the upgrade operation based on the received upgrade file.

[0074] However, during the above process, issues such as state machine resets causing critical signal transitions and system instability during upgrades may arise, requiring manual monitoring and intervention, resulting in low reliability of online upgrades. Because traditional solutions lack hardware-level signal protection mechanisms, relying solely on software protocols may overlook the need for coordinated protection between state machine transitions and critical signal stability, or lead to system malfunctions due to signal glitches, or even system crashes caused by instantaneous signal transitions.

[0075] For example, the technical problem of traditional CPLD online upgrade solutions can be understood as the inability to establish an effective isolation mechanism between the logic refactoring process and signal stability assurance, such as the inability to maintain stable output of key control signals during state machine transitions.

[0076] Online upgrades of CPLDs typically require integrated control based on bus communication and internal status monitoring. Specifically, the control unit can monitor the state machine status, transmit upgrade files, and manually or automatically trigger the upgrade process to complete the functional update.

[0077] However, traditional upgrade solutions have inherent flaws: First, signal output is directly coupled to internal logic, lacking an effective signal isolation mechanism; second, they lack coordinated control logic for state transitions and signal stabilization, making it difficult to guarantee signal continuity during the upgrade process; and finally, they rely on the natural stabilization process of the state machine, failing to actively maintain the stable state of critical signals. These factors make it difficult to achieve truly seamless online upgrades, resulting in challenges in guaranteeing the reliability of the upgrade process and the stability of the system.

[0078] In addition, protection parameters need to be manually configured for different upgrade scenarios. Since the specific mode of state machine transition cannot be predicted and the fixed upgrade process cannot adapt to the diverse control signal requirements, the upgrade solution has limited effectiveness and poor adaptability.

[0079] Alternatively, relying on real-time monitoring and manual intervention at the control end makes it difficult to grasp the complete signal transition patterns and appropriate protection timing, often requiring the sacrifice of upgrade efficiency to ensure system stability.

[0080] Therefore, this application provides a CPLD online upgrade method. By introducing a signal holding mechanism based on GPIO and OR logic operations, a signal protection path independent of the CPLD's internal logic is established. Combined with intelligent monitoring of the state machine's operating status, this achieves automated protection and release of critical control signals. By combining hardware signal holding, real-time status monitoring, and collaborative control of the upgrade process, the method effectively distinguishes between the logic reconfiguration process and stable signal output, thereby achieving precise and automated protection of critical signals during the CPLD upgrade process. This method can adapt to the CPLD upgrade needs of various embedded control scenarios, avoiding system interruptions and signal anomalies caused by traditional solutions, maximizing business continuity, and significantly improving the reliability and system maintenance efficiency of CPLD online upgrades.

[0081] Figure 1 For a schematic diagram of the system architecture provided in this application embodiment, please refer to [link / reference]. Figure 1 This includes electronic devices. Electronic devices can be any device with on-device computing capabilities, such as servers and terminal devices. Electronic devices are equipped with controllers and complex programmable logic devices (CPLDs). The controller can communicate with the CPLD. Specifically, the controller can send upgrade information to the CPLD, and the CPLD can perform upgrade operations based on the received upgrade information, thereby completing the online upgrade of the CPLD.

[0082] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0083] Figure 2 This is a flowchart illustrating an online upgrade method provided in an embodiment of this application. Specifically, as shown... Figure 2 As shown, the method includes the following steps:

[0084] S201, Set the first pin to the first level state.

[0085] The execution subject of this application embodiment can be an electronic device or an online upgrade device installed in the electronic device. The online upgrade device can be implemented by software or by a combination of software and hardware.

[0086] The first level state is the same as the signal state that needs to be maintained when the programmable controller is upgraded. The first level state and the signal state output by the programmable controller are ORed. The first level state is high level.

[0087] The first pin can be a hardware connection pin between the controller and the CPLD for signal transmission. For example, the first pin can be a general purpose input / output (GPIO) pin.

[0088] The first level state can be the level state of the signal output by the controller through the first pin. For example, a high level state indicates that the signal output by the controller through the first pin is at a high level.

[0089] In some embodiments, the electronic device may set the first pin to a first level state based on the following implementation: the first pin is a general-purpose input / output interface; the current operating state is obtained, and the operating state is used to determine whether to upgrade the programmable controller; when the operating state indicates that the programmable controller should be upgraded, the level state of the general-purpose input / output interface pin is set to the first level state.

[0090] The current time can be a periodic detection time, meaning it can be a detection interval at fixed times. For example, the current time could be 8:10 AM. Optionally, the current time can be determined by an external event signal. For example, if the user sends an upgrade signal through a host computer, the current time can be determined based on the sending time of the upgrade signal.

[0091] The operating status can be the current internal operating status of the device. For example, in this embodiment, the operating status can be an upgradeable status or a non-upgradeable status, wherein the upgradeable status indicates that the CPLD can be upgraded online at the current time, and the non-upgradeable status indicates that the CPLD cannot be upgraded online at the current time.

[0092] In some embodiments, the electronic device can acquire status information through a multi-channel parallel monitoring mechanism. Specifically, the electronic device can read the CPLD's version register through the I2C or SPI bus to obtain the current firmware version number, and monitor information such as the CPLD's operating status, state machine transition monitoring, and input / output pin level status, as well as detect external input signals in real time, including remote upgrade commands and local trigger signals. It will also periodically collect hardware status parameters such as power stability and system temperature.

[0093] After collecting the aforementioned data, the electronic device can make judgments based on this data. For example, it can compare the current firmware version with the target version to confirm whether there are version differences; analyze the state machine's state codes and transition logic to determine whether the CPLD is in a preset stable operating state; and verify the validity of external upgrade commands. If the above judgment results meet the preset requirements, the electronic device can determine that the current operating state is an upgradeable state; if the above judgment results do not meet the preset requirements, the electronic device can determine that the current operating state is an unupgradeable state. This operating state acquisition mechanism ensures the accuracy and reliability of upgrade decisions, providing precise state basis for initiating the subsequent upgrade process.

[0094] In some embodiments, when the running state is upgradeable, indicating that the motion state indicates an upgrade of the CPLD, the electronic device can set the pin level to the first level state by writing to the GPIO data register. This process must ensure that the level switching is completed before sending the upgrade file and that sufficient stabilization time is maintained. Furthermore, the setting result can be verified by reading the output status register and the output of the OR gate circuit can be detected to confirm that the signal holding function is normal, thereby building a reliable signal protection mechanism. If the setting fails, a retry mechanism is triggered. After reaching the maximum number of retries, an error log is recorded and the upgrade process is terminated. Once the setting is successful, the GPIO will maintain the first level state until the upgrade is completed and the state machine is running stably before changing the state.

[0095] In some embodiments, when the programmable controller is upgraded, it is necessary to keep the output signal state at a high level. When upgrading the programmable controller, the output signal state of the programmable controller is ORed with a first level state to make the output signal state of the programmable controller at a high level.

[0096] The signal state that needs to be maintained during CPLD upgrades can be the final output level of the CPLD.

[0097] The signal state output by the CPLD can be the level state of the key signals output by the CPLD. Among them, key signals can be power control signals, reset signals, etc.

[0098] In some embodiments, when the CPLD is upgraded, the output signal state needs to be kept at a high level, and the first level state is also set to a high level accordingly. At this time, the electronic device performs a logical OR operation by connecting the CPLD output signal state and the first level state to an OR gate circuit. In this way, when the CPLD causes the output signal to jump due to internal logic reconstruction, since the GPIO pin has output a stable high level (first level state) in advance, according to the logic characteristics of the OR gate, as long as one of the inputs is high, the output will remain at a high level. This ensures that no matter how the internal state of the CPLD changes, the final output signal state is always forced to be maintained at a stable high level. This design effectively solves the problem of transient interruption of key control signals during the upgrade through simple logic circuits and provides a reliable signal holding mechanism.

[0099] For example, if the first pin GPIO is set to a high level, and if the critical signal is at a high level, then the output signal must be kept at a high level during CPLD upgrade; if the critical signal is at a low level, then the output signal must be kept at a high level during CPLD upgrade, as shown in Table 1.

[0100] Table 1

[0101]

[0102] As shown in Table 1, when the critical control signal is at a high or low level, the output signal must remain at a high level during CPLD upgrade. This ensures normal operation of the equipment and prevents it from being affected by internal upgrade operations, thus achieving seamless online upgrades.

[0103] In some embodiments, this application is also applicable to scenarios where the critical signal is active low. Specifically, if the CPLD needs to maintain the output signal state at a low level during upgrade (for example, to maintain a low-level active reset signal in an invalid state), then the first level state should be set to a low level accordingly. In this case, the electronic device performs a logical AND operation by connecting the CPLD output signal state and the first level state to an AND gate circuit. When the GPIO pin outputs a stable low level (first level state) beforehand, according to the logic characteristics of the AND gate (the output is high only when all inputs are high), as long as one input is low, the output remains low. Therefore, regardless of how the CPLD's internal state changes, the final output signal can be forced to remain in a stable low level state, thereby providing protection for the low-level active critical signal. Its logical relationship is shown in Table 2:

[0104] Table 2

[0105]

[0106] As shown in Table 2, under this configuration, regardless of the level of the critical control signal, the output signal must remain at a low level during CPLD upgrades. This application, by flexibly selecting the first level state and the corresponding basic logic gates (OR gates or AND gates), can adapt to various critical signals that are active high or low, ensuring stable operation of the device during upgrades and achieving a widely applicable, seamless online upgrade capability.

[0107] Below, in conjunction with Figure 3 The hardware connection structure for online upgrades is illustrated through specific examples.

[0108] Figure 3 For a schematic diagram of the hardware connection structure for online upgrades provided in this application embodiment, please refer to [link / reference]. Figure 3 The system includes a controller and a CPLD. The controller connects to the CPLD via an I2C bus, which includes a serial clock line (SCL) and a serial data line (SDA) for transmitting upgrade commands and upgrade file data. The controller also connects to the CPLD via a general purpose input / output (GPIO) pin, which serves as the control signal line for the upgrade process. The CPLD also includes four output signals: PWR_EN1, PWR_EN2, PWR_EN3, and PWR_EN4. These four output signal pins are connected to one input of four OR gates, and the other input of the four OR gates is connected to the GPIO pin of the controller. The SCL and SDA lines of the I2C bus need to be pulled up, which can be configured internally by the main controller or implemented through external pull-up resistors. The GPIO pins and the lines of the four key signals PWR_EN1 to PWR_EN4 can be pulled down as needed according to the design requirements. The actual level of these signal lines is ultimately determined by the output control of their respective drivers (controllers or CPLDs).

[0109] In this way, through this hardware connection structure, when the controller sets the GPIO to a high level during the upgrade, the PWR_EN1 to PWR_EN4 signals can be forced to remain at a high level through OR gate logic, thereby shielding the impact of the CPLD's internal state machine transitions on critical control signals.

[0110] S202. Send the upgrade file to the CPLD and obtain the state information of the state machine in the CPLD.

[0111] The upgrade file can be a configuration file that includes new logic functions for the CPLD.

[0112] The state machine can be the state machine responsible for timing control inside the CPLD.

[0113] The state information can be the current level state of the state machine. For example, the level state of the state machine can be a low level state.

[0114] In some embodiments, the electronic device may send an upgrade file to the programmable controller in the following manner: the upgrade file includes multiple data packets; an upgrade instruction is sent to the programmable controller; a response message corresponding to the upgrade instruction sent by the programmable controller is received; and when the response message indicates that the programmable controller can be upgraded, multiple data packets are sent to the programmable controller in sequence.

[0115] The response message is used to indicate that the CPLD has received information sent by the controller.

[0116] Specifically, the controller can send an upgrade command to the CPLD via the I2C bus. After receiving the upgrade command, the CPLD returns a response message to the controller. After receiving the confirmation response from the CPLD, the controller sends each data packet in sequence and waits for the CPLD to return a confirmation after each data packet is sent. If no confirmation is received within a preset time, the data packet is automatically retransmitted. Furthermore, the controller obtains the real-time state information of the state machine by reading the internal state register of the CPLD, including the current state value, the state stability time, and the error state flag. This state information is used to determine the correctness of the upgrade process and to decide on subsequent operation procedures.

[0117] In some embodiments, the electronic device may send an upgrade file to the CPLD based on the following implementation: the upgrade file includes multiple data packets; for the i-th data packet; the i-th data packet is sent to the CPLD; after determining that the CPLD has received the i-th data packet, the (i+1)-th data packet is sent to the CPLD; i takes the values ​​1, 2, ..., N-1 in sequence, and N is the number of data packets.

[0118] In some embodiments, before receiving the upgrade file, the external pin states of the CPLD are maintained by the internal state holding mechanism of the CPLD, such as a hitless or statehold mechanism. After receiving the upgrade file, the external pin states of the CPLD are maintained by an OR operation with the high-level state of the GPIO pin, truly realizing seamless online upgrades.

[0119] In some embodiments, the electronic device may acquire the state information of the state machine in the programmable controller based on the following implementation: determining a first duration; and acquiring the state information of the state machine in the programmable controller after the first duration.

[0120] The first duration is the time required for the CPLD to perform the upgrade based on the upgrade file.

[0121] In some embodiments, the electronic device can determine a first duration based on upgrade operation records of historical periods. Specifically, the first duration covers the entire process required from the configuration loading of the upgrade file to the completion of the reconstruction of the CPLD internal logic. That is, the first duration may include the duration used by the CPLD to configure the upgrade file, the duration required for the CPLD internal logic to complete its operation (the state machine to return to a steady state), and sufficient buffer time reserved on this basis.

[0122] After triggering the upgrade process, the electronic device starts a timer and waits, without performing any status query operations during this period. After the first time interval has elapsed, the electronic device reads the current state value of the state machine via a communication bus (e.g., an I2C bus). This simplifies the judgment logic using a single time threshold, effectively avoiding frequent monitoring during state machine transients. A one-time state confirmation is performed at the moment when a stable state is most likely to be reached, effectively preventing misjudgments caused by the state machine briefly entering the target state in the early stages of stabilization, resulting in high reliability.

[0123] For example, if the time taken for the internal logic of the CPLD to complete is typically 5 seconds and the time taken for the configuration upgrade file is typically 6 ms, after setting a certain buffer duration, the first duration can be set to 6 seconds. That is, after 6 seconds, the state machine in the CPLD is in a steady state, and the electronic device can obtain the state information of the state machine at this time.

[0124] In some embodiments, the electronic device dynamically monitors the state machine's state during a first duration. Specifically, the electronic device continuously monitors the state machine's state value during the upgrade process. When the state value is detected to enter a preset state, a stability timer is started. If the state machine's state value remains unchanged throughout the entire duration window, the state machine is determined to have reached stable operating conditions. If any change occurs in the state value during this period, the timer is reset and monitoring resumes. This method can accurately capture the state machine's stabilization timing, enabling rapid response to the upgrade completion state and effectively improving the execution efficiency of the upgrade process.

[0125] S203. When the status information indicates that the CPLD has completed the upgrade, set the first pin to the second level state.

[0126] The second level state is the opposite of the output state required to be maintained during CPLD upgrade. That is, when the output state required to be maintained during CPLD upgrade is high, the second level state is low. The controller can set the level state of the GPIO pin from high to low. This ensures that when the first pin is set to the second level state, the OR gate logic circuit will release the forced holding of the CPLD output signal, allowing system control to be returned to the newly loaded logic function of the CPLD.

[0127] In some embodiments, the electronic device may set the first pin to a second level state when the status information indicates that the programmable controller has completed the upgrade, based on the following implementation: when the state machine is in the target state and the target state has been maintained for a second duration, it is determined that the status information indicates that the programmable controller has completed the upgrade; the first pin is set to the second level state.

[0128] The target state can be the steady-state level of the internal state machine of the CPLD after the upgrade is completed.

[0129] The second duration can be a pre-set threshold for judging whether the state machine is in a steady state. That is, if the duration of the state machine in the target state is less than the second duration, it indicates that the current state machine has not reached the judgment standard of steady state and needs to continue monitoring. If the duration of the state machine in the target state is greater than or equal to the second duration, it indicates that the current state machine has reached the judgment standard of steady state and it can be determined that the current CPLD has completed the upgrade operation. That is, the status information indicates that the CPLD has completed the upgrade.

[0130] In some embodiments, the electronic device can continuously monitor the current state value of the state machine and start a timer when the state value is detected to be consistent with a preset target state. If the state of the state machine remains unchanged for a second period of time, the state information is determined to instruct the CPLD to complete the upgrade; if the state value changes during this period, the timer is immediately reset and monitoring resumes.

[0131] In some embodiments, the electronic device can write a value corresponding to the second level state to the output data register (e.g., 0 for a low level) and verify whether the level switching was successful by reading the output status register. This operation will release the forced holding of the CPLD output signal by the OR gate, allowing the system to return to normal operating mode.

[0132] The online upgrade method, apparatus, electronic device, storage medium, and program product provided in this application involve setting a first pin to a first level state, which is the same as the signal state that needs to be maintained during CPLD upgrade, and the first level state and the signal state output by CPLD are ORed; sending an upgrade file to CPLD and obtaining the state information of the state machine in CPLD; and setting the first pin to a second level state when the state information indicates that CPLD has completed the upgrade, which is the opposite of the output state that needs to be maintained during CPLD upgrade. In the above method, the electronic device can introduce a signal holding mechanism based on OR logic. When the first pin is set to the first level state, the circuit characteristics of OR logic can ensure that the key signals output by the CPLD are forcibly maintained at the effective level, effectively avoiding signal jumps or interruptions caused by state machine reset, and ensuring the continuous and stable operation of the controlled device during the upgrade process. Furthermore, by monitoring the operating status of the state machine, the timing of releasing the signal holding is precisely controlled. When the state machine is detected to have entered a stable working state, the signal holding is released in a timely manner, and the control is returned to the internal logic of the CPLD. This method not only ensures the stability of key signals during the upgrade process, but also ensures that the system can quickly restore normal control logic after the upgrade is completed. On the basis of improving the reliability of CPLD online upgrade, it also improves the stability and operational stability of the device.

[0133] Based on any of the above embodiments, the method for monitoring the state machine according to the level state of the second pin after the electronic device sends the upgrade file to the CPLD in the above online upgrade method will be described in detail.

[0134] Figure 4 This is a schematic diagram illustrating a method for monitoring the state of a state machine according to an embodiment of this application. Please refer to [link / reference]. Figure 4 The method includes the following steps:

[0135] S401, Detect the third level state of the second pin.

[0136] The second pin can be a hardware connection pin between the controller and the CPLD for signal transmission. For example, the second pin can be a general purpose input / output (GPIO) pin.

[0137] The second level state can be the level state of the signal output by the controller through the second pin. For example, a low level state indicates that the signal output by the controller through the second pin is at a low level.

[0138] In some embodiments, based on any of the above embodiments, this embodiment further optimizes the state monitoring mechanism by adding a second pin (GPIO) to the original hardware structure. Specifically, the hardware connection between the controller and the CPLD adds a second pin (GPIO2) to the original SCL, SDA, and first pin (GPIO1). This second pin is also a general-purpose input / output interface pin of the controller, configured in input mode in this embodiment to receive state feedback signals from the CPLD. After the CPLD's internal logic completes the upgrade and the state machine enters a stable state, it will actively drive the output pin connected to GPIO2 to switch the level from low to high.

[0139] In some embodiments, the electronic device can detect the third level state of the second pin by periodically reading or interrupting the response. Specifically, the electronic device configures the second pin in digital input mode and obtains the current third level state by reading the value of its input data register. This state has two possible values: a low level indicates that the CPLD is still in the process of upgrading or the state machine is not yet stable; a high level indicates that the CPLD has completed the upgrade and the state machine has entered a stable operating state. Furthermore, the electronic device employs anti-jitter processing, ensuring the stability of the level state through continuous multiple samplings to avoid misjudgments caused by transient interference.

[0140] S402. Obtain status information based on the third level state, wherein when the third level state is high, the status information indicates that the programmable controller has completed the upgrade.

[0141] In some embodiments, the electronic device directly acquires status information based on the detected third-level state. When the electronic device detects that the third-level state is high, it can determine that the status information indicates the CPLD has completed the upgrade. At this time, the electronic device will immediately execute subsequent operations, including setting the first pin to the second-level state. This method directly characterizes the operating state of the internal state machine through hardware signals, achieving real-time and accurate status monitoring. Compared with the method of querying the status register through the communication bus, this method has a faster response and does not occupy bus resources, providing the system with another efficient and reliable status monitoring scheme.

[0142] The online upgrade method, apparatus, electronic device, storage medium, and program product provided in this application detect the third level state of the second pin; based on the third level state, status information is obtained, wherein a high level in the third level state indicates that the CPLD has completed the upgrade. In this method, the electronic device constructs a complete upgrade status judgment system through a dual mechanism of level control of the first pin and status monitoring of the second pin. This enables accurate judgment of the CPLD upgrade status in complex embedded system environments, effectively avoiding response delays or misjudgments that may result from relying solely on software queries. Furthermore, by establishing a hardware signal-based status feedback mechanism, when the CPLD's internal state machine reaches a stable state, it can immediately and proactively report the status through level changes of the second pin, eliminating the need for continuous polling by the controller, reducing bus communication load, and improving the real-time performance and overall system efficiency of status monitoring. In addition, this hardware status monitoring method can complete status judgment through simple level detection without complex protocol parsing. This method is applicable to various embedded control scenarios, significantly improving the immediacy of status monitoring and system response speed while enhancing the reliability of the upgrade process.

[0143] Figure 5 This is a flowchart illustrating another online upgrade method provided in an embodiment of this application. Please refer to... Figure 5 The method includes the following steps:

[0144] S501. Obtain the current operating status. The operating status is used to determine whether to upgrade the programmable controller.

[0145] S502. When the operating status indicates that the programmable controller is being upgraded, the level state of the general-purpose input / output interface pins is set to the first level state.

[0146] When upgrading a programmable controller, it is necessary to maintain the output signal state at a high level. During the upgrade, the output signal state of the programmable controller is ORed with the first level state to make the output signal state of the programmable controller at a high level.

[0147] It should be noted that the execution process of S501-S502 above can be found in S201, and will not be repeated here.

[0148] S503: Send upgrade instructions to the programmable controller.

[0149] S504: Receive the response message corresponding to the upgrade instruction sent by the programmable controller, and when the response message indicates that the programmable controller can be upgraded, send multiple data packets to the programmable controller in sequence.

[0150] S505, Determine the first duration.

[0151] The first duration is the time required for the programmable controller to perform an upgrade based on the upgrade file.

[0152] S506. After the first duration, obtain the state information of the state machine in the programmable controller.

[0153] It should be noted that the execution process of S503-S506 above can be found in S202, and will not be repeated here.

[0154] S507. When the state machine is in the target state and the target state has been maintained for a second duration, determine the state information to instruct the programmable controller to complete the upgrade.

[0155] S508, Set the first pin to the second level state.

[0156] It should be noted that the execution process of S506-S507 above can be found in S203, and will not be repeated here.

[0157] This application provides an online upgrade method that achieves steady-state locking of critical signals during CPLD upgrades through the coordinated control of external GPIO signals and AND / OR logic operations. Specifically, the GPIO signals are set to high level during the upgrade phase, and logic gates force the output state of critical signals to be controlled by the GPIO, rather than the CPLD's internal state machine. During this process, the CPLD's I / O output state is frozen, ensuring that critical signals will not abnormally change due to internal state changes when the state machine transitions after the upgrade logic is loaded. This technique effectively solves the problem of critical signal interruption caused by state machine initialization in dynamic reconfiguration schemes, while avoiding the multi-drive contention and cost issues of hardware redundancy schemes. The resulting guarantee of critical signal steady-state stability ensures continuous operation of the device during the upgrade process, with uninterrupted service, significantly improving the system's high availability and stability.

[0158] Below, in conjunction with Figure 6 The timing control diagram in the online upgrade process is explained through specific examples.

[0159] Figure 6 This is a schematic diagram of a timing control diagram provided in an embodiment of this application. Please refer to... Figure 6The specific process is as follows: Before the CPLD is upgraded, the four key signals PWR_EN1, PWR_EN2, PWR_EN3, and PWR_EN4 of the CPLD are all at a high level, and the first pin GPIO is at a low level. When it is determined that the CPLD will be upgraded, the controller will first switch the level of the first pin GPIO, that is, set the first pin GPIO to a high level (first level state). When the CPLD is actually upgraded, the controller and the CPLD transmit data through the connected I2C communication bus (upgrade channel). During this period, the final output state of the four key signals of the CPLD remains at a high level. After the state machine is in a steady state during the state transition process, that is, after it is determined that the CPLD has completed the upgrade, the controller sets the level of the first pin GPIO to a low level.

[0160] Specifically, during the upgrade process, GPIO is prioritized and set to a high level. During the I2C upgrade, the CPLD's internal Hitless or StateHold mechanism is automatically activated, freezing the output pin state and maintaining the pre-upgrade level. When the program loads and the state machine begins transitioning, external GPIO uses OR logic to maintain the state of critical signals such as PWR_EN, ensuring stable output. Once the entire upgrade process is complete and the state machine is running stably, control of the critical signals is returned to the CPLD's internal state machine logic, achieving seamless upgrade of external critical control signals. The CPLD's hitless or StateHold features allow it to freeze I / O during reconfiguration, maintaining the pre-configuration I / O output state. This ensures that devices controlled by the CPLD are unaffected during the upgrade, while external GPIO signals maintain a stable output during state machine transitions. Once the state stabilizes, external signals are withdrawn and handled by internal logic, achieving a seamless online upgrade process.

[0161] This application provides a seamless online upgrade solution applicable to CPLD control power-on timing scenarios. Specifically, the control terminal acts as the main controller, responsible for carrying the new version program and transmitting it through the communication channel; the CPLD, as the upgraded device, receives the instruction code and upgrade file through the I2C interface; GPIO acts as a notification signal, and during the upgrade, a set operation ensures that the PWR_EN signal pin is shielded from critical signal transitions during the state machine transition process by the GPIO level, preventing PWR_EN from momentarily interrupting during the state machine's transition from the initial state to the steady state. This solution effectively shields the signal transitions generated during the state machine's transition from the initial state to the steady state by using GPIO levels, fundamentally eliminating system interruption caused by momentary signal interruptions. In the above process, by controlling the CPLD's external GPIO and I2C upgrade channel, the CPLD can update its internal logic control code while maintaining the stability of critical steady-state timing signals, thereby ensuring uninterrupted operation under CPLD control, preventing service interruptions during the update process, reducing service losses caused by upgrade code, and greatly improving device maintainability.

[0162] Figure 7 This is a schematic diagram of the structure of an online upgrade device provided in an embodiment of this application, as shown below. Figure 7 As shown, the device 70 includes: a first setting module 71, a processing module 72, and a second setting module 73.

[0163] The first setting module 71 is used to set the first pin to a first level state. The first level state is the same as the signal state that needs to be maintained when the programmable controller is upgraded. The first level state is ORed with the signal state output by the programmable controller. The first level state is high level.

[0164] The processing module 72 is used to send an upgrade file to the programmable controller and obtain the state information of the state machine in the programmable controller.

[0165] The second setting module 73 is used to set the first pin to a second level state when the status information indicates that the programmable controller has completed the upgrade. The second level state is the opposite of the output state that the programmable controller needs to maintain during the upgrade.

[0166] The online upgrade device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0167] In one possible implementation, the first setting module 71 is specifically used for:

[0168] Obtain the current operating status, which is used to determine whether to upgrade the programmable controller;

[0169] When the operating status indicator is upgrading the programmable controller, the level state of the general-purpose input / output interface pins is set to the first level state.

[0170] In one possible implementation, the processing module 72 is specifically used for:

[0171] Send upgrade instructions to the programmable controller;

[0172] Receive the response message corresponding to the upgrade instruction sent by the programmable controller, and when the response message indicates that the programmable controller can be upgraded, send multiple data packets to the programmable controller in sequence.

[0173] In one possible implementation, the processing module 72 is specifically used for:

[0174] Determine the first duration, which is the duration required for the programmable controller to perform an upgrade based on the upgrade file;

[0175] After the first duration, the state information of the state machine in the programmable controller is obtained.

[0176] In one possible implementation, the second setting module 73 is specifically used for:

[0177] When the state machine is in the target state and the target state has been maintained for a second duration, the state information is determined to instruct the programmable controller to complete the upgrade.

[0178] Set the first pin to the second level state.

[0179] In one possible implementation, when the programmable controller is upgraded, it is necessary to keep the output signal state at a high level. The first level state is high. When upgrading the programmable controller, the output signal state of the programmable controller is ORed with the first level state to make the output signal state of the programmable controller high.

[0180] In one possible implementation, the device further includes a detection module, which is also used for:

[0181] Detect the third level state of the second pin;

[0182] Based on the third level state, the status information is obtained. When the third level state is high, the status information indicates that the programmable controller has completed the upgrade.

[0183] The online upgrade device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0184] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 8 As shown, the electronic device 80 may include at least one processor 81 and a memory 82.

[0185] Memory 82 is used to store programs. Specifically, the program may include program code, which includes computer-executable instructions.

[0186] The memory 82 may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage.

[0187] The processor 81 is used to execute computer execution instructions stored in the memory 82 to implement the method described in the foregoing method embodiments. The processor 81 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0188] Optionally, the electronic device 80 may also include a communication interface 83. In specific implementations, if the communication interface 83, memory 82, and processor 81 are implemented independently, then the communication interface 83, memory 82, and processor 81 can be interconnected via a bus to complete communication between them. The bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0189] Optionally, in a specific implementation, if the communication interface 83, memory 82, and processor 81 are integrated on a single chip, then the communication interface 83, memory 82, and processor 81 can communicate through an internal interface.

[0190] The electronic device in this embodiment can be used to execute the technical solutions of the above method embodiments. The specific implementation methods and technical effects are similar, and will not be repeated here.

[0191] This application provides a computer-readable storage medium, which may include various media capable of storing computer-executable instructions, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), RAM, a disk, or an optical disk. Specifically, the computer-readable storage medium stores computer-executable instructions, which, when executed by a computer, cause the technical solution shown in the above method embodiment to be executed. The specific implementation and technical effects are similar and will not be repeated here.

[0192] This application provides a computer program product, including a computer program. When the computer program is executed by a computer, the technical solution shown in the above method embodiment is executed. The specific implementation method and technical effect are similar, and will not be repeated here.

[0193] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0194] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0195] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0196] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0197] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0198] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0199] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0200] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An online upgrade method, characterized in that, Applied to a controller, wherein the controller is connected to a programmable controller via a first pin, the method includes: The first pin is set to a first level state, which is the same as the signal state that needs to be maintained when the programmable controller is upgraded. The first level state and the signal state output by the programmable controller are ORed. The first level state is high. Send an upgrade file to the programmable controller and obtain the state information of the state machine in the programmable controller; When the status information indicates that the programmable controller has completed the upgrade, the first pin is set to a second level state, which is the opposite of the output state that the programmable controller needs to maintain during the upgrade.

2. The method according to claim 1, characterized in that, The first pin is a general purpose input / output interface; Setting the first pin to the first level state includes: Obtain the current operating status, which is used to determine whether to upgrade the programmable controller; When the operating status indicates that the programmable controller is being upgraded, the level state of the general-purpose input / output interface pin is set to the first level state.

3. The method according to claim 1, characterized in that, The upgrade file includes multiple data packets; sending the upgrade file to the programmable controller includes: Send an upgrade command to the programmable controller; The system receives a response message corresponding to the upgrade instruction sent by the programmable controller, and when the response message indicates that the programmable controller can be upgraded, it sequentially sends the plurality of data packets to the programmable controller.

4. The method according to claim 1, characterized in that, Obtaining the state information of the state machine in the programmable controller includes: A first duration is determined, which is the duration required for the programmable controller to perform an upgrade based on the upgrade file; After the first duration, the state information of the state machine in the programmable controller is obtained.

5. The method according to claim 1, characterized in that, When the status information indicates that the programmable controller has completed the upgrade, setting the first pin to the second level state includes: When the state machine is in the target state and the target state has been maintained for a second duration, the state information is determined to instruct the programmable controller to complete the upgrade. Set the first pin to the second level state.

6. The method according to any one of claims 1-5, characterized in that, When the programmable controller is upgraded, it is required to maintain the output signal state at a high level. The first level state is high level. When upgrading the programmable controller, the output signal state of the programmable controller is ORed with the first level state to make the output signal state of the programmable controller high level.

7. The method according to any one of claims 1-3, characterized in that, The controller and the programmable controller are also connected via a second pin. After sending an upgrade file to the programmable controller, the method further includes: Detect the third level state of the second pin; The status information is obtained based on the third level state, wherein when the third level state is a high level state, the status information indicates that the programmable controller has completed the upgrade.

8. An online upgrade device, characterized in that, include: The first setting module is used to set the first pin to a first level state. The first level state is the same as the signal state that needs to be maintained when the programmable controller is upgraded. The first level state is ORed with the signal state output by the programmable controller. The first level state is high level. The processing module is used to send an upgrade file to the programmable controller and obtain the state information of the state machine in the programmable controller. The second setting module is used to set the first pin to a second level state when the status information indicates that the programmable controller has completed the upgrade. The second level state is opposite to the output state that the programmable controller needs to maintain during the upgrade.

9. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 7.

11. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-7.

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