Chip layout method based on simulated annealing algorithm and gravity operation, medium and equipment

Abstract

The invention provides a simulated annealing algorithm and gravity operation-based chip layout method, a medium and equipment. The method comprises the following steps of: forming a typesetting block diagram and a chip block diagram according to a typesetting area and the size of a to-be-laid chip; iteratively updating the layout scheme of the chip block diagram based on an annealing algorithm until a global optimal layout scheme is output; the process of updating the layout scheme comprises the following steps: sequentially carrying out disturbance processing and gravity operation in the current layout scheme; the gravity operation comprises the following steps: moving a chip block diagram in the typesetting block diagram to a first gravity point; moving chip block diagrams outside the typesetting block diagram to a second gravity point or a third gravity point; the first gravity point is any vertex of the typesetting block diagram, and the second gravity point and the third gravity point are vertexes sharing the same edge with the first gravity point respectively. According to the invention, based on the framework of the existing simulated annealing algorithm, the updating efficiency of the layout scheme is accelerated through the set gravity operation, and the number of iterations and the layout time can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a chip layout method, medium and device based on simulated annealing algorithm and gravity calculation. Background Technology

[0002] In the semiconductor chip manufacturing process, especially in MPW (Multi-Project Wafer) projects, when planning the photomask layout or designing the circuit layout, it is necessary to place the most devices in a specific space to achieve the maximum space utilization. This requires chip placement, or floor plan.

[0003] The current main approach involves manually planning and placing components within the layout area according to product requirements to find the optimal arrangement. However, this requires repeated adjustments to the layout to achieve the final utilization rate, resulting in excessively long design cycles when there are many components. Some existing technologies propose using simulated annealing algorithms for automatic layout optimization in FPGAs. Simulated annealing is a heuristic iterative search algorithm, typically consisting of an inner loop and an outer loop. The inner loop iteratively optimizes at the current temperature, while the outer loop cools from the initial temperature to the final temperature. During each inner loop, new layout results are obtained through perturbations such as swapping and moving components. Each new layout result is accepted with a certain probability, determined by the annealing temperature and the objective function; higher annealing temperatures and better solutions to the objective function lead to a higher acceptance probability. After the current inner loop ends, the annealing temperature is lowered, and the next inner loop begins, continuing until the annealing temperature reaches the final temperature, at which point the outer loop exits.

[0004] However, in the automatic layout process of the simulated annealing algorithm, the new layout scheme is obtained only by perturbing the components, resulting in a very low convergence speed of the entire system, which greatly affects the layout efficiency.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] The purpose of this invention is to provide an automated chip layout method to achieve higher layout efficiency.

[0007] To address the aforementioned issues, firstly, a chip layout method based on simulated annealing and gravity calculation is provided, comprising the following steps: A layout diagram and a chip diagram are generated based on the layout area and the size information of the chip to be laid out, and both the layout diagram and the chip diagram are rectangular. Based on the simulated annealing algorithm, the layout scheme of the chip block diagram is iteratively updated until the globally optimal layout scheme is output. The process of updating the layout scheme of the chip block diagram includes: perturbing the chip block diagram in the current layout scheme; and performing gravity calculations on the perturbed chip block diagram to obtain a new layout scheme. The gravity calculation includes: moving the chip block diagram located within the layout diagram to a first gravity point; and moving the chip block diagram located outside the layout diagram to a second or third gravity point. The first gravity point is any vertex of the layout diagram, the second gravity point is any vertex in the layout diagram that shares an edge with the first gravity point, and the third gravity point is another vertex in the layout diagram that shares an edge with the first gravity point.

[0008] In this application, based on the existing simulated annealing algorithm framework, the efficiency of updating the layout scheme is accelerated by setting gravity calculation, which can effectively reduce the number of iterations and layout time.

[0009] The first gravity point is the origin, and a coordinate space is constructed by combining the second gravity point and the third gravity point; when updating the layout scheme of the chip block diagram, each chip block diagram is limited to being located within the coordinate space.

[0010] The process of moving the chip block diagram located within the layout diagram toward the first gravity point includes: for the chip block diagram located within the layout diagram, first translating it toward a first side, and then translating it toward a second side; or, for the chip block diagram located within the layout diagram, first translating it toward a second side, and then translating it toward a first side; wherein, the first side is the side in the layout diagram where both the first gravity point and the second gravity point exist simultaneously, and the second side is the side in the layout diagram where both the first gravity point and the third gravity point exist simultaneously. By moving chip block diagrams at different positions to specific areas of the layout diagram, the overall layout efficiency can be accelerated.

[0011] The process of moving the chip block diagram located outside the layout diagram towards the second gravity point or the third gravity point includes: moving the chip block diagram located outside the layout diagram along a first direction on the straight line containing the fourth side towards the third gravity point; and moving the chip block diagram located outside the layout diagram along a second direction on the straight line containing the third side towards the second gravity point. The third side is the other side of the layout diagram adjacent to the second side, and the fourth side is the other side of the layout diagram adjacent to the first side. The first direction is from the first gravity point to the second gravity point, and the second direction is from the first gravity point to the third gravity point. By moving chip block diagrams at different positions to specific areas of the layout diagram, the overall layout efficiency can be accelerated; it can also prevent excessive concentration in individual areas within the layout diagram, thereby increasing the probability of finding the global optimal solution.

[0012] The process of moving the chip block diagram located outside the layout diagram towards the second or third gravity point includes: for the chip block diagram located outside the layout diagram along the first direction of the line containing the fourth side, it is first translated towards the third side and then towards the second side; for the chip block diagram located outside the layout diagram along the second direction of the line containing the third side, it is first translated towards the fourth side and then towards the first side. By moving chip block diagrams at different positions to specific areas of the layout diagram, the overall layout efficiency can be accelerated; it can also prevent excessive concentration in individual areas within the layout diagram, thereby increasing the probability of finding the global optimal solution.

[0013] In the gravity calculation, an interval distance h is defined; for the chip block diagram located within the layout diagram: each chip block diagram is translated sequentially until the currently moved chip block diagram maintains the interval distance h between itself and the chip block diagram in the translation direction or the edge of the layout diagram; for the chip block diagram located outside the layout diagram: when translating towards the fourth side, all chip block diagrams are translated simultaneously until the currently moved chip block diagram maintains the interval distance h between itself and the straight line containing the fourth side; when translating towards the first side... When translating towards the third side, each chip block diagram is translated sequentially until the currently moved chip block diagram maintains the interval distance h with the chip block diagram in the translation direction or the first side; when translating towards the second side, all chip block diagrams are translated simultaneously until the currently moved chip block diagram maintains the interval distance h with the line containing the third side; when translating towards the third side, each chip block diagram is translated sequentially until the currently moved chip block diagram maintains the interval distance h with the chip block diagram in the translation direction or the second side. This satisfies the chip layout rules.

[0014] The process of iteratively updating the layout scheme of the chip block diagram based on the simulated annealing algorithm until the globally optimal layout scheme is output includes: S1, initializing the chip block diagram to obtain the initial layout scheme and calculating the solution of the objective function; S2, updating the layout scheme of the chip block diagram at the current temperature and calculating the current solution of the objective function; S3, comparing the current solution with the previous solution: if the current solution is better than the previous solution, accept the current solution; if the current solution is worse than the previous solution, determine whether to accept the current solution using a probability formula; S4, updating the layout scheme of the chip block diagram and calculating the current solution of the objective function; S5, repeating steps S3 and S4 until the predetermined number of iterations is reached; S6, moving to the next temperature and repeating steps S2 and S5 until the termination temperature and / or the threshold of the objective function are reached, and outputting the globally optimal layout scheme.

[0015] The initialization process involves arranging the chip block diagram in a regular or random manner; after the initialization process, gravity calculations are performed on the chip block diagram.

[0016] Secondly, this application also provides a computer storage medium storing a computer program; when the computer program is run on a computer, it enables the computer to perform a chip layout method based on simulated annealing algorithm and gravity calculation as described in any one of the first aspects.

[0017] Thirdly, this application also provides an electronic device, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to execute a chip layout method based on simulated annealing algorithm and gravity calculation as described in any one of the first aspects.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) In this application, based on the framework of the existing simulated annealing algorithm, the update efficiency of the layout scheme is accelerated by setting gravity operation, which can effectively reduce the number of iterations and layout time; 2) By moving the chip block diagrams at different positions to specific areas of the layout block diagram, the overall layout efficiency can be accelerated; 3) It can prevent excessive concentration in individual areas within the layout block diagram, and can increase the probability of finding the global optimal solution. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a layout scheme for manual layout.

[0021] Figure 2 The main flowchart of the simulated annealing algorithm provided by this invention is shown.

[0022] Figure 3 A schematic diagram of the gravity point and coordinate space provided for this invention.

[0023] Figure 4 This is a schematic diagram of a gravity calculation process provided by the present invention.

[0024] Figures 5 to 10 This is a schematic diagram of the layout process provided in this embodiment.

[0025] Figure 11 This provides the optimal layout scheme at different annealing temperatures in this first embodiment. Detailed Implementation

[0026] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0027] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0029] Example 1 The current standard method for chip layout is manual placement by personnel. Figure 1 An example of a manually arranged layout is shown. Figure 1 In the diagram, blue rectangles represent the layout area, while black rectangles numbered 1-12 each represent a chip to be laid out; a spacing h is maintained between different chips; similarly, the boundaries between chips and the layout area are usually maintained at least a spacing h.

[0030] As mentioned above, manual layout planning is inefficient, and existing automatic layout schemes based on annealing algorithms still have slow convergence speeds because they rely solely on random changes in perturbations to update the layout, requiring further improvement.

[0031] To address this, this application proposes a chip placement method based on simulated annealing algorithm and gravity calculation. This method can perform automatic placement based on the framework of simulated annealing algorithm, but adds a gravity calculation process. Through gravity calculation, chips at different positions can be moved to specific target positions, thereby improving the rate of updating the placement scheme each time and reducing the number of iterations required to obtain a placement scheme that meets the conditions.

[0032] In this first embodiment, a chip layout method based on simulated annealing algorithm and gravity calculation is first provided, including the following steps: Step 1: Generate a layout diagram and a chip diagram based on the layout area and the size information of the chip to be laid out; It is understandable that in the current actual working conditions, the shape of the chips to be laid out is rectangular. Similarly, the layout area (i.e. the area used to arrange and accommodate the chips to be laid out) is also rectangular. Therefore, the specific dimensions of each chip to be laid out can be obtained and a corresponding rectangle can be formed, which is called a chip block diagram. The specific dimensions of the layout area can be obtained and a corresponding rectangle can be formed, which is called a layout block diagram.

[0033] It should be noted that in practice, the area of ​​the provided layout area is usually large enough to accommodate all the chips to be laid out (the spacing between the chips has been taken into account). If the area of ​​the provided layout area is insufficient to accommodate all the chips to be laid out, this can be solved by reducing the number of chips to be laid out or increasing the area of ​​the layout area. Alternatively, a sufficiently large layout area can be provided initially, and the excess layout area can be cut off after a sufficiently compact layout is obtained.

[0034] In this first embodiment, the area of ​​the provided layout area is large enough to accommodate all the chips to be laid out (the spacing between the chips has been taken into account); in other embodiments, a solution can be made by initially providing a sufficiently large layout area and then cutting off the excess layout area after obtaining a sufficiently compact layout scheme.

[0035] Step 2: Iteratively update the chip block diagram layout scheme based on the simulated annealing algorithm until the globally optimal layout scheme is output; Figure 2 The basic flow of the simulated annealing algorithm is shown. Figure 3 A schematic diagram of the gravity point and coordinate space provided by the present invention is shown. Figure 4 The gravity calculation process is shown. Figures 5 to 10 This shows the changes in the layout scheme after each processing in this embodiment.

[0036] Reference Figures 2 to 10 As shown, the specific process is as follows: Step 21: Define the gravity point and construct the coordinate space; like Figure 3 As shown, first define the layout diagram ( Figure 3 Any vertex of the blue rectangular box in the diagram is the first gravity point (i.e., Figure 3 Point A in the layout diagram); define any vertex in the layout diagram that shares an edge with the first gravity point as the second gravity point (i.e., point A in the layout diagram); Figure 3 Point B in the layout diagram); define the other vertex in the layout diagram that shares an edge with the first gravity point as the third gravity point (i.e., point B in the layout diagram). Figure 3 (Point C in the middle).

[0037] It is understandable that after the first point of gravity is determined, there are two possible scenarios for the second and third points of gravity, as follows: Figure 3 a and Figure 3 As shown in b in Example 1. In this first embodiment, using Figure 3 Let's take 'a' as an example to illustrate.

[0038] By defining the first, second, and third gravity points, a two-dimensional coordinate space can be constructed. Specifically, the first gravity point is the origin, the line connecting the first and second gravity points is the first axis (or X-axis), and the line connecting the first and third gravity points is the second axis (or Y-axis), together forming a coordinate space. During subsequent layout, each chip block diagram is required to reside within this coordinate space.

[0039] In this embodiment, the sides of the layout diagram are also defined. Specifically, the side where both the first gravity point and the second gravity point exist simultaneously is designated as the first side; the side where both the first gravity point and the third gravity point exist simultaneously is designated as the second side; the side in the layout diagram adjacent to the second side is designated as the third side; and the side in the layout diagram adjacent to the first side is designated as the fourth side. It can be understood that, as... Figure 3 As shown in 'a', the first to fourth sides are arranged clockwise, as follows: Figure 3 As shown in b, the first to fourth sides are arranged counterclockwise.

[0040] In this embodiment, a first direction and a second direction are also defined. Specifically, the first direction is the direction from the first gravity point to the second gravity point, and the second direction is the direction from the first gravity point to the third gravity point.

[0041] Step 22: Initialize the chip block diagram to obtain the initial layout scheme of the chip block diagram, and calculate the initial solution of the objective function; Initialization involves arranging the chip block diagrams according to a set rule or a random arrangement to obtain an initial layout scheme. In this first embodiment, initialization is a set rule arrangement method, in which all chip block diagrams are arranged at intervals along the first axis. In other embodiments, other set rules or random arrangements may also be used, and there is no limitation on this.

[0042] In this embodiment, to satisfy the chip layout rules and reduce the number of calculations, a spacing distance h is defined. This spacing distance h is used to limit the minimum spacing between different chip block diagrams and between the edges of chip block diagrams and layout block diagrams. Of course, this spacing distance h can be used only in gravity calculations, or it can be omitted.

[0043] like Figure 5 The image shows the initial layout scheme obtained after initialization. It can be understood that in the simulated annealing algorithm, the merits of the layout scheme are judged by using objective functions. Specifically, in this embodiment, two objective functions are used: the first objective function is the ratio of the total area of ​​the chip block diagrams within the layout block diagram to the area of ​​the layout block diagram itself; the second objective function is the ratio of the total area of ​​all chip block diagrams to the area of ​​the smallest bounding rectangle formed by all chip block diagrams.

[0044] In this embodiment, both a first objective function and a second objective function are used; in other embodiments, only one or more objective functions may be used; thus, the merits of the layout scheme can be determined by calculating the solution of the objective function. Furthermore, a penalty mechanism can be introduced when calculating the solution of the objective function: for example, collision penalty: if there is overlap between chip block diagrams, the penalty value is increased; boundary violation penalty: if a chip block diagram exceeds the layout block diagram, the penalty value is increased.

[0045] In this embodiment, two criteria are used to determine which solution is better. Criterion 1 is 1 ÷ (first objective function value + collision penalty value + boundary violation penalty value); Criterion 2 is 1 ÷ (second objective function value + collision penalty value + boundary violation penalty value). Only when both criteria decrease simultaneously is it considered a better solution. It can be understood that in this embodiment, since an interval distance h is set, there is actually no collision penalty, and therefore the collision penalty value can be omitted. The specific settings of the objective function and penalty mechanism can also refer to existing technologies.

[0046] Step 23: Perform gravity calculations on the chip block diagram; In this embodiment, after initialization, a gravity calculation can be performed on the chip block diagram. In other embodiments, this gravity calculation step can be omitted.

[0047] In this application, the purpose of adding gravity calculation is to move the chip block diagrams at different positions to different boundaries, thereby improving the efficiency of the layout scheme and reducing the number of iterations.

[0048] Reference Figure 3 and Figure 4 As shown, three different gravity points (i.e., the first gravity point, the second gravity point, and the third gravity point) are defined on the layout diagram to move chip block diagrams at different positions to different gravity points. In this embodiment, chip block diagrams located within the layout diagram are moved to the first gravity point; chip block diagrams located outside the layout diagram are moved to the second or third gravity point. In this embodiment, a chip block diagram located within the layout diagram means that the chip block diagram is completely within the layout diagram; in this embodiment, a chip block diagram located outside the layout diagram means that at least a portion of the chip block diagram is outside the layout diagram.

[0049] refer to Figure 4 The illustration shows a single chip block diagram being moved each time; in practice, the method of moving one or more chip block diagrams each time can be adopted according to different needs.

[0050] For details, please refer to Figure 4 As shown in a, for chip block diagrams located within the layout block diagram (using... Figure 4 chip frame in Figure 1 (For example), first translate it towards the first side, then translate it towards the second side, thus moving it towards the first gravity point. The result is as follows. Figure 4 As shown in b; of course, you can also first translate towards the second side and then towards the first side, and you can also move to the first gravity point.

[0051] For details, please refer to Figure 4 As shown in 'a', the line containing the fourth side outside the layout diagram (i.e. Figure 4 Chip block diagram in the first direction of the right boundary shown (as shown) Figure 4 chip frame in Figure 2 (For example) Moving towards the third point of gravity involves first translating it towards the third side (i.e., translating it towards the upper boundary), and then translating it towards the second side. The process is as follows: Figure 4 As shown in c and d in the diagram; the line containing the third side outside the layout frame (i.e. Figure 4 Chip block diagram in the second direction of the upper boundary shown (as shown) Figure 4 chip frame in Figure 3 (For example) Moving towards the second point of gravity involves first translating it towards the fourth side (i.e., towards the right boundary) and then translating it towards the first side, as follows: Figure 4 As shown in c and d.

[0052] Since this example moves a single chip block diagram at a time, once the above calculation is completed, the next loop can begin, continuing to move chip block diagrams at different positions to different boundaries.

[0053] As described above, in this embodiment, when performing gravity calculations, an interval distance h is also defined, that is, when moving the chip block diagram each time, the minimum spacing relationship between chip block diagrams and between the edges of the chip block diagram and the layout block diagram needs to be considered.

[0054] Specifically, for chip block diagrams located within the layout diagram, each chip block diagram can be translated sequentially until the currently moved chip block diagram maintains a distance h between its edge and the edge of the chip block diagram in the translation direction or the layout diagram in the translation direction.

[0055] Specifically, for chip block diagrams located outside the layout block diagram, the details are as follows: When translating towards the fourth side, all chip block diagrams are translated simultaneously until the currently moved chip block diagram maintains a distance h between it and the line containing the fourth side; when translating towards the first side, each chip block diagram is translated sequentially until the currently moved chip block diagram maintains a distance h between it and the chip block diagram in the translation direction or the first side. When translating towards the third side, all chip block diagrams are translated simultaneously until the currently moved chip block diagram maintains a distance h between it and the line containing the third side; when translating towards the second side, each chip block diagram is translated sequentially until the currently moved chip block diagram maintains a distance h between it and the chip block diagram in the translation direction or the second side.

[0056] Figure 6 The results of gravity calculations on the initial layout scheme are shown. Figure 5 It can be seen that since the initialization uses a regular arrangement along the first axis, the chip block diagrams within the layout diagram do not need to be moved. However, the chip block diagrams outside the layout diagram are all located in the first direction of the line containing the fourth side and need to be moved towards the third gravity point. That is, they are all first translated towards the third side until the currently moved chip block diagram maintains a distance h between itself and the line containing the third side. The result is as follows: Figure 6 As shown in 'a'; then translate towards the second side, and so on, translating each chip block diagram until the currently moved chip block diagram maintains a distance h from the chip block diagram in the translation direction or the second side, as shown in the figure. Figure 6 As shown in b in the figure.

[0057] It is understandable that after performing gravity calculations, a new layout scheme will be obtained, and the solution of the objective function can be calculated for this layout scheme, and it can be determined whether to retain the solution.

[0058] Step 24: Perform multiple iterations at the initial temperature; It is understandable that the simulated annealing algorithm starts from the initial temperature, performs multiple iterations at each temperature to obtain the optimal layout scheme at the current temperature; then it continuously cools down until the termination temperature is reached, and outputs the optimal layout scheme at the termination temperature as the global optimal layout scheme.

[0059] First, multiple iterations are performed at the initial temperature, with each iteration yielding an updated layout scheme. In this embodiment, the layout scheme is updated by sequentially performing perturbation processing and gravity calculation on the previously obtained layout scheme. Perturbation processing typically includes translation, swapping, and rotation; in this embodiment, translation and swapping perturbations are illustrated. The gravity calculation after perturbation can be performed as described in step 23.

[0060] Taking translational perturbation as an example, the chip block diagram can be randomly translated once or multiple times. The number of translations and the direction of translation can be set randomly; the translation distance for each translation can also be set according to the actual situation, such as a specific value or function value, or a range of translation distances. In this embodiment, the translational perturbation distance is a function related to the annealing temperature. By setting a maximum translation distance at an initial temperature T0, the maximum translation distance at the current temperature T is ln(T) / ln(T0).

[0061] Figure 7 The result after applying a translational perturbation to the current layout scheme is shown. For example... Figure 7 As shown in 'a', the system randomly selected the chip block diagram with ID 1 for translation. The result after moving a preset distance is as follows: Figure 7 As shown in b in the diagram. After completing the perturbation processing, gravity calculations are performed to obtain a new layout scheme. The specific gravity calculation process is as described above and will not be repeated here. The result after the gravity calculation is shown in the diagram. Figure 8 As stated above.

[0062] One or more swap perturbations can also be performed, that is, randomly selecting two chip block diagrams and exchanging their positions. It is understandable that there may be overlap of chip block diagrams after the swap, but this overlap will be adjusted to remove it during gravity calculation.

[0063] Figure 9 The result is shown after perturbing the current layout scheme. For example... Figure 9 As shown in 'a', the system randomly selected chip block diagrams with IDs 4 and 6 and swapped their positions. The result after the swap is shown in 'a'. Figure 9 As shown in b in the diagram. Similarly, after completing the perturbation processing, gravity calculations are performed to obtain a new layout scheme. The specific gravity calculation process is as described above and will not be repeated here. The result after the gravity calculation is shown in the diagram. Figure 10 As shown.

[0064] It's understandable that the objective function can be calculated for the new layout scheme obtained after gravity calculations to obtain the current solution. Then, the current solution is compared with the previous solution (i.e., the temporary solution saved at the current temperature): if the current solution is better than the previous solution, it is accepted and updated as the temporary solution at the current temperature; if the current solution is worse than the previous solution, a probability formula is used to determine whether to accept the current solution as the temporary solution at the current temperature. The higher the current temperature, the higher the acceptance probability, thus avoiding the omission of local optima. Afterwards, the temporary solution at the current temperature is compared with the historical best solution; if it is better than the historical best solution, the historical best solution is updated.

[0065] In this embodiment, two criteria are used to determine which solution is better, the current one or the previous one. Criterion 1 is 1 ÷ (first objective function value + collision penalty value + boundary violation penalty value); Criterion 2 is 1 ÷ (second objective function value + collision penalty value + boundary violation penalty value). Only when both criteria decrease simultaneously is the solution considered better. It can be understood that in this embodiment, due to the set interval distance h, there will be no overlapping collisions after gravity calculation, and therefore no actual collision penalty exists; thus, the collision penalty value can be omitted. The temporary solution at the current temperature and the historical best solution can also be compared using the above criteria.

[0066] In this embodiment, taking translation and swapping perturbations as examples, two perturbations and two gravity calculations were performed. This is considered as completing one iteration. The objective function solution is calculated and compared for the layout scheme obtained after this iteration. In other embodiments, any one or more perturbations such as translation, swapping, or rotation can be used. The objective function solution can be calculated and compared between one perturbation and gravity calculation, or it can be calculated and compared after multiple perturbations and multiple gravity calculations.

[0067] The first iteration at the initial temperature has been completed as described above. Subsequent iterations can be repeated at this temperature until the predetermined number of iterations is reached, yielding the optimal solution for that temperature. In this embodiment, the number of iterations is designed to be 1000 at each temperature.

[0068] After iteration at the current temperature is completed, a temperature update is performed to proceed to the next temperature. The temperature update rate can be controlled by a cooling coefficient. In this embodiment, the initial temperature T0 is 5000, the cooling coefficient is 0.9, and the termination temperature is 1e. -4 That is, it will be performed 169 times. Temperature iteration.

[0069] After entering the next temperature, the algorithm continues to iterate and update at the current temperature according to the above steps until the preset termination temperature is reached. At this point, the algorithm stops looping and the optimal solution at the termination temperature is output as the global optimal layout scheme.

[0070] In other embodiments, a threshold for the objective function can also be set as the termination condition for the algorithm loop. That is, when the objective function solution corresponding to the generated layout scheme reaches the expected goal, the iteration can be terminated and the solution can be output as the globally optimal layout scheme.

[0071] Figure 11 This provides the optimal layout scheme at different annealing temperatures in Embodiment 1. It can be observed that as the annealing temperature decreases, the chip block diagrams are arranged more densely within the layout diagram. At an annealing temperature of 11.0927, all chip block diagrams are already arranged within the layout diagram. Further optimization can further reduce the area of ​​the minimum bounding rectangle formed by all chip block diagrams, resulting in a denser arrangement of the chip block diagrams and higher utilization of the layout area.

[0072] It is understandable that if the globally optimal layout scheme obtained when the algorithm terminates still cannot place all chip block diagrams inside the layout block diagram or achieve the expected results, the layout can be performed again by adjusting the algorithm parameters (such as initial temperature, termination temperature, cooling rate, number of iterations at each temperature, etc.) to obtain a satisfactory layout scheme in turn.

[0073] Example 2 Embodiment 2 of this application provides an electronic device that implements the steps of the aforementioned chip layout method based on simulated annealing algorithm and gravity calculation, or the steps of the aforementioned chip layout method based on simulated annealing algorithm and gravity calculation. This electronic device may include: a processor, a communication interface, memory, and a communication bus. The processor, communication interface, and memory communicate with each other via the communication bus. The processor can call logical instructions from the memory. These logical instructions can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0074] Example 3 This application provides a computer storage medium, including a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by the computer, the computer is able to perform the steps of the chip layout method based on simulated annealing algorithm and gravity calculation described above, or the steps of the chip layout method based on simulated annealing algorithm and gravity calculation described above.

[0075] Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0076] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0077] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A chip layout method based on simulated annealing algorithm and gravity calculation, characterized in that, Includes the following steps: A layout diagram and a chip diagram are generated based on the layout area and the size information of the chip to be laid out, and both the layout diagram and the chip diagram are rectangular. Based on the simulated annealing algorithm, the layout scheme of the chip block diagram is iteratively updated until the globally optimal layout scheme is output. The process of updating the layout scheme of the chip block diagram includes: perturbing the chip block diagram in the current layout scheme; and performing gravity calculations on the perturbed chip block diagram to obtain a new layout scheme. The gravity calculation includes: moving the chip block diagram located within the layout diagram to a first gravity point; and moving the chip block diagram located outside the layout diagram to a second or third gravity point. The first gravity point is any vertex of the layout diagram, the second gravity point is any vertex in the layout diagram that shares an edge with the first gravity point, and the third gravity point is another vertex in the layout diagram that shares an edge with the first gravity point.

2. The chip layout method based on simulated annealing algorithm and gravity calculation according to claim 1, characterized in that, A coordinate space is constructed using the first gravity point as the origin, combined with the second gravity point and the third gravity point; When updating the layout scheme of the chip block diagram, each chip block diagram is limited to being located within the coordinate space.

3. The chip layout method based on simulated annealing algorithm and gravity calculation according to claim 2, characterized in that, The process of moving the chip block diagram located within the layout block diagram toward the first gravity point includes: For the chip block diagram located within the layout diagram, first translate it towards the first side and then towards the second side; or, for the chip block diagram located within the layout diagram, first translate it towards the second side and then towards the first side. Wherein, the first side is the side in the layout diagram where both the first gravity point and the second gravity point exist simultaneously, and the second side is the side in the layout diagram where both the first gravity point and the third gravity point exist simultaneously.

4. The chip layout method based on simulated annealing algorithm and gravity calculation according to claim 3, characterized in that, The process of moving the chip block diagram located outside the layout block diagram toward the second gravity point or the third gravity point includes: The chip block diagram located outside the layout diagram and along the straight line containing the fourth side is moved towards the third gravity point; the chip block diagram located outside the layout diagram and along the straight line containing the third side is moved towards the second gravity point. Wherein, the third side is the other side adjacent to the second side in the layout diagram, and the fourth side is the other side adjacent to the first side in the layout diagram; the first direction is the direction from the first gravity point to the second gravity point, and the second direction is the direction from the first gravity point to the third gravity point.

5. The chip layout method based on simulated annealing algorithm and gravity calculation according to claim 4, characterized in that, The process of moving the chip block diagram located outside the layout block diagram toward the second gravity point or the third gravity point includes: For the chip block diagram located outside the layout block diagram and in the first direction of the straight line containing the fourth side, first translate it towards the third side, and then translate it towards the second side; For the chip block diagram located outside the layout block diagram and on the second direction of the straight line containing the third side, first translate it towards the fourth side, and then translate it towards the first side.

6. A chip layout method based on simulated annealing algorithm and gravity calculation according to any one of claims 3 or 5, characterized in that, In the gravity calculation, the interval distance h is defined; For the chip block diagram located within the layout block diagram: Each of the chip block diagrams is sequentially translated until the currently moved chip block diagram maintains the interval distance h between itself and the edge of the chip block diagram or the layout diagram in the translation direction; For the chip block diagram located outside the layout block diagram: When translating towards the fourth side, all chip block diagrams are translated simultaneously until the currently moved chip block diagram maintains the interval distance h between it and the line containing the fourth side; when translating towards the first side, each chip block diagram is translated sequentially until the currently moved chip block diagram maintains the interval distance h between it and the chip block diagram in the translation direction or the first side. When translating towards the third side, all chip block diagrams are translated simultaneously until the currently moved chip block diagram maintains the interval distance h between it and the straight line containing the third side; when translating towards the second side, each chip block diagram is translated sequentially until the currently moved chip block diagram maintains the interval distance h between it and the chip block diagram in the translation direction or the second side.

7. The chip layout method based on simulated annealing algorithm and gravity calculation according to claim 1, characterized in that, The process of iteratively updating the layout scheme of the chip block diagram based on the simulated annealing algorithm until the globally optimal layout scheme is output includes: S1. Initialize the chip block diagram to obtain the initial layout scheme of the chip block diagram, and calculate the solution of the objective function; S2. At the current temperature, update the layout scheme of the chip block diagram and calculate the current solution of the objective function; S3. Compare the current solution with the previous solution: If the current solution is better than the previous solution, accept the current solution; if the current solution is worse than the previous solution, determine whether to accept the current solution using the probability formula. S4. Update the layout scheme of the chip block diagram and calculate the current solution of the objective function; S5. Repeat steps S3 and S4 until the predetermined number of iterations is reached; S6. Proceed to the next temperature and repeat steps S2 and S5 until the termination temperature and / or the threshold of the objective function are reached, and output the globally optimal layout scheme.

8. The chip layout method based on simulated annealing algorithm and gravity calculation according to claim 1, characterized in that, The initialization process involves arranging the chip block diagram in a regular or random manner. After the initialization process, gravity calculations are performed on the chip block diagram.

9. A computer storage medium, characterized in that, The computer storage medium stores a computer program; when the computer program is run on the computer, it causes the computer to perform a chip layout method based on simulated annealing algorithm and gravity calculation as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to execute a chip layout method based on simulated annealing algorithm and gravity calculation as described in any one of claims 1-8.

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