High-power radio frequency circulator based on silicon-based CMOS (complementary metal oxide semiconductor) process
By using a high-power RF circulator based on silicon-based CMOS technology, and employing a combination of a gyroscope, LC components, and a clock boost circuit, the problem of limited power processing capability in existing RF circulators is solved, achieving improved power processing capability and chip integration, while reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-14
AI Technical Summary
Existing RF circulators based on Si-based CMOS technology suffer from problems such as limited power handling capability, high power consumption, and insufficient integration.
A transmission network consisting of a gyroscope, lumped-parameter LC elements, and a clock boost circuit is adopted. The power processing capability is improved by using a fully differential CMOS transistor switch pair and an LC ladder structure λ/4 transmission line through clock boost technology. The phase delay is achieved by using an LC series-parallel topology and signal control is performed by combining a Gilbert quadrature unit.
Without compromising transistor reliability, it achieves a 3x increase in power handling capability, a 50% reduction in chip area, excellent linearity and isolation, and is suitable for CMOS process integration, thereby reducing power consumption.
Smart Images
Figure CN121864055A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of radio frequency integrated circuit design technology, and specifically relates to a high-power radio frequency circulator based on silicon-based CMOS technology that uses clock boosting technology to improve power capacity. Background Technology
[0002] With the advancement of wireless communication technology, full-duplex communication has become a key technology for resolving the contradiction between limited spectrum resources and increasing data transmission demands, due to its ability to simultaneously transmit and receive signals within the same frequency band. Compared to traditional half-duplex communication, it significantly improves spectrum utilization efficiency, theoretically doubling it. As the demand for high-speed, high-capacity communication continues to increase, the research and application of full-duplex communication technology are receiving increasing attention. Circulators, as a key component of full-duplex RF chips, effectively suppress self-interference by isolating transmitted and received signals, significantly improving communication quality. Compared to traditional antenna isolation methods, circulator designs are more compact and efficient, reducing system complexity and optimizing spectrum utilization, thus driving the development of wireless communication technology. Circulator implementations include traditional magnetic circulators, electrically balanced duplexers (EBD), distributed transmission line-based circulators, and non-magnetic chip-level circulators. Chip-level circulators use transistor switches and switched capacitors instead of magnetic materials, achieving miniaturization, low cost, and high integration. They are easily compatible with modern CMOS processes and suitable for multi-band and broadband applications. However, the transistor switches used in chip-level circulators significantly affect their power handling capabilities. Factors such as on-resistance, breakdown voltage, thermal effects, nonlinear effects, and switching speed collectively determine the stability and power limit of a circulator when processing high-power signals. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to address the problems of limited power processing capability, high power consumption and insufficient integration of existing RF circulators based on Si-based CMOS technology. In order to solve the above problems, a high-power RF circulator based on silicon-based CMOS technology is provided.
[0004] The object of this invention is achieved in the following manner: A high-power radio frequency circulator based on silicon-based CMOS technology. include: A transmission network consisting of a rotary valve and lumped parameter LC elements; The rotary device includes: a first switch pair K1, a second switch pair K2, and a λ / 4 transmission line connected between the first switch pair and the second switch pair; The first switch is connected between the transmitter (TX port) and the λ / 4 transmission line; The second switch is connected between the λ / 4 transmission line and the antenna end (ANT port); The first switch pair and the second switch pair are controlled by complementary, non-overlapping first local oscillator signals LO1⁺, LO1⁻ and second local oscillator signals LO2⁺, LO2⁻, respectively.
[0005] The transmission network includes an LC series-parallel topology, which consists of multiple lumped elements. Each lumped element provides a predetermined phase delay, and the required phase delay is achieved by cascading multiple transmission lines.
[0006] The operation of the gyroscope during the forward signal transmission phase includes: First half of the cycle working status: When For high level, When the signal is low, the input signal v1+(t) at the TX port is switched by the first switch. Non-polarity flip transmission to Transmission line, via After the delay, For high level, When in a low-level state, the second switch is used to... The non-polarity flipped output is sent to the ANT port to form the output signal v2-(t); Second half of the cycle working state: when Low level When the signal is high, the input signal v1+(t) passes through the first switch. The first polarity reversal occurs, after After the delay, Low level When in a high-level state, the second switch... This results in a second polarity reversal, and the final output v2-(t) to the ANT port maintains the same polarity as the input signal v1+(t).
[0007] The operation of the gyroscope during the signal reverse transmission phase includes: First half of the cycle working status: When High level When the signal is low, the input signal v2+(t) at the ANT port is switched by the second switch. Non-polarity switching is transmitted to the transmission line, via After the delay, Low level When in a high-level state, the first switch... A polarity reversal occurs, and the output to the TX port forms v1-(t); Second half-cycle operating state: when... Low level When the signal is high, the input signal v2+(t) passes through the second switch. The first polarity reversal occurs, after After the delay, High level When in a low-level state, the first switch... The non-polarity switching transmission ensures that the final output v1-(t) at port 1 maintains an opposite polarity relationship with the input signal v2+(t).
[0008] The circulator also includes a clock boost circuit, which includes: The first capacitor C1 and the second capacitor C2 are connected in series between the output buffer and the load; Initialization phase: During the first clock cycle, the first capacitor is charged to +VDD, and the second capacitor is charged to -VDD; During the positive half-cycle operation phase: the first capacitor boosts the output voltage VDD, forming a +2VDD voltage at the load terminal; During the negative half-cycle operation phase: the second capacitor reduces the output voltage VDD, and the load terminal voltage range is from -VDD to +2VDD, achieving a peak-to-peak swing of 3VDD.
[0009] The clock boost circuit operates at a voltage that does not exceed the transistor breakdown voltage, and the clock drive circuit operates under the VDD power supply voltage.
[0010] Both the first and second switch pairs are composed of CMOS transistors and adopt a fully differential structure, including two sets of Gilbert quadrature units.
[0011] The λ / 4 transmission line is implemented by an LC lumped parameter network, which includes a multi-stage LC ladder structure, with each stage providing a fixed phase delay.
[0012] The beneficial effects of the present invention are as follows: The rotator structure of the present invention consists of differential transmission lines and two sets of Gilbert orthogonal units. It adopts a fully differential signal design, which reduces the chip area by 50% while increasing the power density by 3 times. It maintains excellent linearity and isolation indicators, is suitable for CMOS process integration, and is superior to traditional circulator designs in terms of power processing capability, integration degree and energy efficiency ratio. Attached Figure Description
[0013] Figure 1 A structural block diagram of a CMOS circulator provided in an embodiment of the present invention; Figure 2 This is a structural block diagram of an LC lumped parameter transmission line provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of the rotary device provided in an embodiment of the present invention; Figure 4 This is a structural block diagram of a clock boost circuit provided in an embodiment of the present invention; Figure 5 The return loss at each port of the circulator at a frequency of 1.4 GHz is simulated for an embodiment of the present invention. Figure 6 The circulator simulation at 1.4 GHz frequency provides the insertion loss and isolation performance at adjacent ports for embodiments of the present invention; Figure 7 The input P1dB value of the circulator at a frequency of 1.4GHz is provided for the embodiments of the present invention. Detailed Implementation
[0014] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0015] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0016] This invention provides a high-power radio frequency circulator based on silicon-based CMOS technology, comprising: A transmission network consisting of a rotary valve and lumped parameter LC elements; The rotary device includes: a first switch pair K1, a second switch pair K2, and a λ / 4 transmission line connected between the first switch pair and the second switch pair; The first switch is connected between the transmitter (TX port) and the λ / 4 transmission line; The second switch is connected between the λ / 4 transmission line and the antenna end (ANT port); The first switch pair and the second switch pair are controlled by complementary, non-overlapping first local oscillator signals LO1⁺, LO1⁻ and second local oscillator signals LO2⁺, LO2⁻, respectively.
[0017] The transmission network includes an LC series-parallel topology, which consists of multiple lumped elements. Each lumped element provides a predetermined phase delay, and the required phase delay is achieved by cascading multiple transmission lines.
[0018] The operation of the gyroscope during the forward signal transmission phase includes: First half of the cycle working status: When High level When the signal is low, the input signal v1+(t) at the TX port is switched by the first switch. Non-polarity flip transmission to Transmission line, via After the delay, High level When in a low-level state, the second switch is used to... The non-polarity flipped output is sent to the ANT port to form the output signal v2-(t); Second half of the cycle working state: when Low level When the signal is high, the input signal v1+(t) passes through the first switch. The first polarity reversal occurs, after After the delay, Low level When in a high-level state, the second switch... This results in a second polarity reversal, and the final output v2-(t) to the ANT port maintains the same polarity as the input signal v1+(t).
[0019] The operation of the gyroscope during the signal reverse transmission phase includes: First half of the cycle working status: When High level When the signal is low, the input signal v2+(t) at the ANT port is switched by the second switch. Non-polarity switching is transmitted to the transmission line, via After the delay, Low level When in a high-level state, the first switch... A polarity reversal occurs, and the output to the TX port forms v1-(t); Second half-cycle operating state: when... Low level When the signal is high, the input signal v2+(t) passes through the second switch. The first polarity reversal occurs, after After the delay, High level When in a low-level state, the first switch... The non-polarity switching transmission ensures that the final output v1-(t) at port 1 maintains an opposite polarity relationship with the input signal v2+(t).
[0020] The circulator also includes a clock boost circuit, which includes: The first capacitor C1 and the second capacitor C2 are connected in series between the output buffer and the load; Initialization phase: During the first clock cycle, the first capacitor is charged to +VDD, and the second capacitor is charged to -VDD; During the positive half-cycle operation phase: the first capacitor boosts the output voltage VDD, forming a +2VDD voltage at the load terminal; During the negative half-cycle operation phase: the second capacitor reduces the output voltage VDD, and the load terminal voltage range is from -VDD to +2VDD, achieving a peak-to-peak swing of 3VDD.
[0021] The clock boost circuit operates at a voltage that does not exceed the transistor breakdown voltage, and the clock drive circuit operates under the VDD power supply voltage.
[0022] Both the first and second switch pairs are composed of CMOS transistors and adopt a fully differential structure, including two sets of Gilbert quadrature units.
[0023] The λ / 4 transmission line is implemented by an LC lumped parameter network, which includes a multi-stage LC ladder structure, with each stage providing a fixed phase delay.
[0024] like Figure 1 As shown, the CMOS circulator includes a transmission network composed of a gyrator and lumped-parameter LC elements. When a signal is input from the transmitter (TX port), the signal is divided into a first transmission path and a second transmission path. The first transmission path is directly connected to the antenna (ANT port) and generates a 90° phase delay. The second transmission path is connected to the ANT port via the gyrator. The gyrator applies a +90° phase shift to the signal, so that the total phase delay of the second transmission path at the ANT port is also 90°. The two signals are in-phase superimposed at the ANT port and simultaneously canceled out at the receiver (RX port). When a signal is input from the ANT port, the signal is divided into a third transmission path and a fourth transmission path. The third transmission path is directly connected to the TX port and generates a 90° phase delay. The fourth transmission path is connected to the RX port via the gyrator. The gyrator applies a +90° phase shift to the signal, so that the total phase delay of the fourth transmission path at the RX port is also 90°. The two signals are in-phase superimposed at the RX port and simultaneously canceled out at the TX port. The detailed structure of the gyrator is shown below. Figure 3 As shown, the system includes a first switch pair K1, a second switch pair K2, and a λ / 4 transmission line connecting them. The input of the first switch pair K1 is connected to the TX port, and the output is connected to one end of the λ / 4 transmission line; the input of the second switch pair K2 is connected to the other end of the λ / 4 transmission line, and the output is connected to the ANT port. The first switch pair K1 and the second switch pair K2 are controlled by two pairs of complementary, non-overlapping local oscillation signals LO1⁺ / LO1⁻ and LO2⁺ / LO2⁻, respectively, to achieve switching of the signal path and polarity control.
[0025] like Figure 2 As shown, the transmission line is implemented using an LC series-parallel topology. The LC lumped-parameter transmission line is implemented using a multi-stage LC ladder network, with each stage providing a fixed phase delay. The required 90° total phase shift can be achieved by cascading multiple stages. This structure significantly reduces chip area compared to traditional microstrip lines.
[0026] The detailed structure of the rotary device is as follows: Figure 3As shown, the system includes a first switch pair K1, a second switch pair K2, and a λ / 4 transmission line connecting them. The input of the first switch pair K1 is connected to the TX port, and the output is connected to one end of the λ / 4 transmission line; the input of the second switch pair K2 is connected to the other end of the λ / 4 transmission line, and the output is connected to the ANT port. The first switch pair K1 and the second switch pair K2 are controlled by two pairs of complementary, non-overlapping local oscillation signals LO1⁺ / LO1⁻ and LO2⁺ / LO2⁻, respectively, to achieve switching of the signal path and polarity control.
[0027] During the forward signal transmission phase: First half of the cycle working status: When High level When the signal is low, the input signal v1+(t) at port 1 is switched by the first switch. Non-polarity flip transmission to Transmission line, via After the delay, High level When in a low-level state, the second switch is used to... The non-polarity flipped output is sent to port 2 to form the output signal v2-(t); Second half of the cycle working state: when Low level When the signal is high, the input signal v1+(t) passes through the first switch. The first polarity reversal occurs, after After the delay, Low level When in a high-level state, the second switch... A second polarity reversal occurs, and the final output v2-(t) to port 2 maintains the same polarity as the input signal v1+(t).
[0028] The operation of the gyroscope circuit during the signal reverse transmission phase includes: First half of the cycle working status: When High level When the signal is low, the input signal v2+(t) at port 2 is switched by the second switch. Non-polarity switching is transmitted to the λ / 4 transmission line, via After the delay, Low level When in a high-level state, the first switch... This generates a polarity reversal, and the output is sent to port 1 to form v1-(t); Second half of the cycle working state: when Low level When the signal is high, the input signal v2+(t) passes through the second switch. The first polarity reversal occurs, after After the delay, at a high level, When in a low-level state, the first switch... The non-polarity switching transmission ensures that the final output v1-(t) at port 1 maintains an opposite polarity relationship with the input signal v2+(t).
[0029] like Figure 4 As shown, the clock boost circuit is implemented using a switched capacitor topology, including a first capacitor. Second capacitor The and It is connected in series between the output buffer and the load; wherein: a) Initialization phase: During the first clock cycle, the first capacitor... The second capacitor is charged to the +VDD potential. a) Charged to -VDD potential; b) Positive half-cycle operation phase: During the positive half-cycle of the subsequent clock cycle, the first capacitor... The second capacitor operates, raising the output voltage to the VDD potential, thereby forming an output voltage of +2VDD at the load terminal; c) Negative half-cycle operating phase: During the negative half-cycle of the clock cycle, the second capacitor... The operation reduces the output voltage to the VDD potential, ultimately achieving a peak-to-peak voltage swing of 3VDD from -VDD to +2VDD at the load.
[0030] Figure 5 The return loss under circulator simulation at 1.4GHz provided in this embodiment of the invention is shown by the simulation curves. The return loss is below -10dB, indicating good signal transmission performance.
[0031] Figure 6 The insertion loss and isolation performance of the circulator at a frequency of 1.4 GHz provided in the embodiment of the present invention are shown by the simulation curves. It can be seen from the simulation curves that the transmit port and the receive port have good insertion loss and good isolation.
[0032] Figure 7 The P1dB compression point of the circulator at a frequency of 1.4GHz provided in the embodiment of the present invention shows that the circulator has good power processing capability.
[0033] This invention discloses a CMOS switching transmission line circulator and its method that uses clock boosting technology to enhance power capacity. The circulator comprises an LC lumped transmission line and a gyrator. Each side of the switching group is controlled by a non-overlapping square wave modulated signal. A switched-capacitor clock bootstrap technique is employed to achieve a clock swing three times larger than the power supply voltage without affecting transistor reliability. This improves the transistor's switching power handling capability while minimizing power consumption. This invention enhances the circulator's power handling capability.
[0034] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several changes and improvements without departing from the overall concept of the present invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A high-power radio frequency circulator based on silicon-based CMOS technology, characterized in that: include: A transmission network consisting of a rotary valve and lumped parameter LC elements; The rotary device includes: a first switch pair K1, a second switch pair K2, and a λ / 4 transmission line connected between the first switch pair and the second switch pair; The first switch pair is connected between the TX port and the λ / 4 transmission line; The second switch pair is connected between the λ / 4 transmission line and the ANT port; The first switch pair and the second switch pair are controlled by complementary, non-overlapping first local oscillator signals LO1⁺, LO1⁻ and second local oscillator signals LO2⁺, LO2⁻, respectively.
2. The high-power radio frequency circulator based on silicon-based CMOS technology according to claim 1, characterized in that: The transmission network includes an LC series-parallel topology, which consists of multiple lumped elements. Each lumped element provides a predetermined phase delay, and the required phase delay is achieved by cascading multiple transmission lines.
3. The high-power radio frequency circulator based on silicon-based CMOS technology according to claim 1, characterized in that: The operation of the gyroscope during the forward signal transmission phase includes: First half of the cycle working status: When High level When the signal is low, the input signal v1+(t) at the TX port is switched by the first switch. Non-polarity flip transmission to Transmission line, via After the delay, When the signal is high or low, the signal is transmitted through the second switch. The non-polarity flipped output is sent to the ANT port to form the output signal v2-(t); Second half of the cycle working state: when Low level When the signal is high, the input signal v1+(t) passes through the first switch. The first polarity reversal occurs, after After the delay, Low level When in a high-level state, the second switch is used to... This results in a second polarity reversal, and the final output v2-(t) to the ANT port maintains the same polarity as the input signal v1+(t).
4. The high-power radio frequency circulator based on silicon-based CMOS technology according to claim 1, characterized in that: The operation of the gyroscope during the signal reverse transmission phase includes: First half of the cycle working status: When High level When the signal is low, the input signal v2+(t) at the ANT port is switched by the second switch. Non-polarity switching is transmitted to the transmission line, via After the delay, Low level When in a high-level state, the first switch... A polarity reversal occurs, and the output to the TX port forms v1-(t); Second half-cycle operating state: when... Low level When the signal is high, the input signal v2+(t) passes through the second switch. The first polarity reversal occurs, after After the delay, High level When in a low-level state, the first switch... The non-polarity switching transmission ensures that the final output v1-(t) at port 1 maintains an opposite polarity relationship with the input signal v2+(t).
5. The high-power radio frequency circulator based on silicon-based CMOS technology according to claim 1, characterized in that: The circulator also includes a clock boost circuit, which includes: The first capacitor C1 and the second capacitor C2 are connected in series between the output buffer and the load; Initialization phase: During the first clock cycle, the first capacitor is charged to +VDD, and the second capacitor is charged to -VDD; During the positive half-cycle operation phase: the first capacitor boosts the output voltage VDD, forming a +2VDD voltage at the load terminal; During the negative half-cycle operation phase: the second capacitor reduces the output voltage VDD, and the load terminal voltage range is from -VDD to +2VDD, achieving a peak-to-peak swing of 3VDD.
6. The high-power radio frequency circulator based on silicon-based CMOS technology according to claim 5, characterized in that: The clock boost circuit operates at a voltage that does not exceed the transistor breakdown voltage, and the clock drive circuit operates under the VDD power supply voltage.
7. The high-power radio frequency circulator based on silicon-based CMOS technology according to claim 1, characterized in that: Both the first and second switch pairs are composed of CMOS transistors and adopt a fully differential structure, including two sets of Gilbert quadrature units.
8. The high-power radio frequency circulator based on silicon-based CMOS technology according to claim 1, characterized in that: The λ / 4 transmission line is implemented by an LC lumped parameter network, which includes a multi-stage LC ladder structure, with each stage providing a fixed phase delay.