Switching circuit and chip

Abstract

The invention discloses a switching circuit and a chip. The switching circuit comprises a power tube, a control unit and a first bias unit, a first end of the power tube is connected with a first end of the load to form an output end of the switching circuit, a second end of the power tube is connected with a first node, a second end of the load is connected with a second node, and the first node and the second node are used for being connected with power supply voltage and ground voltage; the first bias unit is connected with a reference potential and a second node, the first bias unit generates a first bias voltage based on the voltage of the second node and the reference potential in a reverse connection state, and the control unit is connected with the first bias unit, the control end of the power tube and the second node. And the control unit is started based on the control of the first bias voltage so as to control the communication between the control end of the power tube and the second node. According to the switching circuit provided by the invention, the power tube can be turned on only during reverse connection, and the work of the power tube cannot be influenced in other working scenes, so that the power tube can be protected.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a switching circuit and chip. Background Technology

[0002] Figure 1 The diagram shows a typical switching MOS circuit. M0 acts as a power transistor, controlled by the DRV circuit to turn on and off, while the resistor RL serves as the load. In many applications of switching MOS circuits, the resistor RL is an ohmic load. For example... Figure 2 As shown, when the power supply VCC and ground GND are reversed, the internal functional modules of the chip cannot continue to work, the DRV circuit cannot turn on the power transistor M0, and a current path from VCC to GND is formed through the resistor RL. The current in the ampere level continuously flows through the parasitic diode of the power transistor M0, which will damage the power transistor M0.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a switching circuit and chip that can turn on the power transistor when the power supply and ground are reversed.

[0005] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: a switching circuit connected to a load, comprising: a power transistor, a control unit, and a first bias unit;

[0006] The first end of the power transistor is connected to the first end of the load to form the output terminal of the switching circuit. The second end of the power transistor is connected to the first node, and the second end of the load is connected to the second node. The first node and the second node are used to connect to the power supply voltage and the ground voltage. Under normal conditions, the first node is connected to the power supply voltage and the second node is connected to the ground voltage. Under reverse connection conditions, the first node is connected to the ground voltage and the second node is connected to the power supply voltage.

[0007] The first bias unit is connected to a reference potential and a second node. The first bias unit is used to generate a first bias voltage based on the voltage of the second node and the reference potential when in reverse connection state. The control unit is connected to the first bias unit, the control terminal of the power transistor and the second node. The control unit is turned on based on the control of the first bias voltage to control the connection between the control terminal of the power transistor and the second node.

[0008] In one or more embodiments of the present invention, the control unit includes a first transistor, a first terminal of the first transistor being connected to the control terminal of a power transistor, a second terminal of the first transistor being connected to a second node, and the control terminal of the first transistor being connected to a first bias unit to receive a first bias voltage; or

[0009] The control unit includes a first transistor and a current-limiting resistor. A first terminal of the first transistor is connected to a first terminal of the current-limiting resistor. A second terminal of the current-limiting resistor is connected to a control terminal of the power transistor. A second terminal of the first transistor is connected to a second node. The control terminal of the first transistor is connected to a first bias unit to receive a first bias voltage.

[0010] The first transistor is an NMOS transistor.

[0011] In one or more embodiments of the present invention, the first bias unit is used to generate a predetermined value as a first bias voltage when it detects that the difference between the voltage value at the second node and the reference potential exceeds a preset value.

[0012] In one or more embodiments of the present invention, the first bias unit includes a first current limiting module and a first clamping module. The first end of the first current limiting module is connected to a second node, and the second end of the first current limiting module is connected to the first end of the first clamping module and the control unit to generate a first bias voltage. The second end of the first clamping module is connected to a reference potential.

[0013] The first current limiting module includes a first resistor or a first MOSFET. The first terminal of the first resistor is connected to a second node, and the second terminal of the first resistor is connected to the first terminal of a first clamping module and a control unit. The control terminal of the first MOSFET is connected to the first terminal of the first MOSFET, the first terminal of the first clamping module, and the control unit. The second terminal of the first MOSFET is connected to the second node; and / or

[0014] The first clamping module includes a first Zener diode or a second MOSFET. The cathode of the first Zener diode is connected to the second terminal of the first current limiting module and the control unit. The anode of the first Zener diode is connected to the reference potential. The control terminal of the second MOSFET is connected to the second terminal of the second MOSFET, the second terminal of the first current limiting module, and the control unit. The first terminal of the second MOSFET is connected to the reference potential.

[0015] In one or more embodiments of the present invention, the switching circuit further includes a switching module and a switching control unit. The first terminal of the switching module is connected to the control terminal of the power transistor, and the second terminal of the switching module is connected to the control unit. When the switching module is in a reverse connection state, it connects the control terminal of the power transistor and the control unit, and when it is in a normal state, it disconnects the connection between the control terminal of the power transistor and the control unit. The switching control unit is connected to the second terminal of the switching module, the output terminal of the switching circuit, and the power supply voltage. The switching control unit is used to adjust the voltage of the second terminal of the switching module to turn off the switching module when it is in a normal state.

[0016] In one or more embodiments of the present invention, the switch control unit includes a second transistor and a second bias unit. The second bias unit is connected to the output terminal of the switch circuit. The second bias unit is used to generate a predetermined value as a second bias voltage when the voltage value detected on the second node is less than a preset value. The first terminal of the second transistor is connected to the output terminal of the switch circuit, and the second terminal of the second transistor is connected to the second terminal of the switch module. The control terminal of the second transistor is connected to the second bias unit to receive the second bias voltage. The second transistor is turned on based on the control of the second bias voltage to control the connection between the second terminal of the switch module and the output terminal of the switch circuit.

[0017] In one or more embodiments of the present invention, the second bias unit includes a second current limiting module and a second clamping module. The first terminal of the second current limiting module is connected to the power supply voltage. The second terminal of the second current limiting module is connected to the first terminal of the second clamping module and the control terminal of the second transistor to generate a second bias voltage. The second terminal of the second clamping module is connected to the output terminal of the switching circuit.

[0018] The second current limiting module includes a second resistor or a third MOSFET. The first terminal of the second resistor is connected to the power supply voltage, and the second terminal of the second resistor is connected to the first terminal of the second clamping module and the second transistor. The control terminal of the third MOSFET is connected to the first terminal of the third MOSFET, the first terminal of the second clamping module, and the control terminal of the second transistor. The second terminal of the third MOSFET is connected to the power supply voltage; and / or

[0019] The second clamping module includes a second Zener diode or a fourth MOS transistor. The cathode of the second Zener diode is connected to the second terminal of the second current limiting module and the control terminal of the second transistor. The anode of the second Zener diode is connected to the output terminal of the switching circuit. The control terminal of the fourth MOS transistor is connected to the second terminal of the fourth MOS transistor, the second terminal of the second current limiting module, and the control terminal of the second transistor. The first terminal of the fourth MOS transistor is connected to the output terminal of the switching circuit.

[0020] In one or more embodiments of the present invention, the substrate of the first transistor is connected to a reference potential.

[0021] In one or more embodiments of the present invention, the switching circuit further includes a grounding control unit connected to a reference potential and a second node. The grounding control unit is used to cut off the path between the reference potential and the second node in a reverse connection state, and to connect the reference potential and the second node in a normal state.

[0022] The present invention also discloses a chip including the aforementioned switching circuit.

[0023] Compared with the prior art, the switching circuit and chip of the present invention generate a first bias voltage when the power supply voltage and ground voltage are reversed through the first bias unit, thereby turning on the control unit and connecting the control terminal of the power transistor to the power supply voltage to turn on the power transistor. The switching circuit of the present invention only functions to turn on the power transistor when reversed; it will not affect the operation of the power transistor in other operating scenarios, thus protecting the power transistor. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a circuit diagram of a switching circuit in the prior art where the power supply and ground are positively connected.

[0026] Figure 2 This is a circuit diagram of a switching circuit with reversed power and ground connections in the prior art.

[0027] Figure 3 This is a circuit diagram of a switching circuit according to an embodiment of the present invention.

[0028] Figure 4 This is a circuit diagram of the first bias unit in another embodiment of the present invention.

[0029] Figure 5 This is a circuit diagram of the second bias unit in another embodiment of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0031] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0032] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0033] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0034] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0035] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0036] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0037] like Figure 3 As shown, a switching circuit connected to a load RL in one embodiment of the present invention includes: a power transistor M0, a switching module 10, a control unit 20, a first bias unit 30, and a switching control unit 40.

[0038] The first terminal of the power transistor M0 is connected to the first terminal of the load RL to form the output terminal OUT of the switching circuit. The second terminal of the power transistor M0 is connected to the first node a, and the second terminal of the load RL is connected to the second node b. Under normal conditions, the first node a is connected to the power supply voltage VCC and the second node b is connected to the ground voltage GND. Under reverse connection conditions, the first node a is connected to the ground voltage GND and the second node b is connected to the power supply voltage VCC.

[0039] The first terminal of the switching module 10 is connected to the control terminal of the power transistor M0 to form node VG. The second terminal of the switching module 10 is connected to the control unit 20 and the switching control unit 40. The control terminal of the switching module 10 is connected to the control voltage VCP. When the switching module 10 is in the reverse connection state, it connects the control terminal of the power transistor M0 and the control unit 20. When the switching module 10 is in the normal state, it disconnects the connection between the control terminal of the power transistor M0 and the control unit 20. That is, when the switching module 10 is in the reverse connection state, the voltage of the control terminal of the power transistor M0 is raised through the switching module 10 and the control unit 20.

[0040] The first bias unit 30 is connected to the reference potential AVSS and the second node b. The first bias unit 30 is used to generate a predetermined value as the first bias voltage VZN1 when the difference between the voltage value on the second node b and the reference potential exceeds a preset value. The control unit 20 is connected to the first bias unit 30, the second terminal of the switch module 10 and the second node b. The control unit 20 is turned on based on the control of the first bias voltage VZN1 to control the connection between the second terminal of the switch module 10 and the second node b.

[0041] Additionally, the switch control unit 40 is connected to the second terminal of the switch module 10, the output terminal OUT of the switch circuit, and the power supply voltage VCC. The switch control unit 40 is used to adjust the voltage at the second terminal of the switch module 10 to turn off the switch module 10 under normal conditions. That is, when the first node a is connected to the power supply voltage VCC and the second node b is connected to the ground voltage GND, the switch control unit 40 pulls down the voltage at the second terminal of the switch module 10, thereby turning off the switch module 10.

[0042] Specifically, such as Figure 3 As shown, the switching module 10 includes a switching transistor MK. Due to process limitations, the switching transistor MK is a low-voltage transistor. The first terminal of the switching transistor MK is connected to the control terminal of the power transistor M0, and the control terminal of the switching transistor MK is connected to the control voltage VCP. The second terminal of the switching transistor MK is connected to the control unit 20 and the switching control unit 40. The cathode of the parasitic diode DK of the switching transistor MK is connected to the first terminal of the switching transistor MK, and the anode of the parasitic diode DK of the switching transistor MK is connected to the second terminal of the switching transistor MK. In other embodiments, the switching module 10 can use an NMOS transistor. In this case, the control terminal of the switching module 10 is connected to the first terminal of the switching module 10 and the control unit 20, and the second terminal of the switching module 10 is connected to the control terminal of the power transistor M0. That is, the control terminal (gate) of the NMOS transistor is connected to the first terminal (source) of the NMOS transistor and the control unit 20, and the second terminal (drain) of the NMOS transistor is connected to the control terminal of the power transistor M0.

[0043] In one embodiment, the control unit 20 includes a first transistor M1 and a current-limiting resistor Rp. A first terminal of the first transistor M1 is connected to the first terminal of the current-limiting resistor Rp, and a second terminal of the current-limiting resistor Rp is connected to the second terminal of the switching transistor MK of the switching module 10. The second terminal of the first transistor M1 is connected to a second node b. The control terminal of the first transistor M1 is connected to a first bias unit 30 to receive a first bias voltage VZN1. The substrate of the first transistor M1 is connected to a reference potential AVSS. Parasitic diodes are present between the substrate of the first transistor M1 and its first terminal, and between the substrate of the first transistor M1 and its second terminal. The cathode of the parasitic diode between the substrate of the first transistor M1 and its first terminal is connected to the first terminal of the first transistor M1, and the anode is connected to the substrate of the first transistor M1. The cathode of the parasitic diode between the substrate of the first transistor M1 and its second terminal is connected to the second terminal of the first transistor M1, and the anode is connected to the substrate of the first transistor M1. The current-limiting resistor Rp limits current; in other embodiments, the current-limiting resistor Rp may not be provided.

[0044] like Figure 3 As shown, the first bias unit 30 includes a first current limiting module and a first clamping module. The first end of the first current limiting module is connected to the second node b. The second end of the first current limiting module is connected to the first end of the first clamping module and the control terminal of the first transistor M1 of the control unit 20 to generate a first bias voltage VZN1. The second end of the first clamping module is connected to the reference potential AVSS.

[0045] In one embodiment, the first current limiting module includes a first resistor R1, the first end of the first resistor R1 is connected to the second node b, and the second end of the first resistor R1 is connected to the first end of the first clamping module and the control terminal of the first transistor M1 of the control unit 20.

[0046] In other embodiments, such as Figure 4 As shown, the first resistor R1 of the first current limiting module can be replaced by the first MOSFET N1. The control terminal of the first MOSFET N1 is connected to the first terminal of the first MOSFET N1, the first terminal of the first clamping module, and the control terminal of the first transistor M1 of the control unit 20 to generate the first bias voltage VZN1. The second terminal of the first MOSFET N1 is connected to the second node b.

[0047] like Figure 3 As shown, the first clamping module includes a first Zener diode D1. The cathode of the first Zener diode D1 is connected to the second terminal of the first resistor R1 of the first current limiting module and the control terminal of the first transistor M1 of the control unit 20. The anode of the first Zener diode D1 is connected to the reference potential AVSS.

[0048] In other embodiments, such as Figure 4 As shown, the first Zener diode D1 of the first clamping module can be replaced by one or more second MOSFETs. The number of second MOSFETs can be increased or decreased as needed. The control terminal of each second MOSFET is connected to its second terminal. That is, the second MOSFET adopts the "diode connection". If only one second MOSFET is set, the control terminal of the second MOSFET is connected to its second terminal and then connected to the second terminal of the first current limiting module and the control terminal of the first transistor M1 of the control unit 20. The first terminal of the second MOSFET N2 is connected to the reference potential AVSS. Figure 4 The diagram shows three second MOS transistors N21, N22, and N23 connected in series between the control terminal of the first transistor M1 in the control unit 20 and the reference potential AVSS.

[0049] like Figure 3As shown, the switch control unit 40 includes a second transistor M2 and a second bias unit. The second bias unit is connected to the power supply voltage VCC and the output terminal OUT of the switch circuit. The second bias unit generates a predetermined value as a second bias voltage VZN2 when the voltage value at the second node b is detected to be less than a preset value. The first terminal of the second transistor M2 is connected to the output terminal OUT of the switch circuit, and the second terminal of the second transistor M2 is connected to the second terminal of the switch transistor MK of the switch module 10. The control terminal of the second transistor M2 is connected to the second bias unit to receive the second bias voltage VZN2. The second transistor M2 is turned on based on the control of the second bias voltage VZN2 to control the connection between the second terminal of the switch transistor MK of the switch module 10 and the output terminal OUT of the switch circuit. The cathode of the parasitic diode of the second transistor M2 is connected to the second terminal of the second transistor M2, and the anode of the parasitic diode of the second transistor M2 is connected to the first terminal of the second transistor M2.

[0050] In one embodiment, the second bias unit includes a second current limiting module and a second clamping module. The first terminal of the second current limiting module is connected to the power supply voltage VCC. The second terminal of the second current limiting module is connected to the first terminal of the second clamping module and the control terminal of the second transistor M2 to generate a second bias voltage VZN2. The second terminal of the second clamping module is connected to the output terminal OUT of the switching circuit.

[0051] like Figure 3 As shown, the second current limiting module includes a second resistor R2. The first end of the second resistor R2 is connected to the power supply voltage VCC, and the second end of the second resistor R2 is connected to the first end of the second clamping module and the second transistor M2.

[0052] In other embodiments, such as Figure 5 As shown, the second resistor R2 of the second current limiting module can be replaced by the third MOSFET N3. The control terminal of the third MOSFET N3 is connected to the first terminal of the third MOSFET N3, the first terminal of the second clamping module, and the control terminal of the second transistor M2. The second terminal of the third MOSFET N3 is connected to the power supply voltage VCC.

[0053] like Figure 3 As shown, the second clamping module includes a second Zener diode D2. The cathode of the second Zener diode D2 is connected to the second terminal of the second current limiting module and the control terminal of the second transistor M2. The anode of the second Zener diode D2 is connected to the output terminal OUT of the switching circuit.

[0054] In other embodiments, such as Figure 5As shown, the second Zener diode D2 of the second clamping module can be replaced by one or more fourth MOSFETs. The number of fourth MOSFETs can be increased or decreased as needed. The control terminal of the fourth MOSFET is connected to its second terminal, that is, the fourth MOSFET adopts the "diode connection". If only one fourth MOSFET is set, the control terminal of the fourth MOSFET is connected to its second terminal and then connected to the second terminal of the second current limiting module and the control terminal of the second transistor M2. The first terminal of the fourth MOSFET is connected to the output terminal OUT of the switching circuit. Figure 5 The diagram shows three fourth MOS transistors N41, N42, and N43 connected in series between the control terminal of the second transistor M2 and the output terminal OUT of the switching circuit.

[0055] like Figure 3 As shown, the switching circuit also includes a ground control unit 50, which is connected to the reference potential AVSS and the second node b. The ground control unit 50 is used to cut off the path between the reference potential AVSS and the second node b in the reverse connection state, and to connect the reference potential AVSS and the second node b in the normal state.

[0056] In one embodiment, the grounding control unit 50 includes a third transistor M3. The control terminal of the third transistor M3 is connected to the control logic module CTRL inside the chip. The first terminal of the third transistor M3 is connected to the reference potential AVSS, and the second terminal of the third transistor M3 is connected to the second node b. The control logic module CTRL is powered by the voltage at the first node a. The third transistor M3 is driven by the control signal generated by the control logic module CTRL to be turned off in the reverse connection state and turned on in the normal state. Figure 3 In this context, DD is the parasitic diode of the third transistor M3. The parasitic diode DD is used to prevent reverse connection, meaning that in the reverse connection state, there is no path between the second node b and the reference potential AVSS. In other embodiments, the ground control unit 50 may also have an additional separate diode, with the anode of the diode connected to the first terminal of the third transistor M3 and the cathode of the diode connected to the second terminal of the third transistor M3.

[0057] In this embodiment, power transistor M0, first transistor M1, first MOSFET N1, second MOSFET, second transistor M2, third MOSFET N3, fourth MOSFET, and third transistor M3 are NMOS transistors, and the switching transistor MK is a PMOS transistor. In other embodiments, power transistor M0, first transistor M1, first MOSFET N1, second MOSFET, second transistor M2, third MOSFET N3, fourth MOSFET, and third transistor M3 are PMOS transistors, and the switching transistor MK is an NMOS transistor. In one embodiment, first MOSFET N1 and third MOSFET N3 are depletion-type NMOS transistors.

[0058] The first terminal of power transistor M0, the first terminal of switching transistor MK, the first terminal of first transistor M1, the first terminal of first MOSFET N1, the first terminal of second MOSFET, the first terminal of second transistor M2, the first terminal of third MOSFET N3, the first terminal of fourth MOSFET, and the first terminal of third transistor M3 are the sources; the second terminal of power transistor M0, the second terminal of switching transistor MK, the second terminal of first transistor M1, the second terminal of first MOSFET N1, the second terminal of second MOSFET, the second terminal of second transistor M2, the second terminal of third MOSFET N3, the second terminal of fourth MOSFET, and the second terminal of third transistor M3 are the drains; the control terminal of power transistor M0, the control terminal of switching transistor MK, the control terminal of first transistor M1, the control terminal of first MOSFET N1, the control terminal of second MOSFET, the control terminal of second transistor M2, the control terminal of third MOSFET N3, the control terminal of fourth MOSFET, and the control terminal of third transistor M3 are the gates.

[0059] like Figure 3 As shown, the control terminal of the power transistor M0 is connected to the drive circuit DRV. The drive circuit DRV is used to generate a drive signal VG to control the power transistor M0 to turn on and off. The drive circuit DRV is powered by the control voltage VCP, which is the internal power supply of the chip. The control voltage VCP can be generated by the charge pump circuit. The drive circuit DRV is connected to the output terminal OUT to receive the feedback voltage at the output terminal OUT.

[0060] like Figure 3 As shown, the parasitic diode D0 is the parasitic diode between the reference potential AVSS and the first node a. The reference potential AVSS is the internal ground of the chip. When the power supply voltage VCC and the ground voltage GND are reversed (i.e., the first node a is connected to the ground voltage GND and the second node b is connected to the power supply voltage VCC), the drive circuit DRV and the control logic module CTRL will stop working.

[0061] In one embodiment, when the power supply voltage VCC and the ground voltage GND are reversed (i.e., the first node a is connected to the ground voltage GND and the second node b is connected to the power supply voltage VCC), the first bias voltage VZN1 is generated by the first Zener diode D1, which turns on the first transistor M1. Current flows from the first transistor M1 through the current-limiting resistor Rp and the parasitic diode DK of the switching transistor MK into the control terminal of the power transistor M0, thereby pulling up the voltage at the control terminal of the power transistor M0 and turning on the power transistor M0. The current on the load RL flows through the channel of the power transistor M0, reducing the power consumption on the power transistor M0 and thus protecting the power transistor M0. In addition, since the voltage at the output terminal OUT will also be raised, the second transistor M2 will be in the off state, which does not affect the current injection path at the control terminal of the power transistor M0.

[0062] When the power supply voltage VCC and ground voltage GND are positively connected (i.e., the first node a is connected to the power supply voltage VCC and the second node b is connected to the ground voltage GND), and power transistor M0 is turned on and the voltage at the output terminal OUT is positive, the third transistor M3 is turned on, the reference potential AVSS is equal to the ground voltage GND, the first transistor M1 is turned off, and the substrate of the first transistor M1 is connected to the reference potential AVSS, so no leakage current will be generated between the first and second terminals of the first transistor M1. The voltage at the output terminal OUT will rise to approximately equal to the power supply voltage VCC, but less than the drive signal VG. At this time, even if the second transistor M2 is turned on, because the voltage at the output terminal OUT is less than the drive signal VG, it can still ensure that the parasitic diode DK of the switching transistor MK is not conducting, and it will not affect the turn-on state of power transistor M0. The second transistor M2 serves to limit the voltage difference between the first and second terminals of the switching transistor MK, and also prevents leakage current at the control terminal of the switching transistor MK.

[0063] When the power supply voltage VCC and the ground voltage GND are positively connected (i.e., the first node a is connected to the power supply voltage VCC and the second node b is connected to the ground voltage GND), and the power transistor M0 is turned on and the voltage at the output terminal OUT is negative (the negative voltage situation is generally caused by the load being inductive), the second transistor M2 will turn on and pull down the voltage at the second terminal of the switching transistor MK. At the same time, the first transistor M1 will also turn on. However, the parasitic diode DK of the switching transistor MK will not conduct, so there is no current path connected to the control terminal of the power transistor M0, and it will not affect the turn-on state of the power transistor M0.

[0064] When the power supply voltage VCC and the ground voltage GND are positively connected (i.e., the first node a is connected to the power supply voltage VCC and the second node b is connected to the ground voltage GND), the power transistor M0 is off and the voltage at the output terminal OUT is the ground voltage GND. When the second transistor M2 is turned on, it will pull down the voltage at the second terminal of the switching transistor MK. The first transistor M1 is in the off state, the parasitic diode DK of the switching transistor MK will not be turned on, and it will not affect the off state of the power transistor M0.

[0065] When the power supply voltage VCC and the ground voltage GND are positively connected (i.e., the first node a is connected to the power supply voltage VCC and the second node b is connected to the ground voltage GND), when the power transistor M0 is off and the voltage at the output terminal OUT is negative (negative voltage is generally caused by an inductive load), the second transistor M2 will turn on and pull down the voltage at the second terminal of the switching transistor MK. At the same time, the first transistor M1 will also turn on. However, the parasitic diode DK of the switching transistor MK will not conduct, so there is no current path to pull down the control terminal of the power transistor M0, and the power transistor M0 will not be turned on erroneously.

[0066] The present invention also discloses a chip including the above-described switching circuit.

[0067] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0068] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A switching circuit connected to a load, characterized in that, include: Power transistor, control unit, and first bias unit; The first end of the power transistor is connected to the first end of the load to form the output terminal of the switching circuit. The second end of the power transistor is connected to the first node, and the second end of the load is connected to the second node. Under normal conditions, the first node is connected to the power supply voltage and the second node is connected to the ground voltage. Under reverse connection conditions, the first node is connected to the ground voltage and the second node is connected to the power supply voltage. The first bias unit is connected to a reference potential and a second node. The first bias unit is used to generate a first bias voltage based on the voltage of the second node and the reference potential when in reverse connection state. The control unit is connected to the first bias unit, the control terminal of the power transistor and the second node. The control unit is turned on based on the control of the first bias voltage to control the connection between the control terminal of the power transistor and the second node.

2. The switching circuit according to claim 1, characterized in that, The control unit includes a first transistor, a first terminal of which is connected to the control terminal of a power transistor, a second terminal of which is connected to a second node, and the control terminal of which is connected to a first bias unit to receive a first bias voltage. or The control unit includes a first transistor and a current-limiting resistor. A first terminal of the first transistor is connected to a first terminal of the current-limiting resistor. A second terminal of the current-limiting resistor is connected to a control terminal of the power transistor. A second terminal of the first transistor is connected to a second node. The control terminal of the first transistor is connected to a first bias unit to receive a first bias voltage. The first transistor is an NMOS transistor.

3. The switching circuit according to claim 1, characterized in that, The first bias unit is used to generate a predetermined value as the first bias voltage when it detects that the difference between the voltage value at the second node and the reference potential exceeds a preset value.

4. The switching circuit according to claim 3, characterized in that, The first bias unit includes a first current limiting module and a first clamping module. The first end of the first current limiting module is connected to the second node, and the second end of the first current limiting module is connected to the first end of the first clamping module and the control unit to generate a first bias voltage. The second end of the first clamping module is connected to the reference potential. The first current limiting module includes a first resistor or a first MOSFET. The first terminal of the first resistor is connected to a second node, and the second terminal of the first resistor is connected to the first terminal of a first clamping module and a control unit. The control terminal of the first MOSFET is connected to the first terminal of the first MOSFET, the first terminal of the first clamping module, and the control unit. The second terminal of the first MOSFET is connected to the second node; and / or The first clamping module includes a first Zener diode or a second MOSFET. The cathode of the first Zener diode is connected to the second terminal of the first current limiting module and the control unit. The anode of the first Zener diode is connected to the reference potential. The control terminal of the second MOSFET is connected to the second terminal of the second MOSFET, the second terminal of the first current limiting module, and the control unit. The first terminal of the second MOSFET is connected to the reference potential.

5. The switching circuit according to claim 1, characterized in that, The switching circuit further includes a switching module and a switching control unit. The first terminal of the switching module is connected to the control terminal of the power transistor, and the second terminal of the switching module is connected to the control unit. When the switching module is in reverse connection state, it connects the control terminal of the power transistor and the control unit. When in normal state, it disconnects the connection between the control terminal of the power transistor and the control unit. The switching control unit is connected to the second terminal of the switching module, the output terminal of the switching circuit, and the power supply voltage. The switching control unit is used to adjust the voltage of the second terminal of the switching module to turn off the switching module when in normal state.

6. The switching circuit according to claim 5, characterized in that, The switch control unit includes a second transistor and a second bias unit. The second bias unit is connected to the output terminal of the switch circuit. When the voltage value detected at the second node is less than a preset value, the second bias unit generates a predetermined value as a second bias voltage. The first terminal of the second transistor is connected to the output terminal of the switch circuit, and the second terminal of the second transistor is connected to the second terminal of the switch module. The control terminal of the second transistor is connected to the second bias unit to receive the second bias voltage. The second transistor is turned on based on the control of the second bias voltage to control the connection between the second terminal of the switch module and the output terminal of the switch circuit.

7. The switching circuit according to claim 6, characterized in that, The second bias unit includes a second current limiting module and a second clamping module. The first terminal of the second current limiting module is connected to the power supply voltage. The second terminal of the second current limiting module is connected to the first terminal of the second clamping module and the control terminal of the second transistor to generate a second bias voltage. The second terminal of the second clamping module is connected to the output terminal of the switching circuit. The second current limiting module includes a second resistor or a third MOSFET. The first terminal of the second resistor is connected to the power supply voltage, and the second terminal of the second resistor is connected to the first terminal of the second clamping module and the second transistor. The control terminal of the third MOSFET is connected to the first terminal of the third MOSFET, the first terminal of the second clamping module, and the control terminal of the second transistor. The second terminal of the third MOSFET is connected to the power supply voltage; and / or The second clamping module includes a second Zener diode or a fourth MOS transistor. The cathode of the second Zener diode is connected to the second terminal of the second current limiting module and the control terminal of the second transistor. The anode of the second Zener diode is connected to the output terminal of the switching circuit. The control terminal of the fourth MOS transistor is connected to the second terminal of the fourth MOS transistor, the second terminal of the second current limiting module, and the control terminal of the second transistor. The first terminal of the fourth MOS transistor is connected to the output terminal of the switching circuit.

8. The switching circuit according to claim 2, characterized in that, The substrate of the first transistor is connected to a reference potential.

9. The switching circuit according to claim 1, characterized in that, The switching circuit also includes a grounding control unit, which is connected to the reference potential and the second node. The grounding control unit is used to cut off the path between the reference potential and the second node in the reverse connection state, and to connect the reference potential and the second node in the normal state.

10. A chip, characterized in that, Includes the switching circuit as described in any one of claims 1 to 9.

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