Fast automatic frequency calibration circuit and calibration method for phase-locked loop

Abstract

The invention discloses a fast automatic frequency calibration circuit and calibration method for a phase-locked loop. A counter counts reference frequency signals and signals obtained after frequency division of a voltage-controlled oscillator. The decoder comparator calculates a frequency difference value and outputs a selection signal to the count value configurator. And the count value configurator is used for configuring the next count value according to the selection signal output by the decoder comparator, outputting the count value, connecting the count value to the first counter, and controlling the counting time of the counters. The control word generator generates an optimal control word. The counting result is processed and judged after each time of counting is finished, when the difference value between the counting result and the target counting value meets the condition, the next counting value is set to be half of the initial counting value, and the counting time is shortened to be half of the original counting time; and if not, keeping the initial count value. By dynamically configuring the counting value and adjusting the length of the counting time window, the calibration time is flexibly shortened, and the performance of the automatic frequency calibration circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency wireless transceiver integrated circuit technology, and in particular to a fast automatic frequency calibration circuit and calibration method for phase-locked loops. Background Technology

[0002] In a phase-locked loop (PLL) system, automatic frequency calibration switches different sub-bands based on the VCO output frequency by adjusting the control word. Existing automatic frequency calibration structures are of two types: closed-loop and open-loop. Closed-loop automatic frequency calibration is integrated into the PLL loop, with the VCO output signal fed into it for continuous tuning. Open-loop automatic frequency calibration switches sub-bands during coarse tuning and disconnects from the PLL during fine tuning, allowing the PLL loop to handle the adjustment. With the same number of control words, open-loop automatic frequency calibration has a shorter lock-in time than closed-loop automatic frequency calibration.

[0003] Open-loop automatic frequency control systems can be further subdivided into two categories based on the frequency detection technology employed: time-comparison automatic frequency calibration and frequency-comparison automatic frequency calibration. Time-comparison automatic frequency calibration compares signals by converting the period length of the signal into a voltage signal; while frequency-comparison automatic frequency calibration directly compares the frequencies of two signals by counting the number of trigger edges over a period of time. In the design of automatic frequency calibration systems, frequency-comparison automatic frequency calibration is a commonly used architecture.

[0004] In the field of frequency search, common algorithms include linear search and binary search. Linear search involves starting the control word from the smallest or largest sub-band and searching sequentially until the other sub-band is reached. Binary search follows binary rules, using the middle position of a sub-band as the starting point and then expanding the search towards both ends. Compared to linear search, binary search significantly reduces the number of searches and drastically shortens the search time. To shorten the locking time and improve locking accuracy, a hybrid search method combines linear search, binary search, and the minimum error register method. While this method is more flexible and shortens calibration time compared to a single method, the calibration time is still relatively long when the control word has a large number of bits. Summary of the Invention

[0005] This invention provides a fast automatic frequency calibration circuit and calibration method for phase-locked loops. By dynamically configuring the count value and adjusting the length of the counting time window, the calibration time is flexibly shortened, and the performance of the automatic frequency calibration circuit is improved.

[0006] A first aspect of the present invention provides a fast automatic frequency calibration circuit for a phase-locked loop, comprising: a counter value configurator, a first counter, a second counter, a decoder comparator, and a control word generator; The input of the counter value configurator is connected to the output of the decoder comparator, and the output is connected to the input of the first counter. It is used to configure the next count value according to the selection signal output by the decoder comparator, output the configured count value to the first counter, and control the counting time of the first counter. The first counter has its input terminal connected to a reference frequency signal and its output terminal connected to the input terminal of the second counter. It is used to count the input reference frequency signal, stop counting when the count reaches a configured count value, and output a stop signal to the second counter. The input terminal of the second counter is connected to the frequency-divided signal of the voltage-controlled oscillator, and the output terminal is connected to the input terminal of the decoder comparator. It is used to count the frequency-divided signal of the voltage-controlled oscillator and output the count value within the counting time window to the decoder comparator according to the received stop signal. The output of the decoder comparator is connected to the input of the control word generator. The decoder comparator includes a decoder and a comparator. The decoder is used to generate a count value of the target sub-band frequency, and the comparator is used to compare the difference between the count value of the target sub-band frequency and the count value output by the second counter with the difference comparison condition, and output the comparison result to the control word generator. The output of the control word generator is connected to the input of the voltage-controlled oscillator. Based on the comparison results, it uses a hybrid algorithm including binary search, linear search, and minimum error search to find and switch the optimal control word, and outputs the optimal control word to calibrate the frequency of the voltage-controlled oscillator.

[0007] Optionally, in one embodiment of the present invention, the count value M configured in the counter value configurator during the first counting phase after power-on reset is... cnt Let M be the minimum count value that satisfies the frequency resolution. Starting from the second counting phase, the count value configurator switches the next count value based on the selection signal selcnt output by the decoder comparator. When the selection signal selcnt is high, the count value M is... cnt Configured as M / 2, when the select signal selcnt is pulled low, the count value M cnt Configured as M.

[0008] Optionally, in one embodiment of the present invention, the decoder comparator processes and judges the counting result after each counting. When the difference between the count value of the target sub-band frequency and the count value output by the second counter meets the difference comparison condition, the next count value is set to half of the initial count value, and the counting time is shortened to half of the original. When the difference comparison condition is not met, the initial count value is maintained and the next counting is performed.

[0009] Optionally, in one embodiment of the present invention, the difference comparison condition is: ; Where, ΔN c The value of the target sub-band frequency after the c-th count is the difference between the count value output by the second counter and the current count value, where k is the number of control word bits and M is the number of bits. cnt f is the count value. res For the frequency resolution of the voltage-controlled oscillator, f ref Where N is the frequency of the reference frequency signal, and N is the division ratio of the frequency divider.

[0010] Optionally, in one embodiment of the present invention, the first counter is based on the count value M output by the count value configurator. cnt The rising and falling edges of the reference frequency signal are counted, and a stop signal is output after the counting is completed.

[0011] Optionally, in one embodiment of the present invention, the second counter counts the rising and falling edges of the signal after frequency division by the voltage-controlled oscillator, and stops counting and outputs the count value N after receiving the stop signal from the first counter. div .

[0012] Optionally, in one embodiment of the present invention, the second counter includes a binary code to Gray code module, two D flip-flops, and a Gray code to binary code module for transmitting multi-bit data across clocks between asynchronous clocks.

[0013] A second aspect of the present invention provides a fast automatic frequency calibration method for a phase-locked loop (PLL), utilizing the fast automatic frequency calibration circuit for a PLL described in the above embodiments. The method includes the following steps: Upon power-on reset, the midpoint of the control word corresponding to all sub-bands is set as the initial control word, and the count value M is... cnt Configured as M, it simultaneously counts the reference frequency signal and the signal after frequency division by the voltage-controlled oscillator (VCO). The count of the reference frequency signal stops when it reaches M, thus obtaining the period count value N of the current VCO-divided signal. div ; By using the period count value N div The count value N of the target sub-band frequency tarCompare the values ​​and calculate the difference ΔN = |N div -N tar | and switch directions, incrementing the counter by one; By judging the magnitude of the difference ΔN, if the difference comparison condition is not met, then the control word at this time is the optimal control word, and the circuit operation ends; otherwise, the control word is switched using either the linear method or the binary method, and the difference ΔN at this time is registered as ΔN_pre. By determining whether the difference ΔNc meets the difference comparison condition, the next segment count value is configured as M or M / 2. A new round of counting begins. The difference ΔN is counted and calculated. It is then determined whether ΔN_pre is less than or equal to ΔN. If so, the previous control word is the optimal control word. The optimal control word is then output, and the circuit operation ends.

[0014] The fast automatic frequency calibration circuit and calibration method for phase-locked loops in this invention process and judge the counting result after each counting, output a selection signal to configure the counting value of the next segment, and dynamically adjust the length of the counting time window, thereby flexibly shortening the calibration time.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a fast automatic frequency calibration circuit for a phase-locked loop according to an embodiment of the present invention; Figure 2 (a) is a waveform diagram of a circuit based on a hybrid algorithm provided in the background art of an embodiment of the present invention; Figure 2 (b) is a waveform diagram of the automatic frequency calibration circuit of an embodiment of the present invention; Figure 3 This is a simulation waveform diagram of the automatic frequency calibration circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the basic process of the automatic frequency calibration method according to an embodiment of the present invention. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0018] Figure 1 This is a schematic diagram of a fast automatic frequency calibration circuit for a phase-locked loop according to an embodiment of the present invention.

[0019] like Figure 1 As shown, the fast automatic frequency calibration circuit for a phase-locked loop includes: a counter value configurator, a first counter, a second counter, a decoder comparator, and a control word generator; The input of the counter value configurator is connected to the output of the decoder comparator, and the output is connected to the input of the first counter. It is used to adjust the next count value M according to the selection signal selcnt output by the decoder comparator. cnt Configure and output the configured count value M. cnt To the first counter, control the counting time of the first counter; The input terminal of the first counter is connected to a reference frequency signal, and the output terminal is connected to the input terminal of the second counter. This counter counts the input reference frequency signal until it reaches a configured count value M. cnt The counting stops when the time is up, and a stop signal is output to the second counter; The second counter's input is connected to the frequency-divided signal from the voltage-controlled oscillator (VCO), and its output is connected to the input of the decoder's comparator. It is used to count the frequency-divided signal from the VCO and output the count value N within the counting time window based on the received stop signal. div To decoder comparator; The output of the decoder comparator is connected to the input of the control word generator. The decoder comparator includes a decoder and a comparator. The decoder is used to generate the count value N of the target subband frequency. tar The comparator is used to convert the count value N of the target subband frequency. tar The count value N output by the second counter div The difference is compared with the difference comparison condition, and the comparison result is output to the control word generator; The output of the control word generator is connected to the input of the voltage-controlled oscillator. Based on the comparison results, it uses a hybrid algorithm including binary search, linear search, and minimum error search to find and switch the optimal control word, and outputs the optimal control word to calibrate the frequency of the voltage-controlled oscillator.

[0020] In the counter value configurator, the counter value M is configured during the first counting phase after power-on reset. cnt Let M be the minimum count value that satisfies the frequency resolution. Starting from the second counting phase, the count value configurator switches the next count value based on the selection signal selcnt output by the decoder comparator. When the selection signal selcnt goes high (the signal changes from low to high), the count value M is... cntConfigured as M / 2, when the select signal selcnt is pulled low (the signal changes from high to low), the count value M is... cnt Configured as M.

[0021] The decoder comparator processes and judges the counting result after each count. When the difference between the count value of the target sub-band frequency and the count value output by the second counter meets the difference comparison condition, the next count value is set to half of the initial count value, and the counting time is shortened to half of the original. If the difference comparison condition is not met, the initial count value is maintained and the next count is performed.

[0022] The condition for difference comparison is: ; Where, ΔN c The value of the target sub-band frequency after the c-th count is the difference between the count value output by the second counter and the current count value, where k is the number of control word bits and M is the number of bits. cnt f is the count value. res For the frequency resolution of the voltage-controlled oscillator, f ref Where N is the frequency of the reference frequency signal, and N is the division ratio of the frequency divider.

[0023] The first counter is based on the count value M output by the count value configurator. cnt The rising and falling edges of the reference frequency signal are counted, and a stop signal is output after the counting is completed.

[0024] The second counter counts the rising and falling edges of the signal after frequency division by the voltage-controlled oscillator. Upon receiving the stop signal from the first counter, it stops counting and outputs the count value N. div .

[0025] The second counter includes a binary-to-Gray code conversion module, two D flip-flops, and a Gray code-to-binary code conversion module, which transmits multi-bit data across clock cycles between asynchronous clocks.

[0026] In open-loop automatic frequency calibration circuits, a hybrid search algorithm can shorten calibration time and improve calibration accuracy. However, for circuits with control words containing a large number of bits, such as... Figure 2 As shown in (a), the calibration time is still very long, with the time spent on bisection switching accounting for a large proportion. Since the frequency difference between subbands using bisection switching is large, this invention switches the count value through a count value configurator. When the frequency difference is large, that is, when bisection switching is used, a smaller count value is set, which shortens the calibration time compared to the original structure while ensuring calibration accuracy.

[0027] The initial count value M of the counter is the minimum count value that satisfies the frequency resolution. Under this count value condition, the frequencies corresponding to each sub-band can be distinguished within the counting time window. When the counter count value is shortened to M / 2, although the technical time window is shortened to half of its original size, when the target sub-band differs significantly from the current sub-band, the corresponding frequencies can still be distinguished within half of the counting time window. In this case, shortening the counting time window can reduce the calibration time. Furthermore, in digital semi-custom circuits, the division by 2 operation can be performed using a shift register, which is easy to implement in hardware.

[0028] The target subband is decoded to obtain its corresponding count value N. tar The sub-band frequency count value corresponding to the current control word is N. div In order to distinguish between subbands after the binary search switching, the corresponding count values ​​between subbands must be greater than or equal to 1.

[0029] For the counter, the length of each counting time window is The count value corresponding to the sub-band is: ; The frequency difference between the current subband and the subband after switching in the binary method is: ; The target subband count value is: ; Current count value difference: ; If the difference in count values ​​between the target sub-band and the sub-band after the bisection switching must be greater than or equal to 1, then the following criterion can be obtained: ; When the condition is met, the selcnt signal goes high, controlling the count value for the next counting stage to be M / 2; when the condition is not met, the selcnt signal remains low, controlling the count value for the next counting stage to be M. This method can shorten the calibration time of the automatic frequency calibration circuit.

[0030] This method can shorten the calibration time of automatic frequency calibration circuits, such as... Figure 2 Figures (a) and (b) show the waveforms of the circuit using the hybrid search algorithm and the circuit proposed in this invention, respectively, under a 6-bit frequency control word. A comparison reveals that this invention controls the count value M via the selcnt signal. cnt Switching between M and M / 2, the lengths of the three counting time windows are determined by... Reduce to This can significantly shorten the overall calibration time.

[0031] In some embodiments, with a 4-bit control word, the circuit was simulated according to the present invention, and the waveform diagram is shown below. Figure 3 As shown, the frequency control word switches from 8 to 1. After the first count, if the count difference meets the criterion, the `selcnt` signal goes high, and the count value for the next stage is configured as M / 2. The control word switches from 8 to 4 using a binary search method. In the second stage, the counting time window is shortened to half its original value. After counting, if the count difference does not meet the criterion, the `selcnt` signal goes low, and the count value for the next stage is configured as M. The counting time window increases, and the control word switches from 4 to 2 using a binary search method. In the final stage, if the count difference does not meet the criterion, the `selcnt` signal goes low, the count value for the next stage is configured as M, the counting time window remains unchanged, and the control word switches from 2 to 1 using a linear method.

[0032] The rapid automatic frequency calibration method proposed in this invention is illustrated in the flowchart below. Figure 4 As shown, the automatic frequency calibration circuit starts working from power-on reset, with the initial control word set to the sub-band center control word and the count value M. cnt Configured as M, it simultaneously counts the reference frequency signal and the divider output frequency signal. The reference frequency signal counts to stop at M, and a stop signal is output to connect to the counter that counts the divider output signal, thus obtaining the current period count value N of the divider output signal. div ; By analyzing N div and N tar Perform decoding comparison and calculate the difference ΔN = |N div -N tar | and switch directions, incrementing the counter by one; By judging the value of ΔN, if it is less than the criterion, the control word at this time is considered to be the optimal control word, and the circuit operation ends; otherwise, the control word is switched by either the linear method or the binary method, and the current ΔN is registered as ΔN_pre. By determining whether ΔNc meets the condition, the next segment count value is configured as M or M / 2. A new round of counting begins. ΔN is counted and calculated. It is determined whether ΔN_pre is less than or equal to ΔN. If so, the previous control word is the optimal control word. The optimal control word is output, and the circuit operation ends.

[0033] According to embodiments of the present invention, a fast automatic frequency calibration circuit and calibration method for a phase-locked loop (PLL) are proposed. A counter counts both a reference frequency signal and a frequency-divided signal from a voltage-controlled oscillator (VCO). A decoder comparator calculates the frequency difference and outputs a selection signal to a count value configurator. The count value configurator configures the next count value based on the selection signal output by the decoder comparator, and the output count value is connected to a first counter to control the counter's counting time. A control word generator generates the optimal control word using a hybrid algorithm combining binary search, linear search, and minimum error search. This design processes and judges the counting result after each count. When the difference between the count result and the target count value meets a condition, the next count value is set to half of the initial count value, and the counting time is shortened to half. Under this condition, even with a reduced counting time, the frequency difference can still be distinguished; otherwise, the initial count value is maintained. By dynamically configuring the count value and adjusting the counting time window length, the calibration time is flexibly shortened, improving the performance of the automatic frequency calibration circuit.

[0034] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A fast automatic frequency calibration circuit for a phase-locked loop, characterized in that, include: Count value configurator, first counter, second counter, decoder comparator, control word generator; The input of the counter value configurator is connected to the output of the decoder comparator, and the output is connected to the input of the first counter. It is used to configure the next count value according to the selection signal output by the decoder comparator, output the configured count value to the first counter, and control the counting time of the first counter. The first counter has its input terminal connected to a reference frequency signal and its output terminal connected to the input terminal of the second counter. It is used to count the input reference frequency signal, stop counting when the count reaches a configured count value, and output a stop signal to the second counter. The input terminal of the second counter is connected to the frequency-divided signal of the voltage-controlled oscillator, and the output terminal is connected to the input terminal of the decoder comparator. It is used to count the frequency-divided signal of the voltage-controlled oscillator and output the count value within the counting time window to the decoder comparator according to the received stop signal. The output of the decoder comparator is connected to the input of the control word generator. The decoder comparator includes a decoder and a comparator. The decoder is used to generate a count value of the target sub-band frequency, and the comparator is used to compare the difference between the count value of the target sub-band frequency and the count value output by the second counter with the difference comparison condition, and output the comparison result to the control word generator. The output of the control word generator is connected to the input of the voltage-controlled oscillator. Based on the comparison results, it uses a hybrid algorithm including binary search, linear search, and minimum error search to find and switch the optimal control word, and outputs the optimal control word to calibrate the frequency of the voltage-controlled oscillator.

2. The fast automatic frequency calibration circuit for a phase-locked loop according to claim 1, characterized in that, In the counter value configurator, the counter value M is configured during the first counting phase after power-on reset. cnt Let M be the minimum count value that satisfies the frequency resolution. Starting from the second counting phase, the count value configurator switches the next count value based on the selection signal selcnt output by the decoder comparator. When the selection signal selcnt is high, the count value M is... cnt Configured as M / 2, when the select signal selcnt is pulled low, the count value M cnt Configured as M.

3. The fast automatic frequency calibration circuit for a phase-locked loop according to claim 1, characterized in that, The decoder comparator processes and judges the counting result after each count. When the difference between the count value of the target sub-band frequency and the count value output by the second counter meets the difference comparison condition, the next count value is set to half of the initial count value, and the counting time is shortened to half of the original. If the difference comparison condition is not met, the initial count value is maintained and the next count is performed.

4. The fast automatic frequency calibration circuit for a phase-locked loop according to claim 3, characterized in that, The condition for difference comparison is: ； Where, ΔN c The value of the target sub-band frequency after the c-th count is the difference between the count value output by the second counter and the current count value, where k is the number of control word bits and M is the number of bits. cnt f is the count value. res For the frequency resolution of the voltage-controlled oscillator, f ref Where N is the frequency of the reference frequency signal, and N is the division ratio of the frequency divider.

5. The fast automatic frequency calibration circuit for a phase-locked loop according to claim 1, characterized in that, The first counter is based on the count value M output by the count value configurator. cnt The rising and falling edges of the reference frequency signal are counted, and a stop signal is output after the counting is completed.

6. The fast automatic frequency calibration circuit for a phase-locked loop according to claim 1, characterized in that, The second counter counts the rising and falling edges of the signal after frequency division by the voltage-controlled oscillator. Upon receiving the stop signal from the first counter, it stops counting and outputs the count value N. div .

7. The fast automatic frequency calibration circuit for a phase-locked loop according to claim 1, characterized in that, The second counter includes a binary code to Gray code module, two D flip-flops, and a Gray code to binary code module, which transmits multi-bit data across clock cycles between asynchronous clocks.

8. A rapid automatic frequency calibration method for phase-locked loops, characterized in that, Using the fast automatic frequency calibration circuit for a phase-locked loop according to any one of claims 1-7, the method includes the following steps: Upon power-on reset, the midpoint of the control word corresponding to all sub-bands is set as the initial control word, and the count value M is... cnt Configured as M, it simultaneously counts the reference frequency signal and the signal after frequency division by the voltage-controlled oscillator (VCO). The count of the reference frequency signal stops when it reaches M, thus obtaining the period count value N of the current VCO-divided signal. div ; By using the period count value N div The count value N of the target sub-band frequency tar Compare the values ​​and calculate the difference ΔN = |N div -N tar | and switch directions, incrementing the counter by one; By judging the magnitude of the difference ΔN, if the difference comparison condition is not met, then the control word at this time is the optimal control word, and the circuit operation ends; otherwise, the control word is switched using either the linear method or the binary method, and the difference ΔN at this time is registered as ΔN_pre. By determining whether the difference ΔNc meets the difference comparison condition, the next segment count value is configured as M or M / 2. A new round of counting begins. The difference ΔN is counted and calculated. It is then determined whether ΔN_pre is less than or equal to ΔN. If so, the previous control word is the optimal control word. The optimal control word is then output, and the circuit operation ends.

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