All-digital calibration method for segmented resistor string DAC and related product

Abstract

The invention discloses an all-digital calibration method of a segmented resistor string DAC and a related product. The method comprises the steps of obtaining a first input code of a target digital-to-analog converter, determining a second input code according to the first input code based on a preset lookup table, and generating a target analog signal output by the target digital-to-analog converter according to the second input code. Wherein the resolution of the first input code is a first resolution; the preset lookup table represents a mapping relationship between all original input codes and target input codes in the target digital-to-analog converter, the resolution of the original input codes is a first resolution, the resolution of the target input codes is a second resolution, and the second input codes are the target input codes corresponding to the first input codes in the preset lookup table. Therefore, the calculation complexity is reduced, and the accuracy of the output analog signal is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a fully digital calibration method for a segmented resistor string DAC and related products. Background Technology

[0002] Digital-to-analog converters (DACs) convert digital signals into analog signals and are widely used in many fields such as wireless communication, testing equipment, and image and voice processing. With the development of advanced processes and design technologies, as well as the expansion of application scenarios such as the Internet of Things and artificial intelligence, the market demand for high-precision, low-power DACs is becoming increasingly prominent.

[0003] Resistor-series DACs possess inherent monotonicity, a key characteristic that prevents unexpected output inversions, making them widely used in applications with high stability requirements. However, as resolution increases, the number of components explodes, leading to an exponential increase in chip area and manufacturing costs, which becomes unsustainable at high resolutions.

[0004] In related technologies, to alleviate the problem of explosive growth in the number of components, a segmented structure is used to divide the DAC into a coarse adjustment (MSB) resistor string and one or more fine adjustment (LSB) resistor strings.

[0005] However, without inter-segment buffers, severe nonlinear errors arise due to load effects and non-ideal switching resistors, significantly impacting the DAC's integral nonlinearity (INL) and differential nonlinearity (DNL). Meanwhile, while inserting buffers can isolate the segments, it introduces additional power consumption, increases design complexity, and introduces new linearity errors due to op-amp non-ideals (such as offset and finite gain). Summary of the Invention

[0006] To address the aforementioned issues, this application provides a fully digital calibration method and related products for a segmented resistor-string DAC, aiming to reduce DAC errors and improve the accuracy of the analog signal output by the DAC.

[0007] The embodiments of this application disclose the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a fully digital calibration method for a segmented resistor string DAC, which may include:

[0009] Obtain the first input code of the target digital-to-analog converter; wherein, the resolution of the first input code is the first resolution;

[0010] Based on a preset lookup table, a second input code is determined according to a first input code; wherein, the preset lookup table represents the mapping relationship between all original input codes and target input codes in the target digital-to-analog converter, the resolution of the original input code is the first resolution, the resolution of the target input code is the second resolution, and the second input code is the target input code corresponding to the first input code in the preset lookup table;

[0011] The target analog signal output by the target digital-to-analog converter is generated based on the second input code.

[0012] Optionally, it also includes obtaining a preset lookup table through the following methods:

[0013] Obtain all raw input codes of the target digital-to-analog converter; wherein the resolution of the raw input codes is the first resolution;

[0014] Determine the analog output voltage for each original input code;

[0015] The corresponding digital output voltage is determined based on each analog output voltage; wherein, the resolution of the digital output voltage is the second resolution, the digital output voltage represents the product between the digital value and the minimum analog output voltage corresponding to the least significant bit value, the resolution of the least significant bit value is the second resolution, and the second resolution is less than the first resolution;

[0016] The linear model parameters and linear model for each segment are determined based on each digital output voltage; each segment is obtained based on the original code.

[0017] A pre-defined lookup table is constructed based on all target input codes, the linear model parameters corresponding to each segment, and the linear model; the resolution of the target input codes is the second resolution.

[0018] Optionally, a pre-defined lookup table is constructed based on all target input codes, the linear model parameters corresponding to each segment, and the linear model, including:

[0019] Retrieve all target input codes;

[0020] Determine the target segment set corresponding to each target input code; wherein the target segment set includes at least one target segment;

[0021] Based on the linear model parameters and linear model corresponding to each segment, the local codewords and prediction errors of each target segment in each target segment set are determined;

[0022] Based on the target segment with the smallest prediction error in each target segment set, determine the global original codeword corresponding to each target input code;

[0023] A pre-defined lookup table is constructed based on each target input code and the corresponding global original codeword.

[0024] Optionally, generating the target analog signal output by the target digital-to-analog converter based on the second input code includes:

[0025] The corresponding target global codeword is determined based on the second input code;

[0026] The target analog signal is determined based on the target global codeword.

[0027] Secondly, embodiments of this application provide a digital-to-analog converter (DAC), which includes a controller, a digital-to-analog conversion circuit, a first circuit, a second circuit, and a third circuit; the first circuit includes a series circuit... The first circuit consists of a unit resistor, where M is the number of the most significant bits of the input digital code received by the first circuit; the second circuit includes a series resistor. The unit resistor, I is the number of the middle valid bits of the input digital code received by the second circuit; the third circuit includes an interpolation operational amplifier circuit and a buffer circuit; the digital-to-analog converter circuit is connected to the first circuit, the second circuit and the third circuit respectively, and the interpolation operational amplifier circuit and the buffer circuit are connected in series.

[0028] The controller is configured to output a target analog signal; wherein the target analog signal is obtained based on a second input code, the second input code is determined based on a preset lookup and a first input code, the first input code being acquired; wherein the resolution of the first input code is a first resolution; the preset lookup table represents the mapping relationship between all original input codes and target input codes in the digital-to-analog converter, the resolution of the original input codes is the first resolution, the resolution of the target input codes is the second resolution, and the second input code is the target input code corresponding to the first input code in the preset lookup table.

[0029] Optionally, the interpolation operational amplifier circuit includes a current mirror, a high-gain operational amplifier, and a 2 L 2 difference pairs and 2 L -1 switch, where L is the number of least significant bits.

[0030] Thirdly, embodiments of this application provide a fully digital calibration device for a segmented resistor string DAC, the device comprising:

[0031] An acquisition unit is used to acquire the first input code of the target digital-to-analog converter; wherein the resolution of the first input code is a first resolution;

[0032] The calibration unit is used to determine the second input code based on the first input code according to the preset lookup table; wherein, the preset lookup table represents the mapping relationship between all original input codes and target input codes in the target digital-to-analog converter, the resolution of the original input code is the first resolution, the resolution of the target input code is the second resolution, and the second input code is the target input code corresponding to the first input code in the preset lookup table;

[0033] The output unit is used to generate the target analog signal output by the target digital-to-analog converter based on the second input code.

[0034] Fourthly, embodiments of this application provide a control device, including a processor and a memory, wherein the memory is used to store programs, instructions or code, and the processor is used to execute the programs, instructions or code in the memory to complete the all-digital calibration method for a segmented resistor string DAC as described in the first aspect.

[0035] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which is loaded by a processor to execute the all-digital calibration method for a segmented resistor string DAC as described in the first aspect.

[0036] In a sixth aspect, embodiments of this application provide a computer program product, including a computer program or instructions that, when executed, implement the all-digital calibration method for a segmented resistor string DAC as described in the first aspect.

[0037] Beneficial effects:

[0038] The fully digital calibration method for a segmented resistor string DAC provided in this application involves obtaining a first input code of the target digital-to-analog converter (DAC), determining a second input code based on the first input code using a preset lookup table, and generating a target analog signal output by the DAC based on the second input code. The first input code has a first resolution; the preset lookup table represents the mapping relationship between all original input codes and the target input code in the DAC, with the original input codes having a first resolution and the target input codes having a second resolution; the second input code is the target input code in the preset lookup table that corresponds to the first input code.

[0039] Thus, since the pre-set lookup table stores the mapping relationship between all original input codes (first resolution) and target input codes (second resolution) in advance, the second input code can be quickly indexed through the first input code without the need to calculate complex mathematical models (such as polynomial fitting, piecewise linearization, etc.) in real time, which significantly reduces computational complexity. At the same time, since the pre-set lookup table is obtained during the calibration stage, the original codewords can be pre-mapped to the optimal codewords, which can compensate for nonlinear errors and improve the accuracy of the output analog signal. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram of a three-segment digital-to-analog converter provided in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of the structure of a digital-to-analog converter provided in an embodiment of this application;

[0043] Figure 3 A schematic diagram of the structure of an MSB resistor string and an ISB resistor string provided in an embodiment of this application;

[0044] Figure 4 A schematic diagram of an original transfer function curve provided for an embodiment of this application;

[0045] Figure 5 This is a schematic diagram of the structure of an interpolation DAC provided in an embodiment of this application;

[0046] Figure 6 A flowchart illustrating a fully digital calibration method for a segmented resistor string DAC provided in this application embodiment;

[0047] Figure 7 This is a schematic diagram of a fully digital calibration process for a segmented resistor string DAC provided in an embodiment of this application;

[0048] Figure 8 A schematic diagram of an integral nonlinearity (INL) curve provided for related technologies;

[0049] Figure 9a A schematic diagram of the integral nonlinearity (INL) curve of a DAC provided in an embodiment of this application;

[0050] Figure 9b A schematic diagram of the differential nonlinearity (DNL) curve of a DAC provided in an embodiment of this application;

[0051] Figure 10 A schematic diagram of the structure of a fully digital calibration device for a segmented resistor string DAC provided in this application embodiment;

[0052] Figure 11 This is a schematic diagram of the structure of a control device provided in an embodiment of this application. Detailed Implementation

[0053] As described earlier, digital-to-analog converters (DACs) are used to convert digital signals into analog signals and are widely used in wireless communication, testing equipment, image and voice processing, and other fields. With the development of advanced processes and design technologies, and the expansion of application scenarios such as the Internet of Things and artificial intelligence, the demand for high-precision, low-power DACs is becoming increasingly significant. Resistor-string DACs are widely used in applications with high stability requirements due to their inherent monotonicity—a key characteristic that ensures the DAC output does not exhibit unexpected inversions. However, for high-resolution DACs, a fundamental challenge of the traditional resistor-string structure is that it requires… The use of precision resistors and a corresponding number of switches leads to an exponential increase in chip area and manufacturing cost with resolution, making it unacceptable at high resolutions.

[0054] To mitigate the problem of the explosive growth in component count, the industry often adopts a segmented structure, dividing the DAC into a coarse-tuning (MSB) resistor string and one or more fine-tuning (LSB) resistor strings. However, without inter-segment buffers, this structure can lead to severe nonlinearity errors due to load effects and non-ideal switching resistors, significantly compromising the DAC's integral nonlinearity (INL) and differential nonlinearity (DNL). While inserting buffers can isolate the segments, this introduces additional power consumption, design complexity, and new linearity errors caused by op-amp non-ideals (such as offset and finite gain).

[0055] Based on this, embodiments of this application provide a fully digital calibration method and related products for a segmented resistor-string DAC. The method includes obtaining a first input code of the target digital-to-analog converter (DAC), determining a second input code based on the first input code using a preset lookup table, and generating a target analog signal output by the DAC based on the second input code. The first input code has a first resolution; the preset lookup table represents the mapping relationship between all original input codes and the target input code in the DAC, with the original input codes having a first resolution and the target input codes having a second resolution. The second input code is the target input code in the preset lookup table that corresponds to the first input code.

[0056] Thus, since the pre-set lookup table stores the mapping relationship between all original input codes (first resolution) and target input codes (second resolution) in advance, the second input code can be quickly indexed through the first input code without the need to calculate complex mathematical models (such as polynomial fitting, piecewise linearization, etc.) in real time, which significantly reduces computational complexity. At the same time, since the pre-set lookup table is obtained during the calibration stage, the original codewords can be pre-mapped to the optimal codewords, which can compensate for nonlinear errors and improve the accuracy of the output analog signal.

[0057] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0058] The collection and processing of relevant data (including but not limited to experimental data, test data, simulation data, user data, etc.) involved in this application shall strictly comply with the requirements of national laws and regulations when applied in the following embodiments, obtain the informed consent or separate consent of the subject obtaining the data information, and carry out data use and processing within the scope of laws and regulations and the authorization of the subject.

[0059] Because related technologies may have issues such as process mismatch or switching non-idealities, in one possible implementation, this application provides a three-stage segmented digital-to-analog converter (DAC), combined with... Figure 1 As shown, from the most significant bit to the least significant bit, the segments are: Most Significant Bit (MSB), Middle Significant Bit (ISB), and Least Significant Bit (LSB).

[0060] The MSB segment receives the highest bit of the input digital code and is used to generate the coarse adjustment voltage range.

[0061] The ISB segment receives the middle bit of the input digital code, and its reference voltage comes from the two nodes output by the MSB segment, which is used to perform the first subdivision of the voltage range of the MSB segment.

[0062] The LSB segment receives the least significant bit of the input digital code, and its reference voltage comes from the two nodes output by the ISB segment. It is used to further subdivide the voltage range of the ISB segment and output an analog voltage.

[0063] In this embodiment, the original resolution (i.e., the first resolution) N of the DAC is the sum of the three, namely N = M + I + L (e.g., M=6, I=6, L=7, N=19), and the target calibration resolution (i.e., the second resolution) is K (e.g., K=16), and K < N.

[0064] Furthermore, to implement the aforementioned three-stage digital-to-analog converter structure, see [link to documentation]. Figure 2 The figure shows a digital-to-analog converter (DAC) provided in an embodiment of this application. The DAC 20 includes a controller 21, a digital-to-analog conversion circuit 22, a first circuit 23, a second circuit 24, and a third circuit 25.

[0065] The first circuit 23 includes series connections. Each unit resistor, M is the number of bits of the most significant bit of the input digital code received by the first circuit 23.

[0066] In one possible implementation, combining Figure 3 As shown, the MSB resistor string (i.e., the first circuit) consists of... It is composed of individual resistors connected in series to form MSB intervals.

[0067] Among them, the unit resistor can be implemented using ordinary polysilicon resistors and other process devices with small area but certain inherent mismatches. Its matching accuracy is significantly lower than the final target resolution (e.g., only matching at the 5-6 bit level).

[0068] The MSB resistor string receives the highest M bits (MSB code) of the N-bit input digital code. In this embodiment, the MSB code is defined in the range [V(DM), V(DM+2)], and the width of the range is the voltage drop of two unit resistors.

[0069] It should be understood that for MSB code DM, the switches corresponding to node DM and node DM+2 will be closed simultaneously, outputting voltages respectively. and Specifically, for MSB code DM+1, the switches corresponding to nodes DM+1 and DM+3 will be closed simultaneously. Since the voltage across the MSB resistor string is monotonically increasing, V(DM+2) must be greater than V(DM+1). In the complete transfer function of the DAC, the ISB and LSB segments are interpolated within the interval provided by the MSB. When the MSB code increases from DM to DM+1, the DAC's transfer function undergoes a negative transition. This is combined with... Figure 4 As shown, the entire transfer function is divided into 64 identical (2MSB) blocks. However, in reality (i.e., when resistors mismatch), the slopes and intercepts of these 64 transfer functions are not the same. The node voltages of two adjacent resistors are chosen as the outputs. This operation is key to introducing negative transitions and inter-segment overlap (i.e., redundancy).

[0070] The second circuit 24 includes series connections. Each unit resistor, I represents the number of valid bits in the middle of the input digital code received by the second circuit 24.

[0071] The ISB resistor string (i.e., the second circuit) consists of It is composed of individual resistors connected in series to form In each ISB interval, the ISB resistor string receives the middle I bit (ISB code) of an N-bit input digital code. It selects the voltage at the upper and lower nodes of a specific resistor unit within the ISB resistor string as the output. For the ISB code DI, the switches corresponding to nodes DI and DI+1 are simultaneously closed, outputting voltages respectively. and .

[0072] The third circuit 25 includes an interpolation operational amplifier circuit 251 and a buffer circuit 252; the digital-to-analog converter circuit 22 is connected to the first circuit 23, the second circuit 24 and the third circuit 25 respectively, and the interpolation operational amplifier circuit 251 and the buffer circuit 252 are connected in series.

[0073] In one possible implementation, the interpolation operational amplifier circuit 151 includes a current mirror, a high-gain operational amplifier, and each difference pair and -1 switch, where L is the number of least significant bits.

[0074] It should be understood that the LSB resistor string provided by the relevant technology is a passive network. When its output is directly connected to the load, voltage errors and settling time will be slowed down due to the load effect and switching resistance. Therefore, an output buffer is needed to drive the subsequent load. In this way, the third circuit can use this buffer as a third-stage digital-to-analog converter to realize the digital-to-analog conversion function of the lower 7 bits, which can buffer the signal while ensuring accurate voltage interpolation output.

[0075] like Figure 5 As shown, the digital-to-analog converter responds to the low-order LSB (i.e., the third circuit), and the interpolation operational amplifier circuit 151 includes a current mirror, a high-gain operational amplifier, and each difference pair and -1 switch, where L is the number of least significant bits. When When =0, the gate of all transistors is Therefore = When all the gates of the transistors are (In extreme cases, this situation does not exist because one of the transistors' gates is always connected.) Then the output will be... = When it is between the two extreme cases (i.e., the low-order bits of the input are...), Then there is A pipe connected to The remaining 2LSB- All for The output will be Vout= + ( - ) / (2LSB), that is, the final output voltage is in and Interpolation is performed between them.

[0076] Based on the digital-to-analog converter provided in the above embodiments, combined with Figure 6 As shown in the embodiment of this application, a fully digital calibration method for a segmented resistor string DAC is provided, which may include:

[0077] S61: Obtain the first input code of the target digital-to-analog converter.

[0078] The target digital-to-analog converter is the digital-to-analog converter described in any of the above embodiments, which has the function of converting digital signals into analog signals.

[0079] The first input code is the digital signal to be converted received by the target digital-to-analog converter, wherein the resolution of the first input code is the first resolution.

[0080] Resolution refers to the number of bits in the input code, which determines the number of discrete voltage levels that the DAC can represent. For example, 19-bit resolution means that the input code range is 0 to... There are a total of 524,288 states.

[0081] S62: Based on a preset lookup table, determine the second input code according to the first input code.

[0082] A pre-defined lookup table represents the mapping relationship between all raw input codes and target input codes in the target digital-to-analog converter (DAC). The pre-defined lookup table stores the mapping relationship between all possible raw input codes (first resolution) and target input codes (second resolution). For example, it maps a 19-bit raw code to a 16-bit target DAC input code. Here, the resolution of the raw input code is the first resolution, the resolution of the target input code is the second resolution, and the second input code is the target input code in the pre-defined lookup table that corresponds to the first input code.

[0083] As an example, the mapping process can be represented as using the first input code as an index to directly read the corresponding target input code (the second input code) from a lookup table. For example, the original code 0x12345 (19 bits) may be mapped to the target code 0x5678 (16 bits).

[0084] It should be understood that, in the embodiments of this application, the mapping relationship of the preset mapping table can be optimized through calibration to compensate for the nonlinear errors of the DAC (such as INL / DNL) and improve output accuracy. Simultaneously, it supports dynamic updating of the lookup table (such as recalibration) to adapt to changes in DAC characteristics (such as temperature drift), improving flexibility.

[0085] In one possible implementation, the preset lookup table can also be obtained in the following way:

[0086] A1: Obtain all raw input codes of the target digital-to-analog converter.

[0087] The resolution of the original input code is the first resolution.

[0088] The original input code refers to the high-resolution digital signal (e.g., 19-bit) to be mapped, which needs to be converted into a low-resolution (e.g., 16-bit) target input code.

[0089] The first resolution refers to the number of bits in the original input code, which determines the accuracy range of the input signal.

[0090] It should be understood that generating all codewords through a full traversal avoids omitting regions with obvious DAC nonlinear characteristics (such as codewords close to full scale or zero), ensuring completeness; at the same time, it provides basic data for the subsequent creation of a preset lookup table.

[0091] A2: Determine the analog output voltage of each original input code.

[0092] Analog output voltage refers to the actual voltage value obtained after converting digital code. The analog output voltage may deviate from the ideal value due to non-ideal hardware characteristics (e.g., 1LSB of a 16-bit DAC should correspond, but there may be deviations in reality).

[0093] A3: Determine the corresponding digital output voltage based on each analog output voltage.

[0094] The resolution of the digital output voltage is the second resolution. The digital output voltage represents the product between the digital value and the minimum analog output voltage corresponding to the least significant bit value. The resolution of the least significant bit value is the second resolution, which is less than the first resolution.

[0095] Digital output voltage refers to the digital value at the second resolution, represented as binary code, with the smallest step (LSB) corresponding to it. That is, the unit of digital output voltage is LSB (least significant bit value).

[0096] The second resolution represents the target resolution to be converted (e.g., 16 bits), which determines the number of discrete levels of the digital output voltage.

[0097] It should be understood that the resolution mismatch problem is solved by mapping the high-resolution (i.e., first resolution) raw input code to the low-resolution (i.e., second resolution) target input code.

[0098] A4: Determine the corresponding segmental linear model parameters and linear model based on each digital output voltage.

[0099] Each segment is derived from the original code.

[0100] Segmentation refers to the operation of dividing the original input code range into multiple segments (such as each codeword being a segment). The number of segments can be adjusted according to the nonlinear characteristics of the DAC.

[0101] A linear model means that the output of a nonlinear DAC is approximated as a combination of multiple linear segments, where the output is linearly related to the input within each segment. The linear model parameters represent the slope and intercept of the linear model, describing the linear relationship of the i-th segment.

[0102] It should be understood that piecewise fitting captures the local nonlinearity of the DAC more accurately than a global linear model.

[0103] A5: Construct a preset lookup table based on all target input codes, the linear model parameters corresponding to each segment, and the linear model.

[0104] The resolution of the target input code is the second resolution.

[0105] In one possible implementation, step A5 may include:

[0106] B1: Get all target input codes.

[0107] B2: Determine the set of target segments corresponding to each target input code.

[0108] The target segment set includes at least one target segment.

[0109] It should be understood that, based on the value of the target input code, it is determined which original code segment it belongs to (e.g., target code 0x1234 belongs to the original code segment [0x0000, 0x03FF]). This may involve multiple segments (e.g., target code near a segment boundary may belong to the transition area between two segments), but the closest segment can also be chosen.

[0110] B3: Based on the linear model parameters and linear model corresponding to each segment, determine the local codewords and prediction errors of each target segment in each target segment set.

[0111] Local codewords represent approximate values ​​of the target input code relative to the original input code.

[0112] Prediction error refers to the deviation between the analog output voltage corresponding to a local codeword and the ideal voltage.

[0113] B4: Determine the global original codeword corresponding to each target input code based on the target segment with the smallest prediction error in each target segment set.

[0114] It should be understood that the segment with the smallest prediction error is selected from the target segment set, and its corresponding local codeword is used as the candidate original codeword. It is important to note that the target input codeword must be mapped to the globally optimal original codeword, not a locally optimal one.

[0115] B5: Construct a preset lookup table based on each target input code and the corresponding global original codeword.

[0116] It should be understood that error optimization ensures that each target code maps to the original codeword closest to the ideal value, compensating for DAC nonlinearity. Simultaneously, it avoids mapping jumps at segment boundaries, guaranteeing the continuity of the output signal. Furthermore, since the preset lookup table can be directly stored in the FPGA's Block RAM or the ASIC's ROM, real-time calculation is unnecessary.

[0117] S63: Generate the target analog signal output by the target digital-to-analog converter based on the second input code.

[0118] The target analog signal refers to the continuous voltage or current signal output by the target digital-to-analog converter.

[0119] In one possible implementation, step S63 may include: determining the corresponding target global codeword based on the second input code; and determining the target analog signal based on the target global codeword.

[0120] It should be understood that, in the embodiments of this application, since the preset lookup table stores the mapping relationship between all original input codes (first resolution) and target input codes (second resolution) in advance, the second input code can be quickly indexed through the first input code without the need to calculate complex mathematical models (such as polynomial fitting, piecewise linearization, etc.) in real time, which significantly reduces the computational complexity. At the same time, since the preset lookup table is obtained in the calibration stage, the original codewords can be mapped to the optimal codewords in advance, which can compensate for nonlinear errors and improve the accuracy of the output analog signal.

[0121] Based on the digital calibration method provided in the above embodiments, combined with Figure 7 As shown in the illustration, this application also provides a fully digital calibration process for a segmented resistor string DAC. It should be noted that the digital calibration process in this embodiment is a post-processing technique that does not interfere with the analog domain operation of the DAC. Instead, it achieves linearization by reconstructing the mapping relationship between the digital input code and the analog output voltage. Specifically, this application uses the process of calibrating a 19-bit raw input code into a 16-bit linear input code as an example for illustration.

[0122] Step 1: Preprocess and normalize the data.

[0123] It should be understood that the embodiments of this application require the analog measurement data to be converted to the target digital scale to lay the foundation for subsequent pure digital calculations. For the expected 16-bit linear DAC (i.e., the target input code), the expression for its target LSB can be calculated:

[0124] ;

[0125] in, Indicates the target LSB, This represents the analog output voltage corresponding to the most significant bit. This represents the analog output voltage corresponding to the least significant bit (which is zero).

[0126] It should be understood that, in the embodiments of this application, the analog output voltage of the 19-bit DAC (i.e., the original input code) before calibration is digitized. Specifically, each measured analog output voltage can be digitized. ( The formula for converting the input code to a digital value in units of LSBs of the target K-bit DAC (i.e., the target input code of the second resolution) can be:

[0127] ;

[0128] in, This represents the converted numeric value. Indicates the analog output voltage. This represents the minimum value of the LSB.

[0129] Step 2: Perform piecewise modeling of the entire transfer function, decomposing the global nonlinearity into a locally linear problem.

[0130] As an example, the original code can be divided into S= based on the physical structure of the DAC. There are segments, and each segment i contains L= Each code character.

[0131] For each segment i (from 0 to S-1), first extract the Vdigital data corresponding to that segment, and then use the local codeword x (from 0 to L-1) within the segment as the independent variable. A first-order linear regression is performed on the dependent variable to obtain the linear model parameters for this segment. Here, the slope M(i) reflects the gain error of this segment, and the intercept C(i) reflects the offset error of this segment. The linear model for this segment can be expressed as:

[0132] (x)=M(i)*x+C(i);

[0133] In this way, a complex continuous nonlinear curve is simplified into a set of simple discrete linear line segments, which greatly reduces the complexity of subsequent calculations.

[0134] Step 3: Construct a preset lookup table.

[0135] As an example, a global optimal codeword search can be performed to find the best implementation path for each target input code; then, the target input codes can be traversed, and for each input code of the target K-bit DAC... (From 0 to -1), first determine the candidate segment set.

[0136] It should be understood that, due to the target input code Nominal segmentation T= / ( / S), due to redundancy, therefore The target voltage may be generated by segment T or its neighboring segments (T-1, T+1), and these three segment indices are added to the candidate set.

[0137] Furthermore, for each segment j in the candidate set, local codewords are estimated using models M(j) and C(j) for segment j. M(j) and C(j) are obtained from the following two formulas:

[0138] ;

[0139] ;

[0140] Among them, by using the M(j) and C(j) parameters of segment j, the solution can be obtained to generate The ideal local codeword is used to obtain the prediction error Error(j). Finally, the prediction errors of all candidate segments j are compared, and the candidate segment j with the smallest error is selected to obtain the global original codeword as input. The final mapping is then stored in a predefined lookup table (LUT).

[0141] After the above process is completed, a file of size [size missing] is generated. The system uses a preset lookup table to receive a K-bit raw input code when the DAC is working normally. The N-bit target input code mapped by the LUT is obtained by querying the LUT. Then it is used to drive the physical switch of the DAC.

[0142] It should be understood that this process is equivalent to a digital predistorter, which compensates for the nonlinearity of the DAC analog domain through nonlinear address mapping, so that the final macroscopic input-output characteristics present a high-precision straight line.

[0143] It should be understood that, in the embodiments of this application, the digital-to-analog converter (DAC) adopts a unique switching decoding strategy. By simultaneously closing two non-adjacent node switches in the most significant bit segment, it actively introduces negative transitions and inter-segment voltage overlap in the transfer function, thereby constructing rich codeword redundancy.

[0144] Meanwhile, the fully digital calibration method for segmented resistor string DAC provided in this application embodiment can acquire the original transfer curve of the DAC, accurately establish the error model of each segment through segmented linear fitting; then, for each output code of the target resolution, a global optimal search is performed in multiple candidate segments, and the original code with the smallest error is stored in the lookup table.

[0145] In this way, the input code is not used directly during normal operation; instead, the DAC switches are driven by querying this lookup table. This method successfully overcomes the fundamental limitation of physical component matching accuracy on DAC performance while maintaining inherent monotonicity and eliminating the need for any analog calibration circuitry, paving a new path for realizing low-cost, small-area, high-precision data conversion systems.

[0146] Based on the segmented resistor string DAC fully digital calibration method provided in the above embodiments, in order to verify the effectiveness of the embodiments of this application, the poly resistor in SMIC350nm was used for simulation verification, and its matching accuracy was found to be approximately 5-bit level (σ=0.33%).

[0147] As an example, a simulation is performed in MATLAB for a 19-bit raw DAC with MSB=6, ISB=6, and LSB=7. Since the MSB and ISB use resistor series, mismatch must be considered, while the LSB uses an interpolation op-amp, which can be considered to be completely linear.

[0148] Figure 8 The results shown are the INL simulation results of the uncalibrated 16-bit segmented DAC after 200 Monte Carlo simulations. It can be seen that the nonlinearity reaches 20 LSB at this point.

[0149] Figure 9a and Figure 9b The figures show the INL and DNL simulation results of the 16-bit DAC after 200 Monte Carlo simulations using the calibration algorithm of this invention. It can be seen that the INL is basically reduced to within 1 LSB, and the DNL remains within 0.7 LSB. The simulation results comprehensively and strongly confirm the effectiveness of the technical solution of this invention. The described all-digital calibration method can stably transform a highly non-ideal 19-bit DAC based on low-precision components into a high-precision converter with 16-bit linearity.

[0150] Based on the fully digital calibration method for the segmented resistor string DAC provided in the above embodiments, see [link to documentation]. Figure 10 This application also provides a schematic diagram of the structure of a fully digital calibration device for a segmented resistor string DAC.

[0151] Combination Figure 10 As shown, the digital calibration device 100 provided in this embodiment includes:

[0152] The acquisition unit 101 is used to acquire the first input code of the target digital-to-analog converter; wherein the resolution of the first input code is a first resolution;

[0153] The calibration unit 102 is used to determine the second input code based on the first input code according to the preset lookup table; wherein, the preset lookup table represents the mapping relationship between all original input codes and target input codes in the target digital-to-analog converter, the resolution of the original input code is the first resolution, the resolution of the target input code is the second resolution, and the second input code is the target input code corresponding to the first input code in the preset lookup table;

[0154] The output unit 103 is used to generate the target analog signal output by the target digital-to-analog converter according to the second input code.

[0155] In one possible implementation, a building block is also included for obtaining a predefined lookup table in the following manner:

[0156] Obtain all raw input codes of the target digital-to-analog converter; wherein the resolution of the raw input codes is the first resolution;

[0157] Determine the analog output voltage for each original input code;

[0158] The corresponding digital output voltage is determined based on each analog output voltage; wherein, the resolution of the digital output voltage is the second resolution, the digital output voltage represents the product between the digital value and the minimum analog output voltage corresponding to the least significant bit value, the resolution of the least significant bit value is the second resolution, and the second resolution is less than the first resolution;

[0159] The linear model parameters and linear model for each segment are determined based on each digital output voltage; each segment is obtained based on the original code.

[0160] A pre-defined lookup table is constructed based on all target input codes, the linear model parameters corresponding to each segment, and the linear model; the resolution of the target input codes is the second resolution.

[0161] In one possible implementation, the building unit is used for:

[0162] Retrieve all target input codes;

[0163] Determine the target segment set corresponding to each target input code; wherein the target segment set includes at least one target segment;

[0164] Based on the linear model parameters and linear model corresponding to each segment, the local codewords and prediction errors of each target segment in each target segment set are determined;

[0165] Based on the target segment with the smallest prediction error in each target segment set, determine the global original codeword corresponding to each target input code;

[0166] A pre-defined lookup table is constructed based on each target input code and the corresponding global original codeword.

[0167] In one possible implementation, the output unit 103 is used for:

[0168] The corresponding target global codeword is determined based on the second input code;

[0169] The target analog signal is determined based on the target global codeword.

[0170] It should be noted that the digital calibration device provided in this application embodiment has the same beneficial effects as the all-digital calibration method for segmented resistor string DAC provided in the above embodiments, and therefore will not be described again.

[0171] In one possible implementation, see Figure 11 The figure is a schematic diagram of a control device provided in an embodiment of this application.

[0172] The control device may include a memory 1111 and a processor 1112. For example... Figure 11 As shown, the memory can be random access memory (RAM), flash memory, read-only memory (ROM), EPROM, non-volatile read-only memory (Electronic Programmable ROM), registers, hard disks, removable disks, etc.

[0173] The memory 1111 can store computer instructions. When the computer instructions stored in the memory 1111 are executed by the processor 1112, the processor 1112 can be used to execute a fully digital calibration method for a segmented resistor string DAC. The memory 1111 can also store data.

[0174] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape) or a semiconductor medium (e.g., solid-state disk (SSD)).

[0175] This application also provides a readable storage medium for storing the methods provided in the above embodiments. Examples include random access memory (RAM), flash memory, read-only memory (ROM), EPROM, non-volatile read-only memory (EPROM), registers, hard disks, removable disks, or any other form of storage medium in the art.

[0176] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0177] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the product embodiments disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the description of the product embodiments.

[0178] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fully digital calibration method for a segmented resistor-string DAC, characterized in that, The method includes: Obtain the first input code of the target digital-to-analog converter; wherein the resolution of the first input code is a first resolution; Based on a preset lookup table, a second input code is determined according to the first input code; wherein, the preset lookup table represents the mapping relationship between all original input codes and target input codes in the target digital-to-analog converter, the resolution of the original input code is a first resolution, the resolution of the target input code is a second resolution, and the second input code is the target input code corresponding to the first input code in the preset lookup table; The target analog signal output by the target digital-to-analog converter is generated based on the second input code.

2. The all-digital calibration method for a segmented resistor-string DAC according to claim 1, characterized in that, This also includes obtaining the preset lookup table through the following methods: Obtain all raw input codes of the target digital-to-analog converter; wherein the resolution of the raw input codes is a first resolution; Determine the analog output voltage of each of the original input codes; The corresponding digital output voltage is determined based on each of the analog output voltages; wherein, the resolution of the digital output voltage is a second resolution, the digital output voltage represents the product between the digital value and the minimum analog output voltage corresponding to the least significant bit value, the resolution of the least significant bit value is the second resolution, and the second resolution is less than the first resolution; The linear model parameters and linear model for each segment are determined based on each of the digital output voltages; wherein each segment is obtained based on the original code. The preset lookup table is constructed based on all target input codes, the linear model parameters corresponding to each segment, and the linear model; the resolution of the target input codes is the second resolution.

3. The all-digital calibration method for a segmented resistor-string DAC according to claim 2, characterized in that, The step of constructing the preset lookup table based on all target input codes, the linear model parameters corresponding to each segment, and the linear model includes: Retrieve all target input codes; Determine the target segment set corresponding to each of the target input codes; wherein the target segment set includes at least one target segment; Based on the linear model parameters and linear model corresponding to each segment, the local codewords and prediction errors of each target segment in each target segment set are determined; Based on the target segment with the smallest prediction error in each target segment set, determine the global original codeword corresponding to each target input code; The preset lookup table is constructed based on each target input code and the corresponding global primitive codeword.

4. The all-digital calibration method for a segmented resistor-string DAC according to claim 3, characterized in that, The step of generating the target analog signal output by the target digital-to-analog converter according to the second input code includes: The corresponding target global codeword is determined based on the second input code; The target analog signal is determined based on the target global codeword.

5. A digital-to-analog converter, characterized in that, The digital-to-analog converter includes a controller, a digital-to-analog conversion circuit, a first circuit, a second circuit, and a third circuit; the first circuit includes a series connection. A unit resistor, wherein M is the number of the most significant bits of the input digital code received by the first circuit; the second circuit includes series resistors. A unit resistor, wherein I is the number of the middle valid bits of the input digital code received by the second circuit; the third circuit includes an interpolation operational amplifier circuit and a buffer circuit; the digital-to-analog converter circuit is connected to the first circuit, the second circuit and the third circuit respectively, and the interpolation operational amplifier circuit is connected in series with the buffer circuit; The controller is configured to output a target analog signal; wherein the target analog signal is obtained based on a second input code, the second input code is determined based on a preset lookup and a first input code, the first input code being acquired; wherein the resolution of the first input code is a first resolution; the preset lookup table represents the mapping relationship between all original input codes and target input codes in the digital-to-analog converter, the resolution of the original input codes is the first resolution, the resolution of the target input codes is the second resolution, and the second input code is the target input code corresponding to the first input code in the preset lookup table.

6. The digital-to-analog converter according to claim 5, characterized in that, The interpolation operational amplifier circuit includes a current mirror, a high-gain operational amplifier, and 2 L 2 difference pairs and 2 L -1 switch, where L is the number of bits of the least significant bit.

7. A fully digital calibration device for a segmented resistor-string DAC, characterized in that, The device includes: An acquisition unit is used to acquire the first input code of the target digital-to-analog converter; wherein the resolution of the first input code is a first resolution; A calibration unit is used to determine a second input code based on a preset lookup table and the first input code; wherein the preset lookup table represents the mapping relationship between all original input codes and target input codes in the target digital-to-analog converter, the resolution of the original input code is a first resolution, the resolution of the target input code is a second resolution, and the second input code is the target input code corresponding to the first input code in the preset lookup table; The output unit is used to generate the target analog signal output by the target digital-to-analog converter based on the second input code.

8. A control device, characterized in that, It includes a processor and a memory, the memory being used to store programs, instructions, or code, and the processor being used to execute the programs, instructions, or code in the memory to complete the all-digital calibration method for a segmented resistor string DAC as described in any one of claims 1-4.

9. A computer-readable storage medium, characterized in that, The system contains a computer program that is loaded by a processor to execute the digital calibration method as described in any one of claims 1-4.

10. A computer program product, characterized in that, Includes a computer program or instructions that, when executed, implement the all-digital calibration method for a segmented resistor string DAC as described in any one of claims 1-4.

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