LDPC (Low Density Parity Check) decoding method, device, equipment, storage medium and program product

Abstract

Provided are an LDPC decoding method, apparatus, device, storage medium and program product, the LDPC decoding method comprising: determining a first scaling factor according to a first SINR of a communication link transmission symbol, the first scaling factor being used for processing a first log-likelihood ratio LLR, the first LLR being a floating point LLR; performing fixed-point quantization processing on the first LLR according to the first scaling factor to obtain a second LLR; inputting the second LLR into a decoder, and decoding the second LLR by using an LDPC decoding algorithm according to a first sequence to obtain a decoded bit message output by the decoder; the decoder comprises multiple layers of decoding structures arranged in sequence; the first sequence is an inverse sequence of the arrangement sequence of the multiple layers of decoding structures. According to the invention, through a layered LDPC decoding algorithm combining fixed-point quantization and inverted processing, the decoding performance is improved, and the complexity of the LDPC decoding algorithm is reduced.

Description

Technical Field

[0001] This invention relates to the field of wireless technology, and in particular to an LDPC decoding method, apparatus, device, storage medium, and program product. Background Technology

[0002] Low-density parity check (LDPC) is a highly efficient error correction coding technique widely used in modern communication systems. It achieves efficient error detection and correction through a sparse parity check matrix, operating close to the Shannon limit. Fifth-generation mobile communication technology (5G) networks employ LDPC encoding and decoding technology in their data transmission channels (including the Physical Uplink Shared Channel (PUSCH) and Physical Downlink Shared Channel (PDSCH)) to achieve efficient error correction, flexible rate adjustment, and fast processing capabilities, aiming to meet the stringent requirements of high performance and low latency in 5G networks.

[0003] In 5G small cells, to prevent timeouts in the receiving task, the latency requirements for LDPC decoding tasks in PUSCH are extremely stringent. In existing technologies, 5G receivers typically employ LDPC decoding algorithms based on Belief Propagation (BP). This algorithm requires extensive node information updates during multiple iterations, significantly increasing the overall latency of the decoding task. To control this latency, receivers often limit the maximum number of iterations of the LDPC decoding algorithm, which to some extent affects decoding performance and fails to reduce decoding complexity. Summary of the Invention

[0004] This invention provides an LDPC decoding method, apparatus, device, storage medium, and program product to solve the problem of high decoding complexity in existing LDPC decoding algorithms.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] In a first aspect, embodiments of the present invention provide an LDPC decoding method, comprising:

[0007] Based on the first signal-to-interference-plus-noise ratio (SINR), a first scaling factor is determined. The first scaling factor is used to process the first log-likelihood ratio (LLR). The first LLR is a floating-point LLR, and the first SINR is the SINR of the transmission symbol in the communication link.

[0008] The first LLR is subjected to fixed-point quantization based on the first scaling factor to obtain the second LLR;

[0009] The second LLR is input into the decoder, and the second LLR is decoded using the low-density parity-check code (LDPC) decoding algorithm in the first order to obtain the decoded bit message output by the decoder.

[0010] The decoder includes a multi-layer decoding structure arranged in sequence, each layer of the decoding structure including a check node and at least one bit node connected to the check node;

[0011] The first order is the reverse of the arrangement order of the multi-layer decoding structure.

[0012] Optionally, before determining the first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR), the method further includes:

[0013] The first LLR is obtained based on the first distance variable, the first received symbol, and the first SINR;

[0014] Wherein, the first distance variable is a distance variable related to the modulation method of the transmission symbols of the communication link;

[0015] The first received symbol is a received symbol related to the modulation method of the transmission symbol of the communication link.

[0016] Optionally, determining the first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR) includes:

[0017] Based on the second SINR of different modulation and coding methods, the first equivalent SINR is obtained, and the second SINR is the SINR of the simulated link transmission symbol;

[0018] By adjusting the first equivalent SINR using different second scaling factors, a third SINR corresponding to different second scaling factors can be obtained;

[0019] Obtain the CRC check result corresponding to each of the third SINRs;

[0020] Obtain the fourth SINR in the third SINR corresponding to the correct CRC check result, and obtain the third scaling factor in the second scaling factor corresponding to the correct CRC check result;

[0021] Based on different modulation and coding schemes, the fourth SINR and the third scaling factor, a first correspondence is generated, which is used to indicate the correspondence between modulation and coding schemes, equivalent SINR and scaling factor;

[0022] The first scaling factor is determined based on the first SINR, the modulation and coding scheme corresponding to the transmission symbol of the communication link, and the first correspondence.

[0023] Optionally, generating the first correspondence based on different modulation and coding schemes, the fourth SINR, and the third scaling factor includes:

[0024] Under different modulation and coding schemes, a first number of the fourth SINR and a first number of the third scaling factors are obtained, wherein the first number is determined based on the number of the second SINR and the number of TTIs of the preset detection reference signal SRS;

[0025] For each modulation and coding scheme, the first number of fourth SINRs and the first number of third scaling factors are clustered to obtain the fifth SINR and fourth scaling factor corresponding to each modulation and coding scheme;

[0026] The first correspondence is generated based on different modulation and coding schemes, the fifth SINR, and the fourth scaling factor.

[0027] Optionally, the step of performing fixed-point quantization on the first LLR according to the first scaling factor to obtain the second LLR includes:

[0028] The third LLR is obtained based on the first scaling factor and the first LLR;

[0029] The third LLR is shifted to obtain the fourth LLR;

[0030] Peak clipping is performed on the fourth LLR to obtain the second LLR.

[0031] Optionally, the step of inputting the second LLR into the decoder and decoding the second LLR using the Low-Density Parity-Check (LDPC) decoding algorithm in a first order to obtain the decoded bit message output by the decoder includes:

[0032] The second LLR is input into the decoder, and the first operation is performed in the decoder;

[0033] If the first condition is met, the execution of the first operation shall be stopped;

[0034] If the first condition is not met, update the first target LLR to the second target LLR obtained from the first check node, and return to the step of performing the first operation in the decoder;

[0035] Based on the second target LLR obtained from the last execution of the first operation, the decoded bit message output by the decoder is obtained;

[0036] The first operation includes:

[0037] The first verification node obtains the second target LLR based on the first matrix value and the first target LLR;

[0038] The first verification node sends the second target LLR to the first bit node;

[0039] The first bit node updates the LLR currently stored in the first bit node according to the second target LLR, so as to obtain the updated LLR stored in the first bit node;

[0040] Wherein, the first verification node is a verification node in any layer of the multi-layer decoding structure;

[0041] The first matrix value is the matrix value corresponding to the first check node and the first bit node in the check matrix, and the first bit node is the bit node in the decoding structure of the first check node.

[0042] When the first verification node is a verification node in the last layer of the decoding structure, the first target LLR is the second LLR. When the first verification node is a verification node in any layer of the decoding structure other than the last layer, the first target LLR is the second target LLR obtained by the second verification node. The second verification node is the verification node adjacent to the first verification node in the multi-layer decoding structure according to the first order.

[0043] When the first verification node is a first-level verification node, the updated LLR stored in the first bit node is the second target LLR obtained by performing the first operation;

[0044] The first condition includes at least one of the following:

[0045] The first operation has been performed a preset number of times;

[0046] The second target LLR obtained by performing the first operation passes the corresponding verification equation.

[0047] Optionally, the first bit node updates its currently stored LLR based on the second target LLR to obtain the updated LLR stored by the first bit node, including:

[0048] The first bit node updates its currently stored LLR based on the second target LLR, a preset first minimum sum, and a preset second minimum sum, to obtain the updated LLR stored in the first bit node.

[0049] Secondly, embodiments of the present invention also provide an LDPC decoding apparatus, comprising:

[0050] The first processing module is used to determine a first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR). The first scaling factor is used to process the first log-likelihood ratio (LLR), where the first LLR is a floating-point LLR and the first SINR is the SINR of the transmission symbol in the communication link.

[0051] The second processing module is used to perform fixed-point quantization on the first LLR according to the first scaling factor to obtain the second LLR.

[0052] The third processing module is used to input the second LLR into the decoder and decode the second LLR using the low-density parity-check code (LDPC) decoding algorithm in the first order to obtain the decoded bit message output by the decoder.

[0053] The decoder includes a multi-layer decoding structure arranged in sequence, each layer of the decoding structure including a check node and at least one bit node connected to the check node;

[0054] The first order is the reverse of the arrangement order of the multi-layer decoding structure.

[0055] Thirdly, embodiments of the present invention also provide an LDPC decoding device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the LDPC decoding method as described in any one of the first aspects.

[0056] Fourthly, embodiments of the present invention also provide a readable storage medium storing a program, which, when executed by a processor, implements the LDPC decoding method as described in any one of the first aspects.

[0057] Fifthly, embodiments of the present invention also provide a computer program product, including computer instructions, which, when executed by a processor, implement the LDPC decoding method as described in any one of the first aspects.

[0058] The beneficial effects of this invention are:

[0059] The LDPC decoding method provided by this invention determines a first scaling factor based on the first SINR of the transmitted symbol in the communication link, performs fixed-point quantization on the first LLR according to the first scaling factor to obtain a second LLR, realizes fixed-point quantization, inputs the second LLR into a decoder, and decodes the second LLR using the LDPC decoding algorithm according to a first order to obtain the decoded bit message output by the decoder. The decoder includes a multi-layer decoding structure arranged in order, each layer of the decoding structure includes a check node and at least one bit node connected to the check node. The first order is the reverse order of the arrangement of the multi-layer decoding structure, that is, a layered LDPC decoding algorithm that combines fixed-point quantization with reverse order processing. It does not require additional computing resources, thus efficiently completing the mapping from LLR to bit information, improving decoding performance, and reducing the complexity of the LDPC decoding algorithm. Attached Figure Description

[0060] Figure 1 A schematic diagram illustrating the verification matrix provided by this invention;

[0061] Figure 2 A schematic diagram illustrating the row density of BG1 provided by this invention;

[0062] Figure 3 This diagram illustrates the row weighting of BG2 provided by the present invention.

[0063] Figure 4 A flowchart illustrating the LDPC decoding method provided in this embodiment of the invention;

[0064] Figure 5 This is a schematic diagram illustrating the principle of the K-means algorithm provided in this embodiment of the invention.

[0065] Figure 6 A schematic diagram illustrating the first sequence provided in an embodiment of the present invention;

[0066] Figure 7 This is a flowchart illustrating the overall decoding process of the decoder provided in this embodiment of the invention.

[0067] Figure 8 This is a flowchart illustrating the overall process of the LDPC decoding method provided in this embodiment of the invention.

[0068] Figure 9 A schematic diagram illustrating the impact of different algorithms provided in the embodiments of the present invention on SNR and BLER;

[0069] Figure 10 This diagram illustrates the impact of different algorithms provided in this embodiment of the invention on the number of iteration terminations and the SNR.

[0070] Figure 11 This is a schematic diagram of the LDPC decoding device provided in an embodiment of the present invention;

[0071] Figure 12 This is a schematic diagram of the LDPC decoding device provided in an embodiment of the present invention. Detailed Implementation

[0072] To make the technical problems, technical solutions, and advantages of this application clearer, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments. In the following description, specific details such as particular configurations and components are provided merely to aid in a comprehensive understanding of the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Furthermore, for clarity and brevity, descriptions of known functions and structures have been omitted.

[0073] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0074] In the various embodiments of this application, it should be understood that the sequence number of each process described below does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0075] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, without limiting the number of objects; for example, the first object can be one or more. Furthermore, "or" in this application indicates at least one of the connected objects. For example, "A or B" covers three scenarios: Scenario 1: including A but not B; Scenario 2: including B but not A; Scenario 3: including both A and B. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0076] The term "instruction" in this application can be either a direct instruction (or explicit instruction) or an indirect instruction (or implicit instruction). A direct instruction can be understood as one in which the sender explicitly informs the receiver of specific information, the operation to be performed, or the requested result, etc.; an indirect instruction can be understood as one in which the receiver determines the corresponding information based on the instruction sent by the sender, or makes a judgment and determines the operation to be performed or the requested result, etc., based on the judgment result.

[0077] Before describing specific embodiments of the present invention, the following explanation is provided:

[0078] Decoding algorithm:

[0079] Common LDPC decoding algorithms include:

[0080] Belief Propagation (BP) algorithm: It utilizes the information transmission mechanism in graph theory and is suitable for decoding large-scale LDPC codes.

[0081] The Log-Likelihood Ratio (LLR) is an efficient method for decoding LDPC (Low-Density Parity-Check) codes, combining the concepts of the BP algorithm and the Log-Likelihood Ratio (LLR).

[0082] Complexity analysis:

[0083] The complexity of LDPC decoding is typically related to the number of iterations and the choice of bit width. The bit width of the LLR determines the precision of each LLR value; a higher bit width results in higher precision and a more accurate reflection of signal reliability, but it directly impacts storage and computational resource requirements. Higher bit widths require more storage space and higher computational power, especially when LLR values ​​need to be frequently updated and transmitted during iteration. When designing an LDPC decoding system, a trade-off must be struck between decoding performance and implementation complexity. Choosing an appropriate LLR bit width can reduce computational and storage complexity while maintaining good performance. Furthermore, the key to optimizing decoding complexity lies in reducing the number of iterations and improving the efficiency of each iteration. Iteration efficiency can be improved by increasing the decoder's performance or reducing the bit width of the input LLR.

[0084] Balanced performance:

[0085] The performance of LDPC may vary under different channel conditions. The performance balancing method aims to ensure good decoding performance in various environments by dynamically adjusting the decoding strategy.

[0086] It should be noted that LDPC is a linear block code with a sparse parity-check matrix, which can effectively correct bit errors in communication channels and is widely used in digital communication and storage systems. Compared with convolutional codes, LDPC has better error correction capabilities and approaches the Shannon limit in performance. LDPC decoding is the process of decoding the received encoded data to recover the original information. Due to its low-density characteristics and performance close to the Shannon limit, it is widely used in 5G standards to improve the reliability of data transmission by correcting errors in received signals through effective algorithms.

[0087] Specifically, its core concepts include check nodes, bit nodes, and check matrices:

[0088] Bit Node (VN): Also known as Variable Nodes, a bit node represents encoded information bits, with each bit node corresponding to one input bit. Bit nodes receive information from check nodes and send their own state (bit value), typically 0 or 1, to the check nodes.

[0089] Check Node (CN): A check node represents a parity check equation associated with a bit node. Each check node corresponds to a parity bit. The check node performs calculations based on the values ​​of the bit nodes it is connected to, to ensure that specific parity conditions (such as parity check) are met.

[0090] Parity check matrix H: The parity check matrix is ​​a sparse matrix where rows represent parity nodes and columns represent bit nodes. The elements in the matrix are usually 0 or 1, representing the connection relationship between bit nodes and parity nodes.

[0091] A schematic diagram of the parity check matrix H is shown below. Figure 1 As shown, the rows of the H matrix on the left correspond to check nodes, and the columns correspond to bit nodes. There are a total of 4 check equations and 8 bit nodes or 8 LLR inputs. Taking the first row as an example, the first check node... Since there are three consecutive bit nodes, the row weight is 3, and its parity check equation depends only on the first three bit nodes. For example... Figure 1 As shown, the first verification node Just and The same applies to other nodes. For example... Figure 1 A graph that describes the relationship between bit nodes and check nodes in this way is called a Tanner graph.

[0092] Therefore, LDPC decoding is mainly based on graph theory. The core idea is to gradually correct errors through message passing between bit nodes and check nodes. Bit nodes infer whether their LLR is positive by looking at other adjacent bit nodes of the check node, and then decide whether it is 0 or 1.

[0093] The mainstream LDPC decoding algorithms are as follows:

[0094] Belief Propagation (BP) Algorithm: As an iterative decoding algorithm based on Tanner graphs, the BP algorithm's main idea is to calculate the posterior probability of each node by passing information between nodes, and to approximate the correct decoding result through continuous iteration. The estimated value of each bit is updated by passing messages (probability information) in the Tanner graph. The main process includes:

[0095] (1) Initialization: Assign an initial message to each bit node, usually based on the received soft information;

[0096] (2) Message passing: Multiple rounds of message passing occur between the bit node and the check node. In each round, the node updates its message based on the information of its neighboring nodes;

[0097] (3) Convergence check: Iterate until the messages converge or the maximum number of iterations is reached;

[0098] (4) Decision: Make a decision on the bits based on the final message value.

[0099] The Min-Sum algorithm: Based on the backpropagation (BP) algorithm, this algorithm approximates the logarithmic field and simplifies the calculation process by calculating the minimum sum. It is particularly suitable for graph-based message passing mechanisms. The algorithm decodes by passing messages between bit nodes and check nodes, aiming to find the most probable bit value. The main process includes:

[0100] (1) Initialization: Similar to the BP algorithm, initialize the value of the bit node;

[0101] (2) Message update: In each iteration, calculate the minimum sum of each check node and feed the result back to the corresponding bit node;

[0102] (3) Update message: The bit node updates its own value based on the feedback from the check node;

[0103] (4) Convergence check: Repeat the iteration until the stopping condition is met.

[0104] Considering the complexity of engineering implementation and utilizing the LLR results after channel estimation, the minimum sum algorithm is usually used for decoding. It has the advantages of low computational complexity and suitability for hardware implementation. However, compared with other more complex algorithms such as the BP algorithm, the performance of the minimum sum algorithm may be slightly inferior, especially in the case of low signal-to-noise ratio.

[0105] Because the min-sum algorithm uses an approximation method, the message from the check node can be larger than that of the backpropagation (BP) algorithm, resulting in performance loss. Therefore, the industry actually uses an improved min-sum algorithm as the decoder, namely the offset min-sum algorithm.

[0106] Bit Node Passed to adjacent verification nodes The message is recorded as Verification node Pass to adjacent bit nodes The message is recorded as In the minimum sum algorithm, the verification node... The message update formula is:

[0107]

[0108] in, Represents a node The set of connected bit nodes on the parity-check matrix. This indicates that the original node will be excluded. The message is then passed to the node. .

[0109] Meanwhile, considering the parallelization of hardware implementation and the layered nature of the parity-check matrix H under the 5G standard, a layered approach is adopted for message passing: each row of the H matrix is ​​treated as a layer, and the process iterates layer by layer. Once one layer's message iteration is complete, the next layer's message is updated, and so on, until all layers are updated, signifying the completion of one iteration. In summary, the layered processing in the decoder based on the Layered Offset Min-Sum algorithm can be summarized as follows:

[0110] (1) Layered iteration: Divide the bit nodes and check nodes into multiple layers, and update only the nodes of one layer in each iteration;

[0111] (2) Message passing: In each layer, nodes pass messages to each other and update messages;

[0112] (3) Layer-by-layer update: After completing the update of one layer, continue to the next layer until all layers are completed;

[0113] Next, a detailed introduction will be given, in the section... In this iteration, the formula for updating the verification node information is as follows:

[0114]

[0115] The formula for updating bit nodes is:

[0116]

[0117] The verification node updates the formula again:

[0118]

[0119] Finally, if The corresponding bit hard decision is 0, otherwise it is 1.

[0120] In the 5G standard, the parity check matrix is ​​divided into two types, BG1 and BG2. The number of connected bit nodes in each layer is fixed and is called row weight. Figure 2 and Figure 3 The row weights of BG1 and BG2 are displayed respectively.

[0121] like Figure 2 As shown, taking BG1 as an example, BG1 has a maximum of 46 rows. Its vector represents the row weight corresponding to the check nodes in each row. For example, the check bits in the first layer correspond to 19 bit nodes. Higher row weight means stronger error correction capability. Higher row weight means that each check equation involves more bits, allowing more bits to participate in the check, which helps to better identify and correct errors. Processing from low to high row weight allows more reliable check equations to be processed at the end of the iteration, increasing reliability.

[0122] This invention provides an LDPC decoding method, apparatus, device, storage medium, and program product to solve the problem of high decoding complexity in existing LDPC decoding algorithms.

[0123] like Figure 4 As shown, an embodiment of the present invention provides an LDPC decoding method, including:

[0124] Step 401: Determine the first scaling factor based on the first signal to interference plus noise ratio (SINR). The first scaling factor is used to process the first log-likelihood ratio LLR, where the first LLR is a floating-point LLR and the first SINR is the SINR of the transmission symbol in the communication link.

[0125] In this step, the SINR (i.e., the first SINR) of each symbol transmitted in the communication link is obtained. The equivalent SINR of the communication link is calculated based on the first SINR of each symbol. Based on the equivalent SINR of the communication link, the first scaling factor for processing floating-point LLR is determined, or, in other words, the equivalent SINR of the communication link is mapped to the linear gain to the corresponding first scaling factor.

[0126] Step 402: Perform fixed-point quantization on the first LLR according to the first scaling factor to obtain the second LLR.

[0127] In this step, the first floating-point LLR is scaled using the first scaling factor to complete the fixed-point quantization process of the first LLR, resulting in a fixed-point LLR. Therefore, the second LLR is a fixed-point LLR. This step achieves fixed-point quantization of the LLR.

[0128] Step 403: Input the second LLR into the decoder, and decode the second LLR using the low-density parity-check code (LDPC) decoding algorithm in the first order to obtain the decoded bit message output by the decoder.

[0129] The decoder includes a multi-layer decoding structure arranged in sequence, each layer of the decoding structure including a check node and at least one bit node connected to the check node; the first sequence is the reverse of the arrangement order of the multi-layer decoding structure.

[0130] In this step, the fixed-point second LLR is input into the decoder for decoding. Specifically, the fixed-point LLR is input into a Layered LDPC decoder based on reverse processing. The reverse-processing layered LDPC decoding algorithm is used to obtain the decoded bit message output by the decoder. This efficiently maps the LLR to bit information without requiring additional computational resources, improving decoding performance and reducing the complexity of the LDPC decoding algorithm.

[0131] In some embodiments, before determining the first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR), the method further includes:

[0132] The first LLR is obtained based on the first distance variable, the first received symbol, and the first SINR;

[0133] Wherein, the first distance variable is a distance variable related to the modulation method of the transmission symbols of the communication link;

[0134] The first received symbol is a received symbol related to the modulation method of the transmission symbol of the communication link.

[0135] It should be noted that the uplink channel receiver recovers the demodulated signal to obtain the recovered modulation constellation symbol (hereinafter referred to as the received symbol), which is denoted as... The modulation symbol at the transmitting end is The noise of the modulation symbol is Then we have:

[0136]

[0137] For the calculation of floating-point LLR (i.e., the first LLR), the max-log maximum posterior probability (MAP) method can usually be applied, and the final calculation result is expressed as:

[0138]

[0139] However, in actual engineering, a small amount of performance is usually sacrificed in exchange for a simplified LLR. The LLR (i.e., the first LLR) calculation formula is shown as follows:

[0140]

[0141] This can be understood as the modulation scheme of the first LLR and the transmission symbols of the communication link. The relevant distance variable (i.e., the first distance variable) Regarding, and the modulation scheme of the first LLR and the transmission symbols of the communication link. The relevant received symbol (i.e., the first received symbol) related.

[0142] It should also be noted that for different modulation methods, such as Pi / 2-BPSK (a variant of Binary Phase Shift Keying (BPSK), which achieves phase shifting of the modulated signal by π / 2 at odd-numbered positions and maintaining the same phase as BPSK at even-numbered positions), BPSK, Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QAM), 64QAM, and 256QAM, the distance between adjacent constellation points (i.e., the first distance variable) is different. They are shown below:

[0143]

[0144] That is, the first distance variable corresponding to Pi / 2-BPSK, BPSK, and QPSK is The first distance variable corresponding to 16QAM is The first distance variable corresponding to 64QAM is The first distance variable corresponding to 256QAM is .

[0145] It should also be noted that, for variables It is similar to the modulation method of the transmission symbols in the communication link. Relatedly, the following section introduces the corresponding modulation methods. .

[0146] For QPSK:

[0147]

[0148] For 16QAM:

[0149]

[0150] For 64QAM:

[0151]

[0152] For 256QAM:

[0153]

[0154] In summary, the first LLR is finally calculated.

[0155] In some embodiments, determining the first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR) includes:

[0156] Based on the second SINR of different modulation and coding methods, the first equivalent SINR is obtained, and the second SINR is the SINR of the simulated link transmission symbol.

[0157] Specifically, through link-level simulation, the SINR (i.e., the second SINR) is set, and the modulation and coding scheme (MCS) is selected, which is to select the bit coding rate R. Packets with a coding rate of R are sent over a 5G transmission time interval (TTI).

[0158] At the receiver, after equalization, the equivalent SINR on the subcarrier (i.e., the first equivalent SINR) is calculated using the second SINR, and is expressed as: .

[0159] in, Indicates the first equivalent SINR. Indicates the number of subcarriers. This indicates the second SINR.

[0160] By using different second scaling factors, the first equivalent SINR is adjusted to obtain the third SINR corresponding to different second scaling factors.

[0161] Specifically, under this first equivalent SINR, by continuously changing the selected second scaling factor... The value, usually Choose a value that is an integer multiple of the given number, for example .

[0162] Utilizing the selected different second scaling factors The value is used to scale and adjust the first equivalent SINR to obtain different second scaling factors. The corresponding third SINR.

[0163] Obtain the CRC check result corresponding to each of the third SINRs, that is, determine whether the CRC check result corresponding to each third SINR is correct.

[0164] Obtain the fourth SINR in the third SINR corresponding to the correct CRC check result, and obtain the third scaling factor in the second scaling factor corresponding to the correct CRC check result.

[0165] Specifically, if the CRC check result is correct, obtain the fourth SINR from the third SINR corresponding to the correct CRC check result and the third scaling factor from the second scaling factor, and determine a... right.

[0166] A first correspondence is generated based on different modulation and coding schemes, the fourth SINR, and the third scaling factor. The first correspondence is used to indicate the correspondence between modulation and coding schemes, equivalent SINR, and scaling factor.

[0167] This first correspondence can also be called a mapping function. scaling factor Modulation and coding methods Equivalent SINR The correspondence between them is represented as follows:

[0168]

[0169] in, This indicates the bit coding rate.

[0170] The first scaling factor is determined based on the first SINR, the modulation and coding scheme corresponding to the transmission symbol of the communication link, and the first correspondence.

[0171] Specifically, based on the first SINR, the equivalent SINR for the entire system is calculated as follows:

[0172]

[0173] in, Indicates the equivalent SINR, Indicates the first SINR, This indicates the number of symbols transmitted in the communication link.

[0174] That is, equivalent This reflects the impact of the "bit channel" on the success rate of decoding.

[0175] Subsequently, based on the aforementioned mapping function U (i.e., the first correspondence) and the modulation and coding schemes corresponding to the transmission symbols of the communication link, Bit coding rate This allows us to map the first scaling factor.

[0176] It should be noted that, due to the scaling factor Modulation and coding methods Equivalent SINR There is no explicit formula for the mapping between them. The mapping function U (i.e. the first correspondence) can be pre-calculated using aggregation algorithms in machine learning to create a classification table.

[0177] As an optional implementation, generating the first correspondence based on different modulation and coding schemes, the fourth SINR, and the third scaling factor includes:

[0178] Obtain the first number of the fourth SINR and the first number of the third scaling factors under different modulation and coding schemes, wherein the first number is based on the number of the second SINR. The number of TTIs compared to the preset Sounding Reference Signal (SRS) It's confirmed.

[0179] Optionally, the first quantity equals .

[0180] That is, in the time dimension, multiple TTIs of multiple SRS channels are simulated, denoted as... , obtain multiple right, .

[0181] Under the same MCS conditions, the transformation settings (i.e., the second SINR), perform different second SINR simulations, assuming there are a total of A set value (i.e., the second SINR) can be obtained indivual right.

[0182] For each modulation and coding scheme, the first number of fourth SINRs and the first number of third scaling factors are clustered to obtain the fifth SINR and fourth scaling factor corresponding to each modulation and coding scheme.

[0183] It should be noted that in this optional implementation, the unsupervised learning K-means algorithm is used to obtain the mapping function U (i.e., the first correspondence). K-means is an efficient clustering algorithm that achieves data grouping by iteratively optimizing cluster centers and is suitable for various practical application scenarios. The principle of the K-means algorithm is as follows: Figure 5 As shown. Figure 5 As shown, AE represents five sample points, while the gray points are random points, used to find point clusters. There are two seed points K=2, and the seed points are continuously moved to the center of their respective "point clusters".

[0184] In this optional embodiment, the K-means algorithm is used to cluster the first number of fourth SINRs and the first number of third scaling factors for each modulation and coding scheme, thereby finding the corresponding modulation and coding scheme. The fifth SINR and the fourth scaling factor, Based on the simulation in the interval Different selections are made from [1,2,3,…,16]. The value is determined, forming right.

[0185] The correspondences form a table, the boundaries of which are determined by the following formula:

[0186]

[0187] By repeating the above steps with different MCSs, you can obtain different MCSs. The correspondence.

[0188] The first correspondence is generated based on different modulation and coding schemes, the fifth SINR, and the fourth scaling factor.

[0189] according to Pairing, modulation and coding methods and bit coding rate The first correspondence is represented as follows:

[0190]

[0191] in, That is, the fifth SINR. This is the fourth scaling factor.

[0192] For example, the first correspondence is:

[0193] In a certain modulation and coding scheme and a certain bit coding rate The scaling factor is 1 when SINR is greater than or equal to 6.7608, 2 when SINR is greater than or equal to 5.1286 and less than 6.7608, 3 when SINR is greater than or equal to 4.7315 and less than 5.1286, 4 when SINR is greater than or equal to 4.3652 and less than 4.7315, and 4 when SINR is greater than or equal to 0 and less than 4.3652.

[0194] According to the first correspondence mentioned above, when the equivalent SINR calculated based on the first SINR is 5.5, the first scaling factor is 2.

[0195] In some embodiments, the step of performing fixed-point quantization on the first LLR according to the first scaling factor to obtain the second LLR includes:

[0196] The third LLR is obtained based on the first scaling factor and the first LLR.

[0197] Specifically, let the floating-point LLR value (i.e., the first LLR) be... Then we have:

[0198]

[0199] For the decoder implementation, the input is a fixed-point number sequence with a fixed saturation bit width, assuming that its input values ​​have a total of One, saturated bit width is Then we have:

[0200]

[0201] The fixed-point quantization calculation is represented as follows, using the first scaling factor. For the first LLR The third LLR is obtained by performing fixed-point quantization. The representation is as follows:

[0202]

[0203] The third LLR is shifted to obtain the fourth LLR.

[0204] Specifically, the third LLR mentioned above is shifted to the right. The bit is fixed-pointed, resulting in the fourth LLR.

[0205] Peak clipping is performed on the fourth LLR to obtain the second LLR.

[0206] Specifically, the fourth LLR is clipped to target the decoder characteristics, limiting the LLR to the range of [-32, 31], and quantization is completed to obtain the second LLR.

[0207] The fixed-point LLR result (i.e., the second LLR) is input into a decoder using the reverse-order Layered LDPC decoding algorithm as initial information provided by the channel.

[0208] In some embodiments, the step of inputting the second LLR into the decoder and decoding the second LLR using the Low-Density Parity-Check (LDPC) decoding algorithm in a first order to obtain the decoded bit message output by the decoder includes:

[0209] The second LLR is input into the decoder, and the first operation is performed in the decoder;

[0210] If the first condition is met, the execution of the first operation shall be stopped;

[0211] If the first condition is not met, update the first target LLR to the second target LLR obtained from the first check node, and return to the step of performing the first operation in the decoder;

[0212] Based on the second target LLR obtained from the last execution of the first operation, the decoded bit message output by the decoder is obtained;

[0213] The first operation includes:

[0214] The first verification node obtains the second target LLR (also called a message) based on the first matrix value and the first target LLR (also called a message).

[0215] The first verification node sends the second target LLR to the first bit node;

[0216] The first bit node updates the LLR (also called message) currently stored in the first bit node according to the second target LLR, and obtains the updated LLR (also called message) stored in the first bit node.

[0217] Wherein, the first verification node is a verification node in any layer of the multi-layer decoding structure;

[0218] The first matrix value is the matrix value corresponding to the first check node and the first bit node in the check matrix, and the first bit node is the bit node in the decoding structure of the first check node.

[0219] When the first verification node is a verification node in the last layer of the decoding structure, the first target LLR is the second LLR. When the first verification node is a verification node in any layer of the decoding structure other than the last layer, the first target LLR is the second target LLR obtained by the second verification node. The second verification node is the verification node adjacent to the first verification node in the multi-layer decoding structure according to the first order.

[0220] When the first verification node is a first-level verification node, the updated LLR stored in the first bit node is the second target LLR obtained by performing the first operation;

[0221] The first condition includes at least one of the following:

[0222] The first operation has been performed a preset number of times;

[0223] The second target LLR obtained by performing the first operation passes the corresponding verification equation.

[0224] It should be noted that in this embodiment, taking into account the row-duplication characteristic of the parity check matrix designed in the 5G standard, a reverse iterative processing method is directly adopted to reduce the number of algorithm branches. A schematic diagram of the first sequence is shown below. Figure 6 As shown.

[0225] Among them, the decoder involves a parity check matrix. Total number of rows This refers to the total number of layers. This parameter determines the actual number of rows after puncturing based on the bitrate. Each layer corresponds to... Due to the characteristics of convolutional cyclic codes, the bit nodes corresponding to each check node in the check matrix are orthogonal, making it suitable for hardware parallel implementation for acceleration.

[0226] In the decoder, the fixed-point LLR (i.e., the second LLR) output by the fixed-point optimizer is first input into the decoder as the initial message for the bit node, and then decoded. Iteration then begins from the last layer of the decoding structure. The check node of the last layer calculates the message to be passed to the bit node based on the input LLR (second LLR). The bit node, based on the received message To update its own LLR (i.e., to obtain the updated LLR stored in the first bit node), it iterates layer by layer in reverse order from the last to the first layer until the entire parity check matrix is ​​scanned. After the scan is completed, the LLR can provide hard decision information through the sign bit.

[0227] Subsequently, in one optional mode, it is determined whether the termination condition (i.e., the first condition) is met. If the first condition is met, i.e., whether the number of iterations has been reached (i.e., the number of times the first operation has been executed has reached a preset number) or whether the second target LLR obtained from the first operation passes the corresponding check equation, then the information bit sequence is output through hard decision. If not, the above operation is repeated, iterating from the last layer of the decoding structure until the first condition is met. Alternatively, in another optional mode, it is determined whether the second target LLR obtained from the first operation passes the corresponding check equation. If it is, the information bit sequence is output through hard decision. If not, it is determined whether the number of times the first operation has been executed has reached a preset number. If not, the above operation is repeated, iterating from the last layer of the decoding structure until the second target LLR obtained from the first operation passes the corresponding check equation, or until the number of times the first operation has been executed has reached a preset number. If the number of times the first operation has been executed has reached a preset number, the iteration ends, indicating decoding failure. The decoder performs hard bit decision based on the final LLR and outputs the bit sequence.

[0228] For example, such as Figure 7 As shown, the overall decoding process of the decoder is as follows:

[0229] Input vertex LLR (i.e., the second LLR). Then, determine whether the iteration count is satisfied (i.e., whether the number of times the first operation is executed exceeds the preset number). If the iteration count is not satisfied, perform the reverse layer-by-layer iteration operation (i.e., the first operation). In each reverse layer-by-layer iteration operation, check the node update information and bit node update information in reverse order to obtain the updated decoding result obtained by the reverse layer-by-layer iteration operation (i.e., the second target LLR obtained by executing the first operation). Determine whether the termination condition is satisfied (the termination condition is that the updated decoding result passes the corresponding check equation). If the termination condition is satisfied, output the hard decision result, i.e., obtain the information bits output by the decoder. If the termination condition is not satisfied, determine whether the iteration count is satisfied (i.e., whether the number of times the first operation is executed exceeds the preset number). If the iteration count is not satisfied, continue to perform the reverse layer-by-layer iteration operation (i.e., the first operation) until the termination condition is satisfied. If the iteration count is satisfied, output the hard decision result, i.e., obtain the information bits output by the decoder.

[0230] Optionally, the first bit node updates its currently stored LLR based on the second target LLR to obtain the updated LLR stored by the first bit node, including:

[0231] The first bit node updates its currently stored LLR based on the second target LLR, a preset first minimum sum, and a preset second minimum sum, to obtain the updated LLR stored in the first bit node.

[0232] It should be noted that in 5G small cells, a maximum number of iterations is typically set to ensure that the decoder's decoding task does not time out. However, decoding performance is closely related to the number of iterations, and satisfactory performance usually needs to be achieved within a certain number of iterations. Therefore, improving decoder performance within the constraint of the number of iterations is crucial. In this embodiment, the decoder designed in reverse order employs a two-min algorithm to further reduce complexity. The specific calculation formula is as follows:

[0233] The decoder calculates the number of layers nRow corresponding to the parity check matrix based on the code rate, and the layer indices are denoted as 0, 1, …, nRow-1; and determines the maximum number of iterations maxIter (i.e., the preset number of iterations) of the algorithm.

[0234] In each iteration (0, 1, …, maxIter):

[0235] Starting from row nRow-1, scan in reverse order (nRow-1, nRow-2, …, 0):

[0236] CN layer scan: CN calculates the sign product of message R:VN based on the LLR of the connected VN, and records min1 (preset first minimum sum) and min2 (preset second minimum sum).

[0237] Verification Node The message update formula is:

[0238]

[0239] in, Indicates the verification node The set of connected bit nodes on the parity-check matrix. This indicates that the original node will be excluded. The message is then passed to the node. . Indicates the verification node The message before the update. This is represented as a preset value.

[0240] VN layer scan: Receive message R, update LLR based on min1 and min2, the update formula is:

[0241]

[0242] The decoder checks if the termination condition (i.e., the first condition) is met. If it is, the iteration ends early; otherwise, it continues. The decoder performs hard bit decision based on the final LLR and outputs the bit sequence.

[0243] Specifically, in each iteration (0, 1, …, maxIter), the decoder performs the following steps:

[0244] Starting from the LLR corresponding to layer nRow-1, iterate layer by layer in reverse order of the layer indices (nRow-1, …, 1, 0);

[0245] All check nodes (CNs) within the layer sequentially scan the connected bit nodes (0, 1, …, numBits), read the LLR of the current node, and update the sign bit product, minimum value (first minimum sum), and second minimum value (second minimum sum).

[0246] All check nodes (CNs) calculate the final updated LLR;

[0247] All check nodes (CNs) within the layer sequentially scan the connected bit nodes (0, 1, …, numBits) and pass the updated message to the bit nodes;

[0248] Bit nodes update their own LLR based on the transmitted message;

[0249] Determine if the verification equation passes; if it does, terminate the decoding early; otherwise, proceed to the next layer to continue iteration.

[0250] Determine if the maximum number of iterations has been reached. If it has, end the decoding; otherwise, proceed to the next level to continue iterating.

[0251] The decoder makes a hard bit decision based on the final LLR and outputs the bit sequence.

[0252] The following is combined Figure 8 The overall process of the LDPC decoding method provided in this embodiment of the invention is described in detail below:

[0253] The floating-point LLR output from the receiver is input to the LLR fixed-point optimizer, where the equivalent SINR of the communication link transmission is calculated. Based on the equivalent SINR and mapping function U, the scaling factor is calculated, and the floating-point LLR is subjected to LLR fixed-point quantization processing according to the scaling factor to obtain the fixed-point quantized LLR. The fixed-point quantized LLR is then input into a Layered LDPC decoder based on reverse processing for decoding, and the decoded bit sequence is output.

[0254] The simulation results of the Layered LDPC decoding algorithm that iterates through the H matrix in reverse order according to the embodiments of the present invention are described below:

[0255] The LDPC decoder uses CB-level processing. The simulation results for MCS2~20 are shown under 256QAM, therefore the simulation is based on a TDL-A channel. The algorithms involved in the LDPC decoder simulation are explained below:

[0256] Built-in decoder: Intel's closed-source decoder;

[0257] Order layered two-min: A Layered LDPC decoding algorithm that iterates through the H matrix layer by layer in sequence;

[0258] Dynamic layered two-min: A Layered LDPC decoding algorithm that selects layers of the H matrix in a random manner and accesses them dynamically;

[0259] Reverse layered two-min: A Layered LDPC decoding algorithm that iterates through the H matrix in reverse order and sets a minimum of 3 iterations;

[0260] Reverse layered two-min + modified iteration termination judgment: Layered LDPC decoding algorithm that iterates through the H matrix in reverse order.

[0261] First, the impact of different algorithms on SNR (i.e., SINR) and Block Error Rate (BLER) is shown, such as... Figure 9 As shown, the simulation conditions are set under TDL-A channel, with a delay spread of 30ns, a speed of 3km / h, and the average number of iteration terminations for MCS2~20.

[0262] Simulations demonstrate that different access methods to the H matrix layer affect the decoding results. In the 5G standard, the H matrix exhibits a trend of decreasing row weight. Under the same SNR, random access yields the worst decoding performance, while the proposed reverse access method delivers the best performance. Therefore, the reverse decoder can improve decoder performance.

[0263] Finally, the impact of different algorithms on the number of iteration terminations and SNR (i.e., SINR) is presented, such as... Figure 10 As shown, the simulation conditions are set under TDL-A channel, with a delay spread of 30ns, a speed of 3km / h, and the average number of iteration terminations for MCS2~20.

[0264] like Figure 10As shown, under the same SNR, the Layered LDPC decoding algorithm that accesses the H matrix in reverse order performs best, followed by the sequential approach, while dynamic access performs worst. Therefore, the Layered LDPC decoding algorithm based on reverse processing effectively reduces the algorithm complexity by decreasing the number of iterations.

[0265] It should be noted that existing technologies do not consider fixed-point implementation, increasing decoder complexity and reducing decoder performance. Furthermore, they do not consider practicality, using LLR as the decoder input, which does not involve noise power or complex symbols, leading to increased memory overhead and low resource utilization. To address these issues, this invention successfully reduces the complexity of the LDPC decoder while improving decoding performance by jointly dynamically adjusting the Log-Likelihood Ratio (LRR) scaling factor and employing a hierarchical LDPC decoding algorithm with reverse processing. This innovative design not only optimizes latency control but also effectively improves the overall system performance, meeting the demand for efficient decoding and ensuring that 5G networks can provide excellent quality of service in various application scenarios. Moreover, this invention not only improves decoding performance but also effectively reduces computational complexity, ensuring efficient decoding while accelerating the LDPC decoder convergence speed, meeting the stringent requirements of 5G networks for low latency and high reliability, and improving overall performance.

[0266] Furthermore, this invention employs a dynamic scaling factor, utilizing machine learning to pre-simulate and determine the mapping function based on channel characteristics, thereby improving reliability. Then, the scaling factor is found based on the actual equivalent SINR, realizing dynamic LLR fixed-point quantization based on channel characteristics. This fully utilizes channel estimation information to adapt to different channel states, reducing the complexity of the LDPC decoding algorithm. Moreover, this fixed-point quantization is completed before input to the decoder, without affecting the decoder's internal runtime latency.

[0267] Furthermore, this invention employs a reverse-order Layered LDPC decoding algorithm. Based on the sparse nature of the H matrix in the 5G standard, decoding is performed layer by layer in reverse order during each iteration, accelerating LDPC convergence and improving decoding performance. Message updates within the decoder are processed according to a fixed reverse-order logic during each iteration, which is beneficial for memory read / write operations without increasing complexity. Simultaneously, under the 5G standard, the H matrix typically has a larger row weight in the first four layers compared to other layers; updating its information last helps accelerate the overall decoding convergence speed. With the rapid development of communication technologies, especially in 5G, IoT, and satellite communications, the demand for efficient and low-complexity decoding algorithms is increasing. LDPC, due to its superior error correction performance, has become an important component of modern communication systems. Therefore, research on methods balancing complexity and performance in LDPC decoding algorithms has significant market value.

[0268] Compared with existing LDPC decoding algorithms, this invention has the following competitive advantages:

[0269] Performance improvement: By optimizing the balance between complexity and performance, better decoding efficiency can be provided under different channel conditions.

[0270] Resource conservation: Reduces computational complexity in the decoding process, enabling efficient operation even in resource-constrained environments (such as mobile devices or low-power devices).

[0271] Highly adaptable: This method can dynamically adjust the decoding strategy according to different application requirements, thereby improving the user experience.

[0272] This invention is applicable to multiple fields, including:

[0273] Mobile communications: In 5G and future communication standards, optimizing LDPC decoding can significantly improve the reliability and speed of data transmission.

[0274] Satellite communication: Improve the anti-interference capability of satellite signals and ensure high-quality data transmission.

[0275] Data storage: LDPC codes are applied in storage devices to improve data integrity and reliability.

[0276] With the increasing demand for high data rate and low latency communication, the optimization of LDPC decoding algorithms will become an important direction for the future development of communication technology.

[0277] like Figure 11 As shown, this embodiment of the invention also provides an LDPC decoding apparatus, comprising:

[0278] The first processing module 1101 is used to determine a first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR). The first scaling factor is used to process the first log-likelihood ratio (LLR), where the first LLR is a floating-point LLR and the first SINR is the SINR of the transmission symbol in the communication link.

[0279] The second processing module 1102 is used to perform fixed-point quantization on the first LLR according to the first scaling factor to obtain the second LLR.

[0280] The third processing module 1103 is used to input the second LLR into the decoder and decode the second LLR using the low-density parity-check code (LDPC) decoding algorithm in the first order to obtain the decoded bit message output by the decoder.

[0281] The decoder includes a multi-layer decoding structure arranged in sequence, each layer of the decoding structure including a check node and at least one bit node connected to the check node;

[0282] The first order is the reverse of the arrangement order of the multi-layer decoding structure.

[0283] Optionally, the device further includes:

[0284] The fourth processing module is used to obtain the first LLR based on the first distance variable, the first received symbol, and the first SINR;

[0285] Wherein, the first distance variable is a distance variable related to the modulation method of the transmission symbols of the communication link;

[0286] The first received symbol is a received symbol related to the modulation method of the transmission symbol of the communication link.

[0287] Optionally, the first processing module 1101 includes:

[0288] The first processing unit is used to obtain a first equivalent SINR based on the second SINR of different modulation and coding methods, wherein the second SINR is the SINR of the simulated link transmission symbol;

[0289] The second processing unit is used to adjust the first equivalent SINR using different second scaling factors to obtain a third SINR corresponding to different second scaling factors.

[0290] The first acquisition unit is used to acquire the CRC check result corresponding to each of the third SINRs.

[0291] The second acquisition unit is used to acquire the fourth SINR in the third SINR corresponding to the correct CRC check result, and to acquire the third scaling factor in the second scaling factor corresponding to the correct CRC check result;

[0292] The third processing unit is used to generate a first correspondence relationship based on different modulation and coding schemes, the fourth SINR and the third scaling factor. The first correspondence relationship is used to indicate the correspondence relationship between modulation and coding schemes, equivalent SINR and scaling factor.

[0293] The first determining unit is configured to determine the first scaling factor based on the first SINR, the modulation and coding scheme corresponding to the communication link transmission symbol, and the first correspondence.

[0294] Optionally, the third processing unit is specifically used for:

[0295] Under different modulation and coding schemes, a first number of the fourth SINR and a first number of the third scaling factors are obtained, wherein the first number is determined based on the number of the second SINR and the number of TTIs of the preset detection reference signal SRS;

[0296] For each modulation and coding scheme, the first number of fourth SINRs and the first number of third scaling factors are clustered to obtain the fifth SINR and fourth scaling factor corresponding to each modulation and coding scheme;

[0297] The first correspondence is generated based on different modulation and coding schemes, the fifth SINR, and the fourth scaling factor.

[0298] Optionally, the second processing module 1102 includes:

[0299] The fourth processing unit is used to obtain the third LLR based on the first scaling factor and the first LLR;

[0300] The fifth processing unit is used to perform a shifting process on the third LLR to obtain the fourth LLR;

[0301] The sixth processing unit is used to perform peak clipping on the fourth LLR to obtain the second LLR.

[0302] Optionally, the third processing module 1103 includes:

[0303] The seventh processing unit is used to input the second LLR into the decoder and perform the first operation in the decoder;

[0304] The eighth processing unit is configured to stop executing the first operation if the first condition is met;

[0305] The ninth processing unit is used to update the first target LLR to the second target LLR obtained by the first check node if the first condition is not met, and return to the step of performing the first operation in the decoder;

[0306] Based on the second target LLR obtained from the last execution of the first operation, the decoded bit message output by the decoder is obtained;

[0307] The first operation includes:

[0308] The first verification node obtains the second target LLR based on the first matrix value and the first target LLR;

[0309] The first verification node sends the second target LLR to the first bit node;

[0310] The first bit node updates the LLR currently stored in the first bit node according to the second target LLR, so as to obtain the updated LLR stored in the first bit node;

[0311] Wherein, the first verification node is a verification node in any layer of the multi-layer decoding structure;

[0312] The first matrix value is the matrix value corresponding to the first check node and the first bit node in the check matrix, and the first bit node is the bit node in the decoding structure of the first check node.

[0313] When the first verification node is a verification node in the last layer of the decoding structure, the first target LLR is the second LLR. When the first verification node is a verification node in any layer of the decoding structure other than the last layer, the first target LLR is the second target LLR obtained by the second verification node. The second verification node is the verification node adjacent to the first verification node in the multi-layer decoding structure according to the first order.

[0314] When the first verification node is a first-level verification node, the updated LLR stored in the first bit node is the second target LLR obtained by performing the first operation;

[0315] The first condition includes at least one of the following:

[0316] The first operation has been performed a preset number of times;

[0317] The second target LLR obtained by performing the first operation passes the corresponding verification equation.

[0318] Optionally, the seventh processing unit is specifically used for:

[0319] The first bit node updates its currently stored LLR based on the second target LLR, a preset first minimum sum, and a preset second minimum sum, to obtain the updated LLR stored in the first bit node.

[0320] It should be noted that the LDPC decoding apparatus provided in the embodiments of the present invention is an apparatus capable of executing the above-described LDPC decoding method. Therefore, all embodiments of the above-described LDPC decoding method are applicable to this apparatus and can achieve the same or similar technical effects.

[0321] like Figure 12As shown, this embodiment of the invention also provides an LDPC decoding device, including: a processor 1201; and a memory 1203 connected to the processor 1201 via a bus interface 1202. The memory 1203 is used to store programs and data used by the processor 1201 when performing operations, and the processor 1201 calls and executes the programs and data stored in the memory 1203.

[0322] The transceiver 1204 is connected to the bus interface 1202 and is used to receive and send data under the control of the processor 1201. Specifically, the processor 1201 is used to read the program in the memory 1203 and to execute the following processes:

[0323] Based on the first signal-to-interference-plus-noise ratio (SINR), a first scaling factor is determined. The first scaling factor is used to process the first log-likelihood ratio (LLR). The first LLR is a floating-point LLR, and the first SINR is the SINR of the transmission symbol in the communication link.

[0324] The first LLR is subjected to fixed-point quantization based on the first scaling factor to obtain the second LLR;

[0325] The second LLR is input into the decoder, and the second LLR is decoded using the low-density parity-check code (LDPC) decoding algorithm in the first order to obtain the decoded bit message output by the decoder.

[0326] The decoder includes a multi-layer decoding structure arranged in sequence, each layer of the decoding structure including a check node and at least one bit node connected to the check node;

[0327] The first order is the reverse of the arrangement order of the multi-layer decoding structure.

[0328] Optionally, the processor 1201 is further configured to:

[0329] The first LLR is obtained based on the first distance variable, the first received symbol, and the first SINR;

[0330] Wherein, the first distance variable is a distance variable related to the modulation method of the transmission symbols of the communication link;

[0331] The first received symbol is a received symbol related to the modulation method of the transmission symbol of the communication link.

[0332] Optionally, the processor 1201 is specifically used for:

[0333] Based on the second SINR of different modulation and coding methods, the first equivalent SINR is obtained, and the second SINR is the SINR of the simulated link transmission symbol;

[0334] By adjusting the first equivalent SINR using different second scaling factors, a third SINR corresponding to different second scaling factors can be obtained;

[0335] Obtain the CRC check result corresponding to each of the third SINRs;

[0336] Obtain the fourth SINR in the third SINR corresponding to the correct CRC check result, and obtain the third scaling factor in the second scaling factor corresponding to the correct CRC check result;

[0337] Based on different modulation and coding schemes, the fourth SINR and the third scaling factor, a first correspondence is generated, which is used to indicate the correspondence between modulation and coding schemes, equivalent SINR and scaling factor;

[0338] The first scaling factor is determined based on the first SINR, the modulation and coding scheme corresponding to the transmission symbol of the communication link, and the first correspondence.

[0339] Optionally, the processor 1201 is specifically used for:

[0340] Under different modulation and coding schemes, a first number of the fourth SINR and a first number of the third scaling factors are obtained, wherein the first number is determined based on the number of the second SINR and the number of TTIs of the preset detection reference signal SRS;

[0341] For each modulation and coding scheme, the first number of fourth SINRs and the first number of third scaling factors are clustered to obtain the fifth SINR and fourth scaling factor corresponding to each modulation and coding scheme;

[0342] The first correspondence is generated based on different modulation and coding schemes, the fifth SINR, and the fourth scaling factor.

[0343] Optionally, the processor 1201 is specifically used for:

[0344] The third LLR is obtained based on the first scaling factor and the first LLR;

[0345] The third LLR is shifted to obtain the fourth LLR;

[0346] Peak clipping is performed on the fourth LLR to obtain the second LLR.

[0347] Optionally, the processor 1201 is specifically used for:

[0348] The second LLR is input into the decoder, and the first operation is performed in the decoder;

[0349] If the first condition is met, the execution of the first operation shall be stopped;

[0350] If the first condition is not met, update the first target LLR to the second target LLR obtained from the first check node, and return to the step of performing the first operation in the decoder;

[0351] Based on the second target LLR obtained from the last execution of the first operation, the decoded bit message output by the decoder is obtained;

[0352] The first operation includes:

[0353] The first verification node obtains the second target LLR based on the first matrix value and the first target LLR;

[0354] The first verification node sends the second target LLR to the first bit node;

[0355] The first bit node updates the LLR currently stored in the first bit node according to the second target LLR, so as to obtain the updated LLR stored in the first bit node;

[0356] Wherein, the first verification node is a verification node in any layer of the multi-layer decoding structure;

[0357] The first matrix value is the matrix value corresponding to the first check node and the first bit node in the check matrix, and the first bit node is the bit node in the decoding structure of the first check node.

[0358] When the first verification node is a verification node in the last layer of the decoding structure, the first target LLR is the second LLR. When the first verification node is a verification node in any layer of the decoding structure other than the last layer, the first target LLR is the second target LLR obtained by the second verification node. The second verification node is the verification node adjacent to the first verification node in the multi-layer decoding structure according to the first order.

[0359] When the first verification node is a first-level verification node, the updated LLR stored in the first bit node is the second target LLR obtained by performing the first operation;

[0360] The first condition includes at least one of the following:

[0361] The first operation has been performed a preset number of times;

[0362] The second target LLR obtained by performing the first operation passes the corresponding verification equation.

[0363] Optionally, the processor 1201 is specifically used for:

[0364] The first bit node updates its currently stored LLR based on the second target LLR, a preset first minimum sum, and a preset second minimum sum, to obtain the updated LLR stored in the first bit node.

[0365] Among them, Figure 12 In this context, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 1201) and memory (memory 1203). The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides a user interface 1205. A transceiver 1204 may be multiple elements, including transmitters and receivers, providing units for communicating with various other devices over a transmission medium. Processor 1201 is responsible for managing the bus architecture and general processing, and memory 1203 may store data used by processor 1201 during operation.

[0366] In addition, specific embodiments of the present invention also provide a readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the steps of the LDPC decoding method as described above.

[0367] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0368] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can be physically comprised separately, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware plus software functional units.

[0369] The integrated unit implemented as a software functional unit described above can be stored in a computer-readable storage medium. This software functional unit, stored in a storage medium, includes several instructions that cause a computer device (which may be a personal computer, server, or network device, etc.) to execute partial steps of the resource selection method described in the various embodiments of the present invention, or to execute partial steps of the information transmission method described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0370] A specific embodiment of the present invention also provides a computer program product, including computer instructions, which, when executed by a processor, implement the above-described functionality. Figure 4 The various processes of the method embodiments shown can achieve the same technical effect, and will not be described again here to avoid repetition.

[0371] The above describes the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also within the scope of protection of the present invention.

Claims

1. An LDPC decoding method, characterized in that, include: Based on the first signal-to-interference-plus-noise ratio (SINR), a first scaling factor is determined. The first scaling factor is used to process the first log-likelihood ratio (LLR). The first LLR is a floating-point LLR, and the first SINR is the SINR of the transmission symbol in the communication link. The first LLR is subjected to fixed-point quantization based on the first scaling factor to obtain the second LLR; The second LLR is input into the decoder, and the second LLR is decoded using the low-density parity-check code (LDPC) decoding algorithm in the first order to obtain the decoded bit message output by the decoder. The decoder includes a multi-layer decoding structure arranged in sequence, each layer of the decoding structure including a check node and at least one bit node connected to the check node; The first order is the reverse of the arrangement order of the multi-layer decoding structure.

2. The method according to claim 1, characterized in that, Before determining the first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR), the method further includes: The first LLR is obtained based on the first distance variable, the first received symbol, and the first SINR; Wherein, the first distance variable is a distance variable related to the modulation method of the transmission symbols of the communication link; The first received symbol is a received symbol related to the modulation method of the transmission symbol of the communication link.

3. The method according to claim 1, characterized in that, The step of determining the first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR) includes: Based on the second SINR of different modulation and coding methods, the first equivalent SINR is obtained, and the second SINR is the SINR of the simulated link transmission symbol; By adjusting the first equivalent SINR using different second scaling factors, a third SINR corresponding to different second scaling factors can be obtained; Obtain the CRC check result corresponding to each of the third SINRs; Obtain the fourth SINR in the third SINR corresponding to the correct CRC check result, and obtain the third scaling factor in the second scaling factor corresponding to the correct CRC check result; Based on different modulation and coding schemes, the fourth SINR and the third scaling factor, a first correspondence is generated, which is used to indicate the correspondence between modulation and coding schemes, equivalent SINR and scaling factor; The first scaling factor is determined based on the first SINR, the modulation and coding scheme corresponding to the transmission symbol of the communication link, and the first correspondence.

4. The method according to claim 3, characterized in that, The step of generating a first correspondence based on different modulation and coding schemes, the fourth SINR, and the third scaling factor includes: Under different modulation and coding schemes, a first number of the fourth SINR and a first number of the third scaling factors are obtained, wherein the first number is determined based on the number of the second SINR and the number of TTIs of the preset detection reference signal SRS; For each modulation and coding scheme, the first number of fourth SINRs and the first number of third scaling factors are clustered to obtain the fifth SINR and fourth scaling factor corresponding to each modulation and coding scheme; The first correspondence is generated based on different modulation and coding schemes, the fifth SINR, and the fourth scaling factor.

5. The method according to claim 1, characterized in that, The step of performing fixed-point quantization on the first LLR according to the first scaling factor to obtain the second LLR includes: The third LLR is obtained based on the first scaling factor and the first LLR; The third LLR is shifted to obtain the fourth LLR; Peak clipping is performed on the fourth LLR to obtain the second LLR.

6. The method according to claim 1, characterized in that, The step of inputting the second LLR into the decoder and decoding the second LLR using the Low-Density Parity-Check (LDPC) decoding algorithm in a first order to obtain the decoded bit message output by the decoder includes: The second LLR is input into the decoder, and the first operation is performed in the decoder; If the first condition is met, the execution of the first operation shall be stopped; If the first condition is not met, update the first target LLR to the second target LLR obtained from the first check node, and return to the step of performing the first operation in the decoder; Based on the second target LLR obtained from the last execution of the first operation, the decoded bit message output by the decoder is obtained; The first operation includes: The first verification node obtains the second target LLR based on the first matrix value and the first target LLR; The first verification node sends the second target LLR to the first bit node; The first bit node updates its current stored LLR based on the second target LLR, thus obtaining the updated LLR stored in the first bit node; Wherein, the first verification node is a verification node in any layer of the multi-layer decoding structure; The first matrix value is the matrix value corresponding to the first check node and the first bit node in the check matrix, and the first bit node is the bit node in the decoding structure of the first check node. When the first verification node is a verification node in the last layer of the decoding structure, the first target LLR is the second LLR. When the first verification node is a verification node in any layer of the decoding structure other than the last layer, the first target LLR is the second target LLR obtained by the second verification node. The second verification node is the verification node adjacent to the first verification node in the multi-layer decoding structure according to the first order. When the first verification node is a first-level verification node, the updated LLR stored in the first bit node is the second target LLR obtained by performing the first operation; The first condition includes at least one of the following: The first operation has been performed a preset number of times; The second target LLR obtained by performing the first operation passes the corresponding verification equation.

7. The method according to claim 6, characterized in that, The first bit node updates its currently stored LLR based on the second target LLR to obtain the updated LLR stored in the first bit node, including: The first bit node updates its currently stored LLR based on the second target LLR, a preset first minimum sum, and a preset second minimum sum, to obtain the updated LLR stored in the first bit node.

8. An LDPC decoding device, characterized in that, include: The first processing module is used to determine a first scaling factor based on the first signal-to-interference-plus-noise ratio (SINR). The first scaling factor is used to process the first log-likelihood ratio (LLR), where the first LLR is a floating-point LLR and the first SINR is the SINR of the transmission symbol in the communication link. The second processing module is used to perform fixed-point quantization on the first LLR according to the first scaling factor to obtain the second LLR. The third processing module is used to input the second LLR into the decoder and decode the second LLR using the low-density parity-check code (LDPC) decoding algorithm in the first order to obtain the decoded bit message output by the decoder. The decoder includes a multi-layer decoding structure arranged in sequence, each layer of the decoding structure including a check node and at least one bit node connected to the check node; The first order is the reverse of the arrangement order of the multi-layer decoding structure.

9. An LDPC decoding device, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the LDPC decoding method as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that, The readable storage medium stores a program that, when executed by a processor, implements the LDPC decoding method as described in any one of claims 1 to 7.

11. A computer program product, characterized in that, It includes computer instructions that, when executed by a processor, implement the LDPC decoding method as described in any one of claims 1 to 7.

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