Multi-master-device-oriented global bandwidth scheduling and priority control method and system

Abstract

The invention discloses a multi-master-device-oriented global bandwidth scheduling and priority control method and system, and the method comprises the steps: forming a complete end-to-end scheduling system through a software marking mechanism, network-on-chip real-time monitoring, initiating end adaptive adjustment, transmission path adjustment and a master memory controller cooperation strategy; and dynamic management of multi-service flow access behaviors is realized. In the system, a software layer configures initial strategies for different data streams; the main equipment end dynamically adjusts the priority of the sent request based on the real-time load; the network-on-chip carries out secondary adjustment on the priority based on the congestion state of the transmission path; the main memory controller maps the request to different queues for execution according to the final priority; and the system feedback layer collects the overall performance state and feeds back the overall performance state to the software layer so as to dynamically update the strategy. According to the method, software and hardware collaborative and adaptive global bandwidth management is realized, and the overall performance and service quality of the complex system on chip are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of system-on-a-chip design, and in particular to a global bandwidth scheduling and priority control method and system for multiple master devices. Background Technology

[0002] As the scale of System-on-Chip (SoC) continues to expand, multi-core processors, heterogeneous accelerators, high-speed peripheral controllers, and various types of DMA modules work in parallel on the same chip. The bandwidth allocation mechanism of Network-on-Chip (NoC) and storage subsystem has become a key factor affecting system performance and power consumption.

[0003] Early SoCs often employed bandwidth allocation mechanisms based on fixed priorities, round-robin arbitration, or simple weights, which had limited adaptability to multi-service concurrent scenarios. Later, QoS bandwidth management mechanisms were introduced, assigning different priorities, weights, or burst lengths to different data streams. However, these largely relied on static configurations, making it difficult to provide consistently stable performance under complex real-time loads. In the area of ​​on-chip networking, much work has focused on topology optimization, cross-virtual channel isolation, burst control optimization, and buffer depth design. Support for end-to-end dynamic bandwidth scheduling across master devices is limited. Bandwidth management is typically performed only on a single node or local path, lacking a holistic view of the entire access path. Furthermore, the main memory controller's scheduling strategies often operate independently, failing to effectively link with the real-time status of the on-chip network, making it difficult to achieve true system-level closed-loop bandwidth management.

[0004] The rise of applications such as large-scale model inference chips, high-bandwidth video processing, and multi-channel concurrent memory access demands that SoC bandwidth scheduling possess real-time dynamics, global scheduling strategies, and software participation in bandwidth strategy definition to maintain controllable latency for critical services even under full load and high congestion scenarios. However, current technologies mostly focus only on the hardware arbitration algorithm itself, lacking coordination between software strategies and hardware adaptive mechanisms, as well as unified management of the initiating, transmitting, and storing ends, making it difficult to meet the above requirements.

[0005] In existing SoC systems, multi-master bandwidth scheduling and access priority control typically rely on hardware-side pre-defined arbitration algorithms, QoS fields, and burst control strategies. These include: arbitration methods based on fixed priority or round-robin mechanisms, QoS scheduling based on weighted round-robin or weighted bandwidth allocation, access control schemes utilizing AXI QoS fields, scheduling based on NoC internal virtual channels and flow control strategies, and multi-queue and priority domain scheduling techniques of the main memory controller. In practical applications, the bandwidth requirements and priorities of many tasks are determined by the operating system scheduler, driver layer, or upper-layer applications, involving information such as service type, task urgency, and latency requirements. Existing SoC technologies often fail to effectively transmit these task attributes to the hardware side, resulting in software-layer policies not being able to influence hardware arbitration in real time, and hardware being unable to distinguish different data flows based on task-level policies. Bandwidth control remains a local attribute at the hardware, protocol, or NoC layer, lacking cross-layer collaboration.

[0006] Therefore, existing technologies still need further research to improve their performance in sudden, multi-service concurrent environments. Summary of the Invention

[0007] The problem to be solved by this invention is to provide a global bandwidth scheduling and priority control method and system for multi-master devices. The system consists of a software marking mechanism, an on-chip network real-time monitoring module, an initiating end adaptive adjustment unit, a transmission path adjustment unit, and a main memory controller collaborative strategy to form a complete end-to-end scheduling system, thereby realizing dynamic management of multi-service flow access behavior.

[0008] This invention adopts the following technical solution: a global bandwidth scheduling and priority control method for multi-master devices, comprising the following steps:

[0009] Step 1, Software Policy Tagging and Configuration Interface: Through the software programmable configuration interface, task-level attributes, initial priorities, and allowed dynamic adjustment ranges are set for each data flow in the system. The set tag fields, together with the AXI request initiated by the master device, enter the hardware-side arbitrator to realize the binding of software layer business semantics and hardware layer bandwidth management.

[0010] Step 2, Real-time load detection on the master device: Deploy a buffer occupancy monitoring unit and an adaptive adjustment module on each master device interface to monitor the real-time status of the request queue inside the master device. Based on FIFO depth, queuing delay, and burst trend indicators, periodically and adaptively adjust the QoS value of the access transactions initiated by the master device to ensure that the load information of the initiating end affects the arbitration in real time.

[0011] Step 3, NoC Path Status Monitoring and Adjustment: Add a path status monitoring module to each routing node in the NoC to monitor the current channel buffer occupancy, congestion index between virtual channels, upstream and downstream link utilization, and back pressure status on the current routing path in real time. By introducing a transmission-end QoS adjuster, the access through this path is prioritized in real time to obtain the adjusted QoS value on the NoC, thereby achieving end-to-end bandwidth allocation.

[0012] Step 4, Main memory controller collaboration: Set up a DRAM controller and a write-back controller inside the main memory controller. Through the preset priority domain mapping relationship in the main memory controller, the adjusted QoS value is mapped to the corresponding DRAM controller queue for execution, so that the dynamic QoS adjustment on the NoC side continues to penetrate to the storage side.

[0013] Step 5: Participate in the feedback loop: Through the system-level performance feedback module, continuously collect real-time performance indicators from each link from the main device, NoC to the main memory controller, and feed them back to the software layer. The software can dynamically update the registers of the software programmable configuration interface in Step 1 based on the feedback information, forming a complete policy loop from software to hardware and back to software.

[0014] As a preferred embodiment, the software programmable configuration interface in step 1 includes:

[0015] The task attribute register is used to set the task type to which the data stream belongs;

[0016] The data stream priority flag register is used to set the initial priority value of the data stream;

[0017] The QoS range configuration register is used to set the upper and lower limits of the data flow priority that can be dynamically adjusted, the access rate limit, the burst length limit, and a flag indicating whether dynamic adjustment is allowed.

[0018] As a preferred embodiment, the Buffer occupancy monitoring unit in step 2 includes: a request FIFO depth counter, a waiting queue dwell time counter, a burst request accumulation counter, and a traffic trend predictor;

[0019] The buffer occupancy monitoring unit samples the access behavior of the master device periodically and transmits the status to the initiating adaptive adjustment module through the internal bus.

[0020] As a preferred embodiment, the adaptive adjustment module in step 2 performs priority dynamic adjustment according to the following rules:

[0021] When FIFO occupancy approaches the QRR limit, increase the QoS value of the current access.

[0022] When the dwell time exceeds the threshold, a temporary escalation mode is triggered according to the strategy given by the software.

[0023] As the load decreases, gradually restore the QoS to its initial or lowest value;

[0024] If the software has a critical task flag set, increase the priority and adjust the step size.

[0025] As a preferred approach, the adjustment results of the adaptive adjustment module are reflected in subsequent access requests by modifying the AXI QoS field.

[0026] As a preferred embodiment, the QoS regulator at the transmission end described in step 3, driven by changes in hardware state, performs real-time priority correction on accesses through this path, and the strategy includes:

[0027] Step 3.1, Path congestion-driven priority escalation; when the congestion level of a path exceeds the threshold, the priority of transactions from critical tasks is increased to allow them to pass through the bottleneck area as quickly as possible;

[0028] Step 3.2: Cross-virtual channel bandwidth reallocation; dynamically adjust the following based on virtual channel utilization: service ratio of different VCs, arbitration weight, channel occupancy time slice length, and QoS degradation mechanism under backpressure propagation.

[0029] As a preferred embodiment, the DRAM controller in step 4 includes multiple queues, and the adjusted QoS value is mapped to the DRAM controller queues; the main memory write-back controller is used to dynamically adjust the read-write switching threshold of the QoS value, temporarily improve the service priority of critical read transactions, and at the same time limit the burst write operation from crowding out the read operation bandwidth under high load.

[0030] As a preferred embodiment, the system-level performance feedback module described in step 5 includes the following registers or status interfaces: real-time bandwidth utilization of each master device, latency and congestion of each NoC path, priority queue depth of each DRAM controller, and QoS dynamic adjustment history.

[0031] As a preferred option, in step 5, the software performs the following based on the data from the system-level performance feedback module: task priority reconfiguration, dynamic update of bandwidth limit, marking of critical tasks, redefinition of QoS range, and online upgrade of flow control policy; and immediately applies the update results to the software programmable configuration interface to update the task attribute register, data flow priority marking register, and QoS range configuration register, thus forming a policy closed loop.

[0032] The present invention also provides a system-on-a-chip (SoC) for implementing the aforementioned method, comprising: multiple master devices, an on-chip network, and a main memory controller, and further comprising:

[0033] Software configuration layer: includes programmable software configuration interfaces, which configure parameters for each data stream in the system, and send the set tag fields together with the AXI request initiated by the master device into the hardware-side arbitrator to realize the binding of software layer business semantics and hardware layer bandwidth management;

[0034] Master device-side adjustment layer: A buffer occupancy monitoring unit and an adaptive adjustment module are set at each master device interface. The QoS value of the transaction to be sent is dynamically calculated and updated according to the real-time load of the master device, so as to realize adaptive adjustment at the initiating end.

[0035] Transmission path adjustment layer: Each on-chip network and each routing node are deployed with a path status monitoring module and a transmission end QoS adjuster. The QoS value of the transaction is adjusted again according to the transmission path status to achieve coordinated adjustment on the transmission path on the network side.

[0036] Storage-side coordination layer: A coordination scheduling module is set up inside the main memory controller to allocate requests to the corresponding priority queues according to the adjusted QoS values, thereby realizing storage-side mapping;

[0037] System Feedback Layer: The system collects performance status data of each part of the system through the system-level performance feedback module, and feeds it back to the software through registers or interrupts. The software evaluates the effectiveness of the current scheduling strategy and dynamically adjusts the parameters in the software configuration layer to achieve a complete policy closed loop from software to hardware and back to software.

[0038] As a preferred embodiment, in the master device-side adjustment layer, the buffer occupancy monitoring unit samples the access behavior of the master device periodically, and transmits the status to the initiating adaptive adjustment module through the internal bus. The adaptive adjustment module performs dynamic priority adjustment periodically according to preset rules, and reflects the adjustment result in subsequent access requests by modifying the AXI QoS field.

[0039] As a preferred embodiment, in the transmission path adjustment layer, the transmission end QoS adjuster is connected to the path status monitoring module to monitor in real time the current occupancy of the channel buffer of each path, the congestion index between virtual channels, the utilization rate of upstream and downstream links, and the back pressure status on the current routing path, and to perform real-time priority correction for access through the path.

[0040] As a preferred embodiment, the storage-side collaboration layer is pre-configured with a main memory priority domain mapping table and a bandwidth shaping unit, which maps the adjusted QoS values ​​to the corresponding DRAM controller queues for execution in real time.

[0041] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0042] 1. This invention constructs a cross-layer collaborative dynamic bandwidth scheduling system between the software layer, the initiator, the on-chip network, and the main memory controller. Compared with existing technical solutions that rely on static QoS, local arbitration, or independent storage scheduling, it can achieve periodic-level adaptive adjustment of access priorities, path-level congestion-aware adjustment, and dynamic mapping of main memory priority domains, thereby significantly improving the bandwidth utilization efficiency and real-time response capability of critical services in multi-master device concurrent scenarios.

[0043] 2. This invention, through a closed-loop feedback mechanism that combines software and hardware, not only solves the problems of static scheduling strategies, the separation of on-chip transmission and main memory scheduling, and the inability to transmit business semantics to hardware in traditional solutions, but also improves the stability of the system under high load and sudden pressure, making end-to-end access latency more controllable, bandwidth allocation more equitable, and architecture more reusable, thus having significant engineering application value. Attached Figure Description

[0044] Figure 1 This is a flowchart of the global bandwidth scheduling and priority control method for multiple master devices according to the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the application will be further described in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in this invention. All non-innovative embodiments based on these embodiments by other researchers in the art are within the protection scope of this invention. Furthermore, the step numbers in the embodiments of this invention are only set for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0046] Example 1

[0047] A global bandwidth scheduling and priority control method for multi-master devices is proposed. A complete end-to-end scheduling system is formed by software marking mechanism, on-chip network real-time monitoring module, initiator adaptive adjustment unit, transmission path adjustment unit and main memory controller collaborative strategy to realize dynamic management of multi-service flow access behavior.

[0048] To achieve the above objectives, this embodiment employs the following specific technical means, and the process is as follows: Figure 1 As shown.

[0049] Step 1: Software Policy Tagging and Configuration Interface

[0050] To enable the hardware to recognize the access levels of different tasks or data streams, this embodiment provides a set of programmable software interfaces, including:

[0051] The Task Attribute Register (TAR) is used to set the task type to which the data stream belongs;

[0052] The Flow Priority Tag Register (FPTR) is used to set the initial priority value;

[0053] The QoS Range Register (QRR) is used to set the allowed priority upper and lower limits, access rate upper limit, burst length limit, and whether dynamic adjustment is allowed within the lifetime.

[0054] During use, after full chip initialization, the system configures the initial attributes of tasks and data streams via software and removes the master device reset. The configured tag fields are then sent to the hardware-side arbitrator along with the AXI request initiated by the master device, enabling the hardware to differentiate based on task semantics, rather than simply relying on traditional transaction-level QoS fields.

[0055] Step 2: Real-time load monitoring on the master-side device

[0056] In this embodiment, a Master Buffer Occupancy Monitor (MBOM) is deployed on each master device interface (such as CPU, NPU, DMA). This unit includes:

[0057] Request FIFO depth counter, wait queue latency counter, burst request accumulation counter, and traffic trend predictor (estimate future pressure based on the slope of the past N periods).

[0058] Furthermore, MBOM samples the access behavior of the master device periodically and transmits the status to the initiating adaptive QoS controller (MAQC) via the internal bus.

[0059] MAQC dynamically adjusts execution priority according to the following rules:

[0060] When FIFO occupancy approaches the QRR limit, increase the QoS value of the current access.

[0061] When the dwell time exceeds the threshold, the "temporary upgrade" mode is triggered according to the strategy given by the software.

[0062] As the load decreases, gradually restore the QoS to its initial or lowest value;

[0063] If the software is set to a "critical task" flag, the priority adjustment step size will be larger.

[0064] During use, the master device performs real-time load monitoring. When congestion is detected, the master device makes dynamic adjustments and reports to the software sensing end. The software adjusts the initial value according to the scenario. At the same time, it sends memory access commands to the bus end. All adjustment results are reflected in subsequent access requests by modifying the AXI / QoS fields, ensuring that the load information of the initiating end affects the arbitration in real time.

[0065] Step 3: Monitoring and Adjustment of Transmission Path (NoC) Status

[0066] To achieve end-to-end bandwidth allocation, this embodiment adds a Path State Monitor (PSM) module to each routing node within the NoC to collect real-time operational data, including: current channel buffer occupancy, congestion index between virtual channels, upstream and downstream link utilization, and backpressure status on the current routing path.

[0067] Furthermore, based on the above information, this embodiment introduces a Network-Side Adaptive QoS Controller (NAQC) to perform real-time priority correction on accesses through this path.

[0068] Regulation strategies include:

[0069] 1. Path congestion-driven priority escalation: When the congestion level of a path exceeds a threshold, the priority of transactions from critical tasks is increased so that they can pass through the bottleneck area as soon as possible.

[0070] 2. Cross-virtual channel bandwidth reallocation, dynamically adjusted based on virtual channel utilization: service ratio of different VCs, arbitration weight, channel occupancy time slice length, and QoS degradation mechanism under backpressure propagation.

[0071] 3. When the backpressure link remains blocked for N consecutive cycles, in order to avoid long-term congestion, NAQC can temporarily downgrade low-priority transactions and reduce their admission rate.

[0072] All of the above mechanisms are driven by changes in hardware state, thus realizing the global adaptive capability of the transport layer.

[0073] In use, the bus receives memory access commands, monitors path congestion, performs dynamic bus adjustments when congestion occurs, and reports to the software. The software adjusts the initial value according to the scenario and applies back pressure to low-priority master devices when necessary. At the same time, it sends memory access commands to the memory.

[0074] Step 4: Main Memory Controller Coordination Mechanism

[0075] To achieve end-to-end scheduling, this embodiment works in conjunction with the multi-queue strategy within the main memory controller. The DRAM controller includes multiple queues such as LPR, HPR, and VPR (Variable Priority), with different queues having different access priorities.

[0076] Furthermore, a Memory Priority Mapping Table (MPMT) is provided to map the QoS values ​​on the NoC side to the DRAM controller queue:

[0077] When QoS ≥ T1, it is mapped to the HPR queue;

[0078] When T2 ≤ QoS < T1, it is mapped to the VPR queue;

[0079] When QoS < T2, it is mapped to the LPR queue;

[0080] T1 and T2 are the thresholds defined in the main memory priority field mapping table.

[0081] In addition, this embodiment also introduces a main memory-side bandwidth shaping unit (MBSU) to dynamically adjust the read / write switching threshold, temporarily increase the service priority of critical read transactions, and limit burst write operations from crowding out read operation bandwidth under high load.

[0082] When in use, the memory side performs priority queue allocation, and the memory executes commands according to priority. This mechanism ensures that the dynamic QoS adjustment on the NoC side can continuously penetrate to the storage side, so that the bandwidth policy forms a complete closed loop.

[0083] Step 5: Arbitration and Feedback Closed-Loop Mechanism

[0084] To achieve hardware and software synergy, this embodiment sets up a system performance feedback unit (SPFU) module, which provides corresponding registers or status interfaces, including: real-time bandwidth utilization of each master device, latency and congestion of each NoC path, priority queue depth of each DRAM controller, and QoS dynamic adjustment history.

[0085] Furthermore, the software can perform tasks based on SPFU data, including reconfiguring task priorities, dynamically updating bandwidth limits, marking critical tasks, redefining QoS ranges, and upgrading flow control policies online.

[0086] In particular, the software update results will immediately take effect in configuration registers such as TAR, FPTR, and QRR, forming a complete policy closed loop.

[0087] Through the above steps, the method of this embodiment can achieve the following:

[0088] (1) Software-configurable task-level flow attribute tagging: By introducing a mapping mechanism from task attributes to data flow attributes and then to hardware scheduling policies in the SoC, the software sets task-level attributes, initial priority and allowed dynamic adjustment range for each data flow through configuration registers (TAR / FPTR / QRR), thereby realizing the binding of service semantics and hardware bandwidth management.

[0089] (2) Real-time adaptive QoS adjustment structure (MAQC) on the main device: By deploying MBOM and MAQC structures inside the main device, the QoS value of transactions can be dynamically updated periodically based on indicators such as FIFO depth, queuing delay, and burst trend, so as to achieve adaptive adjustment and elastic limitation of access priority.

[0090] (3) On-chip Network Path State Driven Priority Secondary Adjustment (NAQC): By introducing path state monitoring (PSM) into each routing node of NoC, secondary adjustment of transaction QoS is achieved based on real-time buffer occupancy rate, congestion index, and back pressure status, which makes up for the limitation of adjusting bandwidth only from the initiating end.

[0091] (4) Programmable mapping of QoS to main memory priority domain: Through MPMT, the dynamic mapping rules of QoS to priority queues (HPR / VPR / LPR) are used to enable dynamic adjustment on the NoC side to penetrate into the DRAM controller and realize real-time linkage on the storage side.

[0092] (5) End-to-end closed-loop bandwidth scheduling and policy feedback: SPFU collects information such as bandwidth usage, NoC latency, and DRAM queue depth of each master device in real time, enabling the software to update the scheduling policy online and realize bidirectional closed-loop scheduling from software to hardware.

[0093] Example 2

[0094] A global bandwidth scheduling and priority control system for multiple master devices is proposed. The system runs on a SoC containing multiple master devices (such as CPU, GPU, DMA, etc.), on-chip network and main memory controller. The core includes: software configuration layer, master device adjustment layer, transmission path adjustment layer, storage coordination layer and system feedback layer.

[0095] At the software configuration layer, the operating system or driver software sets attribute labels, initial QoS values, allowed adjustment ranges, and other constraints for each data stream or task by writing configuration registers (such as TAR, FPTR, QRR). This information is then sent to the hardware scheduling pipeline with each transaction request.

[0096] At the master device-side adjustment layer, each master device interface is equipped with a buffer monitoring unit and an adaptive adjustment module. The monitoring unit continuously collects data such as the depth of the local request FIFO and the waiting time of requests in the queue. Based on this real-time data and the range configured by the software, the adaptive adjustment module dynamically calculates and updates the QoS value of the upcoming transaction according to a predetermined algorithm (e.g., if FIFO_Depth > threshold Th1, then output Q = min(Q_current + Δ, Q_max)).

[0097] At the transmission path conditioning layer, each routing node in the NoC is equipped with a path state monitoring module and a transmission-end QoS conditioner. The monitoring module collects information such as downstream buffer occupancy (Buf_Occ) and the local node's congestion index (Congestion_Index). Based on this information, the conditioner fine-tunes the QoS value of transactions flowing through the node (e.g., if Congestion_Index > threshold Th2, the QoS of that critical transaction is temporarily increased by one level) to achieve rapid clearing of congestion hotspots and global bandwidth balancing.

[0098] At the storage-side coordination layer, the main memory controller contains a coordination scheduling module, which includes a main memory priority domain mapping table and a bandwidth shaping unit. As a preferred approach, a mapping relationship is defined between QoS values ​​and specific hardware queues (such as HPR, VPR, LPR) (e.g., QoS > T1 maps to HPR). After the adjustments in the first two levels, the final QoS value of a transaction is allocated to the corresponding queue for execution by looking up the table. The bandwidth shaping unit can further implement more refined scheduling strategies based on information such as the depth and read / write ratio of each queue, such as prioritizing read requests in the HPR queue.

[0099] At the system feedback layer, the system-level performance feedback module collects performance counter data from the aforementioned layers, such as bandwidth utilization of each master device, latency of the NoC critical path, and average depth of each DRAM queue, and reports this data to the software via registers or interrupts. Based on this global view, the software can evaluate the effectiveness of the current scheduling strategy and dynamically adjust parameters in the software configuration layer, such as modifying the QoS limit of a critical task or adjusting bandwidth allocation weights, thereby forming a continuously optimizing closed-loop control system.

[0100] In this embodiment, a combination of cross-layer software tagging and hardware scheduling is used. The software sets task attributes through registers and passes these attributes to the arbitrator, NoC, and storage controller along with the transaction, enabling the multi-layer hardware to recognize and perform bandwidth scheduling accordingly.

[0101] Furthermore, in this embodiment, the master device adopts a real-time feedback QoS update logic, which adjusts the QoS hardware structure based on dynamic indicators such as queue depth, latency, and burst behavior within the master device. This includes: MBOM (load monitoring structure), MAQC (QoS dynamic adjustment structure), and dynamic constraints on the upper and lower limits of QoS.

[0102] Furthermore, in this embodiment, the state-driven adjustment mechanism on the NoC routing path is a hardware module and algorithm logic that performs secondary adjustments to the transaction QoS based on the NoC's internal path state (buffer occupancy, congestion, VC utilization, backpressure signal).

[0103] Furthermore, in this embodiment, a dynamic mapping from QoS values ​​to DRAM multi-queue priority domains is used, a mapping table structure and mapping algorithm from QoS to HPR / VPR / LPR are preset, and the DRAM controller queue is dynamically selected based on this mapping.

[0104] Furthermore, in this embodiment, the storage end participates in bandwidth shaping, and the MBSU adopts a hardware strategy to adjust the burst length, priority, and read / write ratio based on DRAM queue depth, read / write switching cost.

[0105] Furthermore, in this embodiment, a system-level closed-loop feedback is used to collect system performance indicators through SPFU and update the bandwidth strategy by software, forming a closed-loop bandwidth control system across the master device, NoC, and main memory controller.

[0106] Furthermore, in this embodiment, through the collaboration of various modules, a complete end-to-end bandwidth management process is formed, consisting of software tagging → master device adjustment → NoC adjustment → storage-side adjustment → software feedback, thereby achieving end-to-end dynamic scheduling.

[0107] In summary, this invention, through a multi-level, distributed real-time monitoring and adjustment mechanism, combined with a software-definable policy interface, achieves global, dynamic, and closed-loop bandwidth management from software task attributes to underlying hardware scheduling resources, significantly improving the overall performance and service quality of complex SoCs in multi-master device and multi-service concurrent scenarios.

[0108] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A global bandwidth scheduling and priority control method for multi-master devices, characterized in that, include: Step 1, Software Policy Tagging and Configuration Interface: Through the software programmable configuration interface, task-level attributes, initial priorities, and allowed dynamic adjustment ranges are set for each data flow in the system. The set tag fields, together with the AXI request initiated by the master device, enter the hardware-side arbitrator to realize the binding of software layer business semantics and hardware layer bandwidth management. Step 2, Real-time load detection on the master device: Deploy a buffer occupancy monitoring unit and an adaptive adjustment module on each master device interface to monitor the real-time status of the request queue inside the master device. Based on FIFO depth, queuing delay, and burst trend indicators, periodically and adaptively adjust the QoS value of the access transactions initiated by the master device to ensure that the load information of the initiating end affects the arbitration in real time. Step 3, NoC Path Status Monitoring and Adjustment: Add a path status monitoring module to each routing node in the NoC to monitor the current channel buffer occupancy, congestion index between virtual channels, upstream and downstream link utilization, and back pressure status on the current routing path in real time. By introducing a transmission-end QoS adjuster, the access through this path is prioritized in real time to obtain the adjusted QoS value on the NoC, thereby achieving end-to-end bandwidth allocation. Step 4, Main memory controller collaboration: Set up a DRAM controller and a write-back controller inside the main memory controller. Through the preset priority domain mapping relationship in the main memory controller, the adjusted QoS value is mapped to the corresponding DRAM controller queue for execution, so that the dynamic QoS adjustment on the NoC side continues to penetrate to the storage side. Step 5: Participate in the feedback loop: Through the system-level performance feedback module, continuously collect real-time performance indicators from each link from the main device, NoC to the main memory controller, and feed them back to the software layer. The software can dynamically update the software programmable configuration interface in Step 1 based on the feedback information, forming a complete policy loop from software to hardware and back to software.

2. The global bandwidth scheduling and priority control method for multi-master devices according to claim 1, characterized in that, The software programmable configuration interface mentioned in step 1 includes: The task attribute register is used to set the task type to which the data stream belongs; The data stream priority flag register is used to set the initial priority value of the data stream; The QoS range configuration register is used to set the upper and lower limits of the data flow priority that can be dynamically adjusted, the access rate limit, the burst length limit, and a flag indicating whether dynamic adjustment is allowed.

3. The global bandwidth scheduling and priority control method for multi-master devices according to claim 1, characterized in that, The buffer occupancy monitoring unit described in step 2 includes: a request FIFO depth counter, a waiting queue latency counter, a burst request accumulation counter, and a traffic trend predictor; The buffer occupancy monitoring unit samples the access behavior of the master device periodically and transmits the status to the initiating adaptive adjustment module through the internal bus.

4. The global bandwidth scheduling and priority control method for multi-master devices according to claim 3, characterized in that, The adaptive adjustment module described in step 2 performs dynamic priority adjustment according to the following rules: When FIFO occupancy approaches the QRR limit, the QoS value of the current access will be automatically increased within the software limits. When the dwell time exceeds the threshold, a temporary escalation mode is triggered according to the strategy given by the software. As the load decreases, gradually restore the QoS to its initial or lowest value; If the software has a critical task flag set, increase the priority and adjust the step size accordingly; The result of the dynamic priority adjustment is reflected in subsequent access requests by modifying the AXI / QoS field.

5. The global bandwidth scheduling and priority control method for multi-master devices according to claim 1, characterized in that, The QoS adjuster at the transmission end, as described in step 3, is driven by changes in hardware state to perform real-time priority correction on accesses through this path. The strategies include: Step 3.1, Path congestion-driven priority escalation; when the congestion level of a path exceeds the threshold, the priority of transactions from critical tasks is increased to allow them to pass through the bottleneck area as quickly as possible; Step 3.2: Cross-virtual channel bandwidth reallocation; dynamically adjust the following based on virtual channel utilization: service ratio of different VCs, arbitration weight, channel occupancy time slice length, and QoS degradation mechanism under backpressure propagation.

6. The global bandwidth scheduling and priority control method for multi-master devices according to claim 1, characterized in that, Step 4 describes a DRAM controller containing multiple queues. The adjusted QoS values ​​are mapped to these queues, as detailed below: When QoS ≥ T1, it is mapped to the HPR queue; When T2 ≤ QoS < T1, it is mapped to the VPR queue; When QoS < T2, it is mapped to the LPR queue; T1 and T2 are the thresholds defined in the main memory priority field mapping table.

7. The global bandwidth scheduling and priority control method for multi-master devices according to claim 6, characterized in that, The main memory write-back controller described in step 4 is used to dynamically adjust the read-write switching threshold for QoS values, temporarily increase the service priority of critical read transactions, and at the same time limit the surge of write operations from crowding out read operation bandwidth under high load.

8. The global bandwidth scheduling and priority control method for multi-master devices according to claim 1, characterized in that, The system-level performance feedback module described in step 5 includes the following registers or status interfaces: real-time bandwidth utilization of each master device, latency and congestion of each NoC path, priority queue depth of each DRAM controller, and QoS dynamic adjustment history. Based on the data from the system-level performance feedback module, the software performs the following actions: task priority reconfiguration, dynamic update of bandwidth limits, marking of critical tasks, redefinition of QoS range, and online upgrade of flow control policies. The updated results are immediately applied to the software programmable configuration interface to update the task attribute register, data flow priority flag register, and QoS range configuration register, forming a policy closed loop.

9. A system-on-a-chip for implementing the method of any one of claims 1 to 8, comprising: Multiple master devices, on-chip network and main memory controller, characterized in that it further includes: Software configuration layer: includes programmable software configuration interfaces, which configure parameters for each data stream in the system, and send the set tag fields together with the AXI request initiated by the master device into the hardware-side arbitrator to realize the binding of software layer business semantics and hardware layer bandwidth management; Master device-side adjustment layer: A buffer occupancy monitoring unit and an adaptive adjustment module are set at each master device interface. The QoS value of the transaction to be sent is dynamically calculated and updated according to the real-time load of the master device, so as to realize adaptive adjustment at the initiating end. Transmission path adjustment layer: Each on-chip network and each routing node are deployed with a path status monitoring module and a transmission end QoS adjuster. The QoS value of the transaction is adjusted again according to the transmission path status to achieve coordinated adjustment on the transmission path on the network side. Storage-side coordination layer: A coordination scheduling module is set up inside the main memory controller to allocate requests to the corresponding priority queues according to the adjusted QoS values, thereby realizing storage-side mapping; System Feedback Layer: The system collects performance status data of each part of the system through the system-level performance feedback module, and feeds it back to the software through registers or interrupts. The software evaluates the effectiveness of the current scheduling strategy and dynamically adjusts the parameters in the software configuration layer to achieve a complete policy closed loop from software to hardware and back to software.

10. The system-on-a-chip according to claim 9, characterized in that: In the master device-side adjustment layer, the buffer occupancy monitoring unit periodically samples the access behavior of the master device and transmits the status to the initiating adaptive adjustment module through the internal bus. The adaptive adjustment module periodically performs priority dynamic adjustment according to preset rules and reflects the adjustment result in subsequent access requests by modifying the AXI QoS field. In the transmission path adjustment layer, the transmission end QoS adjuster is connected to the path status monitoring module to monitor in real time the current occupancy of the channel buffer of each path, the congestion index between virtual channels, the utilization of upstream and downstream links, and the back pressure status on the current routing path, and to perform real-time priority correction for access through the path. The storage-side collaboration layer is pre-configured with a main memory priority domain mapping table and a bandwidth shaping unit, which maps the adjusted QoS values ​​to the corresponding DRAM controller queues for execution in real time.

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