Chip packaging module structure and electronic product

Abstract

The invention discloses a chip packaging module structure and an electronic product, and relates to the technical field of chip packaging, the chip packaging module structure comprises a PCB, an insulating substrate, a first radiator and a second radiator; the insulation substrate is arranged on the PCB, the insulation substrate is provided with a first side and a second side, the insulation substrate is provided with a first chip in an integrated mode, the first chip is located on the second side of the insulation substrate, the insulation substrate is provided with a plurality of via holes penetrating through the first side and the second side, metal is arranged in each via hole, at least part of the via holes are conductive holes, and the first chip is arranged on the first side of the insulation substrate. The metal in the conductive hole is used as a part of an electric connection structure between the PCB and the plurality of chips; the first radiator is in thermal conduction connection with the first chip; the second radiator is arranged on the other side of the PCB, and a longitudinal heat conduction structure is formed between the second radiator and the first chip, so that the second radiator is in heat conduction connection with the first chip; the technical scheme provided by the invention aims to improve the heat dissipation efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip packaging module structure and electronic product. Background Technology

[0002] With the ever-increasing demands for bandwidth and computing power from data centers and high-speed communication systems, traditional optical modules, due to their limited communication speed and high power consumption of digital signal processors, are struggling to meet the requirements for high integration and low latency. Therefore, the industry is actively developing optoelectronic co-packaging technology, especially silicon photonics co-packaging, which integrates high-power ASIC chips (Application-Specific Integrated Circuits) with temperature-sensitive photonic and electronic chips on one or both sides of an insulating substrate, significantly improving the module's integration density and communication speed.

[0003] However, high integration also brings severe thermal management challenges. ASIC chips, as the main heat source, can consume over 300W, and the heat generated can easily be conducted to nearby photonic chips through the package. Since photonic chips are extremely sensitive to temperature fluctuations, thermal crosstalk can lead to performance degradation or even failure, severely restricting the practical application of chip packaging module structures.

[0004] In the existing technology, heat dissipation for high-power chips mainly relies on single-sided liquid cooling technology, which conducts heat through contact between the cold plate and the upper surface of the chip. However, as chip power consumption continues to rise, single-sided heat dissipation is no longer able to effectively dissipate huge amounts of heat due to the limited contact area, and there is a significant risk of thermal failure.

[0005] Therefore, a solution to improve heat dissipation is urgently needed. Summary of the Invention

[0006] The main objective of this invention is to propose a chip packaging module structure and electronic product that aims to improve heat dissipation efficiency.

[0007] To achieve the above objectives, the chip packaging module structure proposed in this invention includes: PCB board; An insulating substrate is disposed on one side of the PCB board. The insulating substrate has a first side facing the PCB board and a second side facing away from the PCB board. The insulating substrate integrates a plurality of chips, including a first chip located on the second side of the insulating substrate. The insulating substrate is provided with a plurality of vias penetrating the first side and the second side. Each via contains metal, and at least a portion of the vias are conductive vias. The metal in the conductive vias is used as part of the electrical connection structure between the PCB board and the plurality of chips. A first heat sink is disposed on the side of the first chip facing away from the insulating substrate and is thermally connected to the first chip; and, The second heat sink is located on the other side of the PCB board, and a vertical heat conduction structure is formed between the second heat sink and the first chip to make the second heat sink and the first chip thermally connected. The vertical heat conduction structure includes metal disposed in the via.

[0008] In one embodiment, the plurality of chips further includes a second chip: The power of the first chip is greater than the power of the second chip; and / or, The first chip includes an ASIC chip, and the second chip includes at least one of an EIC chip and a PIC chip.

[0009] In one embodiment, the second chip is disposed on the second side of the insulating substrate, and a thermoelectric cooler is disposed between the second chip disposed on the second side of the insulating substrate and the first heat sink. The cold end of the thermoelectric cooler is thermally connected to the corresponding second chip, and the hot end of the thermoelectric cooler is thermally connected to the first heat sink.

[0010] In one embodiment, a thermal interface material is provided between the chip disposed on the second side of the insulating substrate and the first heat sink.

[0011] In one embodiment, the first heat sink is a liquid-cooled heat sink; and / or, The second heat sink is a liquid-cooled heat sink.

[0012] In one embodiment, the plurality of vias further includes heat dissipation holes, wherein the metal within the heat dissipation holes is used to conduct heat from the second side of the insulating substrate to the first side; and / or, An underfill adhesive is provided between the plurality of chips and the insulating substrate, and an underfill adhesive is provided between the PCB board and the insulating substrate.

[0013] In one embodiment, solder balls are disposed between the metal of the conductive hole and the PCB board, the solder balls serving as at least part of the electrical connection structure and as part of the longitudinal heat-conducting structure.

[0014] In one embodiment, the longitudinal heat-conducting structure further includes a heat-conducting portion embedded in the PCB board, the heat-conducting portion being part of the longitudinal heat-conducting structure.

[0015] In one embodiment, the heat-conducting portion includes a metal block embedded within the PCB board; and / or, The heat-conducting part is provided corresponding to the first chip.

[0016] The present invention also proposes an electronic product comprising the above-described chip packaging module structure, wherein the chip packaging module structure comprises: PCB board; An insulating substrate is disposed on one side of the PCB board. The insulating substrate has a first side facing the PCB board and a second side facing away from the PCB board. The insulating substrate integrates a plurality of chips, including a first chip located on the second side of the insulating substrate. The insulating substrate is provided with a plurality of vias penetrating the first side and the second side. Each via contains metal, and at least a portion of the vias are conductive vias. The metal in the conductive vias is used as part of the electrical connection structure between the PCB board and the plurality of chips. A first heat sink is disposed on the side of the first chip facing away from the insulating substrate and is thermally connected to the first chip; and, The second heat sink is located on the other side of the PCB board, and a vertical heat conduction structure is formed between the second heat sink and the first chip to make the second heat sink and the first chip thermally connected. The vertical heat conduction structure includes metal disposed in the via.

[0017] The technical solution of this invention improves space utilization and reduces the area occupied by the packaging module on the PCB board by integrating and connecting multiple chips using an insulating substrate. A vertical heat-conducting structure is employed to transfer the heat generated by the first chip through metal within vias to a second heat sink on the other side of the PCB board. This, combined with the first heat sink's cooling of the side of the first chip facing away from the insulating substrate, achieves bidirectional heat dissipation. Specifically, during operation, part of the heat generated by the first chip is directly conducted to the first heat sink, which is thermally connected to it, while the other part is transferred through the vertical heat-conducting path of metal within the vias on the insulating substrate, across the PCB board, to the second heat sink, thus forming an efficient heat dissipation channel from the chip to the heat sinks on both sides. This design effectively improves the heat dissipation efficiency of the chip packaging module, avoids the problem of excessively high chip temperatures caused by insufficient heat dissipation capacity of a single heat sink, and helps ensure the stability and reliability of the first chip and even the entire module under long-term high-load operation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1This is a schematic diagram of an embodiment of the chip packaging module structure provided by the present invention; Figure 2 for Figure 1 A magnified view of a portion of the ASIC chip; Figure 3 This is a schematic diagram of another embodiment of the chip packaging module structure provided by the present invention.

[0020] Explanation of icon numbers: 1. First radiator; 2. Insulating substrate; 21. Via; 211. Conductive hole; 212. Heat dissipation hole; 22. Metal; 23. Rewiring layer; 3. PIC chip; 4. ASIC chip; 5. Semiconductor cooling chip; 6. Fiber optic array; 7. First fixing bolt; 8. Fiber optic cable; 9. Thermal interface material; 10. Fiber optic array support; 11. EIC chip; 12. PCB board; 121. Thermal conductive part; 13. Copper pillar solder joint; 14. Second radiator; 15. Solder ball; 16. Second fixing bolt; 17. Bottom filler glue.

[0021] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0024] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0025] With the ever-increasing demands for bandwidth and computing power from data centers and high-speed communication systems, traditional optical modules, due to their limited communication speed and high power consumption of digital signal processors (DSPs), are struggling to meet the requirements for high integration and low latency. Therefore, the industry is actively developing optoelectronic co-packaging technology, especially silicon photonics co-packaging, which integrates high-power ASIC chips (Application-Specific Integrated Circuits) with temperature-sensitive photonic and electronic chips on one or both sides of an insulating substrate, significantly improving the module's integration density and communication speed.

[0026] However, high integration also brings severe thermal management challenges. ASIC chips, as the main heat source, can consume over 300W, and the heat generated can easily be conducted to nearby photonic chips through the package. Since photonic chips are extremely sensitive to temperature fluctuations, thermal crosstalk can lead to performance degradation or even failure, severely restricting the practical application of chip packaging module structures.

[0027] In the existing technology, heat dissipation for high-power chips mainly relies on single-sided liquid cooling technology, which conducts heat through contact between the cold plate and the upper surface of the chip. However, as chip power consumption continues to rise, single-sided heat dissipation is no longer able to effectively dissipate huge amounts of heat due to the limited contact area, and there is a significant risk of thermal failure.

[0028] Therefore, a solution to improve heat dissipation is urgently needed.

[0029] To address the aforementioned problems, this invention proposes a chip packaging module structure.

[0030] Please see Figure 1 , Figure 2 In one embodiment of the present invention, the chip packaging module structure includes: a PCB board 12, an insulating substrate 2, a first heat sink 1, and a second heat sink 14.

[0031] An insulating substrate 2 is disposed on one side of the PCB board 12. The insulating substrate 2 has a first side facing the PCB board 12 and a second side facing away from the PCB board 12. The insulating substrate 2 integrates a plurality of chips, including a first chip located on the second side of the insulating substrate 2. The insulating substrate 2 is provided with a plurality of vias 21 penetrating the first and second sides. Each via 21 contains metal 22. At least a portion of the vias 21 are conductive vias 211. The metal 22 in the conductive vias 211 serves as part of the electrical connection structure between the PCB board 12 and the plurality of chips. A first heat sink 1 is disposed on the side of the first chip facing away from the insulating substrate 2 and is thermally connected to the first chip. A second heat sink 14 is disposed on the other side of the PCB board 12, and a longitudinal thermal conductive structure is formed between the second heat sink 14 and the first chip to enable thermal conductivity between the second heat sink 14 and the first chip. The longitudinal thermal conductive structure includes metal 22 disposed in the vias 21.

[0032] The technical solution of this invention improves space utilization and reduces the area occupied by the packaging module on the PCB board 12 by integrating and connecting multiple chips using an insulating substrate 2. A vertical heat conduction structure is employed to transfer the heat generated by the first chip through the metal 22 within the via 21 to the second heat sink 14 on the other side of the PCB board 12. This, combined with the first heat sink 1's heat dissipation on the side of the first chip facing away from the insulating substrate 2, achieves bidirectional heat dissipation. Specifically, part of the heat generated by the first chip during operation is directly conducted to the first heat sink 1, which is thermally connected to it, for heat dissipation. The other part is transferred through the vertical heat conduction path of the metal 22 within the via 21 on the insulating substrate 2, via the PCB board 12, to the second heat sink 14, thus forming an efficient heat dissipation channel from the chip to the heat sinks on both sides. This design effectively improves the heat dissipation efficiency of the chip packaging module, avoids the problem of excessively high chip temperature caused by insufficient heat dissipation capacity of a single heat sink, and helps ensure the stability and reliability of the first chip and even the entire module under long-term high-load operation.

[0033] Meanwhile, the metal 22 inside the conductive hole 211 in the via 21 serves as both part of the electrical connection structure between the PCB board 12 and multiple chips and as a medium for vertical heat conduction, making the structural design more compact. While achieving the transfer of chip heat to the PCB board 12 and heat dissipation through the second heat sink 14, it does not add too much structural complexity or space occupation.

[0034] In the chip packaging module structure, the PCB board 12, the insulating substrate 2, and the first chip are stacked sequentially. The via 21 forms a vertical connection path between the PCB board 12 and the first chip, thereby reducing the length of the electrical connection path between the PCB board 12 and the first chip, providing conditions for efficient heat conduction and electrical conductivity. The electrical connection structure includes, but is not limited to, the metal 22 inside the conductive hole 211, the wire, and the solder ball 15.

[0035] Multiple chips can be evenly disposed on the second side of the insulating substrate 2. When the space on the PCB board 12 is relatively sufficient, multiple chips can be partially disposed on the side of the PCB board 12 close to the insulating substrate 2. Multiple chips can also be disposed on the first and second sides of the insulating substrate 2 at the same time to improve the chip space utilization.

[0036] The insulating substrate 2 and the second heat sink 14 are located on both sides of the PCB board 12. The material of the insulating substrate 2 is not limited; it can be glass, silicon (semiconductor), ceramic, or other materials with insulating properties. These materials are generally more resistant to warping than silicon, have better thermal stability, and provide stable high-frequency signals, making them excellent materials for high-frequency optical communication. The first chip is preferably the chip with the highest heat generation among multiple chips; it can be one chip or multiple chips. The first chip is located on the side of the insulating substrate 2 away from the PCB board 12, which facilitates connection to the first heat sink 1 and reduces the impact of the first chip's heat on the PCB board 12. The via 21 can be entirely or partially used as a conductive via 211. The material of the metal 22 inside the conductive via 211 is not limited; it can be copper, gold, or a conductive alloy, prioritizing conductivity. Materials with good electrical and thermal conductivity and easy vertical filling, such as copper, are preferred. The via 21 used as a vertical heat-conducting structure can be a through-hole or a blind via. The via 21 used for the longitudinal heat conduction structure can include conductive holes 211 or via 21 other than conductive holes 211, i.e., heat dissipation holes 212. The downward heat dissipation channel of the longitudinal heat conduction structure is mainly formed by the metal 22 in the via 21 in the insulating substrate, through the solder balls 15 or the bottom filler 17 between the insulating substrate 2 and the PCB board 12, and then through the PCB board 12 to transfer heat to the second heat sink 14. The specific structure of the first heat sink 1 and the second heat sink 14 is not limited, and is based on meeting the heat dissipation requirements, and is usually a liquid-cooled heat sink.

[0037] In one embodiment of the present invention, the plurality of chips further includes a second chip: the power of the first chip is greater than the power of the second chip; in another embodiment, the first chip includes an ASIC chip 4, and the second chip includes at least one of an EIC chip 11 and a PIC chip 3. Either of the above two embodiments may be present, or both may be present simultaneously.

[0038] The second chip can be one or more chips. The second chip has lower power and generates less heat than the first chip. It can be thermally connected to the first heatsink 1 as needed, prioritizing the first heatsink 1 for cooling the primary heat source, the first chip. The ASIC chip 4, as a dedicated integrated circuit, has higher power and generates more heat compared to the EIC chip 11 and PIC chip 3. The first heatsink 1 is used to thermally connect the ASIC chip 4 to improve the overall cooling effect of the packaged module. The specific models of the multiple chips are not limited; in practical implementation, they are mainly switch chips.

[0039] When the first chip and the second chip are arranged on the insulating substrate 2, a certain heat dissipation gap can be reserved between them to avoid the heat from accumulating and affecting the heat dissipation efficiency. In electronic product applications, devices containing the above-mentioned chip packaging module structure can further improve the overall heat dissipation performance by reasonably arranging the positions of the first heat sink 1 and the second heat sink 14. For example, the first heat sink 1 can be placed near the ventilation holes of the device casing to enhance heat dissipation by utilizing natural wind convection; the second heat sink 14 can be placed in contact with the metal frame 22 inside the device to disperse heat to the entire device casing through the frame, achieving large-area heat dissipation.

[0040] Please see Figure 3 In one embodiment of the present invention, the second chip is disposed on the second side of the insulating substrate 2, and a semiconductor cooling chip 5 is disposed between the second chip disposed on the second side of the insulating substrate 2 and the first heat sink 1. The cold end of the semiconductor cooling chip 5 is thermally connected to the corresponding second chip, and the hot end of the semiconductor cooling chip 5 is thermally connected to the first heat sink 1.

[0041] The second chip can be entirely or partially located on the second side of the insulating substrate 2. By adding a thermoelectric cooler 5 between the second chip and the first heat sink 1, active and efficient heat dissipation can be achieved using the Peltier effect. Specifically, when the thermoelectric cooler 5 is connected to a DC power supply, its cold end rapidly absorbs the heat generated by the second chip, causing the operating temperature of the second chip to drop rapidly. The hot end then transfers the absorbed heat to the first heat sink 1, which dissipates the heat. This structural design is particularly suitable for second chips that are temperature-sensitive or have high heat generation power, such as the PIC chip 3, and can effectively solve the problem of insufficient heat dissipation capacity of traditional passive heat dissipation methods in high power density scenarios. At the same time, the introduction of the thermoelectric cooler 5 makes the temperature control of the second chip more precise. By adjusting its operating current or voltage, the cooling capacity can be dynamically adjusted according to the actual heat generation of the second chip, avoiding the impact of excessive temperature fluctuations on the chip's performance stability. In addition, the thickness of the thermoelectric cooler 5 is usually small, which does not significantly increase the overall thickness of the chip packaging module, helping to meet the design requirements of thinner and lighter electronic products. In practical applications, the interface thermal resistance can be further reduced by applying high thermal conductivity grease between the semiconductor cooling chip 5 and the second chip, or by applying high thermal conductivity grease between the semiconductor cooling chip 5 and the first heat sink 1, or by adding an indium thermal pad, so as to maximize the heat transfer efficiency between the cold end and the hot end.

[0042] In practice, the second chip has low heat, and the heat of the second chip located on the side of the insulating substrate 2 close to the PCB board 12 can be directly conducted to the second heat sink 14 through the bottom filler adhesive 17 via the PCB board 12, without the need for an additional independent heat dissipation structure.

[0043] In one embodiment of the present invention, a thermal interface material 9 is provided between the chip disposed on the second side of the insulating substrate 2 and the first heat sink 1.

[0044] The thermal interface material 9 effectively fills the tiny gap between the chip and the first heat sink 1, reducing the thermal resistance at the contact surface and further improving the efficiency of heat transfer from the chip to the first heat sink 1. Specifically, the thermal interface material 9 can be common thermal interface materials such as high thermal conductivity grease, thermal gel, or thermal pads. High thermal conductivity grease has good flowability and filling properties, allowing it to adhere tightly to the surfaces of the chip and the heat sink, forming an efficient heat conduction path. Thermal gel combines viscosity and elasticity, adapting to different assembly gaps and maintaining stable thermal conductivity during use. Thermal pads have a certain thickness and hardness, providing good thermal conductivity while also buffering and protecting the chip. By selecting appropriate thermal interface material 9, its thickness, and application method, it can be ensured that the heat generated by the chip can be quickly and stably transferred to the first heat sink 1, thereby ensuring stable chip operation under suitable temperature conditions.

[0045] In one embodiment of the present invention, the first heat sink 1 is a liquid-cooled heat sink; in another embodiment, the second heat sink 14 is a liquid-cooled heat sink. Either of the above two embodiments may be used, or both may be used simultaneously.

[0046] When the first heat sink 1 and / or the second heat sink 14 are liquid-cooled heat sinks, they are equipped with internal channels for coolant flow. The coolant circulates within these channels, efficiently removing heat transferred from the chip or PCB board 12. This liquid-cooled heat sink can be connected to an external cooling circulation system to achieve continuous cooling and recycling of the coolant, thus ensuring a long-term stable heat dissipation effect. The selection of the thermal interface material 9 between the liquid-cooled heat sink and the chip or PCB board 12 must fully consider the flatness of the bottom surface of the liquid-cooled heat sink and the assembly pressure to ensure unobstructed heat transfer paths. If both embodiments exist simultaneously, i.e., both the first heat sink 1 and the second heat sink 14 are liquid-cooled heat sinks, a dual liquid-cooled heat dissipation structure is formed. This structure can handle the large amount of heat generated by the chip under high load. Through the efficient collaboration of the two-stage liquid cooling, heat is dissipated from both sides of the chip simultaneously, keeping the chip temperature at an extremely low level and providing strong support for the chip's maximum performance.

[0047] In one embodiment of the present invention, the plurality of vias 21 further include heat dissipation holes 212, wherein the metal 22 within the heat dissipation holes 212 is used to conduct heat from the second side of the insulating substrate 2 to the first side; in another embodiment of the present invention, an underfill adhesive 17 is disposed between the plurality of chips and the insulating substrate 2, and an underfill adhesive 17 is disposed between the PCB board 12 and the insulating substrate 2. Either of the above two embodiments may be present, or both may be present simultaneously.

[0048] The metal 22 inside the heat dissipation hole 212 can be made of copper or gold, which have high thermal conductivity. The heat dissipation hole 212, formed by precision machining such as laser-induced etching on the insulating substrate 2, allows the metal 22 to directly penetrate both sides of the substrate through electroplating or other methods. This rapidly and effectively conducts heat that was originally concentrated on the second side of the insulating substrate 2, i.e., the side closer to the chip, to the first side, i.e., the side closer to the PCB board 12 and the second heat sink 14, thereby improving heat dissipation efficiency. This design further optimizes the overall heat dissipation path of the chip packaging module, allowing heat to be dissipated not only through the first heat sink 1 and conducted through the metal 22 inside the conductive hole 211, but also aided by the metal 22 inside the heat dissipation hole 212 of the insulating substrate 2 itself, forming a more three-dimensional and efficient heat dissipation network. This further improves the heat dissipation reliability of the chip packaging module under long-term, high-power operation scenarios, ensuring continuous and stable chip operation.

[0049] In one embodiment, an underfill adhesive 17 is provided between the chip and the insulating substrate 2, and between the insulating substrate 2 and the PCB board 12, to improve installation stability and structural reliability. This underfill adhesive 17 is typically made of a high-strength composite material with certain thermal conductivity, such as epoxy resin. It has good flowability and filling capacity, allowing it to fully penetrate the tiny gaps between the chip and the insulating substrate 2, and between the PCB board 12 and the insulating substrate 2, through capillary action. After curing, it forms a strong support and connection, thereby enhancing mechanical fixation and helping to reduce interfacial thermal resistance. Specifically, during assembly, the underfill adhesive 17 flows into the gaps in a liquid state and, after curing, forms a solid and dense filling layer, enabling heat to be effectively transferred from the chip to the insulating substrate 2. Heat then passes through the metal 22 within the through-holes 21 of the insulating substrate 2, and is subsequently transferred from the insulating substrate 2 to the PCB board 12 or other heat dissipation structures, thus forming part of a longitudinal heat conduction path. Meanwhile, the bottom filler 17 also possesses certain insulating properties, preventing electrical short circuits between the chip and the insulating substrate 2, and between the PCB board 12 and the insulating substrate 2, thus ensuring the electrical safety and stability of the chip packaging module structure. In both embodiments, by placing the bottom filler 17 between the chip and the insulating substrate 2, and between the PCB board 12 and the insulating substrate 2, the heat dissipation path of the entire packaging module is further optimized, improving the efficiency of heat transfer from the chip core to the external heat dissipation structure, which helps maintain the stability of the chip's temperature during high-power operation. When both embodiments are implemented simultaneously, the longitudinal thermal conductivity of the longitudinal thermal conduction structure can be further improved.

[0050] In another embodiment of the present invention, the insulating substrate 2 includes a glass substrate; the glass substrate, with its excellent insulation properties and certain structural strength, provides a stable carrier for the setting of the metal 22 in the heat dissipation hole 212.

[0051] In this embodiment, the TGV glass through-hole technology uses insulating glass as the substrate, which has a lower dielectric constant (approximately 1 / 3 that of silicon) and a loss factor 2-3 orders of magnitude lower. Therefore, it effectively reduces signal attenuation and parasitic effects in high-frequency applications, supporting high-speed communication. Compared to silicon, using insulating glass reduces the risk of substrate warping and delamination during processing, and improves the integration of electrical interconnects. The metal 22 inside the heat dissipation hole 212 is typically columnar.

[0052] Similarly, the two ends of the metal 22 inside the heat dissipation hole 212 can conduct heat through solder balls 15 or through bottom filler glue 17 to conduct heat to the PCB board 12, and then the PCB board 12 transfers the heat to the second heat sink 14, without affecting the electrical transmission of the electrical connection structure.

[0053] In one embodiment of the present invention, a solder ball 15 is provided between the metal 22 of the conductive hole 211 and the PCB board 12. The solder ball 15 serves as at least part of the electrical connection structure and as part of the longitudinal heat-conducting structure.

[0054] The solder balls 15 form a stable electrical connection with the circuitry on the PCB board 12 and the metal 22 within the conductive holes 211. This enables electrical signal transmission between multiple chips and the PCB board 12. Furthermore, the solder balls 15 themselves have excellent thermal conductivity, allowing some of the heat generated by the chips to be transferred to the PCB board 12 through the metal 22 of the conductive holes 211, where it is further dissipated by the second heat sink 14. This design, combining electrical connection and heat conduction, ensures signal transmission stability while fully utilizing the space and material properties of existing electrical connection structures. It eliminates the need for additional independent vertical heat-conducting components, simplifying the module structure, reducing assembly complexity, and effectively improving the vertical heat dissipation efficiency of the chip packaging module. This allows heat to be dissipated more quickly from the chip core area to the PCB board 12.

[0055] In one embodiment of the present invention, the longitudinal heat-conducting structure further includes a heat-conducting part 121 embedded in the PCB board 12, wherein the heat-conducting part 121 is part of the longitudinal heat-conducting structure.

[0056] The heat-conducting part 121 is positioned as close as possible to the solder ball 15, but not in direct contact, to avoid short circuits. This establishes an efficient heat conduction path from the chip to the interior of the PCB board 12. When the heat generated by the chip is transferred to the PCB board 12 via the conductive hole 211, metal 22, and solder ball 15, some of the heat can be conducted to the heat-conducting part 121. Utilizing the extended distribution of the heat-conducting part 121 within the PCB board 12, the heat is quickly dispersed to a larger area of ​​the PCB board 12, and then dissipated through the second heat sink 14 of the PCB board 12 or through the thermal radiation and convection of the PCB board 12 itself, improving heat dissipation efficiency. The arrangement of this heat-conducting part 121 further improves the thermal conductivity of the vertical heat conduction path within the PCB board 12, allowing heat to be transferred to the second heat sink 14 and preventing heat accumulation in localized areas of the PCB board 12. Together with the solder ball 15, it forms part of a multi-layered, highly efficient vertical heat conduction network, thereby significantly enhancing the overall heat dissipation capacity of the chip packaging module and ensuring that the chip maintains stable performance under prolonged high-load operation.

[0057] Specifically, through holes, blind holes, or buried vias can be provided within the PCB board 12 to house the heat-conducting part 121. The heat-conducting part 121 may include 22 metal blocks or multiple 22 metal strips, as long as it does not affect the electrical transmission of the electrical connection structure. When the heat-conducting part 121 is provided as a through hole, insulation treatment can be applied between the heat-conducting part 121 and the electrical connection structure.

[0058] In one embodiment of the present invention, the heat-conducting part 121 includes 22 metal blocks embedded in the PCB board 12; in another embodiment of the present invention, the heat-conducting part 121 is disposed corresponding to the first chip. Either of the above two embodiments may be present, or both may be present simultaneously.

[0059] The metal 22 block can be made of a high thermal conductivity metal material, such as copper, aluminum, or their alloys. The shape and size of the heat-conducting part 121 can be adapted to the internal space of the PCB board 12 and the heat-generating area of ​​the first chip to maximize the coverage of the heat concentration area and improve the heat absorption and conduction effect. When the heat-conducting part 121 is set corresponding to the first chip, it means that the projection position of the heat-conducting part 121 in the PCB board 12 basically coincides with or includes the projection area of ​​the first chip on the PCB board 12. This allows the heat transferred from the chip to the PCB board 12 via the solder balls 15 to reach the heat-conducting part 121 in the shortest distance, reducing heat diffusion during the transfer process and further optimizing the efficiency of the longitudinal heat conduction path. For example, if the mounting area of ​​the first chip on the PCB board 12 is a square with a side length of 4 mm, then the distribution range of the corresponding heat-conducting part 121 in the PCB board 12 should at least cover the 4 mm × 4 mm square area. It can be appropriately expanded according to the heat dissipation requirements to better play its role in dispersing heat. When both embodiments exist simultaneously, that is, the PCB board 12 is embedded with a heat-conducting part 121 in the form of 22 metal blocks, and the 22 metal blocks are also arranged corresponding to the first chip, the 22 metal blocks can more accurately and efficiently conduct heat and disperse the heat generated by the first chip, thereby forming a more powerful heat dissipation synergy effect.

[0060] In one embodiment, the high-power ASIC chip 4 serves as the main heat source, and the heat it generates can be simultaneously discharged bidirectionally through the upper liquid cooling radiator, i.e., the first radiator 1, and the lower liquid cooling system, forming a double-sided heat dissipation path.

[0061] The lower liquid cooling system specifically includes: a PCB board 12 that has undergone thermal conductivity enhancement treatment, which significantly improves its thermal conductivity by embedding high thermal conductivity materials such as copper or aluminum; and a lower liquid cooling radiator, namely the second radiator 14, which is tightly attached to the lower surface of the thermally enhanced PCB board 12 through a thermal interface material 9.

[0062] The insulating substrate 2 is a glass substrate, and the glass substrate has through holes, i.e., vias 21, inside. The through holes include conductive holes 211 for electrical signal transmission and heat dissipation holes 212 dedicated to heat conduction. These through holes are filled with metal 22 to form a vertical high thermal conductivity path through the glass substrate, which significantly improves its thermal conductivity perpendicular to the chip direction, thereby optimizing the heat conduction efficiency from the ASIC chip 4 to the heat dissipation system below.

[0063] Furthermore, the glass substrate itself utilizes its thermal expansion coefficient to match that of the silicon chip, providing stable mechanical support for the chip. By enhancing its longitudinal thermal conductivity through TGV glass via technology, its heat dissipation performance is substantially improved while maintaining excellent mechanical and high-frequency electrical properties.

[0064] Furthermore, a semiconductor cooler can be placed between the photonic integrated chip, i.e., PIC chip 3, and the liquid cooling heat sink. The TEC semiconductor cooler is used to perform precise temperature compensation and control on the photonic integrated chip, further isolating it from the temperature fluctuations of the ASIC chip 4.

[0065] The beneficial effects of this invention are as follows: Significantly improves heat dissipation capacity: By providing two efficient liquid cooling paths, one above and one below, for the high-power ASIC chip 4, and by using TGV technology to enhance the longitudinal thermal conductivity of the glass substrate, the heat dissipation contact area and heat flow channels are effectively increased, overcoming the heat dissipation bottleneck caused by the limited area of ​​single-sided heat dissipation, significantly reducing the chip junction temperature and the overall package temperature, and mitigating the risk of high thermal failure.

[0066] Cost and reliability advantages: Compared with microchannel heat dissipation solutions that are complex to manufacture, have small orifices that are prone to clogging, require extremely high cleanliness of coolant, and are expensive, the upper and lower liquid-cooled heat sink structure and TGV enhanced glass substrate used in this invention are more mature and reliable. The overall manufacturing cost and maintenance requirements are significantly lower than those of microchannel heat dissipation systems of the same level.

[0067] Effective suppression of thermal crosstalk: The double-sided heat dissipation structure, combined with TGV vertical heat conduction, rapidly dissipates the core heat of the ASIC chip 4, reducing the heat transferred laterally to the photonic integrated chip at its source. Combined with the inherent low in-plane thermal conductivity of the glass substrate and the optional TEC temperature control, an excellent thermally stable environment is provided for the photonic integrated chip.

[0068] Enhanced integration and reliability: This structure, combined with TGV technology, provides an efficient and compact solution to the high heat flux density heat dissipation problem in CPO co-packaged optical technology. It makes it possible to integrate high-power ASIC chip 4 and sensitive photonic integrated chip into the same package at a higher density, while enhancing the long-term reliability of the package.

[0069] The core carrier board of the packaging module is a glass substrate. High-power ASIC chip 4, photonic integrated chip (PIC), and other electronic integrated chips (EIC) are integrated onto the glass substrate using advanced packaging processes (such as flip-chip technology). The glass substrate integrates a large number of through-glass vias (TGVs), which are formed into vertical vias through laser processing and filled with metal 22 using processes such as chemical copper plating. In this design, some of the metal 22 in the glass vias is used to transmit electrical signals. Specifically, the metal 22 in the conductive vias 211 is electrically interconnected with the PIC chip 3, EIC chip 11, and ASIC chip 4 via the redistribution layer 23 (RDL) and copper pillar solder joints 13. The metal 22 in the conductive vias 211 is interconnected with solder balls 15 via the redistribution layer 23 to electrically connect each chip to the PCB board 12. The metal 22 in the other portion of the glass vias, i.e., the metal 22 in the heat dissipation holes 212, does not transmit signals but serves as a dedicated heat dissipation via. While ensuring the mechanical strength of the substrate, these vias are densely arranged as much as possible below heat sources such as the ASIC chip 4 to construct an efficient vertical heat dissipation channel from the chip to the bottom of the package. The redistribution layer 23 is located on the first and second sides of the insulating substrate 2 to achieve electrical connections between the metal 22 in the vias 21 and the chips and PCB board 12. The PCB board 12 is equipped with a fiber optic array support 10 to position the fiber optic array 6. The fiber optic array 6 is used to connect the fiber optic cable 8 to enable optical signal interaction with the PIC chip 3.

[0070] A liquid-cooled heat sink is placed on top of the package. This heat sink can adopt a traditional cold plate structure, with its lower surface in close contact with the upper surface of the ASIC chip 4 and other heat-generating chips through a thermally conductive interface material 9 to absorb and remove the heat dissipated upwards by the chips. The thermally conductive interface material can be silicone grease.

[0071] The key improvement of this invention lies in the bottom liquid cooling system at the bottom of the package. Specifically, in the area of ​​the PCB board 12 directly below the high-power ASIC chip 4, a thermally enhanced PCB board 12 is formed by pre-embedding copper blocks or using a high thermal conductivity copper-clad laminate. Subsequently, a bottom liquid cooling radiator is tightly mounted on the lower surface of this thermally enhanced PCB board 12. In this way, the heat conducted downwards by the ASIC chip 4 can preferentially pass through the TGV thermal vias below it quickly through the glass substrate, then through the BGA solder balls 15 and the thermally enhanced PCB board 12, and finally be efficiently carried away by the coolant in the bottom liquid cooling radiator.

[0072] Therefore, the enormous heat (e.g., 300W) generated by the high-power ASIC chip 4 during operation is dissipated simultaneously through two paths: the first path dissipates upwards via the upper liquid cooler; the second path dissipates downwards through the TGV network and the thermally enhanced PCB board 12 to the lower liquid cooler. This dual-sided heat dissipation architecture, which incorporates TGV enhancement technology, not only increases the effective heat dissipation area but, more importantly, provides multiple low-thermal-resistance vertical heat dissipation paths, greatly improving the overall heat dissipation efficiency.

[0073] The upper liquid-cooled heatsink is fixedly connected to the PCB board 12 using the first fixing bolt 7. The lower liquid-cooled heatsink is fixedly connected to the PCB board 12 using the second fixing bolt 16.

[0074] For photonic integrated chips that are extremely sensitive to temperature, a thermoelectric cooler (TEC) can be added between the chip and the upper liquid-cooled heat sink. The cold end of the TEC is attached to the photonic integrated chip, and the hot end is attached to the upper liquid-cooled heat sink. The upper liquid-cooled heat sink provides a stable low-temperature base for the hot end of the TEC, while the TEC uses active cooling to precisely control the temperature of the photonic integrated chip, making it unaffected by the heat fluctuations of the ASIC chip.

[0075] In summary, the double-sided heat dissipation structure provided in this embodiment, through an innovative combination of "upper and lower liquid-cooled heat sinks + thermally enhanced PCB board 12 + TGV enhanced glass substrate," successfully solves the heat dissipation problem of high-power CPO modules in a more cost-effective and reliable manner, laying a solid foundation for the development of next-generation high-speed optical communication equipment. The innovative points of this solution are as follows: (1) Dual-sided heat dissipation architecture: For high-power chips, an innovative dual-sided heat dissipation design of "upper liquid cooling + lower liquid cooling" is adopted. By utilizing the upper and lower surfaces of the chip for heat dissipation at the same time, the area limitation of single-sided heat dissipation is broken, and the heat dissipation capability is fundamentally improved.

[0076] (2) Encrypted TGV vertical heat conduction: Innovatively introduce metal 22 filled glass through-holes in the glass substrate as dedicated heat channels, which significantly enhances the heat conduction capability of the substrate in the vertical direction and provides an efficient heat dissipation path for the core heat source.

[0077] (3) Composition of the lower heat dissipation system: The innovative design consists of a "thermally enhanced PCB" and a "lower liquid cooler", which are connected to the TGV heat conduction channel to form a complete and efficient bottom heat dissipation solution.

[0078] (4) Cost and reliability optimization: The overall solution uses a mature liquid cooling plate to replace the high-cost microchannel, combined with TGV and thermally enhanced PCB, which significantly reduces manufacturing costs and maintenance difficulty while ensuring heat dissipation performance.

[0079] (5) Comprehensive suppression of thermal crosstalk: By combining dual-sided heat dissipation, TGV vertical guidance and optional TEC temperature control, a comprehensive thermal management strategy is formed to block thermal crosstalk from heat sources to sensitive photonic integrated chips from the source.

[0080] The present invention also proposes an electronic product including the above-described chip packaging module structure. The specific structure of this chip packaging module is as described in the above embodiments. Since the electronic product adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0081] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A chip packaging module structure, characterized in that, include: PCB board; An insulating substrate is disposed on one side of the PCB board. The insulating substrate has a first side facing the PCB board and a second side facing away from the PCB board. The insulating substrate integrates a plurality of chips, including a first chip located on the second side of the insulating substrate. The insulating substrate is provided with a plurality of vias penetrating the first side and the second side. Each via contains metal, and at least a portion of the vias are conductive vias. The metal in the conductive vias is used as part of the electrical connection structure between the PCB board and the plurality of chips. The first heat sink is located on the side of the first chip facing away from the insulating substrate and is thermally connected to the first chip. as well as, The second heat sink is located on the other side of the PCB board, and a vertical heat conduction structure is formed between the second heat sink and the first chip to make the second heat sink and the first chip thermally connected. The vertical heat conduction structure includes metal disposed in the via.

2. The chip packaging module structure as described in claim 1, characterized in that, The plurality of chips also includes a second chip: The power of the first chip is greater than the power of the second chip; and / or, The first chip includes an ASIC chip, and the second chip includes at least one of an EIC chip and a PIC chip.

3. The chip packaging module structure as described in claim 2, characterized in that, The second chip is disposed on the second side of the insulating substrate, and a semiconductor cooling chip is disposed between the second chip disposed on the second side of the insulating substrate and the first heat sink. The cold end of the semiconductor cooling chip is thermally connected to the corresponding second chip, and the hot end of the semiconductor cooling chip is thermally connected to the first heat sink.

4. The chip packaging module structure as described in claim 1, characterized in that, A thermal interface material is provided between the chip disposed on the second side of the insulating substrate and the first heat sink.

5. The chip packaging module structure as described in claim 1, characterized in that, The first heat sink is a liquid-cooled heat sink; and / or, The second heat sink is a liquid-cooled heat sink.

6. The chip packaging module structure as described in claim 1, characterized in that, The plurality of vias also include heat dissipation holes, wherein the metal within the heat dissipation holes is used to conduct heat from the second side of the insulating substrate to the first side; and / or, An underfill adhesive is provided between the plurality of chips and the insulating substrate, and an underfill adhesive is provided between the PCB board and the insulating substrate.

7. The chip packaging module structure as described in claim 1, characterized in that, Solder balls are disposed between the metal of the conductive hole and the PCB board. The solder balls are at least part of the electrical connection structure and also part of the longitudinal heat-conducting structure.

8. The chip packaging module structure as described in claim 1, characterized in that, The longitudinal heat-conducting structure also includes a heat-conducting part embedded in the PCB board, which is part of the longitudinal heat-conducting structure.

9. The chip packaging module structure as described in claim 8, characterized in that, The heat-conducting part includes a metal block embedded in the PCB board; and / or, The heat-conducting part is provided corresponding to the first chip.

10. An electronic product, characterized in that, Includes the chip packaging module structure as described in any one of claims 1 to 9.

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