Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device, a method of manufacturing the same, and an electronic apparatus, the semiconductor device including: at least one memory cell including a first transistor and a second transistor vertically stacked, a second gate electrode of the first transistor being connected to a third electrode of the second transistor; a first gate electrode of the first transistor extends in the direction perpendicular to the substrate; the first semiconductor layer of the first transistor surrounds the side wall of the first gate electrode and wraps the bottom wall of the side, facing the substrate, of the first gate electrode, and the second gate electrode is arranged on the side, away from the substrate, of the first electrode of the first transistor and partially surrounds the first semiconductor layer; the second electrode is arranged on the side, away from the substrate, of the first electrode, surrounds the first semiconductor layer and is connected with the first semiconductor layer. The first electrode is at least connected with the bottom wall of the side, facing the substrate, of the first semiconductor layer. According to the scheme provided by the embodiment, the first transistor and the second transistor are vertically stacked, so that the area of the memory unit is reduced, and the memory density is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which improves storage density.

[0006] This application provides a semiconductor device, comprising: at least one memory cell, the memory cell including a first transistor and a second transistor stacked on a substrate in a direction perpendicular to the substrate, the second transistor being disposed on the side of the first transistor facing away from the substrate; the first transistor including: a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer; the second transistor including a third gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer; the second semiconductor layer being connected to the third electrode and the fourth electrode respectively; the second gate electrode being connected to the third electrode; the first gate electrode extending in a direction perpendicular to the substrate; the first semiconductor layer surrounding the sidewall of the first gate electrode and enclosing the bottom wall of the first gate electrode facing the substrate, the second gate electrode being disposed on the side of the first electrode facing away from the substrate and partially surrounding the first semiconductor layer; the second electrode being disposed on the side of the first electrode facing away from the substrate and surrounding the first semiconductor layer and being connected to the first semiconductor layer, the first electrode being at least connected to the bottom wall of the first semiconductor layer facing the substrate.

[0007] In some embodiments, the first electrode is connected to a sidewall region at a distance less than or equal to a preset value from the bottom wall of the first semiconductor layer.

[0008] In some embodiments, the first electrode extends in a direction parallel to the substrate, and the second electrode extends in a direction parallel to the substrate.

[0009] In some embodiments, the second gate electrode includes a first portion extending in a direction parallel to the substrate and a second portion extending in a direction perpendicular to the substrate; the first portion is disposed on the side of the first electrode facing away from the substrate, the second electrode faces the substrate, and the first portion surrounds the first gate electrode; the second portion is connected to the third electrode.

[0010] In some embodiments, the third gate electrode extends in a direction perpendicular to the substrate, the second semiconductor layer surrounds the sidewall of the third gate electrode and encloses the bottom wall of the third gate electrode facing the substrate, and the third electrode and the fourth electrode are connected to the sidewall of the second semiconductor layer.

[0011] In some embodiments, the third electrode extends in a direction parallel to the substrate, the fourth electrode extends in a direction parallel to the substrate, and the third electrode and the fourth electrode are disposed in the same layer.

[0012] In some embodiments, the semiconductor device includes a multilayer memory cell array stacked along a direction perpendicular to the substrate. Each layer of the memory cell array includes a plurality of memory cells arrayed along a first direction and a second direction. The first electrodes of the first transistors of memory cells in the same row of the same layer are connected to the same first bit line. The fourth electrodes of the second transistors of memory cells in the same row of the same layer are connected to the same second bit line. The first gate electrodes of the first transistors of memory cells in the same position of different layers are connected to the same first word line. The third gate electrodes of the second transistors of memory cells in the same position of different layers are connected to the same second word line.

[0013] This disclosure provides a method for manufacturing a semiconductor device, including: A first transistor is formed on a substrate; the first transistor includes: a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer; the first gate electrode extends in a direction perpendicular to the substrate; the first semiconductor layer surrounds the sidewall of the first gate electrode and encloses the bottom wall of the first gate electrode facing the substrate; the second gate electrode is disposed on the side of the first electrode away from the substrate and partially surrounds the first semiconductor layer; the second electrode is disposed on the side of the first electrode away from the substrate and surrounds the first semiconductor layer and is connected to the first semiconductor layer; the first electrode is at least connected to the bottom wall of the first semiconductor layer facing the substrate. A second transistor is formed on the side of the first transistor away from the substrate; the second transistor includes a third gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer; the second semiconductor layer is connected to the third electrode and the fourth electrode respectively; the third electrode is connected to the second gate electrode.

[0014] In some embodiments, forming the first transistor on the substrate includes: A first electrode, a first portion of a second gate electrode, and a second electrode are formed on a substrate, which are stacked sequentially and spaced apart along a direction perpendicular to the substrate. The first electrode, the first portion, and the second electrode overlap in their orthogonal projections onto the substrate. A first hole is formed that penetrates the second electrode and the first portion along a direction perpendicular to the substrate, and the bottom wall of the first hole exposes the first electrode; Based on the first hole, the first portion is laterally etched to a predetermined length to form a lateral groove, the bottom wall of the lateral groove being exposed in the first portion; a second gate insulating layer is formed to fill the lateral groove; A first semiconductor layer, a first gate insulating layer, and a first gate electrode filling the first hole are formed sequentially covering the bottom wall and side wall of the first hole. A second portion extending perpendicular to the substrate is formed as a second gate electrode. The second portion is connected to the first portion, and the distance between the second portion and the substrate on the side facing away from the substrate is greater than the distance between the first gate electrode and the substrate on the side facing away from the substrate.

[0015] In some embodiments, forming the second transistor on the substrate-away side of the first transistor includes: A conductive layer is formed on the side of the first transistor away from the substrate, and the conductive layer is connected to the second portion; A second hole is formed that penetrates the conductive layer along a direction perpendicular to the substrate and does not expose the first gate electrode. The second hole divides the conductive layer into a disconnected third electrode and a fourth electrode, and the third electrode is connected to the second portion. A second semiconductor layer, a second gate insulating layer, and a third gate electrode are formed to sequentially cover the bottom and sidewalls of the second hole.

[0016] This disclosure provides an electronic device, including the semiconductor device described above, or a semiconductor device formed according to any of the manufacturing methods of the semiconductor device described above.

[0017] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes at least one memory cell, the memory cell including a first transistor and a second transistor stacked on a substrate in a direction perpendicular to the substrate, the second transistor being disposed on the side of the first transistor facing away from the substrate; the first transistor including a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer; the second transistor including a third gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer; the second semiconductor layer being connected to the third electrode and the fourth electrode respectively; the second gate electrode being connected to the third electrode; the first gate electrode extending in a direction perpendicular to the substrate; the first semiconductor layer surrounding the sidewall of the first gate electrode and enclosing the bottom wall of the first gate electrode facing the substrate; the second gate electrode being disposed on the side of the first electrode facing away from the substrate and partially surrounding the first semiconductor layer; the second electrode being disposed on the side of the first electrode facing away from the substrate and surrounding the first semiconductor layer and connected to the first semiconductor layer; the first electrode being at least connected to the bottom wall of the first semiconductor layer facing the substrate. The solution provided by the embodiments of this disclosure, with the first transistor and the second transistor vertically stacked, reduces the memory cell area and increases the storage density. Furthermore, the first transistor includes dual gates, and the second gate electrode does not add additional area, enabling multi-bit storage without affecting the storage density.

[0018] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0019] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0020] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0021] Figure 1 A schematic cross-sectional view of a memory cell provided in an embodiment of this disclosure along a direction perpendicular to the substrate; Figure 2A A schematic cross-sectional view of a semiconductor device along a direction perpendicular to the substrate, provided for some embodiments; Figure 2B A schematic cross-sectional view of a semiconductor device along a direction perpendicular to the substrate, provided for other embodiments; Figure 2C A schematic cross-sectional view of a semiconductor device provided in some other embodiments along a direction perpendicular to the substrate; Figure 3 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first electrode, the second gate electrode, and the second electrode in some embodiments; Figure 4 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first hole, provided for some embodiments; Figure 5 A cross-sectional view along the direction perpendicular to the substrate after the formation of the second gate insulating layer, provided for some embodiments; Figure 6 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first semiconductor layer, the first gate insulating layer and the first gate electrode, provided for some embodiments; Figure 7 A cross-sectional view along the direction perpendicular to the substrate after the formation of the fifth insulating layer, provided for some embodiments; Figure 8 A cross-sectional view perpendicular to the substrate after the formation of the third hole, provided for some embodiments; Figure 9 A cross-sectional view along the direction perpendicular to the substrate after the formation of the second portion, provided for some embodiments; Figure 10 A cross-sectional view perpendicular to the substrate after the formation of the conductive layer and the sixth insulating layer, provided for some embodiments; Figure 11 A cross-sectional view perpendicular to the substrate after the formation of the second hole, provided for some embodiments; Figure 12 Equivalent circuit diagrams of memory cells provided in some embodiments; Figure 13 A schematic diagram showing the relationship between gate-source voltage and drain current when the data stored in a storage node is different. Detailed Implementation

[0022] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0023] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0024] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0025] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0026] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0027] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0028] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0029] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0030] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0031] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0032] The term "co-layered A and B" as used in this disclosure includes film layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer with the same material and then undergoing the same patterning process or different patterning processes. Co-layered A and B may be located on the same horizontal plane but not necessarily on the same film layer, or they may be located in different regions of the same film layer but not necessarily on the same horizontal plane.

[0033] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0034] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0035] Figure 1 This is a schematic cross-sectional view of a memory cell provided in an embodiment of this disclosure, perpendicular to the substrate direction. Figure 1 As shown, the memory cell provided in this embodiment may include: a first transistor T1 and a second transistor T2 stacked along a direction perpendicular to the substrate. The second transistor T2 may be disposed on the side of the first transistor T1 away from the substrate. The first transistor T1 may include: a first semiconductor layer 23, a first gate electrode 26, a first gate insulating layer 61, a second gate electrode 27, a second gate insulating layer 62, a first electrode 51, and a second electrode 52. The second transistor T2 may include a second semiconductor layer 24, a third gate insulating layer 63, a third gate electrode 28, a third electrode 53, and a fourth electrode 54. The second gate electrode 27 is connected to the third electrode 53, or the second gate electrode 27 and the third electrode 53 may share the same electrode.

[0036] The solution provided in this embodiment, in which the first transistor and the second transistor are stacked vertically, reduces the storage cell area and increases the storage density compared to the solution in which the first transistor and the second transistor are distributed in a planar manner.

[0037] The first gate electrode 26 extends in a direction perpendicular to the substrate, and the first semiconductor layer 23 surrounds the sidewall of the first gate electrode 26. In some embodiments, the first semiconductor layer 23 may also cover the bottom wall of the first gate electrode 26 facing the substrate. The first semiconductor layer 23 may extend continuously on the sidewall of the first gate electrode 26 and the bottom wall facing the substrate.

[0038] The first gate insulating layer 61 is disposed between the first semiconductor layer 23 and the first gate electrode 26, spaced apart from the first semiconductor layer 23 and the first gate electrode 26. The first gate insulating layer 61 surrounds the sidewall of the first gate electrode 26. In some embodiments, the first gate insulating layer 61 may also cover the bottom wall of the first gate electrode 26 facing the substrate. That is, the first gate insulating layer 61 extends continuously on the sidewall and bottom wall of the first gate electrode 26.

[0039] The first electrode 51 can extend in a direction parallel to the substrate. The first electrode 51 is disposed on the side of the first semiconductor layer 23 facing the substrate and is connected to at least the bottom wall of the first semiconductor layer 23 facing the substrate.

[0040] In some embodiments, the first electrode 51 is also connected to a sidewall region of the first semiconductor layer 23 at a distance less than or equal to a preset value from the bottom wall; that is, the first electrode 51 is also connected to a region on the sidewall of the first semiconductor layer 23 near the bottom wall. The solution provided in this embodiment can increase the contact area between the first electrode 51 and the first semiconductor layer 23, thereby reducing contact resistance.

[0041] The second gate electrode 27 can be disposed on the side of the first electrode 51 away from the substrate and partially surround the first semiconductor layer 23, that is, surrounding a portion of the sidewall of the first semiconductor layer 23. The cross-section of the second gate electrode 27 parallel to the substrate can be a closed loop or an open loop. The second gate electrode 27 may include a first portion extending parallel to the substrate direction and a second portion extending perpendicular to the substrate direction. The first portion surrounds the first semiconductor layer 23, and the second portion is connected to the third electrode 53. The second portion extends perpendicular to the substrate direction away from the substrate and is connected to the third electrode 53 on the substrate-facing side. The solution provided in this disclosure embodiment does not occupy additional area with the second gate electrode 27, and multi-bit storage can be achieved without affecting the storage density.

[0042] The second gate insulating layer 62 is disposed between the first semiconductor layer 23 and a first portion of the second gate electrode 27, spaced between the second gate electrode 27 and the first semiconductor layer 23. The second gate insulating layer 62 surrounds the sidewall of the first semiconductor layer 23 and contacts the sidewall of the first semiconductor layer 23.

[0043] The second electrode 52 may be disposed on the side of the first electrode 51 facing away from the substrate, surrounding the sidewall of the first semiconductor layer 23 and connected to the first semiconductor layer 23. In some embodiments, the second electrode 52 may extend in a direction parallel to the substrate. In some embodiments, the second electrode 52 may fully or partially surround the sidewall of the first semiconductor layer 23, that is, the cross-section of the second electrode 52 parallel to the substrate may be an open loop or a closed loop. A vertical channel is formed between the first electrode 51 and the second electrode 52, that is, the first transistor T1 is a vertical channel transistor. A vertical channel is one in which the carrier transport direction is in a plane perpendicular to the substrate, but it is not limited to the carrier transport direction being in one direction.

[0044] The second electrode 52 and the second gate insulating layer 62 surround different regions of the sidewall of the first semiconductor layer 23.

[0045] In some embodiments, the memory cell may include a first hole K1 extending perpendicular to the substrate direction. The first semiconductor layer 23, the first gate insulating layer 61, and the first gate electrode 26 are sequentially distributed from the outside to the inside within the first hole K1, and the first gate electrode 26 fills the first hole K1. The first semiconductor layer 23 is distributed on the bottom wall and sidewalls of the first hole K1. In some embodiments, in addition to the vertical portions disposed within the first hole K1, the first semiconductor layer 23, the first gate insulating layer 61, and the first gate electrode 26 may also include horizontal portions extending from the inside of the first hole K1 outward along a direction parallel to the substrate direction.

[0046] In some embodiments, the third gate electrode 28 extends in a direction perpendicular to the substrate, and the second semiconductor layer 24 surrounds the sidewall of the third gate electrode 28. In some embodiments, the second semiconductor layer 24 may also surround the bottom wall of the third gate electrode 28 facing the substrate. That is, the second semiconductor layer 24 extends continuously on the sidewall of the third gate electrode 28 and the bottom wall facing the substrate.

[0047] The third gate insulating layer 63 is disposed between the second semiconductor layer 24 and the third gate electrode 28, spaced apart from the second semiconductor layer 24 and the third gate electrode 28. The third gate insulating layer 63 surrounds the sidewall of the third gate electrode 28. In some embodiments, the third gate insulating layer 63 may also surround the bottom wall of the third gate electrode 28 facing the substrate. That is, the third gate insulating layer 63 extends continuously on the sidewall and bottom wall of the third gate electrode 28.

[0048] In some embodiments, the memory cell may include a second hole K2 extending perpendicular to the substrate direction. The second semiconductor layer 24, the third gate insulating layer 63, and the third gate electrode 28 are sequentially distributed from the outside to the inside within the second hole K2, and the third gate electrode 28 fills the second hole K2. The second semiconductor layer 24 and the third gate insulating layer 63 sequentially cover the bottom wall and sidewall of the second hole K2. In some embodiments, in addition to the vertical portions disposed within the second hole K2, the second semiconductor layer 24, the third gate insulating layer 63, and the third gate electrode 28 may also include horizontal portions extending from the inside of the second hole K2 outwards along a direction parallel to the substrate direction.

[0049] The third electrode 53 can extend in a direction parallel to the substrate, and the fourth electrode 54 can extend in a direction parallel to the substrate. The third electrode 53 and the fourth electrode 54 can be distributed in a direction parallel to the substrate. The third electrode 53 and the fourth electrode 54 can be connected to different regions of the sidewall of the second semiconductor layer 24, that is, the third electrode 53 and the fourth electrode 54 are distributed at intervals on the sidewall of the second semiconductor layer 24.

[0050] In some embodiments, the third electrode 53 and the fourth electrode 54 may be disposed in the same layer. The first distance between the third electrode 53 and the substrate and the second distance between the fourth electrode 54 and the substrate may be the same. In this case, a horizontal channel is formed between the third electrode 53 and the fourth electrode 54, and the second transistor T2 is a horizontal channel transistor. A horizontal channel is one in which the carrier transport direction is in a plane parallel to the substrate, but it is not limited to the carrier transport direction being in one direction. However, the embodiments of this disclosure are not limited to this, and the first distance and the second distance may be different.

[0051] Figure 2A A schematic cross-sectional view of a semiconductor device along a direction perpendicular to the substrate, provided for some embodiments. Figure 2B A schematic cross-sectional view of a semiconductor device along a direction perpendicular to the substrate, provided for other embodiments. Figure 2CThis is a schematic cross-sectional view of a semiconductor device provided in some embodiments, perpendicular to the substrate direction. The semiconductor device may include a multilayer memory cell array stacked perpendicular to the substrate direction, multiple first word lines 41 extending perpendicular to the substrate direction, and multiple second word lines 42 extending parallel to the substrate direction. Each memory cell array may include multiple memory cells arrayed along a first direction and a second direction. The first electrodes 51 of memory cells in the same row of cells distributed along the first direction in the same layer are connected to form a single first word line 31. The first electrodes 51 of memory cells in different rows can be connected to different first word lines 31. The fourth electrodes 54 of memory cells in the same row of cells distributed along the first direction in the same layer are connected to the same second word line 32. The fourth electrodes 54 of memory cells in different rows can be connected to different second word lines 32. The first gate electrodes 26 of memory cells at the same position in different layers are connected to the same first word line 41, and the third gate electrodes 28 of memory cells at the same position in different layers are connected to the same second word line 42. In two adjacent memory cells along the first direction, the third electrode 53 of one memory cell is adjacent to the fourth electrode 54 of the other memory cell, as shown below. Figure 2A and Figure 2B As shown, the third electrode 53 of one of the adjacent memory cells can be connected to the fourth electrode 54 of the other memory cell, as... Figure 2A As shown, this can simplify the process; alternatively, the third electrode 53 of one of the adjacent memory cells can be disconnected from the fourth electrode 54 of the other memory cell, reducing leakage current. In other embodiments, the fourth electrodes 54 of adjacent memory cells along the first direction can be adjacent to each other or reuse the same electrode, that is, the structures of two adjacent memory cells along the first direction can be mirror-symmetrical or approximately mirror-symmetrical, such as... Figure 2C As shown.

[0052] In some embodiments, the first bit line 31 may extend along a first direction. Multiple first bit lines 31 on the same layer are distributed at intervals along a second direction.

[0053] This disclosure provides a method for manufacturing a semiconductor device, which may include: A first transistor is formed on a substrate; the first transistor includes: a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer; the first gate electrode extends in a direction perpendicular to the substrate; the first semiconductor layer surrounds the sidewall of the first gate electrode and encloses the bottom wall of the first gate electrode facing the substrate; the second gate electrode is disposed on the side of the first electrode away from the substrate and surrounds the first semiconductor layer; the second electrode is disposed on the side of the first electrode away from the substrate and surrounds the first semiconductor layer and is connected to the first semiconductor layer; the first electrode is at least connected to the bottom wall of the first semiconductor layer facing the substrate. A second transistor is formed on the side of the first transistor away from the substrate; the second transistor includes a third gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer; the second semiconductor layer is connected to the third electrode and the fourth electrode respectively; the third electrode is connected to the second gate electrode.

[0054] In some embodiments, forming the first transistor on the substrate may include: A first electrode, a first portion of a second gate electrode, and a second electrode are formed on a substrate, which are stacked sequentially and spaced apart along a direction perpendicular to the substrate; the first electrode, the first portion, and the second electrode overlap in their orthogonal projections onto the substrate. A first hole is formed that penetrates the second electrode and the first portion along a direction perpendicular to the substrate, and the bottom wall of the first hole exposes the first electrode; Based on the first hole, the first portion is laterally etched to a predetermined length to form a lateral groove, the bottom wall of the lateral groove being exposed in the first portion; a second gate insulating layer is formed to fill the lateral groove; A first semiconductor layer, a first gate insulating layer, and a first gate electrode filling the first hole are formed sequentially covering the bottom wall and side wall of the first hole. A second portion extending perpendicular to the substrate is formed as a second gate electrode. The second portion is connected to the first portion, and the distance between the second portion and the substrate on the side facing away from the substrate is greater than the distance between the first gate electrode and the substrate on the side facing away from the substrate.

[0055] In some embodiments, forming a second transistor on the substrate-away side of the first transistor may include: A conductive layer is formed on the side of the first transistor away from the substrate, and the conductive layer is connected to the second portion; A second hole is formed that penetrates the conductive layer along a direction perpendicular to the substrate and does not expose the first gate electrode. The second hole divides the conductive layer into a disconnected third electrode and a fourth electrode, and the third electrode is connected to the second portion. A second semiconductor layer, a second gate insulating layer, and a third gate electrode are formed to sequentially cover the bottom and sidewalls of the second hole.

[0056] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0057] In one exemplary embodiment, the manufacturing process of the semiconductor device may include: 1) Forming the first portion 271 of the first electrode 51 and the second gate electrode 27 and the second electrode 52; A first insulating film and a first conductive film are sequentially deposited on a substrate, and the first conductive film is patterned to form a first insulating layer 11 and a first electrode 51 disposed on the first insulating layer 11. A second insulating film and a second conductive film are deposited sequentially, and the second conductive film is patterned to form a second insulating layer 12 and a first portion 271 of the second gate electrode 27; the second insulating layer 12 covers the first electrode 51 and the first insulating layer 11. A third insulating film and a third conductive film are deposited sequentially, and the third conductive film is patterned to form a third insulating layer 13 and a second electrode 52; the third insulating layer 13 covers the second insulating layer 12 and the first portion 271; wherein the orthographic projections of the first electrode 51, the second electrode 52 and the first portion 271 on the substrate overlap, and the orthographic projection of the first portion 271 on the substrate is located outside the orthographic projection of the second electrode 52 on the substrate. A fourth insulating film is deposited to form a fourth insulating layer 14 covering the second electrode 52 and the third insulating layer 13; as shown. Figure 3 As shown, Figure 3 A cross-sectional view along the direction perpendicular to the substrate after forming the first portion 271 of the first electrode 51, the second gate electrode 27, and the second electrode 52, for some embodiments.

[0058] In some embodiments, the first, second, third, and fourth insulating films may be low-K dielectric layers, i.e., dielectric layers with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2). The materials for the subsequent fifth and sixth insulating films are similar and will not be described further.

[0059] In some embodiments, the first conductive film, the second conductive film, and the third conductive film may be one or more of the following different types of materials: For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals. Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN). Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0060] The materials for the subsequent fourth, fifth, sixth, and seventh conductive films are similar and will not be described in detail.

[0061] 2) Form the first hole K1; The fourth insulating layer 14, the second electrode 52, the third insulating layer 13, the first portion 271, the second insulating layer 12, and the first electrode 51 are etched along a direction perpendicular to the substrate. The first electrode 51 is partially etched but not completely etched through; alternatively, etching can be performed until the first electrode 51 is exposed, forming the first hole K1. Figure 4 As shown, Figure 4 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first hole K1, provided for some embodiments.

[0062] In some embodiments, the orthographic projection of the first hole K1 onto the substrate may be located within the orthographic projection of the first electrode 51, the first portion 271, and the second electrode 52 onto the substrate, such that the first electrode 51, the second electrode 52, and the first portion 271 can completely surround the first semiconductor layer 23 subsequently formed in the first hole K1, that is, the first electrode 51, the second electrode 52, and the first portion 271 include a closed-loop structure along a cross section parallel to the substrate.

[0063] In some embodiments, the first hole K1 along a cross section parallel to the substrate can be square, circular, etc.

[0064] 3) Forming a second gate insulating layer 62; Based on the first hole K1, the first part 271 is etched laterally (along the direction parallel to the substrate) to a predetermined length, and the first part 271 is not etched through laterally, forming a lateral groove V1, and the bottom wall of the lateral groove V1 is exposed to the first part 271. A second gate insulating film is deposited to fill the lateral groove V1, forming a second gate insulating layer 62, as shown. Figure 5 As shown, Figure 5 This is a cross-sectional view along a direction perpendicular to the substrate after the formation of the second gate insulating layer 62, as provided in some embodiments. The second gate insulating layer 62 surrounds the first hole K1, in which case the first portion 271 is not exposed in the first hole K1, thus preventing the first portion 271 from connecting with the first semiconductor layer 23 subsequently formed in the first hole K1.

[0065] In some embodiments, the material of the second gate insulating film may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The materials of the subsequent first and third gate insulating films are similar to those of the first gate insulating film and will not be described further.

[0066] 4) Forming a first semiconductor layer 23, a first gate insulating layer 61, and a first gate electrode 26; A first semiconductor thin film, a first gate insulating thin film, and a fourth conductive thin film are sequentially deposited on the substrate forming the aforementioned structure, thereby patterning a first semiconductor layer 23, a first gate insulating layer 61, and a first gate electrode 26, as shown below. Figure 6 As shown, Figure 6 A cross-sectional view perpendicular to the substrate is provided for some embodiments after the formation of a first semiconductor layer 23, a first gate insulating layer 61, and a first gate electrode 26. The first semiconductor layer 23 covers the bottom and sidewalls of the first hole K1 and extends beyond the first hole K1, distributed on a portion of the surface of the fourth insulating layer 14 facing away from the substrate; the first gate insulating layer 61 covers the bottom and sidewalls of the first hole K1 on which the first semiconductor layer 23 is formed, and covers the surface of the first semiconductor layer 23 facing away from the substrate outside the first hole K1; the first gate electrode 26 fills the first hole K1 and covers the surface of the first gate insulating layer 61 facing away from the substrate.

[0067] In some embodiments, the first semiconductor thin film may be a material such as silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0068] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0069] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0070] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0071] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0072] The subsequent second semiconductor thin film material is similar and will not be described in detail. In some embodiments, the first semiconductor layer 23 can be polycrystalline silicon, and the second semiconductor layer 24 can be indium gallium zinc tin oxide (InGaZnSnO).

[0073] 5) Form the fifth insulating layer 15; A fifth insulating film is deposited on the substrate forming the aforementioned structure to form a fifth insulating layer 15. The fifth insulating layer 15 covers the side of the first gate electrode 26 facing away from the substrate and also covers the side of the fourth insulating layer 14 facing away from the substrate. Figure 7 As shown, Figure 7 A cross-sectional view along the direction perpendicular to the substrate after the formation of the fifth insulating layer 15, provided for some embodiments.

[0074] 6) Formation of the third hole K3; The fifth insulating layer 15, the fourth insulating layer 14, and the third insulating layer 13 are etched along a direction perpendicular to the substrate to form a third hole K3. The sidewall of the third hole K3 exposes the first portion 271, as shown below. Figure 8 As shown, Figure 8 This is a cross-sectional view along the direction perpendicular to the substrate after the formation of the third hole K3, provided for some embodiments. For example, the first portion 271 may include two end faces disposed opposite each other along the direction parallel to the substrate. The sidewall of the third hole K3 may expose one end face of the first portion 271, and the bottom wall of the third hole K3 may expose the second insulating layer 12. However, the embodiments of this disclosure are not limited to this. It is possible that the bottom wall of the third hole K3 exposes the side of the first portion 271 away from the substrate 1; or, part of the bottom wall of the third hole K3 exposes the side of the first portion 271 away from the substrate 1, and part of the bottom wall exposes the second insulating layer 12, etc. The embodiments of this disclosure are not limited in this respect, as long as the connection between the first portion 271 and the second portion 272 subsequently formed in the third hole K3 can be achieved.

[0075] 7) Forming the second part 272; A fifth conductive thin film is deposited on the substrate forming the aforementioned structure to form a second portion 272 filling the third hole K3; the first portion 271 and the second portion 272 constitute the second gate electrode 27; the second portion 272 is connected to the first portion 271, as follows: Figure 9 As shown, Figure 9 A cross-sectional view along a direction perpendicular to the substrate after the formation of the second portion 272 is provided for some embodiments. The orthographic projection of the second portion 272 onto the substrate may be located outside the orthographic projection of the first gate electrode 26 onto the substrate.

[0076] 8) Forming a conductive layer 50 and a sixth insulating layer 16; A sixth conductive film and a sixth insulating film are sequentially deposited on the substrate forming the aforementioned structure. The sixth conductive film is patterned to form a sixth insulating layer 16 and a conductive layer 50. The conductive layer 50 is connected to the second portion 272. The conductive layer 50 can be connected to the side of the second portion 272 facing away from the substrate. The sixth insulating layer 16 covers the conductive layer 50. Figure 10 As shown, Figure 10 A cross-sectional view along the direction perpendicular to the substrate after the formation of the conductive layer 50 and the sixth insulating layer 16, provided for some embodiments.

[0077] 9) Formation of the second hole K2; The sixth insulating layer 16, the conductive layer 50, and the fifth insulating layer 15 are etched along a direction perpendicular to the substrate to form a second hole K2. The second hole K2 penetrates the sixth insulating layer 16 and the conductive layer 50 but does not penetrate the fifth insulating layer 15, and does not expose the first gate electrode 26. That is, the bottom wall of the second hole K2 exposes the fifth insulating layer 15. Figure 11 As shown, Figure 11 A cross-sectional view along a direction perpendicular to the substrate after the formation of the second hole K2 is provided for some embodiments. The second hole K2 divides the conductive layer 50 into a third electrode 53 and a fourth electrode 54 that are disconnected from each other, and the third electrode 53 is connected to the second gate electrode 27.

[0078] In some embodiments, the orthographic projection of the second hole K2 onto the substrate overlaps with the orthographic projection of the first hole K1 onto the substrate. The solution provided by this disclosure allows the orthographic projections of the first transistor and the second transistor onto the substrate to overlap, reducing the size of the memory cell. However, this disclosure is not limited to this; the orthographic projection of the second hole K2 onto the substrate may not overlap with the orthographic projection of the first hole K1 onto the substrate.

[0079] 10) Forming a second semiconductor layer 24, a third gate insulating layer 63, and a third gate electrode 28; A second semiconductor thin film, a third gate insulating thin film, and a seventh conductive thin film are sequentially deposited on the substrate forming the aforementioned structure, thereby patterning a second semiconductor layer 24, a third gate insulating layer 63, and a third gate electrode 28, as shown below. Figure 1 As shown. The second semiconductor layer 24 covers the bottom wall and sidewalls of the second hole K2, and may extend beyond the second hole K2, distributed on a portion of the surface of the sixth insulating layer 16 facing away from the substrate; the third gate insulating layer 63 covers the bottom wall and sidewalls of the second hole K2 on which the second semiconductor layer 24 is formed, and covers the surface of the second semiconductor layer 24 outside the second hole K2 facing away from the substrate 1; the third gate electrode 28 fills the second hole K2 and covers the surface of the third gate insulating layer 63 facing away from the substrate 1. Different regions of the sidewalls of the second semiconductor layer 24 are respectively connected to the third electrode 53 and the fourth electrode 54.

[0080] In the solution provided in this embodiment, the first transistor and the second transistor are stacked along a direction perpendicular to the substrate, which reduces the area of ​​the memory cell and increases the storage density when using the memory cell to form a memory array. In addition, when the first semiconductor layer is polycrystalline silicon and the second semiconductor layer is metal oxide, metal oxide semiconductors are not resistant to high temperatures, and polycrystalline silicon has a higher formation temperature. Forming the first transistor first and then the second transistor can reduce the thermal budget.

[0081] The manufacturing process described above is merely an example, and the embodiments disclosed herein are not limited thereto. The semiconductor devices described above can be manufactured in other ways.

[0082] Figure 12 Equivalent circuit diagrams of memory cells provided for some embodiments. For example... Figure 12 As shown, the memory cell may include a first transistor T1 and a second transistor T2. The first gate electrode 26 of the first transistor T1 is connected to the first word line 41, the second gate electrode 27 is connected to the third electrode 53 of the second transistor T2, the first electrode 51 of the first transistor T1 is connected to the first bit line 31, the second electrode 52 of the first transistor T1 is connected to the reference voltage terminal Vref, the fourth electrode 54 of the second transistor T2 is connected to the second bit line 32, and the third gate electrode 28 of the second transistor T2 is connected to the second word line 42. The memory cell also includes a memory node SN, which contains the second gate electrode 27 of the first transistor T1. The threshold voltage of the first transistor T1 is different when different data is stored in the memory node SN. A storage node SN can store one or more bits of data. For example, when storing 1 bit of data, if the data stored in storage node SN is "1", the threshold voltage of the first transistor T1 is Vth1. If the data stored in storage node SN is "0", the threshold voltage of the first transistor T1 is Vth2, and Vth2 > Vth1. Therefore, a read voltage greater than Vth1 and less than Vth2 can be applied to the read word line RWL. When the data stored in storage node SN is "0", the first transistor T1 is turned off, and when the data stored in storage node SN is "1", the first transistor T1 is turned on. Different voltages or currents can be detected on the read bit line RBL to determine the data stored in the storage node.

[0083] For example, when storing 2 bits of data, if the data stored by storage node SN is "11", the threshold voltage of the first transistor T1 is Vth11; if the data stored by storage node SN is "10", the threshold voltage of the first transistor T1 is Vth10; if the data stored by storage node SN is "01", the threshold voltage of the first transistor T1 is Vth01; and if the data stored by storage node SN is "00", the threshold voltage of the first transistor T1 is Vth00, and Vth00 > Vth01 > Vth10 > Vth11. Figure 13 When the data stored in storage node SN is different, the gate-source voltage V GS and drain current I D The diagram illustrates the relationship between the stored data and the drain current I at the same voltage. DThe difference is as follows. When reading data, a read voltage greater than Vth01 and less than Vth00 can be applied to the read word line RWL. When the data stored in the storage node SN is "00", the first transistor T1 is turned off. When the data stored in the storage node SN is "01", "10" or "11", the first transistor T1 is turned on, and the degree of conduction is different when storing different data. Different voltages or currents can be detected on the read bit line RBL, thereby determining the data stored in the storage node.

[0084] In some embodiments, the first transistor T1 can be a read transistor, and the second transistor T2 can be a write transistor. The first word line 41 can be a read word line RWL, the first bit line 31 can be a read bit line RBL, the second word line 42 can be a write word line WWL, and the second bit line 32 can be a write bit line WBL.

[0085] Taking N-type transistors as an example, with the first transistor T1 and the second transistor T2 as examples, the operation of the memory cell is as follows:

[0086] During the write operation phase, a conduction level signal (which can be a high level signal) is applied to the write word line WWL to turn on the second transistor T2, and the voltage corresponding to the data to be written is applied to the write bit line WBL to write the data to the storage node SN.

[0087] During the read operation phase, a shutdown level signal (which can be a low level signal) is applied to the write word line WWL to turn off the second transistor T2. A read voltage is applied to the read word line RWL. Depending on the data stored in the memory node, the conduction state of the first transistor T1 varies. The data stored in the memory node SN is determined by detecting the signal on the read bit line RBL. Alternatively, the data stored in the memory node SN can be determined by detecting either the current or voltage on the read bit line RBL.

[0088] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0089] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: At least one memory cell, the memory cell including a first transistor and a second transistor stacked on a substrate in a direction perpendicular to the substrate, the second transistor being disposed on the side of the first transistor facing away from the substrate; the first transistor including a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer; the second transistor including a third gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer; The second semiconductor layer is connected to the third electrode and the fourth electrode respectively; the second gate electrode is connected to the third electrode; the first gate electrode extends in a direction perpendicular to the substrate; the first semiconductor layer surrounds the sidewall of the first gate electrode and encloses the bottom wall of the first gate electrode facing the substrate; the second gate electrode is disposed on the side of the first electrode away from the substrate and partially surrounds the first semiconductor layer; the second electrode is disposed on the side of the first electrode away from the substrate and surrounds the first semiconductor layer and is connected to the first semiconductor layer; the first electrode is at least connected to the bottom wall of the first semiconductor layer facing the substrate.

2. The semiconductor device according to claim 1, characterized in that, The first electrode is connected to the sidewall region where the distance between the first electrode and the bottom wall of the first semiconductor layer is less than or equal to a preset value.

3. The semiconductor device according to claim 1, characterized in that, The first electrode extends in a direction parallel to the substrate, and the second electrode extends in a direction parallel to the substrate.

4. The semiconductor device according to claim 1, characterized in that, The second gate electrode includes a first portion extending in a direction parallel to the substrate and a second portion extending in a direction perpendicular to the substrate; the first portion is disposed on the side of the first electrode facing away from the substrate, the second electrode faces the substrate, and the first portion surrounds the first gate electrode; the second portion is connected to the third electrode.

5. The semiconductor device according to claim 1, characterized in that, The third gate electrode extends in a direction perpendicular to the substrate, the second semiconductor layer surrounds the sidewall of the third gate electrode and encloses the bottom wall of the third gate electrode facing the substrate, and the third electrode and the fourth electrode are connected to the sidewall of the second semiconductor layer.

6. The semiconductor device according to claim 5, characterized in that, The third electrode extends in a direction parallel to the substrate, and the fourth electrode extends in a direction parallel to the substrate, and the third electrode and the fourth electrode are disposed in the same layer.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor device includes a multilayer memory cell array stacked along a direction perpendicular to the substrate. Each layer of the memory cell array includes a plurality of memory cells arranged in an array along a first direction and a second direction. The first electrode of the first transistor of the memory cell in the same row of the same layer is connected to the same first bit line; the fourth electrode of the second transistor of the memory cell in the same row of the same layer is connected to the same second bit line; the first gate electrode of the first transistor of the memory cell in the same position of different layers is connected to the same first word line; and the third gate electrode of the second transistor of the memory cell in the same position of different layers is connected to the same second word line.

8. A method for manufacturing a semiconductor device, characterized in that, include: The first transistor is formed on the substrate; The first transistor includes: a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer; the first gate electrode extends in a direction perpendicular to the substrate; the first semiconductor layer surrounds the sidewall of the first gate electrode and encloses the bottom wall of the first gate electrode facing the substrate; the second gate electrode is disposed on the side of the first electrode away from the substrate and partially surrounds the first semiconductor layer; the second electrode is disposed on the side of the first electrode away from the substrate and surrounds the first semiconductor layer and is connected to the first semiconductor layer; the first electrode is at least connected to the bottom wall of the first semiconductor layer facing the substrate. A second transistor is formed on the side of the first transistor away from the substrate; the second transistor includes a third gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer; the second semiconductor layer is connected to the third electrode and the fourth electrode respectively; the third electrode is connected to the second gate electrode.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The formation of the first transistor on the substrate includes: A first electrode, a first portion of a second gate electrode, and a second electrode are formed on a substrate, which are stacked sequentially and spaced apart along a direction perpendicular to the substrate. The first electrode, the first portion, and the second electrode overlap in their orthogonal projections onto the substrate. A first hole is formed that penetrates the second electrode and the first portion along a direction perpendicular to the substrate, and the bottom wall of the first hole exposes the first electrode; Based on the first hole, the first portion is laterally etched to a predetermined length to form a lateral groove, the bottom wall of the lateral groove being exposed in the first portion; a second gate insulating layer is formed to fill the lateral groove; A first semiconductor layer, a first gate insulating layer, and a first gate electrode filling the first hole are formed sequentially covering the bottom wall and side wall of the first hole. A second portion extending perpendicular to the substrate is formed as a second gate electrode. The second portion is connected to the first portion, and the distance between the second portion and the substrate on the side facing away from the substrate is greater than the distance between the first gate electrode and the substrate on the side facing away from the substrate.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The step of forming the second transistor on the substrate-away side of the first transistor includes: A conductive layer is formed on the side of the first transistor away from the substrate, and the conductive layer is connected to the second portion; A second hole is formed that penetrates the conductive layer along a direction perpendicular to the substrate and does not expose the first gate electrode. The second hole divides the conductive layer into a disconnected third electrode and a fourth electrode, and the third electrode is connected to the second portion. A second semiconductor layer, a second gate insulating layer, and a third gate electrode are formed to sequentially cover the bottom and sidewalls of the second hole.

11. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 7, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 8 to 10.

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