Gate negative trigger bidirectional thyristor

Abstract

The invention belongs to but is not limited to the technical field of semiconductor power devices, and discloses a gate negative trigger bidirectional thyristor, which comprises a tube core, and in a gate region of the tube core, a region, used for forming a gate P-type semiconductor, at the upper right corner is filled with an N + type semiconductor; the thyristor is only triggered and conducted in a second quadrant (MT1 is negative, MT2 is positive, and a gate pole G is a negative signal relative to MT1) and in a third quadrant (MT1 is positive, MT2 is negative, and the gate pole G is a negative signal relative to MT1); in a first quadrant (MT1 is negative, MT2 is positive, and a gate pole G is a positive signal relative to the MT1) and in a fourth quadrant (MT1 is positive, MT2 is negative, and the gate pole G is a positive signal relative to the MT1), a PN junction between the gate pole and the MT1 needs to be reversely punctured by 5-30V voltage, so that the triggering is difficult or the triggering cannot be realized.

Description

Technical Field

[0001] This invention belongs to, but is not limited to, the field of semiconductor power device technology, and particularly relates to a gate negative trigger bidirectional thyristor. Background Technology

[0002] Bidirectional thyristors (bidirectional silicon controlled rectifiers) are classified into four-quadrant and three-quadrant types according to their triggering quadrant: Four-quadrant bidirectional thyristor: Supports quadrant 1 (MT1) - MT2 + G is a positive signal relative to MT1), in the second quadrant (MT1). - MT2 + G is a negative signal relative to MT1), in the third quadrant (MT1). + MT2 - G is a negative signal relative to MT1), in the 4th quadrant (MT1). + MT2 - Triggered by a positive signal (G is positive relative to MT1), it has a wide range of applications, but its anti-interference capability is weak (easily mis-activated by positive signal interference). In existing technology, three-quadrant bidirectional thyristors support triggering in quadrants 1, 2, and 3, and their gates use P-type semiconductors. The positive signal triggering threshold is ≤3V, making them susceptible to mis-activated activation by positive interference; four-quadrant thyristors do not have an N-type gate structure. + In the second and third quadrants, the positive signal triggering sensitivity is ≥1mA, resulting in weak anti-interference capability. Therefore, there is an urgent need for a bidirectional thyristor that operates only in the second and third quadrants and is triggered by a negative signal, but cannot operate in the first and fourth quadrants.

[0003] I. Existing Technology 1: Triac Existing triac structures can enable current conduction in any direction, and have the characteristic of being triggered by positive or negative gate current in any quadrant (first to fourth quadrants) ([Ginza Semiconductor][1], [Wikipedia][2]). This device, widely used in AC phase control, has flexible gate trigger polarity and is not limited to negative triggering or triggering in a specific quadrant.

[0004] TRIAC cannot achieve quadrant-specific triggering control; it can still be triggered in the first and fourth quadrants, lacking the functionality required by this invention to "trigger with a negative gate signal only in the second and third quadrants." Furthermore, TRIAC's structural design is relatively generic, failing to introduce a specific N+ region in the gate area to regulate the reverse breakdown voltage of the PN junction, thus making it difficult to achieve stable negative triggering control.

[0005] II. Existing Technology 2: Standard Bidirectional SCR or Bidirectional Thyristor Some bidirectional thyristor structures can theoretically conduct under arbitrary polarity triggering, and their gates can accept both positive and negative triggering signals to achieve bidirectional conduction. They are similar to the back-to-back structure of two SCRs, achieving bidirectional switching characteristics through gate control.

[0006] Existing bidirectional thyristors cannot electrically limit or suppress the triggering quadrant, and conventional gate structures do not include an electrode G N+ region to increase the reverse breakdown voltage of the PN junction between the gate and MT1, making false triggering possible in the first and fourth quadrants. Such devices lack quadrant selectivity and structural control mechanisms, which are insufficient to prevent triggering in undesirable quadrants, thus affecting precise control and anti-interference performance. Summary of the Invention

[0007] To address the problems existing in the prior art, this invention provides a gate negative trigger bidirectional thyristor, which improves the ability to trigger in a specific quadrant and resist false triggering through structural improvements.

[0008] This invention is implemented as follows: a gate-negative triggered bidirectional thyristor includes a die, wherein the upper right corner region of the gate region of the die, used to form a gate P-type semiconductor, is N-type triggered bidirectional thyristor. + Type semiconductor filling, i.e., electrode GN + district.

[0009] The thyristor is only triggered and turned on in the second quadrant (MT1 is negative, MT2 is positive, and the gate G is a negative signal relative to MT1) and the third quadrant (MT1 is positive, MT2 is negative, and the gate G is a negative signal relative to MT1). In the first quadrant (MT1 is negative, MT2 is positive, and the gate G is a positive signal relative to MT1) and the fourth quadrant (MT1 is positive, MT2 is negative, and the gate G is a positive signal relative to MT1), the PN junction between the gate and MT1 needs to break down in reverse at a voltage of 5~30V, which makes triggering difficult or impossible.

[0010] Furthermore, the N + N-type semiconductors are formed through ion implantation or diffusion processes, and their doping concentration is higher than that of the N-type region around the die.

[0011] Furthermore, the back of the die is provided with N + district.

[0012] Furthermore, the front side of the die is provided with the N-type main electrode MT1. + district.

[0013] Furthermore, a support / insulation area is provided around the core.

[0014] Another object of the present invention is to provide a method for fabricating a gate negative-triggered bidirectional thyristor, comprising: Step 1, Substrate selection: An N-type semiconductor substrate is used to construct the basic structure of a bidirectional thyristor; Step 2, Gate Region Modification: High-concentration N2 is introduced into the original gate P-type boron region through ion implantation or diffusion processes. + Doping is performed, and the doping concentration (higher than the surrounding N-type region) and depth are controlled to stabilize the reverse breakdown voltage of the PN junction between the gate and MT1 at 5~30V.

[0015] First, this invention relates to a bidirectional thyristor that operates only in the second and third quadrants and is triggered by a negative signal, but cannot operate in the first and fourth quadrants. This reduces the possibility of false triggering and provides strong anti-interference capability. The invention significantly improves the resistance to false triggering: the high reverse breakdown threshold for positive signals in the first and fourth quadrants greatly reduces the risk of false triggering.

[0016] The present invention has a simple structure and process: it only uses the "P-type - N" gate region. + The replacement of "type" semiconductors is easily achieved through ion implantation or diffusion processes.

[0017] This invention offers precise scenario adaptation: it is suitable for circuits that require triggering only in the 2nd and 3rd quadrants and have stringent anti-interference requirements (such as power control, motor drive, industrial control, etc.).

[0018] Secondly, the inventiveness of this invention lies not only in the novelty of the device structure and process flow, but also in its application value and industry impact. Firstly, from the perspective of expected revenue and commercial value, this invention provides a bidirectional thyristor operating in a negative triggering mode, breaking through the limitation of traditional bidirectional thyristors that can only be triggered by a mixture of positive and negative signals. This technology enables the thyristor to operate stably in the second and third quadrants, using a negative signal as the triggering condition, providing a more suitable solution for specific circuits. This not only expands the application scenarios of bidirectional thyristors but also provides a reliable component foundation for special circuits requiring negative signal triggering, enhancing the commercial application value of the device in industrial control, power electronics, and special equipment.

[0019] The technical solution of this invention is the first of its kind proposed both internationally and domestically, representing a completely new concept in bidirectional thyristor triggering. For a long time, the industry has lacked a systematic negative triggering design and implementation method for bidirectional thyristors; therefore, this invention fills a technological gap in this area both domestically and internationally. This not only expands the field of thyristors but will also be a significant achievement in promoting the development of the domestic semiconductor device industry and fostering independent intellectual property rights and differentiated competitiveness.

[0020] This invention solves a long-standing and unresolved practical application problem. For a long time, there has been a strong demand for bidirectional thyristors triggered by negative signals in certain specialized circuits, but due to limitations in traditional structures and breakdown characteristics, a feasible solution has remained elusive. This invention, by introducing an electrode G N+ region into the gate region and stabilizing the reverse breakdown voltage of the PN junction between the gate and MT1, achieves for the first time that the device conducts only in the second and third quadrants through a negative trigger signal. This provides a feasible solution for designers of specific circuits, fulfilling a long-desired but previously unachieved technical need.

[0021] This invention also demonstrates a breakthrough in conventional industry perceptions and an overcoming of technological biases. Traditionally, bidirectional thyristors are generally considered to employ a P-type gate structure, with both positive and negative signals triggering conduction being a widely accepted industry norm. However, this invention innovatively creates a high-concentration GN+ electrode region in the gate area, constructing a novel structure that can only be triggered by negative signals. This approach breaks through the industry's fixed mindset regarding the singularity of gate structures, providing a completely different triggering mechanism, thus exhibiting significant creativity and non-obviousness.

[0022] This invention not only presents groundbreaking innovations in device structure, but also demonstrates significant progress in application value, industry standing, problem-solving, and overcoming technological biases. Its achievements have given new direction to the development of the mature bidirectional thyristor and provided solid theoretical and technical support for the innovative application of power electronic devices. Attached Figure Description

[0023] Figure 1 This is a perspective view of a common bidirectional three-quadrant thyristor provided by existing technology; Figure 2 This is a perspective view of the bidirectional two-quadrant thyristor of the present invention provided in an embodiment of the present invention; Figure 3 This is a flowchart of the fabrication method of the gate negative trigger bidirectional thyristor provided in the embodiment of the present invention; Figure 4 This is a cross-sectional view of a conventional bidirectional thyristor (single-stage glass passivation); Figure 5 This is a cross-sectional view of a bidirectional thyristor (single-mesa glass passivation) provided in an embodiment of the present invention; In the diagram: 1. P-region; 2. Electrode GN + Area 3; Back side N + Area 4; Main electrode MT1 N + Zone 5; Support / Insulation Zone. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0025] This invention introduces a high-concentration electrode GN+ region in the gate P region. By controlling the reverse breakdown voltage of the PN junction between the gate and MT1, the device is triggered to conduct only with a negative signal in the second and third quadrants. In contrast, existing TRIACs and bidirectional SCRs lack this quadrant selectivity, posing a risk of false triggering.

[0026] This invention constructs a stable and reliable trigger path in the device structure through regional N+ doping layout; while existing technologies generally rely on trigger level and timing control and lack a reliable structural suppression mechanism.

[0027] The design of this invention improves the reverse breakdown voltage threshold through local doping and spatial structure optimization, reduces the probability of false triggering caused by voltage fluctuations or interference, and makes the control more precise; current technology does not have a dedicated structure to support this.

[0028] like Figure 2 As shown, this embodiment of the invention provides a gate negative-triggered bidirectional thyristor, including a die, wherein the upper right corner of the gate region of the die, used to form a gate P-type semiconductor, is covered by N-type semiconductor. + Type semiconductor filling, that is, having electrodes GN + Zone 2. Figure 2 In the middle, electrode GN + Region 2 is located in the upper right corner of the gate region, adjacent to region P1 and without overlap; the back side N + Zone 3 (purple part in Figure 2) and the front main electrode MT1 N + Zone 4 (brown part in Figure 2) is located on both sides of the core, and support / insulation zone 5 (gray edge part in Figure 2) surrounds the core.

[0029] The thyristor is only triggered and turned on in the second quadrant (MT1 is negative, MT2 is positive, and the gate G is a negative signal relative to MT1) and the third quadrant (MT1 is positive, MT2 is negative, and the gate G is a negative signal relative to MT1). In the first quadrant (MT1 is negative, MT2 is positive, and the gate G is a positive signal relative to MT1) and the fourth quadrant (MT1 is positive, MT2 is negative, and the gate G is a positive signal relative to MT1), the PN junction between the gate and MT1 needs to break down in reverse at a voltage of 5~30V, which makes triggering difficult or impossible.

[0030] Furthermore, the N +N-type semiconductors are formed through ion implantation or diffusion processes, and their doping concentration is higher than that of the N-type region around the die.

[0031] Furthermore, the back of the die is provided with N + district.

[0032] Furthermore, the front side of the die is provided with the N-type main electrode MT1. + district.

[0033] Furthermore, a support / insulation area is provided around the core.

[0034] The structure of this gate-negative-triggered bidirectional thyristor consists of multiple functional regions. P-region 1 is located in the upper right corner of the gate region of the die. The area that should form a P-type semiconductor is filled by electrode GN+ region 2, thus forming a PN junction with special breakdown characteristics between the gate and MT1. The doping concentration of electrode GN+ region 2 is higher than that of the surrounding region, ensuring that the breakdown voltage of the PN junction is stable between 5 and 30V in reverse. This arrangement determines the triggering behavior of the device in different quadrants, ensuring that it can only achieve gate triggering with a negative signal in the second and third quadrants.

[0035] The back N+ region 3 is formed on the back side of the substrate. Together with the main electrode MT1 N+ region 4, it forms the main current path, thereby ensuring that the thyristor has a low on-state voltage drop and a high current carrying capacity after conduction. As the main contact layer of MT2, the back N+ region 3 reduces the ohmic contact resistance through high-concentration N+ doping, and at the same time accelerates carrier recombination in the reverse turn-off state, improving the device's turn-off speed and breakdown voltage.

[0036] The main electrode MT1, N+ region 4, is located on the front side of the die, adjacent to electrode G, N+ region 2, and P region 1. During operation, MT1 serves as the current input or output terminal, with the current direction determined by the quadrant. When a negative signal is input to the gate, the potential difference between MT1 and electrode G, N+ region 2, triggers the conduction of the PN junction, thereby guiding the main current to form a stable path between MT1 and the back N+ region 3. This design avoids positive signal triggering in the first and fourth quadrants, structurally ensuring negative gate triggering characteristics.

[0037] The supporting insulation region 5 is distributed around the device periphery, providing mechanical support, edge passivation, and insulation protection. Its main function is to limit edge leakage current, improve the reliability of the device under high-voltage operating conditions, and facilitate the assembly of the device with external packages during the manufacturing process. Overall, through a reasonable spatial layout and functional division of labor, the P region 1, electrode G N+ region 2, back N+ region 3, main electrode MT1 N+ region 4, and supporting insulation region 5 enable the bidirectional thyristor to achieve negative triggering only in a specific quadrant in the circuit, thereby avoiding false triggering and improving anti-interference capabilities.

[0038] Structural improvements in this invention embodiment: Compared to existing three-quadrant thyristors (Figure 1), this invention replaces the original P-type boron region with N-type in the gate region. + Type semiconductor region. Figure 1 explanation: The blank area is the boron region (P-region 1); the purple area is the N-type semiconductor region on the back of the die. + Area; the brown part is the main electrode MT1 N on the front of the die. + In Figure 1, position "6" of the gate region is a P-type boron region. This invention replaces the P-type boron region (corresponding to position "6" in Figure 1) in the upper right corner of the gate region with an N-type boron region. + Type semiconductor, forming electrode GN + Zone 2; Triggering principle: Quadrant 2 (MT1⁻, MT2) + (G is a negative signal relative to MT1): The PN junction between the gate and MT1 is forward biased, and can be triggered to conduct with a low voltage.

[0039] Quadrant 3 (MT1) + (MT2⁻, G is a negative signal relative to MT1): Similarly, the PN junction is forward biased and low voltage triggers conduction.

[0040] Quadrant 1 (MT1⁻, MT2) + G is a positive signal relative to MT1), in the 4th quadrant (MT1). + (MT2⁻, G is a positive signal relative to MT1): The PN junction between the gate and MT1 is reverse biased, requiring a reverse voltage of 5~30V to break down for triggering. Conventional trigger signals (a few volts) are difficult to meet, so triggering is difficult or not triggered, thus achieving shielding against positive signal interference.

[0041] like Figure 3 As shown, this embodiment of the invention provides a method for fabricating a gate-negative triggered bidirectional thyristor, comprising: Step 1, Substrate selection: An N-type semiconductor substrate is used to construct the basic structure of a bidirectional thyristor; Step 2, Gate Region Modification: High-concentration N2 is introduced into the original gate P-type boron region through ion implantation or diffusion processes. + Doping, controlling the doping concentration (higher than the surrounding N-type region) and depth, stabilizes the reverse breakdown voltage of the PN junction between the gate and MT1 at 5~30V.

[0042] This invention is specifically applied to low-frequency AC switching or phase control functions, with a negative trigger signal. Voltage: 600-1200V; Current: 1-40 Amperes; Trigger current in the second and third quadrants: 0.1-50mA.

[0043] The application of the gate negative trigger bidirectional thyristor in the motor drive circuit of the present invention is as follows: It is suitable for the drive control circuit of a three-phase asynchronous motor, which needs to achieve precise start-stop and speed regulation of the motor through a negative trigger signal, and has high requirements for electromagnetic interference protection (such as avoiding false triggering caused by power grid fluctuations or electromagnetic noise during motor operation).

[0044] Technical parameters Operating voltage: 600V Operating current: 10A Trigger quadrants: Only quadrant 2 (MT1 is negative, MT2 is positive, and the gate G is a -2 to -3V negative signal relative to MT1) and quadrant 3 (MT1 is positive, MT2 is negative, and the gate G is a -2 to -3V negative signal relative to MT1). Trigger current: 0.5~10mA (under negative signal) Anti-interference characteristics: In quadrants 1 and 4, the PN junction between the gate and MT1 needs to break down in reverse at 8~12V. Conventional positive interference signals (≤5V) cannot trigger conduction. Working principle: In the motor drive circuit, when the motor needs to be started, a negative trigger signal in the second or third quadrant is input to the gate of the thyristor through the control circuit, causing the thyristor to conduct and the motor to be connected to the power supply; when it needs to be stopped or the speed adjusted, the negative trigger signal is cut off, and the thyristor is turned off. Because it only responds to negative trigger signals and requires a high reverse breakdown voltage for positive signals, it can effectively resist positive electromagnetic interference generated during motor operation and avoid malfunctions.

[0045] Example 2: Application of gate negative triggering bidirectional thyristors in industrial power control systems For output control of industrial high-frequency power supplies (such as photovoltaic inverters and industrial heating power supplies), it is necessary to stably adjust the power output power through negative trigger signals, and it is required to have strong anti-interference capabilities in high-voltage environments (such as avoiding abnormal output caused by positive signal noise inside the power supply system).

[0046] Technical parameters Operating voltage: 1200V Operating current: 30A Trigger quadrants: Only quadrant 2 (MT1 is negative, MT2 is positive, and the gate G is a -3 to -4V negative signal relative to MT1) and quadrant 3 (MT1 is positive, MT2 is negative, and the gate G is a -3 to -4V negative signal relative to MT1). Trigger current: 1~30mA (under negative signal) Anti-interference characteristics: In quadrants 1 and 4, the PN junction between the gate and MT1 needs to break down in reverse at a voltage of 5~30V. Conventional positive interference signals (≤8V) cannot trigger conduction. Working principle: In industrial power control systems, thyristors act as power switching elements, controlling the conduction angle of the power output through the switching on and off of negative trigger signals to achieve power regulation. Because they only respond to negative trigger signals in the 2nd and 3rd quadrants and require a 5-30V reverse breakdown voltage for positive signals, they can effectively shield positive signal noise within the power system (such as pulse interference generated by high-frequency switching), ensuring stable power output and meeting the power supply accuracy requirements of industrial equipment.

[0047] The gate-negative triggered bidirectional thyristor provided in this embodiment of the invention includes: 1. Material sheet: N-type, 111 crystal orientation, resistivity: 25-35Ω`cm, sheet thickness 210-240um; 2. Cleaning: Use solution #3, solution #1, and solution #2. 3. Primary oxidation: Oxide layer thickness 1.6µm; 4. Photolithography in the isolation zone; 5. Cleaning: Use solution #3, solution #1, and solution #2. 6. Boron pre-expansion in the isolation zone: boron latex source or BBr3, cube: 2-5Ω / □; 7. Cleaning: Use hydrofluoric acid to remove BSG from the surface; use solution No. 3, solution No. 1, and solution No. 2; 8. Boron-based expansion in the isolation zone: generally 1270-1286℃, nitrogen and oxygen gases; time: 100-160h; 9. Cleaning: Rinse the surface oxide layer with hydrofluoric acid, using solution No. 3, solution No. 1, and solution No. 2; 10. Pre-expansion of dilute boron: boron latex source, 50-54Ω / □ (square). 11. Cleaning: Rinse the surface oxide layer with hydrofluoric acid, using solution No. 3, solution No. 1, and solution No. 2; 12. Light boron oxidation: 80-86 Ω / □ (square) 13. Cleaning: Rinse the surface oxide layer with hydrofluoric acid, using solution No. 3, solution No. 1, and solution No. 2; 14. Dilute boron main expansion: temperature 1255℃, gas nitrogen and oxygen; time: 30h; block size 44-52Ω / hole; 15. Remove the surface oxide layer; 16. Pre-expansion and main expansion of concentrated boron: Injection of boron latex source (surface concentration as needed), generally 5-80 Ω / □; (whether to perform high-temperature push-bonding of concentrated boron depends on the needs.) 17. Oxidation: Oxidation layer thickness 1.6µm; 18. Photolithography of the cathode region (photolithography of the gate cathode region and the normal cathode region) 19. Cleaning: Solution No. 3, Solution No. 1, Solution No. 2; 20. Phosphorus pre-expansion: Block: 1.0~1.2Ω / □; 21. Cleaning: Rinse off PSG with hydrofluoric acid, using solution No. 3, solution No. 1, and solution No. 2; 22. Phosphorus main expansion: The main expansion temperature and time are determined according to the IGT requirements, generally between 1200-1255℃, with nitrogen, hydrogen, and oxygen gases; time: 1-6 hours. 23. Groove area photolithography.

[0048] Example 1

[0049] In one specific embodiment, an N-type 111-oriented silicon wafer is provided as a substrate, with a resistivity of 28 Ω·cm and a thickness of 220 μm. In the upper right corner of the gate region P-region 1 on the front side of the substrate, an electrode G N+ region 2 is formed using an ion implantation process, with the doping concentration controlled at 1 × 10^20 cm^-3, higher than the background concentration of 1 × 10^16 cm^-3 in the surrounding N-type region. Thus, the PN junction between the gate and MT1 possesses a stable reverse breakdown voltage of 5-30V, allowing the device to be triggered by negative signals only in the second and third quadrants.

[0050] In another embodiment, electrode G N+ region 2 is obtained by pre-depositing BBr3 and pushing the junction at high temperature, with a diffusion depth of 0.8 μm and a sheet resistance of approximately 3 Ω / □. Since electrode G N+ region 2 replaces the original P-type gate region, the possibility of positive signal triggering in the first and fourth quadrants is avoided, thereby achieving gate negative triggering characteristics in the structure.

[0051] Example 2

[0052] In another specific embodiment, phosphorus diffusion is performed on the back side of the substrate using POCl3 source gas. The process is completed at a temperature of 1250°C for 3 hours to form a back-side N+ region 3 with a doping concentration of 5 × 10^19 cm^-3. This back-side N+ region 3 serves as the contact region for MT2, forming a current loop with the front electrode of MT1 when the device is turned on, effectively reducing the overall on-state voltage drop.

[0053] In another embodiment, the back-side N+ region 3 is prepared by ion implantation and annealed at 1255°C for 2 hours under a nitrogen and oxygen atmosphere to form a uniform doping distribution. This structure accelerates carrier recombination when the device is turned off, avoids an increase in reverse leakage current, and improves breakdown voltage performance.

[0054] Example 3

[0055] In one specific embodiment, a main electrode MT1 N+ region 4 is formed on the front side of the die using a phosphorus ion implantation process with an implantation energy of 60 keV and a dose of 1 × 10^15 cm^-2, followed by annealing at 1200°C for 1 hour. This MT1 N+ region 4 is arranged adjacent to the gate electrode G N+ region 2, guiding current from MT1 to the back N+ region 3 under the action of a negative trigger signal, ensuring stable conduction.

[0056] In another embodiment, the MT1 N+ region 4 is formed using a diffusion process, with a sheet resistance controlled at 1.2 Ω / □ and a depth of approximately 0.6 μm. This structure significantly reduces the forward voltage drop during device operation while improving current carrying capacity, making it suitable for high current density environments.

[0057] Example 4

[0058] In one specific embodiment, a supporting insulating region 5 is fabricated around the device, with a 1.6 μm thick oxide layer formed using the LOCOS process, and oxide filling is injected at the edges. This region provides electrical insulation to prevent edge leakage current and mechanically supports the die.

[0059] In another embodiment, the supporting insulating region 5 is designed as a composite structure, including a silicon dioxide layer and a silicon nitride passivation layer. The silicon dioxide layer has a thickness of 1.8 μm, and the silicon nitride layer has a thickness of 0.3 μm. This design effectively limits electric field concentration during high-voltage operation of the device, ensuring the reliability of the edge region, while also providing a fixed substrate for external soldering in subsequent packaging.

[0060] Example 5

[0061] In one specific embodiment, an N-type 111-oriented silicon wafer with a resistivity of 30 Ω·cm and a thickness of 230 μm is first provided. A 1.6 μm thick oxide layer is formed through a single oxidation process, and an isolation region is defined by photolithography. A boron diffusion process is used, resulting in a surface resistivity of approximately 3 Ω / □ for the isolation region. After main diffusion, a stable isolation layer is formed. An electrode G N+ region 2 is introduced into the gate P region 1, stabilizing the reverse breakdown voltage of the PN junction between the gate and MT1 at 5-30V.

[0062] In another embodiment, electrode G N+ region 2 is formed using an ion implantation process with a dose of 5 × 10^15 cm^-2, and annealing conditions of 1270°C for 2 hours. N+ region 3 is formed on the back side using a phosphorus diffusion process at 1230°C for 4 hours, with a nitrogen and oxygen mixture as the protective gas. The resulting device exhibits negative gate triggering characteristics, and can only be triggered and turned on in the second and third quadrants.

[0063] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A gate-negative triggered bidirectional thyristor, characterized in that, The thyristor includes a die in which an electrode GN+ region is formed in the gate region P of the die. The electrode GN+ region replaces the original P-type doped region forming the gate, thereby forming a PN junction with a specific reverse breakdown voltage between the gate and the main electrode MT1, so that the thyristor can be triggered to conduct only by a negative signal under the conditions of the second and third quadrants.

2. The gate negative-triggered bidirectional thyristor according to claim 1, characterized in that, The doping concentration of the N+ region of the electrode G is higher than that of the N-type region around the die, so as to ensure that the reverse breakdown voltage of the PN junction between the gate and MT1 is stable in the range of 5-30V.

3. A gate-negative triggered bidirectional thyristor, characterized in that, The back side of the die has a back N+ region, which serves as the contact area of ​​MT2 and provides a low contact resistance path to form a current path with the main electrode MT1 N+ region when the thyristor is turned on.

4. The gate-negative-triggered bidirectional thyristor according to claim 3, characterized in that, The back N+ region is formed by high-concentration doping to reduce ohmic contact resistance and accelerate carrier recombination during turn-off.

5. A gate-negative-triggered bidirectional thyristor, characterized in that, The die has a main electrode MT1 N+ region on the front side. The main electrode MT1 N+ region is adjacent to the electrode G N+ region and the P region, and is used to establish a main current path from MT1 to the back N+ region when a negative signal is triggered.

6. The gate-negative triggered bidirectional thyristor according to claim 5, characterized in that, The main electrode MT1 N+ region can significantly reduce the forward conduction voltage drop and improve the current carrying capacity during the thyristor's conduction process.

7. A gate-negative-triggered bidirectional thyristor, characterized in that, The die is surrounded by a support and insulation area, which provides mechanical support, edge passivation and insulation protection for the device, thereby reducing edge leakage current and improving reliability under high voltage conditions.

8. The gate-negative triggered bidirectional thyristor according to claim 7, characterized in that, The supporting insulating region provides a support platform during device packaging, enabling the device to be stably assembled with external electrodes.

9. A method for fabricating a gate-negative triggered bidirectional thyristor, characterized in that, Includes the following steps: Step 1: Provide an N-type semiconductor substrate with a crystal orientation of 111, a resistivity of 25-35 Ω·cm, and a thickness of 210-240 μm; Step two: An isolation region is formed using oxidation, photolithography, and boron pre-expansion. Step 3: Introduce a high-concentration electrode G N+ region in the gate region P region by ion implantation or diffusion to stabilize the reverse breakdown voltage of the PN junction between the gate and MT1 at 5-30V.

10. The preparation method according to claim 9, characterized in that, The N+ region on the back side is formed by phosphorus diffusion, with a diffusion temperature range of 1200-1255℃ and a time of 1-6 hours, using nitrogen, hydrogen, and oxygen as protective and auxiliary atmospheres.

Images