Chip system, time difference determination method, storage medium and electronic equipment

Abstract

Disclosed are a chip system, a time difference determination method, a storage medium and an electronic device, the chip system comprising: a first system-on-chip and a second system-on-chip, the first system-on-chip comprising a processor and a DMA controller; the processor is used for starting the DMA controller so as to indicate the DMA controller to execute a plurality of data handling tasks in the configuration chain table; the DMA controller is used for reading a first timestamp corresponding to the first on-chip system based on the first data handling task and writing the first timestamp into a first storage address of the memory; based on the second data handling task, reading a second timestamp corresponding to the second on-chip system and writing the second timestamp into a second storage address of the memory; transmitting an interrupt signal to a processor in response to the completion of execution of the plurality of data handling tasks; and the processor is also used for responding to the interrupt signal, reading the first timestamp and the second timestamp, and determining a time difference between the first system-on-chip and the second system-on-chip based on the first timestamp and the second timestamp. Under the condition that hardware cost is not increased, it can be ensured that the precision of the time difference reaches the microsecond level or even the nanosecond level, and the requirement of a high-precision scene is met.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and in particular to a chip system, a time difference determination method, a storage medium, and an electronic device. Background Technology

[0002] With the rapid development of autonomous driving technology, Peripheral Component Interconnect Express (PCIe), due to its high bandwidth and low latency, has become a core transmission link in applications such as autonomous driving data acquisition and data feedback. To ensure data consistency and system real-time performance in autonomous driving scenarios, it is necessary to accurately measure the time difference between the local clock of the local PCIe device and the remote clock of the remote PCIe device. This is to enable high-precision time synchronization between the local and remote PCIe devices, or to analyze the PCIe link latency between them.

[0003] However, due to limitations in software scheduling and hardware conditions, the time difference between the local clock of the local PCIe device and the remote clock of the remote PCIe device is usually in the millisecond range, which is not very accurate and cannot meet the needs of high-precision scenarios. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a chip system, a time difference determination method, a storage medium, and an electronic device to solve the problem that the low accuracy of time difference determination cannot meet the requirements of high-precision scenarios.

[0005] A first aspect of this disclosure provides a chip system, including: a first system-on-a-chip (SoC) and a second SoC, connected via a high-speed peripheral component interconnect link. The first SoC includes a processor and a direct memory access controller (DMC). The processor is configured to initiate the DMC to instruct it to execute multiple data transfer tasks in a configuration list. The DMC is configured to: read a first timestamp corresponding to the first SoC and write the first timestamp to a first storage address in memory based on a first data transfer task in the multiple data transfer tasks; read a second timestamp corresponding to the second SoC and write the second timestamp to a second storage address in memory based on a second data transfer task in the multiple data transfer tasks; transmit an interrupt signal to the processor in response to the completion of the execution of the multiple data transfer tasks in the configuration list; and, in response to the interrupt signal, read the first timestamp from the first storage address in memory, read the second timestamp from the second storage address in memory, and determine a time difference between the first SoC and the second SoC based on the first timestamp and the second timestamp.

[0006] A second aspect of this disclosure provides a time difference determination method applied to a chip system, the chip system including a first system-on-a-chip (SoC) and a second SoC, the first SoC and the second SoC being connected via a high-speed peripheral component interconnect link; the method includes: activating a direct memory access controller (DMC) in the first SoC to instruct the DMC to execute multiple data transfer tasks in a configuration list; reading a first timestamp corresponding to the first SoC based on a first data transfer task among the multiple data transfer tasks and writing the first timestamp to a first storage address in memory; reading a second timestamp corresponding to the second SoC based on a second data transfer task among the multiple data transfer tasks and writing the second timestamp to a second storage address in memory; generating an interrupt signal in response to the completion of the execution of the multiple data transfer tasks in the configuration list; reading the first timestamp from the first storage address in memory and reading the second timestamp from the second storage address in memory in response to the interrupt signal; and determining a time difference between the first SoC and the second SoC based on the first timestamp and the second timestamp.

[0007] A third aspect of this disclosure provides a computer program product that, when an instruction processor in the computer program product is executed, performs the time difference determination method of the second aspect of this disclosure.

[0008] A fourth aspect of this disclosure provides an electronic device comprising: a processor; a memory for storing processor-executable instructions; and a processor for reading executable instructions from the memory and executing the instructions to implement the time difference determination method of the second aspect embodiment described above.

[0009] This disclosure provides a chip system in which a processor starts a DMA controller and instructs the DMA controller to execute multiple data transfer tasks in a configuration linked list. Since the DMA controller operates independently of the processor after startup, it can automatically and continuously execute data transfer tasks in the configuration linked list, starting from the first node. Therefore, the DMA controller can sequentially read the first timestamp (e.g., local timestamp) of the first on-chip system and the second timestamp (e.g., remote timestamp) of the second on-chip system, and the two read operations are not affected by processor scheduling. This ensures that the time difference between the read local and remote timestamps has extremely high precision, reaching the microsecond or even nanosecond level. This disclosure utilizes the SG characteristics of the DMA controller in the on-chip system and configures an SG linked list, enabling the DMA controller to automatically and continuously read the local and remote timestamps without being affected by system scheduling. Therefore, without increasing hardware costs, it can ensure the time difference precision reaches the microsecond or even nanosecond level, meeting the needs of high-precision scenarios. Attached Figure Description

[0010] Figure 1 This is a schematic diagram illustrating communication between PCIe devices via a PCIe link, provided in an exemplary embodiment of this disclosure.

[0011] Figure 2 This is a schematic diagram of the structure of a chip system provided in an exemplary embodiment of this disclosure.

[0012] Figure 3 This is a schematic diagram of the structure of a chip system provided in another exemplary embodiment of this disclosure.

[0013] Figure 4 This is a schematic diagram of the structure of a chip system provided in yet another exemplary embodiment of this disclosure.

[0014] Figure 5 This is a flowchart illustrating a time difference determination method provided in an exemplary embodiment of this disclosure.

[0015] Figure 6 This is a flowchart illustrating a time difference determination method provided in another exemplary embodiment of this disclosure.

[0016] Figure 7 This is a flowchart illustrating a time difference determination method provided in yet another exemplary embodiment of this disclosure.

[0017] Figure 8 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0018] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0019] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0020] Application Overview

[0021] Figure 1 This is a schematic diagram illustrating communication between PCIe devices via a PCIe link, as shown below. Figure 1 As shown, a local PCIe device includes a local PCIe controller and a local clock, while a remote PCIe device includes a remote PCIe controller and a remote clock. The local and remote PCIe devices can communicate via a PCIe link. Since the local and remote clocks are clocks in two different PCIe devices, there may be a time difference between them, causing the time of the local PCIe device to be out of sync with the time of the remote PCIe device.

[0022] For example, in applications such as autonomous driving data acquisition and autonomous driving data feedback, the requirements for the stability and accuracy of time synchronization are very stringent. Therefore, it is necessary to synchronize the local clock of the local PCIe device and the remote clock of the remote PCIe device to ensure data consistency and system real-time performance.

[0023] Without hardware-level timestamp capture capabilities, PCIe devices cannot achieve high-precision clock synchronization via Ethernet GPTP (Generalized Precision Time Protocol). In this case, time synchronization between local and remote PCIe devices can be achieved through processor scheduling. For example, the processor reads the local timestamp of the local clock and the remote timestamp of the remote clock, calculates the time difference between the two timestamps, and then synchronizes the local and remote PCIe devices based on this difference. However, this synchronization scheme suffers from millisecond-level delays due to potential preemption by higher-priority tasks or interrupts between the two read operations. Consequently, the accuracy of time synchronization is affected by system scheduling, making it difficult to meet the high-precision requirements of scenarios such as autonomous driving.

[0024] In some examples, when data is transmitted between a local PCIe device and a remote PCIe device via a PCIe link, a link latency exists. This PCIe link latency is a key indicator affecting the real-time performance of data transmission and the overall system throughput. The time difference between the local clock of the local PCIe device and the remote clock of the remote PCIe device can be obtained through software or hardware measurement methods to further determine the PCIe link latency. However, software measurement of PCIe link latency is affected by factors such as system scheduling and interrupt handling, resulting in measurement errors at the millisecond level, which is insufficient for high-precision scenarios. Hardware measurement of PCIe link latency requires dedicated hardware instruments, leading to high measurement costs and cumbersome operation.

[0025] In summary, whether performing high-precision time synchronization between local and remote PCIe devices, or measuring the PCIe link latency between them, it is necessary to determine the time difference between the local clock of the local PCIe device and the remote clock of the remote PCIe device. Because the accuracy of this time difference is limited by software scheduling and hardware constraints, it is typically only in the millisecond range, which is poor and cannot meet the requirements of high-precision scenarios, thus affecting the accuracy of time synchronization and link latency.

[0026] Exemplary System

[0027] Figure 2 This is a schematic diagram of the structure of a chip system, such as... Figure 2 As shown, the chip system 20 includes a first system-on-a-chip (SoC) 201 and a second SoC 202, which are connected via a high-speed peripheral interconnect PCIe link. The first SoC 201 includes a processor 2011, a Direct Memory Access (DMA) controller 2012, and a first clock 2013. The second SoC 202 includes a second clock 2021.

[0028] For example, the first system-on-chip 201 and the second system-on-chip 202 are two independent chips that can communicate with each other via a PCIe link. For instance, the first system-on-chip can be a local PCIe device, and the second system-on-chip 202 can be a remote PCIe device (also known as a peer PCIe device). Therefore, the clock module (such as the first clock 2013) in the first system-on-chip 201 can be called the local clock, and the clock module (such as the second clock 2021) in the second system-on-chip 202 can be called the remote clock or peer clock. The timestamp corresponding to the local clock is the local timestamp, and the timestamp corresponding to the remote clock is the remote timestamp or peer timestamp.

[0029] In some examples, the local timestamp and the remote timestamp can be the time of the Real-Time Clock (RTC) module or the time of the network interface card (NIC) module. This disclosure does not limit the type of the local timestamp and the remote timestamp.

[0030] Processor 2011 is used to start DMA controller 2012 to instruct DMA controller 2012 to execute multiple data transfer tasks in the configuration list.

[0031] For example, the configuration list may include multiple data transfer tasks, each of which can be represented by a node in the configuration list. Therefore, multiple nodes in the configuration list represent multiple data transfer tasks respectively, and the configuration list can be regarded as the task list of the DMA controller 2012.

[0032] In some examples, the linked list can be configured as a scatter-gather (SG) linked list. An SG linked list typically consists of multiple nodes, each containing a source address, a destination address, a data length (such as the number of bytes in the clock register), and a pointer to the next node. Each node in the SG linked list is used to perform a data transfer task. Based on the data length in the node, data stored at the source address can be transferred to the destination address, and then the data transfer task corresponding to the next node is executed according to the pointer to the next node in that node.

[0033] The processor 2011 can pre-build a configuration list in memory and write the starting address of the configuration list in memory into the register of the DMA controller 2012. This memory can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR) or off-chip memory. This disclosure does not limit the type of memory; the following embodiments use DDR memory as an example for illustrative purposes.

[0034] After the configuration list is constructed, the processor 2011 can start the DMA controller 2012 via a write operation. For example, the processor 2011 can write a preset value into the control / command register of the DMA controller 2012. This write operation is equivalent to a start command, used to start the DMA controller 2012 and instruct the DMA controller 2012 to begin executing tasks in the configuration list.

[0035] Once the DMA controller 2012 is started, it can automatically and continuously execute data transfer tasks in the SG linked list, starting from the first node. Therefore, during the execution of data transfer tasks in the SG linked list, the DMA controller 2012 does not require intervention from the processor 2011, and the processor 2011's resources can be released to execute other tasks.

[0036] For example, after processor 2011 starts DMA controller 2012, DMA controller 2012 can start from the first node of the SG linked list, read data from the source address according to the configuration in the first node, and write the data to the target address. After completing the data transfer in the first node, DMA controller 2012 finds the next node through the pointer in the first node and continues to execute data transfer until it finds an empty node at the end of the SG linked list, indicating that all data transfer tasks in the SG linked list have been completed. During the execution of multiple data transfer tasks in the SG linked list, DMA controller 2012 does not require intervention from processor 2011; therefore, the data transfer process is not affected by processor scheduling.

[0037] In order to determine the time difference between the first clock 2013 of the first system-on-chip 201 and the second clock 2021 of the second system-on-chip 202, it is necessary to first read the local timestamp (e.g., the first timestamp) of the first clock 2013 and the remote timestamp (e.g., the second timestamp) of the second clock 2021. Therefore, the processor 2011 can read the local timestamp and the remote timestamp by constructing a configuration linked list.

[0038] For example, the configuration linked list may include multiple data transfer tasks, including a first data transfer task and a second data transfer task. The first data transfer task reads a local timestamp and writes it to a first storage address. The source address of the first data transfer task is the physical address of the first clock register in the first on-chip system, and the destination address of the first data transfer task is the first storage address. The first clock register may be the clock register corresponding to the first clock of the first on-chip system, and the data length of the first data transfer task may be the number of bytes in the first clock register.

[0039] The second data transfer task is used to read the remote timestamp and write it to the second storage address. The source address of the second data transfer task is the PCIe address of the second clock register in the second on-chip system, and the destination address is the second storage address. The second clock register can be the clock register corresponding to the second clock of the second on-chip system, and the data length of the second data transfer task can be the number of bytes in the second clock register.

[0040] For example, a configuration list can include two nodes, node 1 and node 2. Node 1's source address is the physical address of the local clock's register, and its destination address is local DDR address 1. Based on node 1's configuration, the local timestamp can be read from the local clock's register physical address and written to DDR address 1. Node 2's source address is the PCIe address of the remote clock, and its destination address is DDR address 2. Based on node 2's configuration, the remote timestamp can be read from the remote clock's PCIe address and written to DDR address 2. Using this configuration list, the local clock's local timestamp can be moved to DDR address 1 first, and then the remote clock's remote timestamp can be moved to DDR address 2.

[0041] For example, a configuration list can include two nodes, node 1 and node 2. Node 1's source address is the PCIe address of the remote clock, and its destination address is DDR address 1. Based on node 1's configuration, the remote timestamp can be read from the remote clock's PCIe address and written to DDR address 1. Node 2's source address is the physical address of the local clock's register, and its destination address is the local DDR address 2. Based on node 2's configuration, the local timestamp can be read from the local clock's physical register address and written to DDR address 2. Using this configuration list, the remote timestamp of the remote clock can be moved to DDR address 1 first, and then the local timestamp of the local clock can be moved to DDR address 2.

[0042] The configuration linked list constructed in this disclosure can either first transfer the local timestamp of the local clock and then transfer the remote timestamp of the remote clock, or it can transfer the remote timestamp of the remote clock first and then transfer the local timestamp of the local clock. This disclosure does not limit this approach. The following embodiments use the example of transferring the local timestamp of the local clock first and then the remote timestamp of the remote clock for illustrative purposes. It should be noted that whether the local timestamp or the remote timestamp is transferred first has no impact on the accuracy of the time difference calculation.

[0043] The DMA controller 2012 is configured to read the first timestamp corresponding to the first on-chip system 201 and write the first timestamp to a first storage address in memory based on the first data transfer task among multiple data transfer tasks; read the second timestamp corresponding to the second on-chip system 202 and write the second timestamp to a second storage address in memory based on the second data transfer task among multiple data transfer tasks; and transmit an interrupt signal to the processor in response to the completion of multiple data transfer tasks in the configuration list.

[0044] For example, after the DMA controller 2012 starts up, it can automatically and continuously execute the data transfer tasks in the SG linked list, starting from the first node and proceeding node by node, according to the configuration linked list. To ensure that the first system-on-chip 201 can read the local timestamp and the remote timestamp, the first clock 2013 of the first system-on-chip 201 and the second clock 2021 of the second system-on-chip 2021 can be mapped to the memory address space of the processor 2011 through system software, thereby allowing the processor 2011 or the DMA controller 2012 to access the memory via memory-mapped I / O (MMIO).

[0045] When reading the first timestamp (also known as the local timestamp), the DMA controller 2012 can read the first timestamp from the physical address of the first clock register of the first on-chip system based on the first data transfer task. When reading the second timestamp (also known as the remote timestamp), the DMA controller 2012 can read the second timestamp from the second clock register of the second on-chip system based on the second data transfer task.

[0046] like Figure 2 As shown, taking the configuration list indicating that the local clock's local timestamp is transferred first, followed by the remote clock's remote timestamp, as an example, after the DMA controller 2012 starts, it executes the first data transfer task according to the configuration of node 1. It reads the local timestamp ts_local from the local clock register of the first on-chip system 201 and writes it to DDR address 1. Then, according to the configuration of node 2, it executes the second data transfer task, reading the remote timestamp ts_remote from the remote clock register of the second on-chip system 202 and writing it to DDR address 2. When all data transfer tasks in the configuration list have been completed, the DMA controller 2012 transmits an interrupt signal to the processor 2011 to inform it that all data transfer tasks have been completed.

[0047] When the DMA controller 2012 reads the local timestamp ts_local and the remote timestamp ts_remote respectively from nodes 1 and 2 in the SG linked list, these two read operations are automatically and consecutively executed by the DMA controller 2012. Therefore, the entire read process is not affected by the scheduling of the processor 2011; for example, it will not be preempted by high-priority tasks or interrupts that the processor needs to execute between the two read operations. Therefore, this disclosure, through the SG characteristics of the DMA controller 2012, can ensure that the time difference calculation result between the read local timestamp ts_local and the remote timestamp ts_remote has extremely high accuracy, reaching the microsecond or even nanosecond level.

[0048] like Figure 3 As shown, the first system-on-a-chip 201 further includes a first communication controller 2014, and the second system-on-a-chip 202 further includes a second communication controller 2022. The first communication controller 2014 and the second communication controller 2022 can be PCIe controllers. For example, the first communication controller 2014 can be a local PCIe controller, and the second communication controller 2022 can be a remote PCIe controller.

[0049] The DMA controller 2012 is specifically used to generate a request message based on the PCIe address in the second data transfer task and transmit the request message to the first communication controller.

[0050] The first communication controller 2014 is used to transmit request messages to the second communication controller 2022 in the second system-on-chip 202 via a PCIe link.

[0051] The second communication controller 2022 is used to respond to the request message, read the second timestamp corresponding to the second system on chip 202, and transmit the response message to the first communication controller 2014 through the PCIe link.

[0052] The first communication controller 2014 is used to obtain the second timestamp corresponding to the second system-on-chip 202 based on the response message.

[0053] For example, when reading the remote timestamp of the remote clock, the system software can map the second clock 2021 of the second system-on-chip 2021 to the memory address space of the processor 2011, for example, mapping the address of the second clock register value of the second clock 2021 to the PCIe address space. Therefore, subsequent read and write operations on this PCIe address will be converted by the PCIe controller into a Transaction Layer Packet (TLP) conforming to the PCIe protocol specification, and transmitted via the PCIe link to the peer device (such as the second system-on-chip 202), where it will parse and respond accordingly.

[0054] For example, such as Figure 3As shown, when the DMA controller 2012 executes the second transfer task corresponding to node 2 in the SG linked list, since the source address corresponding to node 2 is the PCIe address of the remote clock, the DMA controller 2012 will transmit a request message (such as a PCIe transaction layer packet) to the first communication controller 2014. After receiving the PCIe TLP, the first communication controller 2014 will further transmit the PCIe TLP to the second communication controller 2022 in the second system-on-chip 202 via the PCIe link. After receiving the PCIe transaction layer packet, the second communication controller 2022 will read the second timestamp of the second clock register of the second system-on-chip 202, and then send a response message including the second timestamp back to the first communication controller 2014 via the PCIe link. After receiving the response message, the first communication controller 2014 can obtain the second timestamp corresponding to the second system-on-chip 202 based on the response message.

[0055] This embodiment of the disclosure configures an SG linked list so that after reading the local timestamp, the remote timestamp can be read immediately, ensuring that the two read operations—reading the local timestamp and reading the remote timestamp—are not affected by system scheduling. Furthermore, the time interval between the two read operations is merely the hardware time required for the DMA controller 2012 to switch SG nodes and perform two MMIO accesses, typically on the order of microseconds or even nanoseconds, thus ensuring high accuracy of the determined time difference.

[0056] In some embodiments, the processor 201 is further configured to periodically start the DMA controller 2012 according to a preset period to instruct the DMA controller 2012 to periodically execute multiple data transfer tasks in a configuration list.

[0057] For example, since the first clock 2013 and the second clock 2021 are clock modules in two independent chips, the time difference between the local clock and the remote clock can be determined periodically, whether in time synchronization scenarios or in PCIe link latency measurement scenarios. For instance, the processor 2011 can periodically start the DMA controller 2012 according to a preset time period, so that the DMA controller 2012 sequentially executes multiple data transfer tasks in the configuration list according to the time period. That is, after creating the configuration list, the processor 2011 can periodically start the DMA controller 2012 to execute multiple data transfer tasks in the configuration list, thereby periodically calculating the time difference for time synchronization or PCIe link latency measurement.

[0058] The processor 2011 is also configured to, in response to an interrupt signal, read a first timestamp from a first memory address in memory, read a second timestamp from a second memory address in memory, and determine a time difference between the first system-on-chip 201 and the second system-on-chip 202 based on the first timestamp and the second timestamp.

[0059] For example, after the DMA controller 2012 writes the local timestamp and the remote timestamp into the memory address respectively, it will transmit an interrupt signal to the processor 2011. After receiving the interrupt signal, the processor 2011 can read the local timestamp and the remote timestamp from the memory respectively and calculate the time difference between the local timestamp and the remote timestamp.

[0060] For example, such as Figure 3 As shown, after the DMA controller 2012 writes the local timestamp ts_local to DDR address 1 and the remote timestamp ts_remote to DDR address 2, since all tasks in the SG linked list have been completed, the DMA controller 2012 will transmit an interrupt signal to the processor 2011. Upon receiving the interrupt signal, the processor 2011 can read the local timestamp ts_local from DDR address 1 and the remote timestamp ts_remote from DDR address 2, and calculate the time difference between the local and remote timestamps.

[0061] For example, the time difference offset can be the remote timestamp ts_remote minus the local timestamp ts_local, or the local timestamp ts_local minus the remote timestamp ts_remote. This disclosure does not limit the specific calculation method, and the different calculation methods represent the same physical meaning.

[0062] Taking the time difference offset as the difference between the remote timestamp ts_remote and the local timestamp ts_local as an example, when the time difference offset is greater than 0, it means that the time value of the first clock 2013 is earlier than the time value of the second clock 2021. When the time difference offset is less than 0, it means that the time value of the first clock 2013 is later than the time value of the second clock 2021.

[0063] In the scenario of synchronizing the time of the first system-on-a-chip 201 and the second system-on-a-chip 202, after determining the time difference offset, the first system-on-a-chip 201 and the second system-on-a-chip 202 can be synchronized according to the time difference offset.

[0064] In some embodiments, such as Figure 4As shown, in order to synchronize the time of the first system-on-chip 201 and the second system-on-chip 202, the clock module (such as the first clock 2013) in the first system-on-chip 201 may include a clock correction register 2013a and a clock correction circuit 2013b.

[0065] The processor 2011 is also used to write the time difference into the clock correction register 2013a.

[0066] The clock correction circuit 2013b is used to synchronize the first on-chip system 201 and the second on-chip system 202 according to the time difference written in the clock correction register 2013a.

[0067] For example, after determining the time difference between the local clock and the remote clock, in order to synchronize the time between the local PCIe device and the remote PCIe device, the processor can write the time difference offset value into the clock correction register 2013a of the local clock module (such as the first clock 2013). The clock correction circuit 2013b built into the local clock module will monitor the offset value in the clock correction register 2013a in real time and adjust the current time of the local clock according to the offset value to ensure that the local clock and the remote clock are time aligned.

[0068] In some embodiments, adjusting the current time of the local clock based on the offset value can be done in several ways. For example, if the local clock is slower than the remote clock (e.g., the local timestamp value is less than the remote timestamp value), to ensure time synchronization between the local and remote clocks, the offset value can be added to the local clock's time counter, causing the local clock to align instantly with the remote clock. As another example, if the local clock is faster than the remote clock (e.g., the local timestamp value is greater than the remote timestamp value), to ensure time synchronization between the local and remote clocks, the offset value can be subtracted from the local clock's time counter, or the local clock can be paused from counting the offset value, thereby synchronizing the local and remote clocks.

[0069] In other embodiments, besides directly compensating the local clock time based on the time difference offset value, the oscillation frequency of the local clock can be fine-tuned to make the local clock run slightly faster or slower, gradually narrowing the time difference with the remote clock and preventing the offset from increasing again later. For example, if the local clock is slower than the remote clock, the oscillation frequency of the local clock can be slightly increased to make it run slightly faster, gradually narrowing the time difference. Conversely, if the local clock is faster than the remote clock, the oscillation frequency of the local clock can be slightly decreased to make it run slightly slower, gradually narrowing the time difference.

[0070] For example, since the first clock 2013 and the second clock 2021 are clock modules in two independent chips, after synchronizing the first clock 2013 and the second clock 2021, a time difference may arise again as the first on-chip system 201 and the second on-chip system 202 operate. Therefore, the processor 2011 can repeatedly start the DMA controller 2012 according to a preset period to read the local timestamp and the remote timestamp and calculate the time difference, and periodically synchronize the first on-chip 201 and the second on-chip system 202 according to the calculated time difference to ensure that the local clock and the remote clock can maintain microsecond-level synchronization.

[0071] In the scenario of measuring the PCIe link latency between the first system-on-a-chip 201 and the second system-on-a-chip 202, the PCIe device has hardware-level timestamp capture capability and can achieve high-precision time synchronization through Ethernet GPTP. Therefore, before the processor 2011 starts the DMA controller 2012, the first system-on-a-chip 201 and the second system-on-a-chip 202 can be synchronized with high precision.

[0072] For example, before the processor 2011 starts the DMA controller 2012, the GPTP protocol can be used to synchronize the local clock (e.g., the first clock 2013) and the remote clock (e.g., the second clock 2021) to ensure that the references of the two clocks are consistent. After synchronizing the first clock 2013 and the second clock 2021, the local timestamp of the first clock 2013 and the remote timestamp of the second clock 2021 should be consistent. However, because the DMA controller 2012 converts its memory access operation into a PCIe TLP and sends it to the peer when reading the remote timestamp, a PCIe link transmission delay occurs during the reading of the remote timestamp. Therefore, the time difference offset between the read remote timestamp and the local timestamp is the PCIe link delay.

[0073] To determine the transmission delay of the PCIe link, the local clock and the remote clock can be synchronized using the GPTP protocol. Then, the DMA controller 2012 is started by the processor 2011. The DMA controller 2012 reads the local timestamp and the remote timestamp in sequence according to the configuration list and calculates the time difference offset between the local timestamp and the remote timestamp. This time difference offset is the delay time of the PCIe link.

[0074] For example, since the first system-on-chip 201 and the second system-on-chip 202 are two independent chips, the PCIe link latency between them is not constant due to factors such as link load, hardware characteristics, and link noise. Therefore, the processor 2011 can repeatedly start the DMA controller 2012 according to a preset cycle to read the local timestamp and the remote timestamp, periodically calculate the PCIe link latency, and generate a link latency statistical distribution map. Based on this link latency statistical distribution map, comprehensive and reliable technical support can be provided for PCIe link performance optimization (such as adjusting packet size and optimizing load distribution), service timing calibration (such as time offset compensation for data fusion), and hardware maintenance (such as link fault diagnosis).

[0075] In determining the latency of a PCIe link, this disclosure first performs high-precision time synchronization between the local clock and the remote clock to ensure that their times are consistent. Then, it reads the local timestamp of the local clock and the remote timestamp of the remote clock. Since the TLP (Time Limit Point) needs to be sent to the peer via the PCIe link when reading the remote clock's timestamp, the read remote timestamp is the time after accounting for the PCIe link transmission delay. In other words, the time difference between the local and remote timestamps indicates the transmission delay of data transfer between the first and second on-chip systems via the PCIe link. Therefore, after reading the local and remote timestamps, the PCIe link transmission delay can be obtained by calculating the difference between them.

[0076] It should be noted that in the scenario of time synchronization between the first system-on-chip 201 and the second system-on-chip 202, since neither system-on-chip 201 nor system-on-chip 202 possesses hardware-level timestamp capture capabilities, high-precision clock synchronization cannot be achieved via Ethernet GPTP. Therefore, to improve the accuracy of time synchronization, the SG feature of the DMA controller in the system-on-chip can be utilized. By configuring an SG linked list, the DMA controller can automatically and continuously read the local and remote timestamps. The reading process is not affected by system scheduling, thus ensuring that the time synchronization accuracy can reach the microsecond or even nanosecond level. In the scenario of measuring the PCIe link latency, the first system-on-chip 201 and the second system-on-chip 202 possess hardware-level timestamp capture capabilities. High-precision clock synchronization can first be achieved via Ethernet GPTP. Then, by utilizing the SG feature of the DMA controller in the system-on-chip and configuring an SG linked list, the DMA controller can automatically and continuously read the local and remote timestamps, thereby calculating the PCIe link latency. This method for determining PCIe link latency is also unaffected by factors such as system scheduling and interrupt handling, ensuring high accuracy of the determined PCIe link latency. Moreover, the link latency does not require measurement using dedicated instruments, thus reducing measurement costs.

[0077] The chip system provided in this disclosure utilizes the SG characteristics of the existing DMA controller in the on-chip system to configure an SG linked list, and controls the DMA controller to automatically and continuously read the local timestamp and remote timestamp sequentially according to the task nodes in the SG linked list. Since this disclosure requires no processor intervention when reading the local and remote timestamps, the two read operations are not affected by system scheduling, ensuring that the accuracy of the time difference between the determined local clock and remote clock reaches the microsecond or even nanosecond level, thus meeting the requirements of high-precision scenarios. Whether in time synchronization scenarios or PCIe link latency measurement scenarios, this solution can ensure that the time synchronization accuracy and link latency accuracy reach the microsecond or even nanosecond level.

[0078] Exemplary methods

[0079] Figure 5 This is a schematic flowchart illustrating a time difference determination method provided in an exemplary embodiment of this disclosure. This embodiment can be applied to an electronic device, which may include a first system-on-a-chip (SoC) and a second SoC, connected via a PCIe link. Figure 5 As shown, the method includes the following steps:

[0080] Step 501: Start the DMA controller in the first on-chip system to instruct the DMA controller to execute multiple data transfer tasks in the configuration list.

[0081] For example, the configuration list can be an SG linked list, which includes multiple nodes. Each node contains a source address, a destination address, a data length, and a pointer to the next node. Each node in the configuration list is used to perform a data transfer task. Based on the data length in the node, the data stored at the source address can be transferred to the destination address, and then the data transfer task corresponding to the next node can be executed according to the pointer to the next node in that node.

[0082] In some examples, the processor can start the DMA controller via a write operation. For instance, the processor can write a preset value to the control / command register of the DMA controller to start the DMA controller 2012 and instruct it to begin executing tasks in the configuration list.

[0083] The configuration list can include multiple data transfer tasks, such as a first data transfer task and a second data transfer task. The first data transfer task reads the local timestamp and writes it to a first storage address, while the second data transfer task reads the remote timestamp and writes it to a second storage address.

[0084] The source address of the first data transfer task is the physical address of the first clock register in the first on-chip system, and the destination address of the first data transfer task is the first memory address. The source address of the second data transfer task is the PCIe address of the second clock register in the second on-chip system, and the destination address of the second data transfer task is the second memory address.

[0085] It should be noted that before step 501 above, a configuration linked list can be constructed in memory, and the starting address of the configuration linked list in memory can be written into the register of the DMA controller. When constructing the configuration linked list, the first node can be configured to move the local timestamp, and the second node can be configured to move the remote timestamp, that is, move the local timestamp first and then move the remote timestamp. When creating the configuration linked list, the first node can also be configured to move the remote timestamp, and the second node can be configured to move the local timestamp, that is, move the remote timestamp first and then move the local timestamp. This disclosure does not limit this, and the following embodiments use the example of moving the local timestamp first and then moving the remote timestamp for illustrative purposes.

[0086] Step 502: Based on the first data transfer task among multiple data transfer tasks, read the first timestamp corresponding to the first on-chip system and write the first timestamp into the first storage address of the memory.

[0087] The first timestamp can be called the local timestamp, which is the timestamp corresponding to the local clock (such as the first clock) of the first on-chip system. The memory can be DDR or off-chip memory. This disclosure does not limit the type of memory. The following embodiments use DDR memory as an example for illustrative purposes. When the memory is DDR, the storage address can be a DDR address.

[0088] To ensure that the first system-on-a-chip can read the local timestamp and the remote timestamp, the local clock of the first system-on-a-chip and the remote clock of the second system-on-a-chip can be mapped into the processor's memory address space through system software, thereby allowing the processor or DMA controller to access them via MMIO.

[0089] After the DMA controller starts, it can read the first timestamp corresponding to the first clock in the first on-chip system based on the first node in the SG linked list and write the first timestamp to DDR address 1. The first timestamp can be the time of the RTC module or the time of the network card module. This application embodiment does not limit the type of the first timestamp.

[0090] Step 503: Based on the second data transfer task among multiple data transfer tasks, read the second timestamp corresponding to the second on-chip system and write the second timestamp into the second storage address of the memory.

[0091] The second timestamp can be called the remote timestamp, which is the timestamp corresponding to the remote clock (such as the second clock) of the second on-chip system.

[0092] After the DMA controller starts, it can read the second timestamp corresponding to the second clock in the second on-chip system according to the second node in the SG linked list and write the first timestamp to DDR address 2. The second timestamp can be the time of the RTC module or the time of the network card module. This embodiment does not limit the type of the second timestamp, and the type of the second timestamp can be the same as the type of the first timestamp.

[0093] When reading the remote timestamp from the remote clock, the system software can map the second clock of the second on-chip system to the processor's memory address space. For example, the address of the second clock register value can be mapped to the PCIe address space. Therefore, subsequent read and write operations on this PCIe address will be converted by the PCIe controller into a TLP conforming to the PCIe protocol specification. This PCIe TLP is then transmitted to the peer device (such as the second on-chip system) via the PCIe link, where it is parsed and processed accordingly to obtain the remote timestamp.

[0094] Step 503 may include: the DMA controller generating a request message based on the second data transfer task among multiple data transfer tasks, and transmitting the request message to the second communication controller of the second on-chip system through the first communication controller; the second communication controller responding to the request message reading the second timestamp corresponding to the second on-chip system, and transmitting a response message to the first communication controller through the PCIe link; the DMA controller reading the second timestamp corresponding to the second on-chip system based on the response message and writing the second timestamp to the second storage address of the memory.

[0095] Step 504: In response to the completion of multiple data transfer tasks in the configuration list, an interrupt signal is generated.

[0096] Once all tasks in the configuration list have been completed, the DMA controller can generate an interrupt signal to notify the processor that all data transfer tasks have been completed.

[0097] Step 505: In response to the interrupt signal, read the first timestamp from the first storage address of the memory and read the second timestamp from the second storage address of the memory.

[0098] Step 506: Determine the time difference between the first system-on-a-chip and the second system-on-a-chip based on the first timestamp and the second timestamp.

[0099] After the DMA controller writes the local timestamp and the remote timestamp into the memory address respectively, it will send an interrupt signal to the processor. After receiving the interrupt signal, the processor can read the local timestamp and the remote timestamp from the memory respectively and calculate the time difference between the local timestamp and the remote timestamp.

[0100] For example, in order to periodically determine the time difference between the local clock and the remote clock, steps 501-506 can be performed periodically to ensure that the local clock and the remote clock can be synchronized at the microsecond level, or a link delay statistical distribution map can be generated.

[0101] like Figure 6 As shown, in the time synchronization scenario, after executing steps 501-506, step 507 can also be executed: write the time difference into the clock correction register, and synchronize the first on-chip system and the second on-chip system according to the time difference written in the clock correction register.

[0102] After determining the time difference between the local clock and the remote clock, in order to synchronize the first on-chip system and the second on-chip system, the time difference can be written into the clock correction register of the local clock module (such as the first clock), and the current time of the local clock is adjusted according to the time difference stored in the clock correction register to ensure that the local clock and the remote clock are aligned. Because this disclosure allows the DMA controller to automatically and continuously read the local timestamp and the remote timestamp when synchronizing the first on-chip system and the second on-chip system, and the reading process is not affected by system scheduling, the time synchronization accuracy can reach the microsecond or even nanosecond level.

[0103] like Figure 7 As shown, in the scenario of measuring PCIe link latency, before executing steps 501-506, step 508 can be executed first: time synchronization of the first on-chip system and the second on-chip system.

[0104] To measure PCIe link latency, the local clock and remote clock can be synchronized using the GPTP protocol to ensure that the clock references at both ends are consistent. Since the DMA controller's memory access operation is converted into a PCIe TLP and sent to the peer when reading the remote timestamp, a TLP transmission delay occurs during the reading of the remote timestamp. Therefore, the time difference between the read remote timestamp and the local timestamp is the PCIe link latency. Because the scheme for determining PCIe link latency in this disclosure is unaffected by system scheduling, interrupt handling, or other factors, it ensures high accuracy of the determined PCIe link latency. Furthermore, the link latency does not require dedicated instruments for measurement, thus reducing measurement costs.

[0105] The time difference determination method provided in this disclosure utilizes the SG characteristics of the existing DMA controller in the on-chip system to configure an SG linked list, and controls the DMA controller to automatically and continuously read the local timestamp and remote timestamp sequentially according to the task nodes in the SG linked list. Since this disclosure requires no processor intervention when reading the local and remote timestamps, the two read operations are not affected by system scheduling, ensuring that the accuracy of the determined time difference between the local clock and the remote clock reaches the microsecond or even nanosecond level, thus meeting the requirements of high-precision scenarios. Whether in time synchronization scenarios or PCIe link delay measurement scenarios, this solution can ensure that the time synchronization accuracy and link delay accuracy reach the microsecond or even nanosecond level.

[0106] Exemplary electronic devices

[0107] Figure 8 A structural diagram of an electronic device provided in an embodiment of this disclosure includes at least one processor 81 and a memory 82.

[0108] The processor 81 may be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and may control other components in the electronic device 80 to perform desired functions.

[0109] The memory 82 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 81 may execute one or more computer program instructions to implement the time difference determination method and / or other desired functions of the various embodiments of this disclosure described above.

[0110] In one example, the electronic device 80 may also include an input device 83 and an output device 84, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0111] The input device 83 may also include, for example, a keyboard, a mouse, etc.

[0112] The output device 84 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0113] Of course, for the sake of simplicity, Figure 8 Only some of the components of the electronic device 80 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 80 may include any other suitable components depending on the specific application.

[0114] Exemplary computer program products and computer-readable storage media

[0115] In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the time difference determination methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0116] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0117] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the time difference determination methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0118] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0119] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0120] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A chip system, comprising: A first system-on-a-chip (SoC) and a second SoC are connected via a high-speed peripheral component interconnect link. The first SoC includes a processor and a direct memory access controller. The processor is configured to initiate the direct memory access controller to instruct the direct memory access controller to execute multiple data transfer tasks in the configuration linked list; The direct memory access controller is used to read the first timestamp corresponding to the first on-chip system and write the first timestamp into the first storage address of the memory based on the first data transfer task in the plurality of data transfer tasks. Based on the second data transfer task among the plurality of data transfer tasks, the second timestamp corresponding to the second on-chip system is read and written to the second storage address of the memory; in response to the completion of the plurality of data transfer tasks in the configuration list, an interrupt signal is transmitted to the processor; The processor is further configured to, in response to the interrupt signal, read the first timestamp from the first storage address in the memory and read the second timestamp from the second storage address in the memory; And based on the first timestamp and the second timestamp, determine the time difference between the first system-on-a-chip and the second system-on-a-chip.

2. The chip system according to claim 1, wherein The processor is also configured to construct the configuration linked list in the memory and write the starting address of the configuration linked list in the memory into the register of the direct memory access controller; The configuration linked list includes the first data transfer task and the second data transfer task. The source address of the first data transfer task is the physical address of the first clock register in the first on-chip system, and the destination address of the first data transfer task is the first storage address. The source address of the second data transfer task is the high-speed peripheral component interconnection domain address of the second clock register in the second on-chip system, and the destination address of the second data transfer task is the second storage address.

3. The chip system according to claim 2, wherein The direct memory access controller is specifically used to read the first timestamp from the physical address of the first clock register based on the first data transfer task.

4. The chip system according to claim 2, wherein The first system-on-a-chip includes a first communication controller, and the second system-on-a-chip includes a second communication controller; The direct memory access controller is specifically used to generate a request message based on the high-speed peripheral component interconnection domain address in the second data transfer task, and transmit the request message to the first communication controller. The first communication controller is configured to transmit the request message to the second communication controller in the second system-on-a-chip via the high-speed peripheral component interconnection link; In response to the request message, the second communication controller reads the second timestamp corresponding to the second on-chip system and transmits a response message to the first communication controller through the high-speed peripheral component interconnection link; The first communication controller is configured to obtain the second timestamp corresponding to the second on-chip system based on the response message.

5. The chip system according to claim 1, wherein The processor is also configured to periodically activate the direct memory access controller according to a preset period, so as to instruct the direct memory access controller to periodically execute the plurality of data transfer tasks in the configuration list.

6. The chip system according to any one of claims 1 to 5, wherein, The clock module of the first on-chip system includes a clock correction register and a clock correction circuit; The processor is also configured to write the time difference into the clock correction register; The clock correction circuit is used to synchronize the time between the first on-chip system and the second on-chip system according to the time difference written in the clock correction register.

7. The chip system according to any one of claims 1 to 5, wherein, The processor is further configured to: synchronize the time of the first system-on-chip and the second system-on-chip before starting the direct memory access controller; The time difference is used to indicate the transmission delay of data transmission between the first system-on-a-chip and the second system-on-a-chip via the high-speed peripheral component interconnect link.

8. A time difference determination method applied to a chip system, the chip system comprising a first system-on-a-chip (SoC) and a second SoC, the first SoC and the second SoC being connected via a high-speed peripheral component interconnect link; the method comprising: Start the direct memory access controller in the first system on chip to instruct the direct memory access controller to execute multiple data transfer tasks in the configuration linked list; Based on the first data transfer task among the plurality of data transfer tasks, read the first timestamp corresponding to the first on-chip system and write the first timestamp into the first storage address of the memory; Based on the second data transfer task among the plurality of data transfer tasks, read the second timestamp corresponding to the second on-chip system and write the second timestamp into the second storage address of the memory; An interrupt signal is generated in response to the completion of the plurality of data transfer tasks in the configuration list; In response to the interrupt signal, the first timestamp is read from the first storage address of the memory, and the second timestamp is read from the second storage address of the memory; Based on the first timestamp and the second timestamp, the time difference between the first system-on-a-chip and the second system-on-a-chip is determined.

9. A computer-readable storage medium storing a computer program that, when executed by a processor, is used to implement the time difference determination method of claim 8.

10. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the time difference determination method of claim 8.

Images