Double-reset control system
By introducing two reset chips and FPGA logic control, a dual reset control system was designed, which solved the problem that external reset and software reset could not be synchronized to achieve safe reset of FLASH, and realized safe and reliable reset of DSP and FLASH.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INST OF COMP TECH & APPL
- Filing Date
- 2025-11-21
- Publication Date
- 2026-04-17
AI Technical Summary
In the existing technology, external reset and software reset can only reset the DSP, and cannot simultaneously achieve safe reset of FLASH.
A dual-reset control system is designed using two reset chips and FPGA logic control. The reset chips and FPGA are connected through optocouplers and signal connectors to achieve synchronous reset of DSP and FLASH.
It enables safe and reliable reset of DSP and FLASH, ensuring that the system can work normally during power-on, external reset and software reset, and avoiding FLASH malfunction.
Smart Images
Figure CN121879543A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of aircraft control system technology, specifically a dual reset control system. Background Technology
[0002] The reset control system is a crucial component of aircraft product design. Resetting ensures that all components within the system are in a defined initial state, and can be used to correct occasional system malfunctions. Types of reset mechanisms in aircraft product design primarily include power-on reset, external reset, and software reset. Power-on reset can be achieved using a reset chip, ensuring the system is in a defined initial state after power-on. External reset can be achieved by inputting a switch signal, restoring the system to its initial state. Software reset can be achieved by sending software commands, restoring the system to its initial state.
[0003] Currently, the power-on reset of aircraft products can reset the DSP and FLASH, but external reset and software reset can only reset the DSP and cannot simultaneously achieve a safe reset of the FLASH. Summary of the Invention
[0004] The purpose of this invention is to provide a dual reset control system that solves the problem that external reset and software reset only reset the DSP and cannot simultaneously achieve safe FLASH reset. By introducing two reset chips and FPGA logic control, the reset requirements of the aircraft are met. The specific technical solution proposed in this invention is as follows: A dual reset control system includes a reset chip A (1), a reset chip B (2), a DSP (3), an FPGA (4), a FLASH (5), an optocoupler (6), and a signal connector (7). The output of the signal connector (7) is connected to the input of the optocoupler (6), the output of the optocoupler (6) is connected to the input of the FPGA (4), the output of the FPGA (4) is connected to the input of the reset chip A (1), the reset chip B (2), and the DSP (3), respectively, the output of the reset chip A (1) is connected to the input of the FPGA (4), the output of the DSP (3) is connected to the input of the FPGA (4), and the output of the reset chip B (2) is connected to the input of the FLASH (5).
[0005] Furthermore, the DONE signal output by the FPGA (4) controls the manual reset pin MR of the reset chip A (1), and the reset control signal output by the FPGA (4) controls the manual reset pin MR of the reset chip B (2).
[0006] Furthermore, after the system is powered on, the FPGA loads the program, DONE is low, MR is low, and the valid reset signal RESETA output by the reset chip A is low; after the FPGA completes the program loading, DONE is high, MR is high, the reset chip A outputs RESETA equal to the reset delay time Td, RESETA is high, and the power-on reset ends. When the DSP reset pin is pulled to ground, the initial state after power-on is low, and the DSP is in a reset state until the reset delay time Td of the FPGA output reset signal RESETA to the DSP ends, at which point the DSP reset ends. During system power-up, when the power supply voltage of reset chip B is lower than the threshold voltage, the effective reset signal RESETB output by reset chip B is low; when the power supply voltage of reset chip B is higher than the threshold voltage, and the reset control signal output by FPGA is high and MR is high, after reset chip B outputs the reset signal RESETB with a reset delay time Td, RESETB is high, and the power-up reset ends. The FLASH reset pin is pulled down to ground by default. After power-on, its initial state is low, and the FLASH is in a reset state until the reset delay time Td of the reset signal RESETB output by the reset chip B to the FLASH ends, at which point the FLASH reset ends.
[0007] Furthermore, after the system is powered on, the FLASH reset completion time precedes the DSP reset completion time.
[0008] Furthermore, during the system power-down process, when the power supply voltage of the reset chip B is lower than the threshold voltage, the reset chip B outputs a valid reset signal RESETB to the FLASH to ensure that the FLASH is in a reset state.
[0009] Furthermore, the FPGA (4) includes a top-level module (8), an address decoding module (9), and a reset control module (10). The output of the top-level module (8) is connected to the input of the reset control module (10) and the address decoding module (9), respectively. The output of the address decoding module (9) is connected to the input of the reset control module (10), and the output of the reset control module (10) is connected to the input of the top-level module (8).
[0010] Furthermore, during system operation, when an external reset signal is input, the external reset signal is sent to the optocoupler (6) via the signal connector (7), and then to the FPGA (4). After being processed by the top-level module (8), it is sent to the reset control module (10). After signal filtering and synchronization processing, it identifies whether the external reset signal is valid. If valid, it outputs a Tz low-pulse reset signal and a 1us low-pulse reset control signal, where Tz is the maximum reset delay time of the reset chip.
[0011] Furthermore, the reset control module (10) first outputs a 1us low pulse reset control signal, and after a 2ms delay, outputs a Tz reset signal to the DSP. The 1us reset control signal is sent to the MR pin of the reset chip B. MR becomes low level, RESETB becomes low level, MR becomes high level after 1us, RESETB continues to remain low level, and becomes high level after a reset delay time Td. When RESETB is low level, FLASH is in reset state. The DSP's initial reset time is earlier than the FLASH's initial reset time, and the FLASH's reset completion time is earlier than the DSP's reset completion time.
[0012] Furthermore, during system operation, when the DSP executes the software reset instruction, the software reset instruction is processed by the FPGA top-level module (8) and then sent to the address decoding module (9). After decoding, it is sent to the reset control module (10) to identify whether the software reset is valid. If it is valid, a Tz low pulse reset signal and a 1us low pulse reset control signal are output. Tz is the maximum reset delay time of the reset chip.
[0013] Furthermore, the reset control module (10) first outputs a 1us low pulse reset control signal, and after a 2ms delay, outputs a Tz reset signal to the DSP. The 1us reset control signal is sent to the MR pin of the reset chip B. MR becomes low level, RESETB becomes low level, MR becomes high level after 1us, RESETB continues to remain low level, and becomes high level after a reset delay time Td. When RESETB is low level, FLASH is in reset state. The DSP's initial reset time is earlier than the FLASH's initial reset time, and the FLASH's reset completion time is earlier than the DSP's reset completion time.
[0014] This invention, by introducing two reset chips and FPGA logic control, enables safe and reliable reset of the DSP and FLASH through power-on reset, external reset, and software reset. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the principle of the present invention; Figure 2 This is a block diagram of the FPGA used in this invention. Detailed Implementation
[0016] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0017] In this invention, the dual reset control system is designed by introducing two reset chips and FPGA logic control. In response to the aircraft's reset requirements, the design of the dual reset control system focuses on the two reset chips and FPGA logic control.
[0018] In a specific embodiment of the present invention, the dual reset control system is as follows: Figure 1 As shown, it includes reset chip A (1), reset chip B (2), DSP (3), FPGA (4), FLASH (5), optocoupler (6) and signal connector (7).
[0019] like Figure 2 As shown, the FPGA includes a top-level module (8), an address decoding module (9), and a reset control module (10).
[0020] The output of the signal connector (7) is connected to the input of the optocoupler (6), the output of the optocoupler (6) is connected to the input of the FPGA (4), the output of the FPGA (4) is connected to the input of the reset chip A (1), the reset chip B (2), and the DSP (3), respectively, the output of the reset chip A (1) is connected to the input of the FPGA (4), the output of the DSP (3) is connected to the input of the FPGA (4), and the output of the reset chip B (2) is connected to the input of the FLASH (5).
[0021] In the FPGA, the output of the top-level module (8) is connected to the input of the reset control module (10) and the address decoding module (9), respectively. The output of the address decoding module (9) is connected to the input of the reset control module (10), and the output of the reset control module (10) is connected to the input of the top-level module (8).
[0022] In this invention, reset chip A and reset chip B are chips of the same model and specifications. The DONE signal output by the FPGA controls the manual reset pin MR of reset chip A, and the reset control signal output by the FPGA controls the manual reset pin MR of reset chip B. The MR pins of both reset chips are in a pull-up state by default.
[0023] After the system powers on, the FPGA loads the program, with DONE and MR at low levels. Reset chip A continuously outputs a valid reset signal RESETA at a low level. After the FPGA completes program loading, DONE goes high, meaning MR goes high. Reset chip A then outputs RESETA for the reset delay time Td, after which RESETA goes high, ending the power-on reset. The DSP reset pin is pulled down to ground by default, and its initial state after power-on is low. The DSP remains in reset state until the Td value of the RESETA signal output from the FPGA to the DSP ends, ending the DSP reset. During system power-on, if the power supply voltage of reset chip B is lower than the threshold voltage, reset chip B outputs a valid reset signal RESETB at a low level. When the power supply voltage of reset chip B is higher than the threshold voltage, and the reset control signal output by the FPGA is high (MR is high), reset chip B outputs RESETB for the reset delay time Td, after which RESETB goes high, ending the power-on reset. The FLASH reset pin is pulled down to ground by default. After power-on, its initial state is low, and the FLASH remains in the reset state until the Td of the reset signal RESETB output by the reset chip B to the FLASH ends, at which point the FLASH reset ends.
[0024] After the system powers on, the FLASH reset completes before the DSP reset, ensuring that the DSP can reliably load the program from the FLASH after resetting. During system power-down, when the power supply voltage of reset chip B falls below the threshold voltage, reset chip B outputs a valid reset signal RESETB to the FLASH, ensuring that the FLASH is in a reset state. This prevents potential FLASH malfunctions caused by DSP program crashes.
[0025] During system operation, when an external reset signal is input, the external reset signal is sent to the optocoupler via the signal connector, then to the FPGA, processed by the top-level module (8), and then sent to the reset control module (10). After signal filtering and synchronization processing, the external reset signal is identified as valid. If valid, a Tz low-pulse reset signal and a 1us low-pulse reset control signal are output. The reset control module (10) first outputs a 1us low-pulse reset control signal, and after a 2ms delay, outputs a Tz reset signal to the DSP. The 1us reset control signal is sent to the MR pin of the reset chip B. MR becomes low, RESETB becomes low, MR becomes high after 1us, and RESETB remains low for a reset delay time Td before becoming high. When RESETB is low, the FLASH is in a reset state. The DSP's initial reset time precedes the FLASH's initial reset time, and the FLASH's reset completion time precedes the DSP's reset completion time, ensuring that the DSP can interact normally with the FLASH after the reset is completed.
[0026] During system operation, when the DSP executes a software reset instruction, the software reset instruction is processed by the FPGA top-level module (8) and then sent to the address decoding module (9). After decoding, it is sent to the reset control module (10) to identify whether the software reset is valid. If valid, it outputs a Tz low-pulse reset signal and a 1us low-pulse reset control signal. The reset control module (10) first outputs a 1us low-pulse reset control signal, and after a 2ms delay, outputs a Tz reset signal to the DSP. The 1us reset control signal is sent to the MR pin of the reset chip B. MR becomes low, RESETB becomes low, MR becomes high after 1us, RESETB remains low for a reset delay time Td, and then becomes high. When RESETB is low, the FLASH is in a reset state. The DSP's initial reset time precedes the FLASH's initial reset time, and the FLASH's reset completion time precedes the DSP's reset completion time, which ensures that the DSP can interact normally with the FLASH after the reset is completed.
[0027] Td represents the typical reset delay time of the reset chip. Tz represents the maximum reset delay time of the reset chip.
[0028] This invention introduces two reset chips and FPGA logic control, which not only ensures that power-on reset, external reset and software reset can safely reset the DSP, but also ensures that power-on reset, external reset and software reset can safely reset the FLASH.
[0029] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A dual reset control system, characterized by, It includes a reset chip A (1), a reset chip B (2), a DSP (3), an FPGA (4), a FLASH (5), an optocoupler (6), and a signal connector (7). The output of the signal connector (7) is connected to the input of the optocoupler (6). The output of the optocoupler (6) is connected to the input of the FPGA (4). The output of the FPGA (4) is connected to the input of the reset chip A (1), the reset chip B (2), and the DSP (3), respectively. The output of the reset chip A (1) is connected to the input of the FPGA (4). The output of the DSP (3) is connected to the input of the FPGA (4). The output of the reset chip B (2) is connected to the input of the FLASH (5).
2. A dual reset control system according to claim 1, wherein, The DONE signal output by the FPGA (4) controls the manual reset pin MR of the reset chip A (1), and the reset control signal output by the FPGA (4) controls the manual reset pin MR of the reset chip B (2).
3. A dual reset control system according to claim 2, wherein, After the system is powered on, the FPGA loads the program. DONE is low, MR is low, and the valid reset signal RESETA output by reset chip A is low. After the FPGA completes the program loading, DONE is high, MR is high, and reset chip A outputs RESETA equal to the reset delay time Td. RESETA is high, and the power-on reset ends. When the DSP reset pin is pulled to ground, the initial state after power-on is low, and the DSP is in a reset state until the reset delay time Td of the FPGA output reset signal RESETA to the DSP ends, at which point the DSP reset ends. During system power-up, when the power supply voltage of reset chip B is lower than the threshold voltage, the effective reset signal RESETB output by reset chip B is low; when the power supply voltage of reset chip B is higher than the threshold voltage, and the reset control signal output by FPGA is high and MR is high, after reset chip B outputs the reset signal RESETB with a reset delay time Td, RESETB is high, and the power-up reset ends. The FLASH reset pin is pulled down to ground by default. After power-on, its initial state is low, and the FLASH is in a reset state until the reset delay time Td of the reset signal RESETB output by the reset chip B to the FLASH ends, at which point the FLASH reset ends.
4. A dual reset control system according to claim 3, wherein After the system is powered on, the FLASH reset completes before the DSP reset completes.
5. A dual reset control system as claimed in claim 3, wherein, During system power-down, when the power supply voltage of reset chip B is lower than the threshold voltage, reset chip B outputs a valid reset signal RESETB to FLASH to ensure that FLASH is in a reset state.
6. A dual reset control system as claimed in claim 1, wherein, The FPGA (4) includes a top-level module (8), an address decoding module (9), and a reset control module (10). The output of the top-level module (8) is connected to the input of the reset control module (10) and the address decoding module (9), respectively. The output of the address decoding module (9) is connected to the input of the reset control module (10), and the output of the reset control module (10) is connected to the input of the top-level module (8).
7. A dual reset control system according to claim 6, wherein During system operation, when an external reset signal is input, the external reset signal is sent to the optocoupler (6) via the signal connector (7), and then to the FPGA (4). After being processed by the top-level module (8), it is sent to the reset control module (10). After signal filtering and synchronization processing, it identifies whether the external reset signal is valid. If it is valid, it outputs a Tz low-pulse reset signal and a 1us low-pulse reset control signal, where Tz is the maximum reset delay time of the reset chip.
8. A dual reset control system according to claim 7, wherein, The reset control module (10) first outputs a 1us low pulse reset control signal, and after a 2ms delay, outputs a Tz reset signal to the DSP. The 1us reset control signal is sent to the MR pin of the reset chip B. MR becomes low level, RESETB becomes low level, MR becomes high level after 1us, RESETB continues to remain low level, and becomes high level after a reset delay time Td. When RESETB is low level, FLASH is in reset state. The DSP's initial reset time is earlier than the FLASH's initial reset time, and the FLASH's reset completion time is earlier than the DSP's reset completion time.
9. A dual reset control system according to claim 6, characterized in that, During system operation, when the DSP executes the software reset instruction, the software reset instruction is processed by the FPGA top-level module (8) and sent to the address decoding module (9). After decoding, it is sent to the reset control module (10) to identify whether the software reset is valid. If it is valid, a Tz low pulse reset signal and a 1us low pulse reset control signal are output. Tz is the maximum reset delay time of the reset chip.
10. A dual reset control system according to claim 9, characterized in that, The reset control module (10) first outputs a 1us low pulse reset control signal, and after a 2ms delay, outputs a Tz reset signal to the DSP. The 1us reset control signal is sent to the MR pin of the reset chip B. MR becomes low level, RESETB becomes low level, MR becomes high level after 1us, RESETB continues to remain low level, and becomes high level after a reset delay time Td. When RESETB is low level, FLASH is in reset state. The DSP's initial reset time is earlier than the FLASH's initial reset time, and the FLASH's reset completion time is earlier than the DSP's reset completion time.