Floating-point number arithmetic circuit, processor, chip product and equipment

Abstract

The invention discloses a floating-point number operation circuit, a processor, a chip product and equipment, and relates to the field of digital integrated circuits. The floating-point number operation circuit comprises a preprocessing unit, a first addition operation unit, a second addition operation unit and a selection unit, wherein the first addition operation unit and the second addition operation unit execute addition operation in parallel; the preprocessing unit is used for preprocessing the first mantissa and the second mantissa to obtain a first addend and a second addend; the first additive operation unit is used for executing additive operation based on the first addend, the second addend and the first numerical value to obtain a first operation result; the second additive operation unit is used for executing additive operation based on the first addend and the second addend to obtain a second operation result; and the selection unit is used for selecting a numerical value from the first operation result and the second operation result as a sum value of the first mantissa and the second mantissa. And the logic chain of floating-point number operation is shortened, so that the time required by the floating-point number operation is saved.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuits, and particularly to a floating-point arithmetic circuit, processor, chip product, and device. Background Technology

[0002] A floating-point number consists of 1 sign bit, n exponent bits, and m digit bits, where n and m are positive integers greater than or equal to 1. Floating-point addition is one of the most frequently used operations in computers; it involves adding two floating-point numbers.

[0003] In related technologies, adding floating-point numbers first requires aligning the exponents of the two floating-point numbers to be added. Then, the two mantissas after exponent alignment are added (or subtracted). Next, it is determined whether the result is less than 0. If the result is less than 0, the result needs to be negated to obtain the corresponding positive number (i.e., the result needs to be inverted and then 1 is added). Then, the positive number is checked for leading zeros. Finally, normalization is performed, which includes shifting the mantissa result of the positive number based on the leading zero detection result, calculating the exponent, and rounding.

[0004] However, the above method requires two serial adders during the operation (to obtain the result and to negate the result to obtain the corresponding positive number), resulting in a long logic chain and increasing the time resources spent on floating-point addition calculations. Summary of the Invention

[0005] This application provides a floating-point arithmetic circuit, a processor, a chip product, and a device. The technical solution provided by this application is as follows: According to one aspect of the embodiments of this application, a floating-point arithmetic circuit is provided, the floating-point arithmetic circuit including: a preprocessing unit, a first addition unit, a second addition unit, and a selection unit, wherein the first addition unit and the second addition unit perform addition operations in parallel; The preprocessing unit is used to perform preprocessing on the first mantissa and the second mantissa to obtain the first addend corresponding to the first mantissa and the second addend corresponding to the second mantissa, wherein the first mantissa is the mantissa of the first floating-point number and the second mantissa is the mantissa of the second floating-point number; The first addition unit is used to perform an addition operation based on the first addend, the second addend, and the first numerical value to obtain a first operation result; The second addition unit is used to perform an addition operation based on the first addend and the second addend to obtain a second operation result; The selection unit is used to select a value from the first calculation result and the second calculation result as the sum of the first tail number and the second tail number.

[0006] According to one aspect of the embodiments of this application, a processor is provided, the processor including the floating-point arithmetic circuit.

[0007] According to one aspect of the embodiments of this application, a chip product is provided, the chip product including a processor, the processor including the floating-point arithmetic circuit.

[0008] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor, the processor including the floating-point arithmetic circuit.

[0009] According to one aspect of the embodiments of this application, an arithmetic method for a floating-point arithmetic circuit is provided. The floating-point arithmetic circuit includes: a preprocessing unit, a first addition unit, a second addition unit, and a selection unit, wherein the first addition unit and the second addition unit perform addition operations in parallel. The preprocessing unit performs preprocessing on the first mantissa and the second mantissa to obtain the first addend corresponding to the first mantissa and the second addend corresponding to the second mantissa, wherein the first mantissa is the mantissa of the first floating-point number and the second mantissa is the mantissa of the second floating-point number; The first addition unit performs an addition operation based on the first addend, the second addend, and the first numerical value to obtain a first operation result; The second addition unit performs an addition operation based on the first addend and the second addend to obtain a second operation result; The selection unit selects a value from the first calculation result and the second calculation result as the sum of the first tail number and the second tail number.

[0010] The technical solutions provided in this application embodiment may have the following beneficial effects: By using two parallel addition units to process the first and second floating-point numbers, the operation only needs to wait for the processing time of one addition unit, which shortens the logic chain of floating-point operations and thus saves the time required for floating-point operations. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1This is a schematic diagram of the floating-point number format provided in one possible implementation of this application; Figure 2 This is a schematic diagram of a floating-point arithmetic circuit provided in one possible implementation of this application; Figure 3 This is a schematic diagram of a floating-point arithmetic circuit provided in one possible implementation of this application; Figure 4 This is a schematic diagram of a floating-point arithmetic circuit provided in another possible implementation of this application; Figure 5 This is a flowchart of an arithmetic method applied to a floating-point arithmetic circuit, provided in one possible implementation of this application; Figure 6 This is a schematic diagram of a possible implementation of the mantissa shifting method provided in this application; Figure 7 This is a block diagram of a computer device provided in one possible implementation of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0014] A floating-point number consists of 1 sign bit, n exponent bits, and m bit bits, where n and m are positive integers greater than or equal to 1. Taking a single-precision floating-point number (FP32) as an example... Figure 1 As shown, the 32-bit width includes 1 sign bit, 8 exponent bits, and 23 mantissa bits.

[0015] Floating-point addition is one of the most frequently used operations in computers. It involves adding two floating-point numbers together. Sometimes, floating-point addition also appears in the form of floating-point multiplication and addition, where two numbers are multiplied first, and then added to a third number.

[0016] Floating-point addition typically involves the following steps: 1. Align the exponents of the two floating-point numbers to be added; 2. Add (or subtract) the two mantissas after aligning the exponents; 3. Determine if the result of adding the last digits is less than 0. If it is less than 0, take the negative of the last digits to get the corresponding positive number. 4. Perform leading zero detection on the result of adding the mantissas of the positive numbers; 5. Normalization operations include shifting the mantissa of positive numbers based on the leading zero detection results, calculating exponents, and performing rounding operations.

[0017] In related techniques, two addition operations need to be calculated separately in steps 2 and 3. For example... Figure 2 As shown, in step 2, the two mantissas are usually added (or subtracted). However, since the floating-point format requires the mantissa to be positive, if subtraction is performed, the result may be negative. Therefore, in step 3, the sign bit of the result needs to be checked. If it is negative, the result needs to be inverted and then 1 is added to get the corresponding positive number.

[0018] It can be seen that, under the relevant technology, the mantissa addition in floating-point addition requires passing through two adders sequentially.

[0019] The first adder can add two exponent-aligned mantissas. For subtraction, one of the mantissas needs to be negated (i.e., bitwise inverted and then incremented). Therefore, the first adder has three addends: two are exponent-aligned mantissas (one of which may have been bitwise inverted), and the third is the increment needed for subtraction. Note that when the sticky bit is not zero, incrementing is not necessary even during subtraction.

[0020] When the sticky bit of the second adder is 0 and the output of the first adder is negative, the calculation result needs to be negated, and then another inversion and addition operation is performed.

[0021] The related technical solutions require two serial adders during the mantissa addition process, resulting in a long logic chain and increasing the time resources spent on floating-point addition calculations.

[0022] This application proposes a parallel adder scheme that can reduce the time spent on floating-point addition calculations.

[0023] Please refer to Figure 3 The diagram illustrates a floating-point arithmetic circuit provided in one possible implementation of this application. The floating-point arithmetic circuit 300 includes a preprocessing unit 310, a first addition unit 320, a second addition unit 330, and a selection unit 340, wherein the first addition unit 320 and the second addition unit 330 perform addition operations in parallel.

[0024] The preprocessing unit 310 is used to perform preprocessing on the first mantissa and the second mantissa to obtain the first addend corresponding to the first mantissa and the second addend corresponding to the second mantissa, wherein the first mantissa is the mantissa of the first floating-point number and the second mantissa is the mantissa of the second floating-point number.

[0025] In some embodiments, the operation between the first floating-point number and the second floating-point number can be either an addition operation or a subtraction operation. For example, if the first floating-point number is A and the second floating-point number is B, then the floating-point arithmetic circuit can be used to calculate A+B, or it can be used to calculate AB or BA.

[0026] In some embodiments, when performing subtraction on floating-point numbers, considering that an adder is used in the floating-point arithmetic circuit, the subtraction operation can be regarded as an addition operation, where the sign bit of the subtrahend is reversed. For example, AB can be regarded as A+(-B), and BA can be regarded as B+(-A).

[0027] In some embodiments, if the first floating-point number and the second floating-point number are to be added, then during the preprocessing process, only the exponents of the first mantissa and the second mantissa need to be aligned to obtain the first addend and the second addend.

[0028] In some embodiments, if a subtraction operation is performed between a first floating-point number and a second floating-point number, then during the preprocessing process, in addition to aligning the exponents of the first and second mantissas, the subtrahend also needs to be inverted to obtain the first and second addends.

[0029] The first addition unit 320 is used to perform addition operations based on the first addend, the second addend, and the first numerical value to obtain the first operation result.

[0030] In some embodiments, the first value is 1. In some embodiments, the first value is the same as the exponent of the first addend and the second addend. For example, the first addend is 0.5, which is represented in binary as 0.1000, or normalized to 01000×2. -4 The second addend is 0.2, which is represented in binary as 0.0011, or normalized as 00011 × 2. -4 At this point, the first value is 0.0001, or standardized to 1×2. -4 .

[0031] In some embodiments, the first operation result includes a first sum and a second sum, wherein the first sum is the sum of the first addend, the second addend, and the first value, and the second sum is obtained by inverting the first sum.

[0032] The second addition unit 330 is used to perform addition operations based on the first addend and the second addend to obtain the second operation result.

[0033] In some embodiments, the second operation result includes a third sum and a fourth sum. The third sum is the sum of the first addend and the second addend, and the fourth sum is obtained by inverting the third sum.

[0034] In some embodiments, the first addition unit and the second addition unit operate in parallel.

[0035] Selection unit 340 is used to select a value from the first operation result and the second operation result as the sum of the first mantissa and the second mantissa.

[0036] In some embodiments, there is only one correct value in the first operation result and the second operation result. Therefore, it is necessary to select the correct value from the first operation result and the second operation result as the sum of the first and second tail numbers.

[0037] The technical solution provided in this application uses two parallel addition units to process the operation of the first floating-point number and the second floating-point number. During the operation, only the processing time of one addition unit needs to be waited, which shortens the logic chain of floating-point number operation and thus saves the time required for floating-point number operation.

[0038] Next, the detailed design scheme of the floating-point arithmetic circuit will be explained.

[0039] I. First Addition Operation Unit In some embodiments, the first addition unit includes a first adder and a first inverter. For example, as shown... Figure 4 As shown, the first addition unit 410 includes a first adder 411 and a first inverter 412.

[0040] In some embodiments, the first calculation result includes a first sum and a second sum.

[0041] In some embodiments, the first adder 411 is used to calculate the sum of the first addend, the second addend, and the first value to obtain a first sum value.

[0042] In some embodiments, the first adder 411 is further configured to send a first sign bit to the selection unit, the first sign bit being the sign bit in the first sum.

[0043] For example, if the first sum is positive, then the first sign bit is 0; if the first sum is negative, then the first sign bit is 1. It should be noted that the sum can also be regarded as a floating-point number. Each floating-point number includes its own sign bit. The sign bit in the first sum is used to indicate whether the first sum is positive or negative. The sign bit in the third sum is used to indicate whether the third sum is positive or negative. Of course, the second and fourth sums also have their own sign bits. The sign bit of the sum should not be confused with the sign bits of the first and second mantissas.

[0044] In some embodiments, the first inverter 412 is used to invert the first sum to obtain the second sum.

[0045] In some embodiments, inverting the first sum means keeping the sign bit unchanged and inverting the remaining bits. For example, if the first sum is 0.1011, inverting it results in a second sum of 0.0100. Alternatively, if the first sum is 1.0011, inverting it results in a second sum of 1.1100.

[0046] II. Second Addition Unit In some embodiments, the second addition unit includes a second adder and a second inverter. For example, as shown... Figure 4 As shown, the first addition unit 420 includes a first adder 421 and a first inverter 422.

[0047] In some embodiments, the second calculation result includes a third sum and a fourth sum.

[0048] In some embodiments, the second adder 421 is used to calculate the sum of the first addend and the second addend to obtain a third sum.

[0049] In some embodiments, the second adder 421 is further configured to send a second sign bit to the selection unit, the second sign bit being the sign bit in the second sum.

[0050] For example, if the third sum is positive, then the first sign bit is 0; if the third sum is negative, then the first sign bit is 1.

[0051] In some embodiments, the second inverter 422 is used to invert the third sum to obtain the fourth sum.

[0052] In some embodiments, inverting the third sum means keeping the sign bit unchanged and inverting the remaining bits. For example, if the third sum is 0.1011, inverting it results in a fourth sum of 0.0100. Alternatively, if the third sum is 1.0011, inverting it results in a fourth sum of 1.1100.

[0053] The first and second operation results are determined by parallel first and second addition units, respectively. During the operation, only the processing time of one addition unit (including one adder and one inverter) is required, which saves the time required for floating-point operations compared to waiting for two serial adders to operate.

[0054] III. Selection Unit In some embodiments, the selection unit includes a first multiplexer and a second multiplexer. For example, as shown... Figure 4 As shown, the selection unit 430 includes a first multiplexer 431 and a second multiplexer 432.

[0055] In some embodiments, the first multiplexer 431 is used to determine a first option value based on first indication information, sticky bit indication information, a first sign bit, and a second sign bit.

[0056] In some embodiments, the first indication information is used to indicate the smaller exponent between the first mantissa and the second mantissa. In some embodiments, the first indication information is sent from the preprocessing unit to the selection unit. Exemplarily, the first indication information is sent from the preprocessing unit to the first multiplexer.

[0057] In some embodiments, the first indication information consists of at least one bit. For example, the first indication information occupies one bit, where a value of 1 indicates that the exponent of the first mantissa is less than the exponent of the second mantissa, meaning the first mantissa has a smaller exponent; a value of 0 indicates that the exponent of the first mantissa is greater than the exponent of the second mantissa, meaning the second mantissa has a smaller exponent. Alternatively, the first indication information occupies one bit, where a value of 0 indicates that the exponent of the first mantissa is less than the exponent of the second mantissa, meaning the first mantissa has a smaller exponent; a value of 1 indicates that the exponent of the first mantissa is greater than the exponent of the second mantissa, meaning the second mantissa has a smaller exponent.

[0058] For example, the first indication information occupies 2 bits, where the first bit corresponds to the first mantissa and the second bit corresponds to the second mantissa. If the first bit is 1 and the second bit is 0, it means that the first mantissa is less than the second mantissa, that is, the first mantissa is the smaller exponent. If the second bit is 1 and the first bit is 0, it means that the first mantissa is greater than the second mantissa, that is, the second mantissa is the smaller exponent.

[0059] In some embodiments, the sticky bit indication information is used to indicate whether a sticky bit exists after the first mantissa and the second mantissa are shifted. In some embodiments, the sticky bit indication information is sent from the preprocessing unit to the selection unit. Exemplarily, the sticky bit indication information is sent from the preprocessing unit to the first multiplexer.

[0060] In some embodiments, the sticky bit indication information consists of at least one bit. For example, the sticky bit indication information occupies one bit, where a value of 1 indicates that a sticky bit exists after shifting the first and second mantissas; a value of 0 indicates that no sticky bit exists after shifting the first and second mantissas. Alternatively, the sticky bit indication information occupies one bit, where a value of 0 indicates that a sticky bit exists after shifting the first and second mantissas; a value of 1 indicates that no sticky bit exists after shifting the first and second mantissas.

[0061] In some embodiments, the first sign bit is the sign bit in the first sum, the second sign bit is the sign bit in the third sum, the first sum is the sum of the first addend, the second addend, and the first value, and the third sum is the sum of the first addend and the second addend. For a description of the first sum, the first sign bit, the third sum, and the second sign bit, please refer to the descriptions in the embodiments concerning the first addition unit and the second addition unit described above.

[0062] In some embodiments, the first option value is obtained by integrating the first indication information, the sticky bit indication information, the first sign bit, and the second sign bit. For example, the first option value is obtained by arranging the first indication information, the sticky bit indication information, the first sign bit, and the second sign bit in sequence.

[0063] For example, the first option value is obtained by arranging the first indication information, the sticky bit indication information, the first sign bit, and the second sign bit in that order. Taking the first indication information occupying 1 bit and the sticky bit indication information occupying 1 bit as an example, for instance, a first option value of 1011 indicates that the first mantissa has a small exponent, there is no sticky bit, and both the first and third sums are negative. For instance, a first option value of 1000 indicates that the first mantissa has a small exponent, there is no sticky bit, and both the first and third sums are positive.

[0064] In some embodiments, the first option value is used to indicate one of a first sum, a second sum, a third sum, and a fourth sum. Exemplarily, the first option value occupies at least 2 bits. For example, if the first option value occupies 2 bits, a value of 00 indicates that the sum of the first and second mantissas is the first sum; a value of 01 indicates that the sum of the first and second mantissas is the second sum; a value of 10 indicates that the sum of the first and second mantissas is the third sum; and a value of 11 indicates that the sum of the first and second mantissas is the fourth sum.

[0065] For example, the first option value occupies 4 bits, where the first bit corresponds to the first sum, the second bit to the second sum, the third bit to the third sum, and the fourth bit to the fourth sum. For instance, if the value of the i-th bit is 1, it means that the sum corresponding to the i-th bit is the sum of the first and second mantissas, i∈{1,2,3,4}. For example, if the first option value is 1000, it means the sum of the first and second mantissas is the first sum; if the first option value is 0100, it means the sum of the first and second mantissas is the second sum; if the first option value is 0010, it means the sum of the first and second mantissas is the third sum; and if the first option value is 0001, it means the sum of the first and second mantissas is the fourth sum.

[0066] For example, if the value of the i-th bit is 0, it means that the sum of the i-th bit is the sum of the first and second mantissas, i∈{1,2,3,4}. For instance, if the first option value is 0111, it means that the sum of the first and second mantissas is the first sum; if the first option value is 1011, it means that the sum of the first and second mantissas is the second sum; if the first option value is 1101, it means that the sum of the first and second mantissas is the third sum; and if the first option value is 1110, it means that the sum of the first and second mantissas is the fourth sum.

[0067] In some embodiments, the second multiplexer 432 is configured to select a value as the sum of the first mantissa and the second mantissa based on the first option value, from the first operation result and the second operation result.

[0068] In some embodiments, the selection unit 430 is further configured to output the sum of the first mantissa and the second mantissa. In some embodiments, the second multiplexer 432 is further configured to output the sum of the first mantissa and the second mantissa.

[0069] The circuit uses two multiplexers to select the sum of the first and second mantissas from the first and second operation results. The two multiplexers perform two steps respectively: determining the correct sum and selecting the correct sum from the operation results. The circuit structure is simple.

[0070] IV. Preprocessing Unit In some embodiments, the preprocessing unit includes an exponential comparator and a shifter. For example, as shown... Figure 4 As shown, the preprocessing unit 440 includes an exponent comparator 441 and a shifter 442.

[0071] In some embodiments, the exponent comparator 441 is used to send a displacement value to the shifter, the displacement value being the exponent difference between the first mantissa and the second mantissa.

[0072] In some embodiments, the exponent comparator 441 is used to compare the exponents of the first mantissa and the second mantissa to determine the larger value of the first mantissa and the second mantissa.

[0073] In some embodiments, the exponent comparator 441 is further configured to send first indication information to the selection unit 430, the first indication information being used to indicate the smaller exponent value between the first mantissa and the second mantissa. In some embodiments, the indication comparator 441 is configured to send the first indication information to the first multiplexer 431.

[0074] In some embodiments, shifter 442 is used to align the exponents of the first mantissa and the second mantissa according to the shift value, and use the first mantissa after exponent alignment as the first addend, and the second mantissa after exponent alignment as the second addend.

[0075] In some embodiments, the smaller exponent in the first mantissa and the second mantissa is aligned with the exponent of the larger exponent, which is called left alignment; the larger exponent in the first mantissa and the second mantissa is aligned with the exponent of the smaller exponent, which is called right alignment.

[0076] In some embodiments, the floating-point arithmetic circuit may default to left-aligned or right-aligned exponent alignment. In some embodiments, the floating-point arithmetic circuit may set a default exponent, for example, both the first and second mantissas may be normalized to n×2. -4 In the form of.

[0077] In some embodiments, the shifter 442 is further configured to send sticky bit indication information to the selection unit 430, the sticky bit indication information being used to indicate whether there is a sticky bit after the first mantissa and the second mantissa are shifted. In some embodiments, the shifter 442 is configured to send sticky bit indication information to the first multiplexer 431.

[0078] The first indication information and the sticky bit indication information are used to assist the selection unit in determining the sum of the first mantissa and the second mantissa from the first operation result and the second operation result, so as to ensure the correctness of the obtained result.

[0079] In some embodiments, the preprocessing unit further includes a third inverter and a fourth inverter. For example, as shown... Figure 4 As shown, the preprocessing unit 440 also includes a third inverter 443 and a fourth inverter 444.

[0080] In some embodiments, when the inverting indication information corresponding to the first mantissa is a first value, the third inverter 443 is used to invert the first addend.

[0081] In some embodiments, when the inversion indication information corresponding to the second mantissa is a first value, the fourth inverter 444 is used to invert the second addend.

[0082] In some embodiments, only one of the first and second mantissas has a first value corresponding to the inversion indication information. In some embodiments, the first value refers to one possible value of the inversion indication information, and the second value refers to another possible value of the inversion indication information, and the first value and the second value are different. In some embodiments, the inversion indication information occupies at least one bit and is used to indicate whether the mantissa is inverted. For example, the inversion indication information occupies 1 bit, in which case the first value is 1 and the second value is 0. When the inversion indication information corresponding to the first mantissa is 1, the first mantissa is inverted, and the inversion indication information corresponding to the second mantissa is 0; or, the first value is 0 and the second value is 1. When the inversion indication information corresponding to the first mantissa is 0, the first mantissa is inverted, and the inversion indication information corresponding to the second mantissa is 1.

[0083] It should be noted that the value of the inversion indicator is unrelated to the role of the mantissa in the actual calculation. For example, the inversion indicator for the subtrahend can be the first value, and the inversion indicator for the minuend can also be the first value. For instance, if we need to calculate AB, we can treat B as the subtrahend to calculate A + (-B), thus requiring B to be inverted; or we can treat A as the subtrahend to calculate (-A) + B, in which case A needs to be inverted. The calculation is (-A) + B, but the result AB can still be obtained, which can be determined by the selection unit. For example, the result of AB and the result of (-A) + B are opposites, so we can invert the result of (-A) + B to obtain the result of AB. Therefore, there is no need to worry about whether to invert the subtrahend, and thus no need to set up additional hardware modules to determine which mantissa to invert, simplifying circuit configuration.

[0084] In some embodiments, when the first mantissa and the second mantissa are added together, the inversion indication information corresponding to the first mantissa is a second value, and the inversion indication information corresponding to the second mantissa is also a second value.

[0085] In some embodiments, if the first mantissa and the second mantissa are added, it is not necessary to invert the first addend and the second addend.

[0086] In some embodiments, the preprocessing unit may include only one of the third and fourth inverters, and the subtrahend is passed through the link where the inverter is located each time a floating-point subtraction operation is performed.

[0087] The above embodiments describe the structure of the floating-point arithmetic circuit. Compared with the floating-point arithmetic method based on two serial adders in related technologies, this application uses two parallel adders to perform floating-point arithmetic, which reduces the length of the critical path and the time required for floating-point arithmetic, effectively improving the efficiency of floating-point arithmetic.

[0088] To determine which of the four sums (first, second, third, and fourth sums) the sum of the first and second last digits corresponds to, please refer to cases one through seven below. Case one corresponds to floating-point addition, while cases two through seven correspond to floating-point subtraction.

[0089] Case 1: When both the first and second last digits are addends, the first option value is used to indicate that the sum of the first and second last digits is the third sum value.

[0090] Since the mantissa is positive in floating-point rules, when both the first and second mantissas are addends, there is no need to consider the effect of the sign on the result. Therefore, the third sum can be directly determined as the sum of the first and second mantissas. For example, the operation relationship between the first and second mantissas is first mantissa + second mantissa. For instance, if the first mantissa is 0.1100 (0.75) and the second mantissa is 0.0100 (0.25), then the sum of the first and second mantissas is 01.0000 (1). In this case, the first option value is used to instruct the second selector to select the third sum as the sum of the first and second mantissas.

[0091] Case 2: If it is determined from the sticky bit indication information that there is no sticky bit after the first mantissa and the second mantissa are shifted, and the value of the first sign bit is 0, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the first sum value.

[0092] In some embodiments, a sticky bit refers to whether the portion of the smaller exponent value discarded after exponent alignment is 0. Since the sticky bit is generated by the smaller exponent value, it is not necessary to indicate which mantissa generated the sticky bit if the preprocessing unit sends the first indication information. If the preprocessing unit does not send the first indication information, then it is necessary to indicate which mantissa generated the sticky bit.

[0093] Regarding the presence of sticky bits, taking 0.2 as an example, the binary representation of 0.2 is 0.0011 (0011 cycle). If 0.2 and 0.75 are aligned by exponent, and 4 bits are considered as a group, then the binary representation of 0.2 will be approximately equal to 0.0011, and the first 4 bits discarded are 0011, which is not equal to 0. Therefore, it is considered that 0.2 has sticky bits.

[0094] For example, if the first mantissa is 0.1000 (0.5) and the second mantissa is 0.0100 (0.25), and a subtraction operation is performed, the first addend remains 0.1000, and the second addend is 1.1011 obtained by inverting the second mantissa (treating the second mantissa as a negative number). There are no sticky bits, and the first sum is 0.0100 (0.25), meaning the first sign bit is 0. Therefore, the sum of the first and second mantissas is the first sum value. The first option value is then used to instruct the second selector to choose the first sum value as the sum of the first and second mantissas.

[0095] Case 3: If it is determined from the sticky bit indication information that there is no sticky bit after the first mantissa and the second mantissa are shifted, and the first sign bit is 1, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the fourth sum value.

[0096] For example, if the first mantissa is 0.0100 (0.25) and the second mantissa is 0.1000 (0.5), and a subtraction operation is performed, the first addend remains 0.0100, and the second addend is 1.0111 obtained by inverting the second mantissa (treating the second mantissa as negative). There are no sticky bits, so the first sum is 1.1100, meaning the first sign bit is 1. Therefore, the sum of the first and second mantissas is the fourth sum, which is 1.0100 (-0.25). The first option value is then used to instruct the second selector to choose the fourth sum as the sum of the first and second mantissas.

[0097] Case 4: If a sticky bit exists after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is the first value, and the second sign bit is 0, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the third sum value.

[0098] For example, if the first mantissa is 0.1100 (0.75) and the second mantissa is 0.0011 (0.2), and a subtraction operation is performed, the first addend is still 0.1100, and the second addend is 1.1100 obtained by inverting the second mantissa (treating the second mantissa as a negative number). There is a sticky bit, and the inversion indicator corresponding to the smaller exponent of the first and second mantissas is the first value. At this point, the third sum is 0.1000, meaning the second sign bit is 0. Therefore, the sum of the first and second mantissas is the third sum. That is, the sum of the first and second mantissas is 0.1000 (0.5). The actual value should be 0.1000 1100 (1100 repeating), with the remaining digits discarded. The first option value is used to instruct the second selector to choose the third sum as the sum of the first and second mantissas.

[0099] Case 5: If a sticky bit exists after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is the first value, and the second sign bit is 1, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the fourth sum value.

[0100] For example, if the first mantissa is 0.1011 (0.7) and the second mantissa is 0.0100 (0.25), and a subtraction operation is performed, the first addend is 1.0100 obtained by inverting the first mantissa (treating the first mantissa as negative), and the second addend is still 0.0100. There is a sticky bit, and the inversion indicator corresponding to the smaller exponent of the first and second mantissas is the first value. At this point, the third sum is 1.1000, meaning the second sign bit is 1. Therefore, the sum of the first and second mantissas is the fourth sum, which is 0.0111 (0.45). The actual value should be 0.011100011 (00011 repeating), with the remaining digits discarded. The first option value is used to instruct the second selector to choose the fourth sum as the sum of the first and second mantissas.

[0101] Case 6: If a sticky bit exists after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is the second value, and the first sign bit is 0, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the first sum value.

[0102] For example, if the first mantissa is 0.1011 (0.7) and the second mantissa is 0.0100 (0.25), and a subtraction operation is performed, the first addend is still 0.1011, and the second addend is 1.1011 obtained by inverting the second mantissa (treating the second mantissa as a negative number). There is a sticky bit, and the inversion indicator corresponding to the smaller exponent of the first and second mantissas is the second value. At this time, the first sum is 0.0111, meaning the first sign bit is 0. Therefore, the sum of the first and second mantissas is the first sum. That is, the sum of the first and second mantissas is 0.0111 (0.45). At this time, the actual value should be 0.011100011 (00011 repeating), with the remaining digits discarded. The first option value is used to instruct the second selector to select the first sum as the sum of the first and second mantissas.

[0103] Case 7: If a sticky bit exists after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is the second value, and the first sign bit is 1, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the second sum value.

[0104] For example, if the first mantissa is 0.0011 (0.2) and the second mantissa is 0.1100 (0.75), and a subtraction operation is performed, the first addend is still 0.0011, and the second addend is 1.0011 obtained by inverting the second mantissa (treating the second mantissa as a negative number). There is a sticky bit, and the inversion indicator corresponding to the smaller exponent of the first and second mantissas is the second value. At this point, the first sum is 1.0111, meaning the first sign bit is 1. Therefore, the sum of the first and second mantissas is the second sum, which is 1.1000 (0.55). The actual value should be 1.1000 1100 (1100 repeating), with the remaining digits discarded. The first option value is used to instruct the second selector to choose the second sum as the sum of the first and second mantissas.

[0105] In some embodiments, if the first option value is used to indicate one of the first sum, second sum, third sum, and fourth sum, then the above filtering method is performed by the first multiplexer. In some embodiments, if the first option value is used to indicate information formed by integrating the first indication information, the sticky bit indication information, the first sign bit, and the second sign bit, then the above filtering method is performed by the second multiplexer.

[0106] Using the above method, the selected unit can filter out the correct sum from the first sum, second sum, third sum, and fourth sum, and use it as the sum of the first and second last digits.

[0107] This application also provides the calculation method applied to the above-mentioned floating-point arithmetic circuit. Please refer to... Figure 5 The diagram illustrates a flowchart of an arithmetic method applied to a floating-point arithmetic circuit, provided in one possible implementation of this application. The method includes at least one of the following steps 510-540.

[0108] In some embodiments, the floating-point arithmetic circuit includes a preprocessing unit, a first addition unit, a second addition unit, and a selection unit, wherein the first addition unit and the second addition unit perform addition operations in parallel.

[0109] Step 510: The preprocessing unit performs preprocessing on the first mantissa and the second mantissa to obtain the first addend corresponding to the first mantissa and the second addend corresponding to the second mantissa, wherein the first mantissa is the mantissa of the first floating-point number and the second mantissa is the mantissa of the second floating-point number.

[0110] In some embodiments, the preprocessing unit includes an exponent comparator and a shifter. In some embodiments, the exponent comparator sends a shift value to the shifter, the shift value being the exponent difference between the first mantissa and the second mantissa. In some embodiments, the shifter aligns the exponents of the first mantissa and the second mantissa according to the shift value, and uses the exponent-aligned first mantissa as the first addend and the exponent-aligned second mantissa as the second addend.

[0111] In some embodiments, the exponent comparator is further configured to send a first indication information to the selection unit, the first indication information being used to indicate the smaller exponent value between the first mantissa and the second mantissa.

[0112] In some embodiments, the shifter is further configured to send sticky bit indication information to the selection unit, the sticky bit indication information being used to indicate whether there is a sticky bit after the first mantissa and the second mantissa are shifted.

[0113] In some embodiments, the preprocessing unit further includes a third inverter and a fourth inverter. In some embodiments, when the inversion indication information corresponding to the first mantissa is a first value, the third inverter is used to invert the first addend. In some embodiments, when the inversion indication information corresponding to the second mantissa is a first value, the fourth inverter is used to invert the second addend.

[0114] Step 520: The first addition unit performs an addition operation based on the first addend, the second addend, and the first numerical value to obtain the first operation result.

[0115] In some embodiments, the first operation result includes a first sum and a second sum, and the first addition operation unit includes a first adder and a first inverter.

[0116] In some embodiments, a first adder is used to calculate the sum of a first addend, a second addend, and a first numerical value to obtain a first sum. In some embodiments, a first inverter is used to invert the first sum to obtain a second sum.

[0117] In some embodiments, the first adder is further configured to send a first sign bit to the selection unit, the first sign bit being the sign bit in the first sum value.

[0118] Step 530: The second addition unit performs an addition operation based on the first addend and the second addend to obtain the second operation result.

[0119] In some embodiments, the second operation result includes a third sum and a fourth sum, and the second addition unit includes a second adder and a second inverter. In some embodiments, the second adder is used to calculate the sum of the first addend and the second addend to obtain the third sum. In some embodiments, the second inverter is used to invert the third sum to obtain the fourth sum.

[0120] In some embodiments, the second adder is further configured to send a second sign bit to the selection unit, the second sign bit being the sign bit in the second sum.

[0121] Step 540: The selection unit selects a value from the first operation result and the second operation result as the sum of the first tail number and the second tail number.

[0122] In some embodiments, the selection unit includes a first multiplexer and a second multiplexer.

[0123] In some embodiments, a first multiplexer is configured to determine a first option value based on first indication information, sticky bit indication information, a first sign bit, and a second sign bit; wherein the first indication information indicates the smaller exponent between the first mantissa and the second mantissa, the sticky bit indication information indicates whether a sticky bit exists after shifting the first mantissa and the second mantissa, the first sign bit is the sign bit in the first sum, the second sign bit is the sign bit in the third sum, the first sum is the sum of the first addend, the second addend, and the first value, and the third sum is the sum of the first addend and the second addend. In some embodiments, a second multiplexer is configured to select a value from the first operation result and the second operation result as the sum of the first mantissa and the second mantissa based on the first option value.

[0124] In some embodiments, when both the first and second mantissas are addends, the first option value is used to indicate that the sum of the first and second mantissas is the third sum.

[0125] In some embodiments, if it is determined from the sticky bit indication information that there is no sticky bit after the first mantissa and the second mantissa are shifted, and the value of the first sign bit is 0, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the first sum value.

[0126] In some embodiments, if it is determined from the sticky bit indication information that there is no sticky bit after the first mantissa and the second mantissa are shifted, and the first sign bit is 1, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the fourth sum value.

[0127] In some embodiments, after a sticky bit is determined to exist after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is a first value, and the second sign bit is 0, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is a third sum value.

[0128] In some embodiments, after it is determined that there is a sticky bit after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is a first value, and the second sign bit is 1, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is a fourth sum value.

[0129] In some embodiments, after a sticky bit is determined to exist after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is a second value, and the first sign bit is 0, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is a first sum value.

[0130] In some embodiments, after a sticky bit is determined to exist after the first mantissa and the second mantissa are shifted according to the sticky bit indication information, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is a second value, and the first sign bit is 1, the first option value is used to indicate that the sum of the first mantissa and the second mantissa is a second sum value.

[0131] The above are method embodiments corresponding to the floating-point arithmetic circuit embodiments. For details not disclosed in the method embodiments of this application, please refer to the floating-point arithmetic circuit embodiments of this application.

[0132] The technical solution provided in this application uses two parallel addition units to process the operation of the first floating-point number and the second floating-point number. During the operation, only the processing time of one addition unit needs to be waited, which shortens the logic chain of floating-point number operation and thus saves the time required for floating-point number operation.

[0133] This application also provides exemplary embodiments to illustrate the solution of this application.

[0134] When performing addition or subtraction on two floating-point numbers, their exponents must first be aligned. This alignment generates the two mantissas to be added and a sticky bit (named "sticky") resulting from the exponent alignment. After exponent alignment, the exponents of the two floating-point numbers being added or subtracted should be the same. Typically, the mantissa of the smaller exponent is shifted right to increase its exponent to match that of the other floating-point number. During this right shift, non-zero values ​​may be shifted out of the least significant bit, resulting in a loss of precision; this is where the sticky bit comes in.

[0135] The function of adding or subtracting two exponent-aligned mantissas (named mat0 and mat1) is described by the following formula.

[0136] If it's an addition, then calculate directly using the following formula: Res = mat0 + mat1 If it's a subtraction, two steps are required. First, invert the subtrahend (let's assume it's mat0). Then, based on the value of the sticky bit, decide whether to add 1. Second, if the addition result is negative, adjust it to positive by taking the negative bit. The formula is as follows: Step 1: Sub_res = sticky ? ~mat0+mat1:~mat0+mat1+1; Step 2: Res=sub_res<0 ? (sticky ? ~sub_res:~sub_res+1):sub_res.

[0137] In the formula, Res represents the final calculation result, Sub_res represents the intermediate calculation result when calculating subtraction, "~" means bitwise inversion, and "a ? b : c" means that if condition a is true, the result is equal to b, otherwise the result is equal to c.

[0138] The proposed solution in this application can be described as follows.

[0139] If subtraction is performed, the subtrahend needs to be inverted. The neg flag (invert flag) corresponding to the inverted mantissa will be set to valid, and the mantissa inversion operation is first processed based on neg. After padded mat0 and mat1 with at least 2 bits of 0 in the high-order bits, they are then inverted to obtain add0 (the first addend) and add1 (the second addend) respectively. It should be noted that only one of neg0 and neg1 can be valid at a time. Furthermore, one of the neg flags can be fixed to be invalid based on upstream calculations, which does not affect the core idea of ​​this proposal.

[0140] Add0 = neg0 ? ~mat0 : mat0 Add1 = neg1 ? ~mat1 : mat1 Then use add0 and add1 to perform two additions simultaneously: Mid_res0 = add0 + add1 Mid_res1 = add0 + add1 + 1 The highest bits of Mid_res0 (third sum) and Mid_res1 (first sum) are named Sgn_res0 (second sign bit) and Sgn_res1 (first sign bit) respectively. They can be used to determine the sign of Mid_res0 and Mid_res1. If the highest bit is 1, the result is less than 0; otherwise, the result is greater than or equal to 0.

[0141] There are several possible values ​​for the final result.

[0142] Case 1: Neg0 and Neg1 are both equal to 0 (i.e., addition). The final result is calculated according to the following formula: Res = Mid_res0 Scenario 2: When performing subtraction, there are no sticky bits and mid_res1>=0. The final calculation result is calculated according to the following formula: Res = Mid_res1 Case 3: When performing subtraction, there is no sticky bit and mid_res1 < 0. The final calculation result is calculated according to the following formula: Res = ~Mid_res0 Case 4: When performing subtraction, there are sticky bits, and the mantissa that generates the sticky bit is the same as the valid mantissa of neg, and mid_res0>=0, the final result is calculated according to the following formula: Res = Mid_res0 Case 5: When performing subtraction, there are sticky bits, and the mantissa that generates the sticky bits is the same as the valid mantissa of neg, and mid_res0 < 0. The final result is calculated according to the following formula: Res = ~Mid_res0 Case 6: When performing subtraction, there are sticky bits, and the mantissa that generates the sticky bits is not the same as the valid mantissa of neg, and mid_res1>=0. The final result is calculated according to the following formula: Res = Mid_res1 Case 7: When performing subtraction, there are sticky bits, and the mantissa that generates the sticky bits is not the same as the valid mantissa of neg, and mid_res1 < 0. The final result is calculated according to the following formula: Res = ~Mid_res1 Exponent Difference Calculation: Calculate the difference in exponents between two floating-point numbers being added or subtracted, and obtain the shift value shf_val (sticky bit indicator) and a sticky_mat_sel (first indicator). shf_val indicates how the mantissa shifting module should shift the two mantissas to achieve exponent alignment. sticky_mat_sel indicates the smaller exponent of the two floating-point numbers; if a sticky bit is generated, it must originate from the smaller exponent.

[0143] Mantissa shift: Based on the calculation result of the exponent difference calculation module, the two mantissas are shifted. After the shift, the exponents corresponding to the least significant and most significant bits of the two mantissas should be the same. Furthermore, the high-order bits of the two shifted numbers are padded with 0s by 2 bits. Simultaneously, the sticky bits are calculated. If the part of the lower-order bit of the smaller exponent that does not participate in the addition is not all 0s, then the sticky bits are valid; otherwise, the sticky bits are invalid.

[0144] There are several ways to implement mantissa shift, such as... Figure 6 As shown, assuming the exponents of the two floating-point numbers are exp0 and exp1, and exp0-exp1=5, the mantissa shift module can perform the calculation add1 = mat1>>5, and the viscous bit can be calculated using the following formula: sticky = mat1[4:0]==0? 0:1 Inversion logic: When performing subtraction, one of the two mantissas needs to be bitwise inverted. The inversion logic is calculated according to the following formula: add0 = neg0 ? ~add0 : add0 add1 = neg1 ? ~add1 : add1 Adders: Two adders perform addition on two numbers that have been shifted and inverted. One of the adders needs to add an extra 1, calculated according to the following formula: mid_res0 = add0 + add1 mid_res1 = add0 + add1 + 1 Furthermore, the highest bit of mid_res0 is taken as sgn_res0, and the highest bit of mid_res1 is taken as sgn_res1.

[0145] Selection Decision: Decide which result to use as the result for adder adjustment (to obtain the correct result through debugging). Calculate several selection signals that will not be valid simultaneously using the following formula: sticky_neg_same0 = ((neg0==1)&&(sticky_mat_sel==MAT0)) sticky_neg_same1 = ((neg1==1)&&(sticky_mat_sel==MAT1)) sticky_neg_same = sticky_neg_same0 || sticky_neg_same1 sel_p1 = ((Sticky==0)&&(res1_sgn==0)) || ((Sticky==1)&&(sticky_neg_same==0)&&(res1_sgn==0)) sel_p0n = ((Sticky==0)&&(res1_sgn==1))|| ((Sticky==1)&&(sticky_neg_same==1)&&(res0_sgn==1)) sel_p0 = (neg0==neg1)|| ((Sticky==1)&&(sticky_neg_same==1)&&(res0_sgn==0)) sel_p1n = ((Sticky==1)&&(sticky_neg_same==0)&&(res1_sgn==1)) Here, sel_p1 indicates that mid_res1 is taken as the output result, which includes two cases: when the sticky bit is invalid during subtraction and mid_res1 is greater than or equal to 0, and when the sticky bit is valid during subtraction, the mantissa that generates the sticky bit and the mantissa that is inverted are not the same mantissa, and mid_res1 is greater than or equal to 0. These correspond to cases two and six mentioned above.

[0146] Where sel_p0 means taking mid_res0 as the output result, which includes two cases: when calculating addition, or when performing subtraction, there are sticky bits and the mantissa that produces the sticky bits is the same as the valid mantissa of neg, and mid_res1>=0, corresponding to cases one and four described above.

[0147] Here, `sel_p0n` indicates that `~mid_res0` is taken as the output result, which includes two cases: either the sticky bit is invalid and `mid_res1` is less than 0 when performing subtraction, or the sticky bit is valid and the mantissa that generates the sticky bit is the same as the valid mantissa of `neg`, and `mid_res0` is less than 0. These correspond to cases three and five mentioned above.

[0148] Here, sel_p1n indicates that ~mid_res1 is taken as the output result, which includes one case: when the sticky bit is valid during subtraction, the mantissa that generates the sticky bit is not the same as the mantissa that is valid in neg, and mid_res1 is less than 0. This corresponds to case seven mentioned above.

[0149] Finally, sel_p1n, sel_p0n, sel_p0, and sel_p1 are combined to form or translated into res_sel (the first option value).

[0150] Selector: Select one from mid_res0, mid_res1, ~mid_res0, ~mid_res1 as the mantissa-adjusted result Res (the sum of the first and second mantissas) according to the instruction of rel_sel.

[0151] This application changes the original two serial adders for floating-point mantissa addition and subtraction to two parallel adders and a set of selectors in serial order, thereby reducing the length of the critical path in computation.

[0152] The floating-point arithmetic process will be illustrated with specific examples below.

[0153] I. Addition Operations (Case 1) Assume the first mantissa is 0.1000 (0.5) and the second mantissa is 0.0100 (0.25). The exponent of the current result is already aligned, so the calculation process of the preprocessing unit will not be described again.

[0154] In addition, there is no need to invert the mantissa. Therefore, the first addend is still 0.1000 and the second addend is still 0.0100. At this time, the sum of the first and second mantissas is the third sum, that is, 0.1000 + 0.0100 = 0.1100 (0.75).

[0155] II. Subtraction 1. The result is positive and there are no sticky positions (Case 2) Assume the first mantissa is 0.1100 (0.75) and the second mantissa is 0.1000 (0.5), where the inversion indication information corresponding to the second mantissa is the first value. Then, the preprocessing module sends the first indication information and the sticky bit indication information to the selection unit. The first indication information is used to indicate that the smaller exponent is the second mantissa, and the sticky bit indication information is used to indicate that there is no sticky bit.

[0156] At this point, the first addend is still 0.1100. The second addend is obtained by treating the second mantissa as a negative number and then inverting its bits. The second addend is 1.0111. After calculation, the first sum is 0.0100, and the first sign bit is 0. Therefore, the sum of the first and second mantissas should be the first sum, i.e., 0.1000 - 0.1100 = 0.0100 (0.25).

[0157] 2. The result is negative and there are no sticky positions (Case 3) Assume the first mantissa is 0.1000 (0.5) and the second mantissa is 0.1100 (0.75), where the inversion indication information corresponding to the second mantissa is the first value. Then, the preprocessing module sends the first indication information and the sticky bit indication information to the selection unit. The first indication information is used to indicate that the smaller exponent is the first mantissa, and the sticky bit indication information is used to indicate that there is no sticky bit.

[0158] At this point, the first addend is still 0.1000, and the second addend is obtained by treating the second mantissa as a negative number and then inverting its bits. The second addend is 1.0011. After calculation, the first sum is 1.1100, and the first sign bit is 1. Therefore, the sum of the first and second mantissas should be the fourth sum, i.e., 0.1000 - 0.1100 = 1.0100 (-0.25).

[0159] 3. The result is positive and there is a viscous position (Case 4). Assume the first mantissa is 0.1100 (0.75) and the second mantissa is 0.0011 (0.2), where the inversion indication information corresponding to the second mantissa is the first value. Then, the preprocessing module sends the first indication information and the sticky bit indication information to the selection unit. The first indication information is used to indicate that the smaller exponent is the second mantissa, and the sticky bit indication information is used to indicate the presence of a sticky bit.

[0160] At this point, the first addend is still 0.1100. The second addend is obtained by treating the second mantissa as a negative number and then inverting it bit by bit, so the second addend is 1.1100. After calculation, the third sum is 0.1000, and the second sign bit is 0. Therefore, the sum of the first and second mantissas should be the third sum, i.e., 0.1100 - 0.0011 = 0.1000 (0.55, approximately equal to 0.5, other bits are discarded).

[0161] 4. The result is negative, and there is a viscous position (Case 7). Assume the first mantissa is 0.0011 (0.2) and the second mantissa is 0.1100 (0.75), where the inversion indication information corresponding to the second mantissa is the first value. Then, the preprocessing module sends the first indication information and the sticky bit indication information to the selection unit. The first indication information is used to indicate that the smaller exponent is the first mantissa, and the sticky bit indication information is used to indicate the presence of a sticky bit.

[0162] At this point, the first addend is still 0.0011. The second addend is obtained by treating the second mantissa as a negative number and then inverting its bits, so the second addend is 1.0011. After calculation, the third sum is 1.0111, with the first sign bit set to 1. Therefore, the sum of the first and second mantissas should be the second sum, i.e., 0.0011 - 0.1100 = 1.1000 (-0.55, approximately equal to -0.5, with other bits discarded).

[0163] In some embodiments, a processor is also provided, the processor including the above-described floating-point arithmetic circuit.

[0164] In some embodiments, a chip product is also provided, the chip product including a processor, the processor including the above-described floating-point arithmetic circuit.

[0165] Please refer to Figure 7 This is a simplified structural block diagram of a computer device 700 provided in one possible implementation of this application. The computer device 700 can be used to implement the arithmetic methods applied to floating-point arithmetic circuits provided in the above embodiments.

[0166] Typically, computer device 700 includes a processor 701 and a memory 702.

[0167] Processor 701 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 701 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 701 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 701 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 701 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning. Processor 701 includes the aforementioned floating-point arithmetic circuitry.

[0168] The memory 702 may include one or more computer-readable storage media, which may be non-transitory. The memory 702 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 702 is used to store a computer program configured to be executed by one or more processors to implement the above-described arithmetic methods applied to floating-point arithmetic circuits.

[0169] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on the computer device 700, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0170] In some embodiments, the computer device 700 may be a server, a server cluster, an artificial intelligence computing cluster, a cloud computing cluster, etc., wherein the artificial intelligence computing cluster may also be simply referred to as an intelligent computing cluster or a smart computing cluster, and this application does not limit it in this regard.

[0171] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0172] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A floating point number operation circuit, characterized by comprising: The floating-point arithmetic circuit includes: a preprocessing unit, a first addition unit, a second addition unit, and a selection unit, wherein the first addition unit and the second addition unit perform addition operations in parallel; The preprocessing unit is used to perform preprocessing on the first mantissa and the second mantissa to obtain the first addend corresponding to the first mantissa and the second addend corresponding to the second mantissa, wherein the first mantissa is the mantissa of the first floating-point number and the second mantissa is the mantissa of the second floating-point number; The first addition unit is used to perform an addition operation based on the first addend, the second addend, and the first numerical value to obtain a first operation result; The second addition unit is used to perform an addition operation based on the first addend and the second addend to obtain a second operation result; The selection unit is used to select a value from the first calculation result and the second calculation result as the sum of the first tail number and the second tail number.

2. The floating-point number operation circuit according to claim 1, wherein The first operation result includes a first sum and a second sum, and the first addition operation unit includes a first adder and a first inverter; The first adder is used to calculate the sum of the first addend, the second addend, and the first value to obtain the first sum value; The first inverter is used to invert the first sum to obtain the second sum.

3. The floating-point arithmetic circuit according to claim 2, characterized in that, The first adder is further configured to send a first sign bit to the selection unit, the first sign bit being the sign bit in the first sum.

4. The floating-point number operation circuit according to claim 1, wherein The second operation result includes a third sum and a fourth sum, and the second addition operation unit includes a second adder and a second inverter; The second adder is used to calculate the sum of the first addend and the second addend to obtain the third sum value; The second inverter is used to invert the third sum to obtain the fourth sum.

5. The floating-point arithmetic circuit according to claim 4, characterized in that, The second adder is further configured to send a second sign bit to the selection unit, the second sign bit being the sign bit in the second sum value.

6. The floating-point arithmetic circuit according to claim 1, characterized in that, The selection unit includes a first multiplexer and a second multiplexer; The first multiplexer is used to determine a first option value based on the first indication information, the sticky bit indication information, the first sign bit, and the second sign bit; Wherein, the first indication information is used to indicate the smaller exponent between the first mantissa and the second mantissa, the sticky bit indication information is used to indicate whether there is a sticky bit after the first mantissa and the second mantissa are shifted, the first sign bit is the sign bit in the first sum, the second sign bit is the sign bit in the third sum, the first sum is the sum of the first addend, the second addend and the first value, and the third sum is the sum of the first addend and the second addend; The second multiplexer is used to select a value from the first operation result and the second operation result as the sum of the first mantissa and the second mantissa, based on the first option value.

7. The floating-point arithmetic circuit according to claim 6, characterized in that, When both the first and second mantissas are addends, the first option value is used to indicate that the sum of the first and second mantissas is the third sum value; or, If, based on the sticky bit indication information, it is determined that there are no sticky bits after the first mantissa and the second mantissa are shifted, and the first sign bit is 0, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the first sum value; or, If, based on the sticky bit indication information, it is determined that there are no sticky bits after the first and second mantissas are shifted, and the first sign bit is 1, then the first option value is used to indicate that the sum of the first and second mantissas is the fourth sum value; or, If, based on the sticky bit indication information, it is determined that a sticky bit exists after the first mantissa and the second mantissa are shifted, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is a first value, and the second sign bit is 0, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the third sum value; or... If, based on the sticky bit indication information, it is determined that a sticky bit exists after the first mantissa and the second mantissa are shifted, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is a first value, and the second sign bit is 1, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the fourth sum value; or... If, based on the sticky bit indication information, it is determined that a sticky bit exists after the first mantissa and the second mantissa are shifted, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is the second value, and the first sign bit is 0, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the first sum value; or... If, based on the sticky bit indication information, it is determined that there is a sticky bit after the first mantissa and the second mantissa are shifted, and the inversion indication information corresponding to the smaller exponent of the first mantissa and the second mantissa indicated by the first indication information is the second value, and the first sign bit is 1, then the first option value is used to indicate that the sum of the first mantissa and the second mantissa is the second sum value.

8. The floating-point arithmetic circuit according to any one of claims 1 to 7, characterized in that, The preprocessing unit includes an exponent comparator and a shifter; The exponent comparator is used to send a displacement value to the shifter, the displacement value being the exponent difference between the first mantissa and the second mantissa; The shifter is used to align the exponents of the first mantissa and the second mantissa according to the shift value, and to use the first mantissa after exponent alignment as the first addend, and the second mantissa after exponent alignment as the second addend.

9. The floating-point arithmetic circuit according to claim 8, characterized in that, The exponent comparator is also used to send a first indication information to the selection unit, the first indication information being used to indicate the smaller exponent value between the first mantissa and the second mantissa.

10. The floating-point arithmetic circuit according to claim 8, characterized in that, The shifter is also used to send sticky bit indication information to the selection unit, the sticky bit indication information being used to indicate whether there is a sticky bit after the first mantissa and the second mantissa are shifted.

11. The floating-point arithmetic circuit according to claim 8, characterized in that, The preprocessing unit further includes a third inverter and a fourth inverter; When the inverting indication information corresponding to the first mantissa is a first value, the third inverter is used to invert the first addend; When the inverting indication information corresponding to the second mantissa is a first value, the fourth inverter is used to invert the second addend.

12. A processor, characterized in that, The processor includes a floating-point arithmetic circuit as described in any one of claims 1 to 11.

13. A chip product, characterized in that, The chip product includes a processor, which includes a floating-point arithmetic circuit as described in any one of claims 1 to 11.

14. A computer device, characterized in that, The computer device includes a processor, the processor including the floating-point arithmetic circuitry as described in any one of claims 1 to 11.

15. An arithmetic method applied to a floating-point arithmetic circuit, characterized in that, The floating-point arithmetic circuit includes: a preprocessing unit, a first addition unit, a second addition unit, and a selection unit, wherein the first addition unit and the second addition unit perform addition operations in parallel; The preprocessing unit performs preprocessing on the first mantissa and the second mantissa to obtain the first addend corresponding to the first mantissa and the second addend corresponding to the second mantissa, wherein the first mantissa is the mantissa of the first floating-point number and the second mantissa is the mantissa of the second floating-point number; The first addition unit performs an addition operation based on the first addend, the second addend, and the first numerical value to obtain a first operation result; The second addition unit performs an addition operation based on the first addend and the second addend to obtain a second operation result; The selection unit selects a value from the first calculation result and the second calculation result as the sum of the first tail number and the second tail number.

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