Chip supporting batch configuration of registers, task execution method, medium and equipment

Abstract

The invention discloses a chip supporting batch configuration of registers, a task execution method, a medium and equipment. The chip supporting batch configuration of registers comprises a processor, and the processor is used for obtaining first indication information for indicating a plurality of task execution circuits to participate in target task processing and task configuration information to be shared by the task execution circuits; the batch configuration circuit is used for acquiring first indication information and task configuration information from the processor; and based on the first indication information and the task configuration information, configuring first registers corresponding to the plurality of task execution circuits respectively, so that the plurality of task execution circuits cooperatively execute the target task. According to the embodiment of the invention, processor resources can be saved.

Description

Technical Field

[0001] This disclosure relates to chip technology, and in particular to a chip, task execution method, medium, and device that support batch configuration registers. Background Technology

[0002] Currently, chips are being used more and more widely. For example, in the field of driving technology, intelligent driving chips and intelligent cockpit chips are being used more and more extensively.

[0003] In some cases, it is necessary to use multiple circuits in a chip to work together to perform the same task. Before the task is executed, the processor in the chip needs to configure these circuits separately, which will greatly waste processor resources. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a chip, task execution method, medium, and device that support batch configuration of registers.

[0005] According to one aspect of the present disclosure, a chip supporting bulk configuration registers is provided, comprising: The processor is configured to acquire first indication information indicating multiple task execution circuits to participate in the target task processing, and task configuration information to be shared by the multiple task execution circuits. A batch configuration circuit is used to acquire the first indication information and the task configuration information from the processor; based on the first indication information and the task configuration information, it configures the first registers corresponding to the multiple task execution circuits respectively, so that the multiple task execution circuits can collaboratively execute the target task.

[0006] According to another aspect of the present disclosure, a task execution method based on a chip supporting batch configuration registers is provided, comprising: The processor in the chip acquires first indication information indicating multiple task execution circuits to participate in the target task, as well as task configuration information to be shared by the multiple task execution circuits. The first indication information and the task configuration information from the processor are obtained through the batch configuration circuit in the chip; The batch configuration circuit in the chip configures the first registers corresponding to the multiple task execution circuits based on the first indication information and the task configuration information, so that the multiple task execution circuits can work together to execute the target task.

[0007] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program that is executed by a processor to perform the above-described task execution method based on a chip supporting bulk configuration registers.

[0008] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the above-described task execution method based on a chip that supports batch configuration registers.

[0009] According to another aspect of the present disclosure, a computer program product is provided that, when instructions in the computer program product are executed by a processor, performs the above-described task execution method based on a chip supporting bulk configuration registers.

[0010] Based on the chip, task execution method, medium, device, and program product supporting batch configuration registers provided in the above embodiments of this disclosure, the batch configuration circuit can configure the first registers corresponding to multiple task execution circuits participating in the target task processing based on the first instruction information and task configuration information from the processor, so that the multiple task execution circuits can collaboratively execute the target task. That is, in the embodiments of this disclosure, for scenarios that require multiple circuits to collaboratively execute the same task, the processor only needs to provide the first instruction information and task configuration information to the batch configuration circuit, and the batch configuration circuit can directly configure the multiple circuits used to collaboratively execute the same task without the need for related configuration by the processor, thereby saving processor resources. Attached Figure Description

[0011] Figure 1 This is a system architecture diagram to which some exemplary embodiments of this disclosure apply.

[0012] Figure 2 This is one of the schematic diagrams of a chip supporting bulk configuration registers provided by some exemplary embodiments of this disclosure.

[0013] Figure 3 This is a schematic diagram of the structure of a batch configuration circuit in some exemplary embodiments of this disclosure.

[0014] Figure 4 This is the second schematic diagram of the structure of a chip that supports bulk configuration registers, provided by some exemplary embodiments of this disclosure.

[0015] Figure 5This is the third schematic diagram of the structure of a chip that supports bulk configuration registers, provided by some exemplary embodiments of this disclosure.

[0016] Figure 6-1 This is a schematic diagram illustrating the implementation principle of using multiple modules to collaboratively execute the same task in related technologies.

[0017] Figure 6-2 This is a schematic diagram illustrating the implementation principle of using multiple modules to collaboratively perform the same task in some exemplary embodiments of this disclosure.

[0018] Figure 6-3 This is a comparative schematic diagram illustrating the implementation principles of using multiple modules to collaboratively execute the same task in related technologies and some exemplary embodiments of this disclosure.

[0019] Figure 7 This is one of the flowcharts illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0020] Figure 8 This is a second flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0021] Figure 9 This is the third flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0022] Figure 10 This is the fourth flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0023] Figure 11 This is the fifth flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0024] Figure 12 This is the sixth flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0025] Figure 13 This is the seventh flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0026] Figure 14 This is the eighth flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0027] Figure 15 This is the ninth flowchart illustrating a task execution method for a chip that supports batch configuration registers, provided by some exemplary embodiments of this disclosure.

[0028] Figure 16 This is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of this disclosure. Detailed Implementation

[0029] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0030] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0031] Application Overview Currently, chips have a wide range of applications. For example, in the field of driving technology, intelligent driving chips and smart cockpit chips are widely used. Another example is in the field of imaging, where image processing chips are widely used.

[0032] In some cases, it is necessary to use multiple circuits on a chip to coordinate the execution of the same task. For example, multiple Direct Memory Access (DMA) controllers on a chip need to coordinate the execution of the same data transfer task. Before the task is executed, the processor on the chip needs to configure the multiple circuits used to coordinate the execution of the same task, which will greatly waste processor resources.

[0033] Exemplary System Figure 1 This is a system architecture diagram applicable to some exemplary embodiments of the present disclosure, including a processor 20 and a batch configuration circuit 40. The batch configuration circuit 40 can be electrically connected to the processor 20. The processor 20 does not need to directly configure multiple circuits used to collaboratively perform the same task. The batch configuration circuit 40 can configure multiple circuits used to collaboratively perform the same task on behalf of the processor 20, thereby saving processor 20 resources.

[0034] Exemplary chip Embodiments of this disclosure provide a chip that supports bulk configuration registers. Optionally, the chip that supports bulk configuration registers can be a system-on-a-chip (SOC), such as, but not limited to, intelligent driving chips, intelligent cockpit chips, etc.

[0035] Figure 2 This is a schematic diagram of the structure of a chip supporting bulk configuration registers provided by some exemplary embodiments of this disclosure. For example... Figure 2As shown, the chips that support batch configuration of registers include: Processor 20 is used to acquire first indication information indicating multiple task execution circuits 30 to participate in target task processing, and task configuration information to be shared by multiple task execution circuits 30. Batch configuration circuit 40 is used to obtain first instruction information and task configuration information from processor 20; based on the first instruction information and task configuration information, it configures the first register 301 corresponding to the multiple task execution circuits 30 respectively, so that the multiple task execution circuits 30 can coordinately execute the target task.

[0036] Optionally, processor 20 is circuitry for issuing tasks. Processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), etc.

[0037] Optionally, the batch configuration circuit 40 can replace the function of the processor in related technologies and is a circuit for configuring multiple circuits used to collaboratively perform the same task.

[0038] In embodiments of this disclosure, a software program running on a chip supporting batch configuration registers can determine a target task to be executed and determine multiple circuits for collaboratively executing the target task. The target task may include, but is not limited to, data transfer tasks, image processing tasks, etc., and image processing tasks may include, but are not limited to, image scaling tasks, convolution calculation tasks, pooling calculation tasks, etc. The multiple circuits for collaboratively executing the target task may also be referred to as multiple task execution circuits 30 to participate in the target task processing. If the target task is a data transfer task, the multiple task execution circuits 30 may correspond to multiple DMA controllers. If the target task is an image scaling task, the multiple task execution circuits 30 may correspond to multiple image scaling circuits. If the target task is a convolution calculation task, the multiple task execution circuits 30 may correspond to multiple convolution calculation circuits. The software program running on the chip supporting batch configuration registers can provide the processor 20 with first indication information indicating the multiple task execution circuits 30 to participate in the target task processing, and task configuration information to be shared by the multiple task execution circuits 30. Accordingly, the processor 20 can obtain the first indication information and the task configuration information. The first indication information may include the identification information of each of the multiple task execution circuits 30. The task configuration information can be configuration information used to define the target task, such as configuration information used to define the task type, task size, etc. of the target task. The processor 20 can be electrically connected to the batch configuration circuit 40. The processor 20 can send the first instruction information and the task configuration information to the batch configuration circuit 40, and correspondingly, the batch configuration circuit 40 can receive the first instruction information and the task configuration information.

[0039] The batch configuration circuit 40 can be electrically connected to multiple task execution circuits 30. Based on the first indication information and task configuration information, the batch configuration circuit 40 can configure the first registers 301 corresponding to each of the multiple task execution circuits 30. Here, the first register 301 corresponding to any task execution circuit 30 refers to a register within that task execution circuit 30. By writing information into this register, the behavior of that task execution circuit 30 can be precisely controlled. Configuring the first registers 301 corresponding to each of the multiple task execution circuits 30 based on the first indication information and task configuration information can be understood as writing information into the first registers 301 corresponding to each of the multiple task execution circuits 30, so that the multiple task execution circuits 30 respond to the information written into their respective first registers 301 and collaboratively execute the target task. Optionally, the target task can be viewed as a collection of multiple subtasks. The multiple task execution circuits 30 can each execute one subtask of the target task, and the multiple task execution circuits 30 can jointly complete the target task.

[0040] In the embodiments of this disclosure, the batch configuration circuit 40 can configure the first registers 301 corresponding to the multiple task execution circuits 30 to participate in the target task processing based on the first instruction information and task configuration information from the processor 20, so that the multiple task execution circuits 30 can collaboratively execute the target task. That is, in the embodiments of this disclosure, for scenarios that require multiple circuits to collaboratively execute the same task, the processor 20 only needs to provide the first instruction information and task configuration information to the batch configuration circuit 40, and the batch configuration circuit 40 can directly configure the multiple circuits used to collaboratively execute the same task without the processor 20 needing to perform related configuration, thereby saving processor 20 resources.

[0041] In some optional examples, such as Figure 3 As shown, the batch configuration circuit 40 includes a second register 401 and a configuration sub-circuit 403; Batch configuration circuit 40 is used to acquire first instruction information and task configuration information from processor 20; based on the first instruction information and task configuration information, it configures the first registers 301 corresponding to the multiple task execution circuits 30 respectively, so that the multiple task execution circuits 30 coordinately execute the target task, including: The second register 401 is used to acquire and store the first instruction information from the processor 20; The configuration sub-circuit 403 is used to acquire and store task configuration information from the processor 20; based on the first base address in the first address range corresponding to the configuration sub-circuit 403, the first storage address of the task configuration information in the first address range, and the first indication information, it determines the first destination address in the first register 301 corresponding to the multiple task execution circuits 30 respectively; and writes the task configuration information into the first register 301 corresponding to the multiple task execution circuits 30 respectively according to the first destination address corresponding to the multiple task execution circuits 30 respectively. Multiple task execution circuits 30 are used to collaboratively execute target tasks based on the task configuration information stored in their respective first registers 301.

[0042] Optionally, the second register 401 may be a circuit for temporarily storing information.

[0043] Optionally, the configuration sub-circuit 403 can be a circuit for configuring multiple task execution circuits 30. The first address range corresponding to the configuration sub-circuit 403 can be understood as an address range specifically reserved for use by the configuration sub-circuit 403. The first base address in the first address range corresponding to the configuration sub-circuit 403 can be, for example, the starting address in the first address range. In some implementations, the configuration sub-circuit 403 also has a storage function. For example, the configuration sub-circuit 403 can include a storage medium for supporting the storage function, in which case the first address range can be the address range corresponding to the storage space that the storage medium can provide. In other implementations, the configuration sub-circuit 403 does not have a storage function, in which case the storage medium can be located outside the configuration sub-circuit 403, ensuring that the configuration sub-circuit 403 can access the storage medium.

[0044] In the embodiments of this disclosure, the processor 20 can be electrically connected to the second register 401. The processor 20 can send first indication information to the second register 401, and correspondingly, the second register 401 can receive and store the first indication information. The processor 20 can also be electrically connected to the configuration sub-circuit 403. The processor 20 can send task configuration information to the configuration sub-circuit 403, and correspondingly, the configuration sub-circuit 403 can receive and store the task configuration information. Here, the task configuration information can be stored in a first address range corresponding to the configuration sub-circuit 403. The configuration sub-circuit 403 can be electrically connected to the second register 401, and the configuration sub-circuit 403 can read the first indication information from the second register 401. The configuration sub-circuit 403 can also determine the first destination address in the first register 301 corresponding to each of the multiple task execution circuits 30 based on the first base address in the first address range corresponding to the configuration sub-circuit 403, the first storage address of the task configuration information in the first address range, and the first indication information. The first destination address in the first register 301 corresponding to any task execution circuit 30 can be understood as the write address of the task configuration information in the first register 301 corresponding to that task execution circuit 30. According to the first destination addresses corresponding to the multiple task execution circuits 30, the configuration sub-circuit 403 can write the task configuration information to the first register 301 corresponding to each of the multiple task execution circuits 30, thus enabling register configuration of the multiple task execution circuits 30, i.e., configuring the multiple task execution circuits 30.

[0045] In some optional embodiments of this disclosure, the first indication information includes a second base address within the second address range corresponding to the first register 301. Optionally, each of the first registers 301 corresponding to multiple task execution circuits 30 may have a corresponding second address range. The second address range corresponding to the first register 301 of any task execution circuit 30 can be understood as an address range specifically reserved for use by that task execution circuit 30. The second base address within any second address range may, for example, be the starting address within that second address range.

[0046] The configuration sub-circuit 403 is used to determine the first destination address in the first register 301 corresponding to each of the multiple task execution circuits 30, based on the first base address of the first address range corresponding to the configuration sub-circuit 403, the first storage address of the task configuration information in the first address range, and the first indication information, including: The configuration sub-circuit 403 is used to determine the first address offset of the first storage address relative to the first base address; and to apply the first address offset to the second base addresses corresponding to the multiple task execution circuits 30 respectively, so as to obtain the first destination addresses corresponding to the multiple task execution circuits 30 respectively.

[0047] Optionally, the configuration sub-circuit 403 can subtract the first storage address from the first base address to obtain the first address offset of the first storage address relative to the first base address. Assuming the first base address is represented as addr1, the first storage address as addr2, and the first address offset of the first storage address relative to the first base address as offset1, then offset1 = addr2 - addr1. For any task execution circuit 30 among the multiple task execution circuits 30, the configuration sub-circuit 403 can sum the second base address corresponding to that task execution circuit 30 with the first address offset to obtain the first destination address corresponding to that task execution circuit 30. Assuming the second base address is represented as addr3 and the first destination address as addr4, then addr4 = addr3 + offset1. Thus, through subtraction, addition, and other operational logic, the configuration sub-circuit 403 can efficiently and reliably calculate the first destination addresses corresponding to the multiple task execution circuits 30 respectively.

[0048] In an optional example, the multiple task execution circuits 30 can be four task execution circuits 30, sequentially represented as task execution circuit P1, task execution circuit P2, task execution circuit P3, and task execution circuit P4. The second address ranges corresponding to task execution circuits P1, P2, P3, and P4 can be 100~200, 200~300, 300~400, and 400~500, respectively. Therefore, the second base address within the second address range of task execution circuit P1 can be 100, the second base address within the second address range of task execution circuit P2 can be 200, the second base address within the second address range of task execution circuit P3 can be 300, and the second base address within the second address range of task execution circuit P4 can be 400. The first address range corresponding to the configuration sub-circuit 403 can be 2000~2100, and therefore the first base address is 2000. Assuming the first storage address of the task configuration information within the first address range is 2050, then the first address offset = 2050 - 2000 = 50. Therefore, the four second base addresses (100, 200, 300, and 400) can be added to the first address offset of 50 to obtain four first destination addresses: 150, 250, 350, and 450, respectively. The configuration sub-circuit 403 can write task configuration information to the first register 301 corresponding to task execution circuit P1 according to the first destination address 150; to the first register 301 corresponding to task execution circuit P2 according to the first destination address 250; to the first register 301 corresponding to task execution circuit P3 according to the first destination address 350; and to the first register 301 corresponding to task execution circuit P4 according to the first destination address 450. In this way, batch configuration of task execution circuits P1, P2, P3, and P4 can be achieved. Task execution circuits P1, P2, P3, and P4 can collaboratively execute the target task based on the task configuration information stored in their respective first registers 301.

[0049] It should be noted that in the above embodiments, the address offset of the first destination address relative to the second base address is consistent with the address offset of the first storage address relative to the first base address. In specific implementations, these two address offsets can also be set to be inconsistent but have a fixed conversion relationship. For example, the difference between the former address offset and the latter address offset can be a preset value (e.g., 10, 20, etc.). In this case, after obtaining the first address offset mentioned above, the first address offset can be added to the preset value to obtain another address offset, and this other address offset can be applied to the second base addresses corresponding to the multiple task execution circuits 30 respectively to obtain the first destination addresses corresponding to the multiple task execution circuits 30 respectively.

[0050] In the embodiments of this disclosure, the configuration sub-circuit 403 can combine the first base address in the first address range, the first storage address of the task configuration information in the first address range, and the first indication information to calculate the first destination address in the first register 301 corresponding to each of the multiple task execution circuits 30 for writing the task configuration information, and write the task configuration information accordingly, thereby configuring the multiple task execution circuits 30 so that the multiple task execution circuits 30 can collaboratively execute the target task. That is, in the embodiments of this disclosure, the processor 20 provides the batch configuration circuit 40 with the first indication information and the task configuration information, and the batch configuration circuit 40 can perform batch register configuration for the multiple task execution circuits 30 accordingly, thereby saving processor 20 resources and improving register configuration efficiency.

[0051] In some optional examples, the task configuration information to be shared by multiple task execution circuits 30 includes enable signal configuration information and task parameter configuration information, and any one of the multiple task execution circuits 30 is represented as the target task execution circuit; Multiple task execution circuits 30 are used to collaboratively execute a target task based on task configuration information stored in their respective first registers 301, including: The target task execution circuit is used to obtain the subtask determination rules corresponding to the target task execution circuit; based on the task parameter configuration information stored in the first register 301 corresponding to the target task execution circuit, the target subtask in the target task is determined according to the subtask determination rules; and in response to the enable signal configuration information stored in the first register 301 corresponding to the target task execution circuit, the target subtask is executed.

[0052] Optionally, the enable signal configuration information can be configuration information used to activate the task execution circuit 30; the task parameter configuration information can be configuration information used to characterize the task parameters of the target task. Taking the case where the target task is a data transfer task as an example, the task parameters of the target task may include the amount of data to be transferred, the address of the data source to be transferred, the destination address of the data to be transferred, etc. Taking the case where the target task is an image scaling task as an example, the task parameters of the target task may include the scaling factor, the image storage address, etc.

[0053] In the embodiments of this disclosure, the target task execution circuit can obtain the subtask determination rules corresponding to the target task execution circuit. These subtask determination rules refer to rules used to assist the target task execution circuit in determining the subtasks to be executed from the target task, such as address mapping rules, which can be used to map any given address to another address. Here, the target task execution circuit may have pre-configured subtask determination rules, in which case the target task execution circuit can obtain the pre-configured subtask determination rules; alternatively, the processor 20 can send the subtask determination rules to the target task execution circuit, and the target task execution circuit can obtain the subtask determination rules sent by the processor 20. The target task execution circuit can also determine the target subtasks in the target task according to the subtask determination rules, based on the task parameter configuration information stored in the first register 301 corresponding to the target task execution circuit.

[0054] In an optional example, the multiple task execution circuits 30 can be four task execution circuits 30, referred to as task execution circuit P1, task execution circuit P2, task execution circuit P3, and task execution circuit P4, respectively. The task parameter configuration information stored in the first register 301 corresponding to any of the task execution circuits P1, P2, P3, and P4 includes V as the amount of data to be transferred, 210 as the address of the data source to be transferred, and 810 as the address of the data destination to be transferred.

[0055] Assuming task execution circuit P1 is the target task execution circuit, the subtask determination rule corresponding to task execution circuit P1 may include address mapping rule Q1. Address mapping rule Q1 may indicate that the address of the data source to be transferred is mapped from 210 to 1210, and the address of the data destination to be transferred is mapped from 810 to 1810. Then, according to the subtask determination rule corresponding to task execution circuit P1, the determined target subtask may be the task of transferring data of volume V from source address 1210 to destination address 1810. Task execution circuit P1 can respond to the enable signal configuration information stored in the corresponding first register 301 and start executing the determined target subtask.

[0056] Assuming task execution circuit P2 is the target task execution circuit, the subtask determination rule corresponding to task execution circuit P2 may include address mapping rule Q2. Address mapping rule Q2 may indicate that the address of the data source to be transferred is mapped from 210 to 2210, and the address of the data destination to be transferred is mapped from 810 to 2810. Then, according to the subtask determination rule corresponding to task execution circuit P2, the determined target subtask may be the task of transferring data of volume V from source address 2210 to destination address 2810. Task execution circuit P2 can respond to the enable signal configuration information stored in the corresponding first register 301 and start executing the determined target subtask.

[0057] In this way, based on the task parameter configuration information stored in the first register 301 corresponding to the target task execution circuit, and combined with the sub-task determination rules corresponding to the target task execution circuit, the target task execution circuit can adaptively determine the target sub-task to ensure the correctness and rationality of the determined target sub-task. Under the action of the enable signal configuration information, multiple task execution circuits 30 can execute the corresponding target sub-tasks respectively, thereby completing the target task efficiently and reliably through the coordinated work of multiple task execution circuits 30.

[0058] In some optional examples, such as Figure 4 As shown, chips that support batch configuration of registers also include: Bus component 50; The batch configuration circuit 40 also includes: The first instruction information obtained by the processor 20 is transmitted to the second register 401 via the bus component 50 and the bus interface 405 via the bus interface 405. The task configuration information obtained by the processor 20 is transmitted to the configuration sub-circuit 403 via the bus component 50 and the bus interface 405. The task configuration information stored in the configuration sub-circuit 403 is transmitted to multiple task execution circuits 30 via the bus interface 405 and the bus component 50.

[0059] Optionally, bus component 50 can interconnect different circuits within the chip supporting the bulk configuration register to support information transmission between different circuits. Bus interface 405 can be a dedicated interface circuit between other circuits in the bulk configuration circuit 40 and bus component 50. Here, bus component 50 can be electrically connected to processor 20, bus interface 405, and multiple task execution circuits 30, respectively, and bus interface 405 can be electrically connected to second register 401 and configuration sub-circuit 403, respectively.

[0060] In the embodiments of this disclosure, in response to acquiring first indication information and task configuration information, the processor 20 can transmit the first indication information sequentially through the bus component 50 and the bus interface 405 to the second register 401 for storage, and transmit the task configuration information sequentially through the bus component 50 and the bus interface 405 to the configuration sub-circuit 403 for storage. Furthermore, the configuration sub-circuit 403 can transmit the task configuration information sequentially through the bus interface 405 and the bus component 50 to the multiple task execution circuits 30 according to the first destination addresses corresponding to each of the multiple task execution circuits 30, thereby configuring the multiple task execution circuits 30. Thus, by introducing the bus component 50 and the bus interface 405, information transmission between different circuits can be effectively supported, and on this basis, batch register configuration of multiple task execution circuits 30 can be effectively realized.

[0061] In some optional examples, Multiple task execution circuits 30 coordinate to execute the target task, including: Different task execution circuits 30 in the multiple task execution circuits 30 are used to execute different sub-tasks in the target task.

[0062] For example, as described above, multiple task execution circuits 30 can each determine and execute their respective target sub-tasks.

[0063] like Figure 5 As shown, chips that support batch configuration of registers also include: Interrupt controller 60; The batch configuration circuit 40 includes: Interrupt collector 407 is used to collect first interrupt signals generated by multiple task execution circuits 30 respectively, representing the completion of corresponding subtasks; determine the first collection state of the first interrupt signals corresponding to the multiple task execution circuits 30 respectively; in response to the first collection state corresponding to the multiple task execution circuits 30 indicating that the collection is completed, generate a second interrupt signal representing the completion of the target task; and report the second interrupt signal to the processor 20 via the interrupt controller 60.

[0064] Optionally, the interrupt collector 407 can be a circuit for collecting interrupt signals. The interrupt controller 60 can be a circuit for centrally managing interrupt signals; for example, the interrupt controller 60 can be used for priority arbitration, distribution, etc. of interrupt signals.

[0065] In embodiments of this disclosure, the interrupt collector 407 can be electrically connected to multiple task execution circuits 30 (e.g., via interrupt signal lines). If any task execution circuit 30 completes a corresponding subtask, it can send a first interrupt signal indicating the completion of the corresponding subtask to the interrupt collector 407. Correspondingly, the interrupt collector 407 can receive the first interrupt signal from the task execution circuit 30. The interrupt collector 407 can determine a first collection state for the first interrupt signals corresponding to the multiple task execution circuits 30. Here, if the interrupt collector 407 has received a first interrupt signal from any task execution circuit 30, the first receiving state corresponding to that task execution circuit 30 can indicate that collection is complete; if the interrupt collector 407 has not received a first interrupt signal from any task execution circuit 30, the first receiving state corresponding to that task execution circuit 30 can indicate that collection is not complete. If the first collection states corresponding to multiple task execution circuits 30 all indicate collection completion, meaning the interrupt collector 407 has received first interrupt signals from the multiple task execution circuits 30 respectively, and the multiple task execution circuits 30 have all completed their respective sub-tasks, then the target task is completed. Therefore, the interrupt collector 407 can generate a second interrupt signal representing the completion of the target task. The interrupt collector 407 can be electrically connected to the interrupt controller 60, and can send the second interrupt signal to the interrupt controller 60. Correspondingly, the interrupt controller 60 can receive the second interrupt signal. The interrupt controller 60 can be electrically connected to the processor 20, and can send the second interrupt signal to the processor 20. In this way, the processor 20 can determine that the target task has been completed, and the processor 20 can perform interrupt processing. For example, the processor 20 can issue a new target task, that is, for the new target task, send the corresponding first indication information and the corresponding task configuration information to the batch configuration circuit 40.

[0066] In the embodiments of this disclosure, the batch configuration circuit 40 reports a second interrupt signal to the processor 20 via the interrupt controller 60 when the target task has been completed. The processor 20 does not need to perform interrupt processing for the first interrupt signals corresponding to the multiple task execution circuits 30, which helps to avoid the overhead and delay caused by the processor 20 performing multiple interrupt processing, and also helps to save processor 20 resources.

[0067] In some optional examples, The processor 20 is also used to acquire second indication information indicating whether to mask the second interrupt signal; The second register 401 is also used to acquire and store second instruction information from the processor 20; In response to the second indication information stored in the second register 401 indicating that the second interrupt signal is not masked, the interrupt collector 407 is used to report the second interrupt signal to the processor 20 via the interrupt controller 60. In response to the second indication information stored in the second register 401 indicating that the second interrupt signal is masked, the interrupt collector 407 is configured to prevent the reporting of the second interrupt signal to the processor 20 via the interrupt controller 60, and the processor 20 is used to obtain the second interrupt signal from the interrupt controller 60.

[0068] Optionally, the processor 20 obtains the second instruction information in a similar way to the processor 20 obtaining the first instruction information described above, and will not be repeated here. Here, if the processor 20 is currently under heavy load, or if the processor 20 is currently performing a critical task that cannot be interrupted, the second instruction information can instruct the second interrupt signal to be masked. If the processor 20 is currently under light load, or if the processor 20 is currently performing a task that can be interrupted, the second instruction information can instruct the second interrupt signal not to be masked. The processor 20 can be electrically connected to the second register 401. The processor 20 can send the second instruction information to the second register 401, and correspondingly, the second register 401 can receive and store the second instruction information. The interrupt collector 407 can be electrically connected to the second register 401, and correspondingly, the interrupt collector 407 can read the second instruction information stored in the second register 401. In some implementations, the interrupt collector 407 can also be electrically connected to the processor 20.

[0069] If the second indication information stored in the second register 401 indicates that the second interrupt signal is not masked, the interrupt collector 407 can actively report the second interrupt signal. For example, if the first collection states corresponding to multiple task execution circuits 30 all indicate that collection is complete (i.e., the target task has been completed), the interrupt collector 407 can generate a second interrupt signal representing the completion of the target task and immediately report the second interrupt signal to the processor 20 via the interrupt controller 60. In this way, the processor 20 can perform interrupt processing in a timely manner.

[0070] If the second indication information stored in the second register 401 indicates that the second interrupt signal is masked, and the interrupt collector 407 does not actively report the second interrupt signal, the processor 20 can obtain the second interrupt signal from the interrupt collector 407. For example, after a critical task that cannot be interrupted is completed, the processor 20 can obtain the second interrupt signal by sending an interrupt polling instruction to the interrupt collector 407. This satisfies the processor 20's polling needs while avoiding interruption of critical tasks executed by the processor 20.

[0071] In some optional examples, Processor 20 is also used to acquire interrupt clearing configuration information to be shared by multiple task execution circuits 30; The batch configuration circuit 40 also includes: Configuration sub-circuit 403 is used to acquire and store interrupt clearing configuration information from processor 20; based on the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information, it determines the second destination address in the first register 301 corresponding to the multiple task execution circuits 30 respectively; and writes the interrupt clearing configuration information into the first register 301 corresponding to the multiple task execution circuits 30 respectively according to the second destination address corresponding to the multiple task execution circuits 30 respectively. Multiple task execution circuits 30 are used to clear the corresponding first interrupt signal in response to the interrupt clearing configuration information stored in their respective first registers 301.

[0072] Optionally, the processor 20 obtains the interrupt clearing configuration information in a similar manner to the processor 20 obtaining the first indication information described above, and will not be repeated here. The interrupt clearing configuration information may be configuration information used to indicate the completion of the clearing task related to interrupt signals.

[0073] In the embodiments of this disclosure, the processor 20 can be electrically connected to the configuration sub-circuit 403. The processor 20 can send interrupt clearing configuration information to the configuration sub-circuit 403, and correspondingly, the configuration sub-circuit 20 can receive the interrupt clearing configuration information and store the interrupt clearing configuration information. Here, the interrupt clearing configuration information can be stored in the first address range corresponding to the configuration sub-circuit 403. The configuration sub-circuit 403 can be electrically connected to the second register 401, and the configuration sub-circuit 403 can read the first indication information from the second register 401. The configuration sub-circuit 403 can also determine the second destination address in the first register 301 corresponding to each of the multiple task execution circuits 30 based on the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information; wherein, the second destination address in the first register 301 corresponding to any task execution circuit 30 can be understood as: the write address of the interrupt clearing configuration information in the first register 301 corresponding to that task execution circuit 30. According to the second destination address corresponding to each of the multiple task execution circuits 30, the configuration sub-circuit 403 can write interrupt clearing configuration information to the first register 301 corresponding to each of the multiple task execution circuits 30, thereby enabling the configuration of the registers of the multiple task execution circuits 30.

[0074] In some optional embodiments of this disclosure, the first indication information includes the second base address in the second address range corresponding to the first register 301; The configuration sub-circuit 403 is used to determine the second destination address in the first register 301 corresponding to each of the multiple task execution circuits 30, based on the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information, including: The configuration sub-circuit 403 is used to determine the second address offset of the second storage address relative to the first base address; and to apply the second address offset to the second base address corresponding to the multiple task execution circuits 30 respectively, so as to obtain the second destination address corresponding to the multiple task execution circuits 30 respectively.

[0075] Optionally, the specific implementation of the configuration sub-circuit 403 in determining the second destination addresses corresponding to the multiple task execution circuits 30 can be referred to the relevant introduction above on the determination method of the first destination addresses corresponding to the multiple task execution circuits 30, and will not be repeated here.

[0076] In the embodiments of this disclosure, the configuration sub-circuit 403 can combine the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information to calculate the second destination address in the first register 301 corresponding to each of the multiple task execution circuits 30 for writing the interrupt clearing configuration information, and write the interrupt clearing configuration information accordingly, thereby configuring the multiple task execution circuits 30. In this way, the multiple task execution circuits 30 can respectively respond to the interrupt clearing configuration information written in their respective first registers 301 and stop outputting the first interrupt signal. That is, in the embodiments of this disclosure, the processor 20 provides interrupt clearing configuration information to the batch configuration circuit 40, which can then perform batch register configuration on the multiple task execution circuits 30 accordingly, so that all the multiple task execution circuits 30 stop outputting the first interrupt signal.

[0077] In some optional examples, processor 20 is configured to prevent writing interrupt clearing configuration information to configuration sub-circuit 403 according to the second memory address before the second interrupt signal is received.

[0078] It should be noted that before the interrupt collector 407 reports the second interrupt signal to the processor 20 via the interrupt controller 60 so that the processor 20 can obtain the second interrupt signal, or before the processor 20 actively obtains the second interrupt signal from the interrupt controller 60, if the processor 20 writes interrupt clearing configuration information to the configuration sub-circuit 403 according to the second storage address, the interrupt clearing configuration information will be written to the second destination address corresponding to the multiple task execution circuits 30 respectively, causing the multiple task execution circuits 30 to stop outputting the first interrupt signal. If the first interrupt signal corresponding to any task execution circuit 30 has not yet been collected by the interrupt collector 407, the interrupt collector 407 will not be able to completely collect the first interrupt signals corresponding to the multiple task execution circuits 30 respectively, and naturally will not generate the second interrupt signal. Accordingly, the processor 20 will not be able to obtain the second interrupt signal subsequently. In view of this, in the embodiments of this disclosure, the hardware logic in the processor 20 can be set to prohibit writing interrupt clearing configuration information to the configuration sub-circuit 403 according to the second storage address before the second interrupt signal is obtained. This helps to avoid the situation where the processor 20 is unable to obtain the second interrupt signal. Therefore, when the target task is completed, the processor 20 can perform interrupt processing normally.

[0079] In some optional examples, like Figure 5 As shown, chips that support batch configuration of registers also include: Interrupt controller 60; The batch configuration circuit 40 includes: Interrupt collector 407 is used to collect third interrupt signals generated by multiple task execution circuits 30 respectively, indicating functional abnormalities of the task execution circuits 30, and fourth interrupt signals generated by other circuits in the batch configuration circuit 40 other than interrupt collector 407, indicating functional abnormalities of other circuits; determine a second collection state for the third interrupt signals corresponding to the multiple task execution circuits 30, and a third collection state for the fourth interrupt signals; in response to the second collection state and / or third collection state indicating completion of collection corresponding to at least one task execution circuit 30, generate a fifth interrupt signal indicating that there are circuits with functional abnormalities in the multiple task execution circuits 30 and the batch configuration circuit 40; and report the fifth interrupt signal to the processor 20 via interrupt controller 60.

[0080] Optionally, the interrupt collector 407 can be a circuit for collecting interrupt signals. The interrupt controller 60 can be a circuit for centrally managing interrupt signals; for example, the interrupt controller 60 can be used for priority arbitration, distribution, etc. of interrupt signals.

[0081] In the embodiments of this disclosure, the interrupt collector 407 can be electrically connected to multiple task execution circuits 30 (e.g., electrically connected via interrupt signal lines). If any task execution circuit 30 detects a functional abnormality (e.g., clock error, power supply error, etc.) through a self-test mechanism, the task execution circuit 30 can generate a third interrupt signal indicating the functional abnormality and send the generated third interrupt signal to the interrupt collector 407. Correspondingly, the interrupt collector 407 can receive the third interrupt signal from the task execution circuit 30. The interrupt collector 407 can also be electrically connected to other circuits in the batch configuration circuit 40 besides the interrupt collector 407 (which may include the second register 401, configuration sub-circuit 403, etc.). If the other circuit detects a functional abnormality through a self-test mechanism, the other circuit can generate a fourth interrupt signal indicating the functional abnormality and send the generated fourth interrupt signal to the interrupt collector 407. Correspondingly, the interrupt collector 407 can receive the fourth interrupt signal. Interrupt collector 407 can determine a second collection state for a third interrupt signal corresponding to a plurality of task execution circuits 30, and a third collection state for a fourth interrupt signal. Here, if interrupt collector 407 has received a third interrupt signal from any task execution circuit 30, the second collection state corresponding to that task execution circuit 30 can indicate that collection is complete; if interrupt collector 407 has not received a third interrupt signal from any task execution circuit 30, the second collection state corresponding to that task execution circuit 30 can indicate that collection is not complete. Similarly, if interrupt collector 407 has received a fourth interrupt signal, the third collection state can indicate that collection is complete; if interrupt collector 407 has not received a fourth interrupt signal, the third collection state can indicate that collection is not complete. If the second collection state corresponding to at least one of the plurality of task execution circuits 30 indicates that collection is complete, and / or the third collection state indicates that collection is complete, i.e., there is a malfunctioning circuit in the plurality of task execution circuits 30 and the batch configuration circuit 40, then interrupt collector 407 can generate a fifth interrupt signal characterizing the malfunctioning circuit in the plurality of task execution circuits 30 and the batch configuration circuit 40. Interrupt collector 407 can be electrically connected to interrupt controller 60. Interrupt collector 407 can send a fifth interrupt signal to interrupt controller 60, and correspondingly, interrupt controller 60 can receive the fifth interrupt signal. Interrupt controller 60 can be electrically connected to processor 20, and interrupt controller 60 can send the fifth interrupt signal to processor 20. In this way, processor 20 can identify circuits with functional abnormalities in multiple task execution circuits 30 and batch configuration circuits 40, and processor 20 can perform interrupt handling. For example, processor 20 can determine which specific circuit has a functional abnormality and perform fault repair on that circuit.

[0082] In the embodiments of this disclosure, when there are circuits with malfunctions in the multiple task execution circuits 30 and the batch configuration circuit 40, the batch configuration circuit 40 reports a fifth interrupt signal to the processor 20 via the interrupt controller 60. The processor 20 does not need to perform interrupt processing for the third interrupt signal and the fourth interrupt signal corresponding to the multiple task execution circuits 30, which helps to avoid the overhead and delay caused by the processor 20 performing multiple interrupt processing, and also helps to save processor 20 resources.

[0083] In some optional examples, The processor 20 is also used to acquire third indication information indicating whether to mask the fifth interrupt signal; The second register 401 is also used to acquire and store third instruction information from the processor 20; In response to the third indication information stored in the second register 401 indicating that the fifth interrupt signal is not masked, the interrupt collector 407 is used to report the fifth interrupt signal to the processor 20 via the interrupt controller 60; In response to the third indication information stored in the second register 401 indicating that the fifth interrupt signal is masked, the interrupt collector 407 is configured to prevent the reporting of the fifth interrupt signal to the processor 20 via the interrupt controller 60, and the processor 20 is used to obtain the fifth interrupt signal from the interrupt collector 407.

[0084] Optionally, the processor 20 obtains the third instruction information in a similar way to the processor 20 obtaining the first instruction information described above, and will not be repeated here. Here, if the processor 20 is currently under heavy load, or if the processor 20 is currently performing a critical task that cannot be interrupted, the third instruction information can instruct the fifth interrupt signal to be masked. If the processor 20 is currently under light load, or if the processor 20 is currently performing a task that can be interrupted, the third instruction information can instruct the fifth interrupt signal not to be masked. The processor 20 can be electrically connected to the second register 401. The processor 20 can send the third instruction information to the second register 401, and correspondingly, the second register 401 can receive and store the third instruction information. The interrupt collector 407 can be electrically connected to the second register 401, and correspondingly, the interrupt collector 407 can read the third instruction information stored in the second register 401. In some implementations, the interrupt collector 407 can also be electrically connected to the processor 20.

[0085] If the second indication information stored in the second register 401 indicates that the fifth interrupt signal is not masked, it means that the interrupt collector 407 can actively report the fifth interrupt signal. For example, if the second collection state and / or the third collection state corresponding to at least one task execution circuit 30 indicates that collection is complete, the interrupt collector 407 can generate the fifth interrupt signal and immediately report the fifth interrupt signal to the processor 20 via the interrupt controller 60. In this way, the processor 20 can perform interrupt processing in a timely manner.

[0086] If the second indication information stored in the second register 401 indicates that the fifth interrupt signal is masked, and the interrupt collector 407 does not actively report the fifth interrupt signal, the processor 20 can obtain the fifth interrupt signal from the interrupt collector 407. For example, after a critical task that cannot be interrupted is completed, the processor 20 can obtain the fifth interrupt signal by sending an interrupt polling instruction to the interrupt collector 407. This satisfies the processor 20's polling needs while avoiding interruption of critical tasks executed by the processor 20.

[0087] In some optional examples, the processor 20 is configured to, in response to a fifth interrupt signal, obtain from the interrupt collector 407 the second collection state and the third collection state corresponding to the multiple task execution circuits 30 respectively; based on the second collection state and the third collection state corresponding to the multiple task execution circuits 30 respectively, determine the target functional abnormal circuit in the multiple task execution circuits 30 and the batch configuration circuit 40; and obtain the abnormal details information of the target functional abnormal circuit from the register corresponding to the target functional abnormal circuit.

[0088] In the embodiments of this disclosure, the interrupt collector 407 may record the second collection state and the third collection state corresponding to each of the multiple task execution circuits 30. If the interrupt collector 407 reports a fifth interrupt signal to the processor 20 via the interrupt controller 60, so that the processor 20 obtains the fifth interrupt signal, or the processor 20 actively obtains the fifth interrupt signal from the interrupt collector 407, the processor 20 can obtain the second collection state and the third collection state corresponding to each of the multiple task execution circuits 30 from the interrupt collector 407. By analyzing the second collection state and the third collection state corresponding to each of the multiple task execution circuits 30, the processor 20 can determine which specific circuits in the multiple task execution circuits 30 and the batch configuration circuit 40 have functional abnormalities. The determined circuits can be called target functional abnormal circuits. The processor 20 can obtain the abnormality details information of the target functional abnormal circuit from the register corresponding to the target functional abnormal circuit. The abnormality details information includes, but is not limited to, error type, error level, etc.

[0089] In an optional example, for any task execution circuit 30, if the task execution circuit 30 detects a functional abnormality through a self-test mechanism, the task execution circuit 30 can store the abnormality details in the corresponding first register 301. Thus, if the second collection state corresponding to the task execution circuit 30 indicates that collection is complete, the processor 20 can identify the task execution circuit 30 as the target functionally abnormal circuit and retrieve the abnormality details from the corresponding first register 301.

[0090] In another alternative example, for other circuits in the batch configuration circuit 40 besides the interrupt collector 407, if the other circuit detects a functional abnormality through a self-test mechanism, the other circuit can store the abnormality details in the second register 401. Thus, if the third collection state indicates that collection is complete, the processor 20 can identify the other circuit as the target functional abnormality circuit and retrieve the abnormality details from the second register 401.

[0091] In the embodiments of this disclosure, the processor 20 can efficiently and reliably determine which circuits are experiencing functional abnormalities by reading and analyzing the information in the interrupt collector 407, i.e., identify the target functional abnormal circuits. By reading the registers corresponding to the target functional abnormal circuits, the processor 20 can efficiently and reliably obtain the abnormality details of the target functional abnormal circuits, so as to handle the functional abnormalities in a timely and effective manner. For example, if the error level of the target functional abnormal circuit is high, the fault repair of the target functional abnormal circuit can be prioritized.

[0092] It should be noted that the above describes the method for clearing the first interrupt signal. In some embodiments, a similar method can be used to clear the third interrupt signal.

[0093] In some embodiments, the processor 20 may also be configured to prohibit querying the status information (e.g., the running details information of the task execution circuit 30) in the first register 301 corresponding to multiple task execution circuits 30 during the normal execution of the target task via the batch configuration circuit 40. This is because, due to the different working states and stages of different task execution circuits 30, the values ​​representing the status information in the first register 301 corresponding to different task execution circuits 30 may be different at the same time. If the query operation is performed, different task execution circuits 30 may return different values, which may easily trigger errors.

[0094] In related technologies, such as Figure 6-1As shown, if N circuits (which can also be called N modules) need to collaboratively execute the same task, the CPU can start from the first module and configure the registers corresponding to each of the N modules sequentially. In response to the completion of register configuration for each of the N modules, the N modules can begin working. If any of the N modules completes its corresponding subtask, an interrupt can be triggered, notifying the CPU to handle the interrupt. The CPU can not only handle interrupts but also determine whether the interrupt handling for all N modules has been completed, i.e., whether all N modules have completed their corresponding subtasks. If the interrupt handling for all N modules has not been completed, it means that some modules have not yet completed their corresponding subtasks, and the CPU waits for them to complete their subtasks. If the interrupt handling for all N modules has been completed, the task is complete. It is easy to see that in related technologies, the CPU needs to perform register configuration and interrupt handling operations multiple times, which consumes a lot of time and CPU resources, resulting in high operating system overhead and latency, making it unsuitable for scenarios with high bandwidth and latency requirements.

[0095] In comparison, in the embodiments of this disclosure, such as Figure 6-2As shown, if N modules (equivalent to multiple task execution circuits 30 mentioned above) need to collaboratively execute the same task, the CPU (equivalent to the processor 20 mentioned above) can receive task information (such as the first instruction information and task configuration information mentioned above) issued by the software program. The CPU can configure the second register 401 in the batch configuration circuit 40 to specify the value of N, the base address of the registers of each of the N modules (equivalent to the second base address mentioned above), and whether to mask the interrupt signal (corresponding to the second and third instruction information mentioned above). The CPU can also send configuration data (equivalent to the task configuration information mentioned above) to the configuration sub-circuit 403 in the batch configuration circuit 40. The configuration sub-circuit 403 can forward the configuration data so that all N modules can receive the configuration data to configure the registers corresponding to the N modules respectively. In response to the completion of the configuration of the registers corresponding to the N modules, the N modules can start working. If any of the N modules completes the corresponding sub-task, an interrupt can be triggered, and the interrupt signal (equivalent to the first interrupt signal mentioned above) can be sent to the interrupt collector 407 in the batch configuration circuit 40. The batch configuration circuit 40 can collect interrupt signals and determine whether interrupt signals from N modules have been received. If interrupt signals corresponding to N modules have been collected, all tasks are completed, and the batch configuration circuit 40 can trigger an interrupt to the CPU (equivalent to reporting the second interrupt signal as mentioned above). If interrupt signals corresponding to N modules have not been collected, some modules have not yet completed their corresponding sub-tasks, and the circuit waits for them to complete their sub-tasks. Therefore, in this embodiment, the CPU configures N modules through the batch configuration circuit 40, rather than directly configuring N modules. Furthermore, the batch configuration circuit 40 collects interrupt signals from N modules and aggregates them into a single interrupt signal for the CPU to handle. Clearly, the CPU only needs to perform one register configuration and one interrupt handling operation, effectively saving CPU resources, reducing operating system overhead and latency, and making it suitable for scenarios with high bandwidth and latency requirements.

[0096] If it is necessary to use modules 1 to 8 (each module 1 to 8 is a task execution circuit 30 mentioned above) to collaboratively execute the same task, in related technologies, such as Figure 6-3 The solid lines in the diagram indicate that the processor 20 needs to send eight task messages to the bus component 50 for configuring the registers in modules 1 through 8. Furthermore, any module from 1 to 8 can trigger an interrupt signal upon completion of its corresponding subtask, notifying the processor 20 of an pending interrupt via the interrupt controller 60. Each time the processor 20 receives an interrupt signal, it needs to query the registers of the corresponding module; that is, the eight interrupt signals from the eight modules will cause the processor 20 to perform eight interrupt processing operations.

[0097] In comparison, in the embodiments of this disclosure, such as Figure 6-3 The link shown by the dashed line in the middle allows the processor 20 to provide task information (such as the first instruction information and task configuration information mentioned above) to the batch configuration circuit 40 via the bus component 50. The batch configuration circuit 40 can then send task configuration information to modules 1 to 8 via the bus component 50 to configure the registers in modules 1 to 8 respectively (equivalent to the first register 301 mentioned above). Furthermore, any module in modules 1 to 8 can trigger an interrupt signal (equivalent to the first interrupt signal mentioned above) to the batch configuration circuit 40 after the corresponding subtask is completed. The batch configuration circuit 40 will only trigger an interrupt to the processor 20 via the interrupt controller 60 after collecting 8 interrupt signals (i.e., report the second interrupt signal to the processor 20), thereby effectively saving processor 20 resources and reducing operating system overhead and latency.

[0098] In summary, in the embodiments of this disclosure, for the same task, the processor 20 does not need to perform multiple register configuration operations or multiple interrupt handling operations. Instead, it can complete the batch configuration of registers with the help of the batch configuration circuit 40, and only needs to handle one interrupt triggered by the batch configuration circuit 40. This can effectively save processor 20 resources, reduce operating system overhead and latency, shorten the time required for task execution, and enable more tasks to be completed or more information to be transmitted within the same time, thereby increasing transmission bandwidth. In addition, it can also reduce the burden and power consumption of the processor 20, which is beneficial to reducing chip area and cost.

[0099] Exemplary methods The embodiments of this disclosure also provide a task execution method based on a chip that supports batch configuration registers. Specific implementations of the chip supporting batch configuration registers can be found in the description of the exemplary chip section above, and will not be repeated here.

[0100] Figure 7 This is a flowchart illustrating a task execution method for a chip supporting batch configuration registers, provided by some exemplary embodiments of this disclosure. For example... Figure 7 As shown, the method provided in the embodiments of this disclosure includes: Step 710: The processor in the chip obtains the first indication information of the multiple task execution circuits that are to participate in the target task, as well as the task configuration information to be shared by the multiple task execution circuits. Step 720: Obtain first instruction information and task configuration information from the processor through the batch configuration circuit in the chip; Step 730: Based on the first instruction information and task configuration information, the batch configuration circuit in the chip configures the first registers corresponding to the multiple task execution circuits respectively, so that the multiple task execution circuits can work together to execute the target task.

[0101] In some optional examples, the bulk configuration circuitry includes: a second register and a configuration sub-circuit; like Figure 8 As shown, step 720 includes: Step 810: Obtain and store the first instruction information from the processor through the second register; Step 820: Obtain and store task configuration information from the processor through the configuration sub-circuit; Step 730 includes: Step 830: Based on the first base address in the first address range corresponding to the configuration sub-circuit, the first storage address of the task configuration information in the first address range, and the first indication information, the configuration sub-circuit determines the first destination address in the first register corresponding to each of the multiple task execution circuits; and writes the task configuration information into the first register corresponding to each of the multiple task execution circuits according to the first destination address corresponding to each of the multiple task execution circuits. Step 840: Multiple task execution circuits coordinate to execute the target task based on the task configuration information stored in their respective first registers.

[0102] In some optional examples, the first indication information includes: the second base address in the second address range corresponding to the first register; Step 830 includes: Determine the first address offset of the first storage address relative to the first base address; Apply a first address offset to the second base address corresponding to each of the multiple task execution circuits to obtain the first destination address corresponding to each of the multiple task execution circuits.

[0103] In some optional examples, the task configuration information to be shared by multiple task execution circuits includes: enable signal configuration information and task parameter configuration information, and any one of the multiple task execution circuits is represented as the target task execution circuit; Step 840 includes: The target task execution circuit obtains the subtask determination rules corresponding to the target task execution circuit; based on the task parameter configuration information stored in the first register corresponding to the target task execution circuit, the target subtask in the target task is determined according to the subtask determination rules; in response to the enable signal configuration information stored in the first register corresponding to the target task execution circuit, the target subtask is executed.

[0104] In some optional examples, the chip supporting bulk configuration registers also includes: a bus component; the bulk configuration circuit also includes: a bus interface, wherein first instruction information obtained by the processor is transmitted to a second register via the bus component and the bus interface, task configuration information obtained by the processor is transmitted to a configuration sub-circuit via the bus component and the bus interface, and task configuration information stored in the configuration sub-circuit is transmitted to multiple task execution circuits via the bus interface and the bus component.

[0105] In some optional examples, Multiple task execution circuits work together to execute a target task, including: Different task execution circuits in multiple task execution circuits are used to execute different subtasks in the target task; Chips that support bulk configuration registers also include: interrupt controllers; bulk configuration circuitry includes: interrupt collectors; like Figure 9 As shown, the method provided in the embodiments of this disclosure further includes: Step 910: Collect the first interrupt signals representing the completion of the corresponding subtasks generated by multiple task execution circuits through the interrupt collector; determine the first collection state of the first interrupt signals corresponding to the multiple task execution circuits respectively; Step 920: In response to the fact that the first collection states corresponding to the multiple task execution circuits all indicate that the collection is complete, a second interrupt signal representing the completion of the target task is generated by the interrupt collector; and the second interrupt signal is reported to the processor via the interrupt controller.

[0106] In some optional examples, such as Figure 10 As shown, the method provided in the embodiments of this disclosure further includes: Step 1010: Obtain second indication information from the processor indicating whether to mask the second interrupt signal; Step 1020: Obtain and store the second instruction information from the processor through the second register; Step 920 includes: Step 1030: In response to the second indication information stored in the second register indicating that the second interrupt signal is not masked, the second interrupt signal is reported to the processor via the interrupt controller; The methods provided in the embodiments of this disclosure further include: Step 1040: In response to the second indication information stored in the second register indicating that the second interrupt signal is masked, the interrupt collector is configured to prohibit the reporting of the second interrupt signal to the processor via the interrupt controller, and the processor obtains the second interrupt signal from the interrupt collector.

[0107] In some optional examples, such as Figure 11 As shown, the method provided in the embodiments of this disclosure further includes: Step 1110: Obtain the interrupt clearing configuration information to be shared by multiple task execution circuits through the processor; Step 1120: Obtain and store interrupt clearing configuration information from the processor through the configuration sub-circuit; determine the second destination address in the first register corresponding to each of the multiple task execution circuits based on the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information; write the interrupt clearing configuration information to the first register corresponding to each of the multiple task execution circuits according to the second destination address corresponding to each of the multiple task execution circuits. Step 1130: The corresponding first interrupt signal is cleared by multiple task execution circuits responding to the interrupt clearing configuration information stored in their respective first registers.

[0108] In some optional examples, the first indication information includes: the second base address in the second address range corresponding to the first register; like Figure 12 As shown, based on the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information, the second destination address in the first register corresponding to each of the multiple task execution circuits is determined, including: Step 1210: Determine the second address offset of the second storage address relative to the first base address; Step 1220: Apply a second address offset to the second base address corresponding to each of the multiple task execution circuits to obtain the second destination address corresponding to each of the multiple task execution circuits.

[0109] In some optional examples, the processor is configured to prevent the writing of interrupt clear configuration information to the configuration subcircuit according to the second memory address before the bulk configuration circuit reports the second interrupt signal.

[0110] In some optional examples, chips that support bulk configuration registers also include: an interrupt controller, and the bulk configuration circuitry includes: an interrupt collector; like Figure 13 As shown, the method provided in the embodiments of this disclosure further includes: Step 1310: Collect the third interrupt signals generated by multiple task execution circuits to indicate abnormal function of the task execution circuits, and the fourth interrupt signals generated by other circuits in the batch configuration circuit (excluding the interrupt collector) to indicate abnormal function of other circuits; determine the second collection state for the third interrupt signals corresponding to the multiple task execution circuits, and the third collection state for the fourth interrupt signals. Step 1320: In response to a second collection state and / or a third collection state indicating collection completion corresponding to at least one task execution circuit, a fifth interrupt signal is generated by the interrupt collector to characterize a circuit with a functional abnormality in the plurality of task execution circuits and the batch configuration circuit; the fifth interrupt signal is reported to the processor via the interrupt controller.

[0111] In some optional examples, such as Figure 14 As shown, the method provided in the embodiments of this disclosure further includes: Step 1410: Obtain the third indication information indicating whether to mask the fifth interrupt signal through the processor; Step 1420: Obtain and store the third instruction information from the processor through the second register; Step 1320 includes: Step 1430: In response to the third indication information stored in the second register indicating that the fifth interrupt signal is not masked, the fifth interrupt signal is reported to the processor via the interrupt controller; The methods provided in the embodiments of this disclosure further include: Step 1440: In response to the third indication information stored in the second register indicating that the fifth interrupt signal is masked, the interrupt collector is configured to prevent the second interrupt signal from being reported to the processor via the interrupt controller, and the processor obtains the fifth interrupt signal from the interrupt collector.

[0112] In some optional examples, such as Figure 15 As shown, the method provided in the embodiments of this disclosure further includes: Step 1510: The processor responds to the fifth interrupt signal and obtains the second collection state and the third collection state corresponding to the multiple task execution circuits from the interrupt collector; based on the second collection state and the third collection state corresponding to the multiple task execution circuits, the target functional abnormal circuit in the multiple task execution circuits and the batch configuration circuit is determined; the abnormal details information of the target functional abnormal circuit is obtained from the register corresponding to the target functional abnormal circuit.

[0113] In the methods disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the exemplary chip section above can be flexibly selected and combined as needed to achieve the corresponding functions and effects. This disclosure does not list them all.

[0114] The beneficial technical effects corresponding to the exemplary embodiments of this method can be found in the corresponding beneficial technical effects of the exemplary chip section described above, and will not be repeated here.

[0115] Exemplary electronic devices Figure 16The illustration shows a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 1600 includes one or more processors 1610 and memory 1620.

[0116] The processor 1610 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1600 to perform desired functions.

[0117] The memory 1620 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1610 may execute one or more computer program instructions to implement the task execution methods of the various embodiments of this disclosure described above and / or other desired functions.

[0118] In one example, the electronic device 1600 may also include an input device 1630 and an output device 1640, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0119] The input device 1630 may also include, for example, a keyboard, a mouse, etc.

[0120] The output device 1640 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0121] Of course, for the sake of simplicity, Figure 16 Only some of the components of the electronic device 1600 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1600 may include any other suitable components depending on the specific application.

[0122] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps of the task execution methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0123] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0124] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps of the task execution methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0125] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0126] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. The specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the specific details described above.

[0127] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A chip supporting batch configuration registers, comprising: The processor is configured to acquire first indication information indicating multiple task execution circuits to participate in the target task processing, and task configuration information to be shared by the multiple task execution circuits. A batch configuration circuit is used to acquire the first indication information and the task configuration information from the processor; based on the first indication information and the task configuration information, it configures the first registers corresponding to the multiple task execution circuits respectively, so that the multiple task execution circuits can collaboratively execute the target task.

2. The chip of claim 1, wherein, The batch configuration circuit includes: a second register and a configuration sub-circuit; The batch configuration circuit is used to acquire the first indication information and the task configuration information from the processor; based on the first indication information and the task configuration information, it configures the first registers corresponding to the multiple task execution circuits respectively, so that the multiple task execution circuits coordinately execute the target task, including: The second register is used to acquire and store the first indication information from the processor; The configuration sub-circuit is used to acquire and store the task configuration information from the processor; based on the first base address in the first address range corresponding to the configuration sub-circuit, the first storage address of the task configuration information in the first address range, and the first indication information, it determines the first destination address in the first register corresponding to each of the multiple task execution circuits; and writes the task configuration information into the first register corresponding to each of the multiple task execution circuits according to the first destination address corresponding to each of the multiple task execution circuits. The multiple task execution circuits are used to collaboratively execute the target task based on the task configuration information stored in their respective first registers.

3. The chip according to claim 2, wherein, The first indication information includes: the second base address in the second address range corresponding to the first register; The configuration sub-circuit is used to determine the first destination address in the first register corresponding to each of the multiple task execution circuits, based on the first base address in the first address range corresponding to the configuration sub-circuit, the first storage address of the task configuration information in the first address range, and the first indication information, including: The configuration sub-circuit is used to determine the first address offset of the first storage address relative to the first base address; and to apply the first address offset to the second base addresses corresponding to the plurality of task execution circuits respectively, so as to obtain the first destination address corresponding to the plurality of task execution circuits respectively.

4. The chip according to claim 2, wherein, The task configuration information to be shared by multiple task execution circuits includes: enable signal configuration information and task parameter configuration information, and any one of the multiple task execution circuits is represented as the target task execution circuit; Multiple task execution circuits are configured to collaboratively execute the target task based on the task configuration information stored in their respective corresponding first registers, including: The target task execution circuit is used to obtain the subtask determination rule corresponding to the target task execution circuit; based on the task parameter configuration information stored in the first register corresponding to the target task execution circuit, determine the target subtask in the target task according to the subtask determination rule; and execute the target subtask in response to the enable signal configuration information stored in the first register corresponding to the target task execution circuit.

5. The chip according to any one of claims 2-4, wherein, The chip also includes: Bus components; The batch configuration circuit also includes: The first indication information obtained by the processor is transmitted to the second register via the bus component and the bus interface. The task configuration information obtained by the processor is transmitted to the configuration sub-circuit via the bus component and the bus interface. The task configuration information stored in the configuration sub-circuit is transmitted to multiple task execution circuits via the bus interface and the bus component.

6. The chip according to claim 1, wherein, Multiple task execution circuits coordinate to execute the target task, including: Different task execution circuits in the plurality of task execution circuits are used to execute different sub-tasks in the target task; The chip also includes: Interrupt controller; The batch configuration circuit includes: An interrupt collector is configured to collect first interrupt signals representing the completion of the corresponding subtasks generated by a plurality of task execution circuits; determine a first collection state for the first interrupt signals corresponding to the plurality of task execution circuits; generate a second interrupt signal representing the completion of the target task in response to the first collection state corresponding to the plurality of task execution circuits indicating that collection is complete; and report the second interrupt signal to the processor via the interrupt controller.

7. The chip according to claim 6, wherein, The processor is also configured to acquire second indication information indicating whether to mask the second interrupt signal; The second register is also used to acquire and store the second indication information from the processor; In response to the second indication information stored in the second register indicating that the second interrupt signal is not masked, the interrupt collector is used to report the second interrupt signal to the processor via the interrupt controller; In response to the second indication information stored in the second register indicating that the second interrupt signal is masked, the interrupt collector is configured to prevent the reporting of the second interrupt signal to the processor via the interrupt controller, and the processor is configured to obtain the second interrupt signal from the interrupt collector.

8. The chip according to claim 6 or 7, wherein, The processor is also configured to acquire interrupt clearing configuration information to be shared by multiple task execution circuits; The batch configuration circuit also includes: A configuration sub-circuit is configured to acquire and store the interrupt clearing configuration information from the processor; determine the second destination address in the first register corresponding to each of the multiple task execution circuits based on the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information; and write the interrupt clearing configuration information into the first register corresponding to each of the multiple task execution circuits according to the second destination address corresponding to each of the multiple task execution circuits. The plurality of task execution circuits are used to clear the corresponding first interrupt signal in response to the interrupt clearing configuration information stored in the corresponding first register.

9. The chip according to claim 8, wherein, The first indication information includes: the second base address in the second address range corresponding to the first register; The configuration sub-circuit is used to determine the second destination address in the first register corresponding to each of the multiple task execution circuits, based on the first base address in the first address range, the second storage address of the interrupt clearing configuration information in the first address range, and the first indication information, including: The configuration sub-circuit is used to determine the second address offset of the second storage address relative to the first base address; and to apply the second address offset to the second base address corresponding to the plurality of task execution circuits respectively, so as to obtain the second destination address corresponding to the plurality of task execution circuits respectively.

10. The chip according to claim 8, wherein, The processor is configured to prevent writing the interrupt clearing configuration information to the configuration sub-circuit according to the second memory address before the second interrupt signal is received.

11. The chip according to claim 1, wherein, The chip also includes: Interrupt controller, The batch configuration circuit includes: An interrupt collector is configured to collect third interrupt signals generated by a plurality of task execution circuits, indicating functional abnormalities of the task execution circuits, and fourth interrupt signals generated by other circuits in the batch configuration circuit, excluding the interrupt collector, indicating functional abnormalities of the other circuits; determine a second collection state for the third interrupt signals corresponding to the plurality of task execution circuits, and a third collection state for the fourth interrupt signals; in response to the second collection state and / or the third collection state indicating completion of collection for at least one of the task execution circuits, generate a fifth interrupt signal indicating that there is a functional abnormality in the plurality of task execution circuits and the batch configuration circuit; and report the fifth interrupt signal to the processor via the interrupt controller.

12. The chip according to claim 11, wherein, The processor is also configured to acquire third indication information indicating whether to mask the fifth interrupt signal; The second register is also used to acquire and store the third indication information from the processor; In response to the third indication information stored in the second register indicating that the fifth interrupt signal is not masked, the interrupt collector is used to report the fifth interrupt signal to the processor via the interrupt controller; In response to the third indication information stored in the second register indicating that the fifth interrupt signal is masked, the interrupt collector is configured to prevent the reporting of the second interrupt signal to the processor via the interrupt controller, and the processor is configured to obtain the fifth interrupt signal from the interrupt collector.

13. The chip according to claim 12, wherein, The processor is configured to respond to the fifth interrupt signal, obtain the second collection state and the third collection state corresponding to the plurality of task execution circuits respectively from the interrupt collector; and determine the target functional abnormal circuit among the plurality of task execution circuits and the batch configuration circuit based on the second collection state and the third collection state corresponding to the plurality of task execution circuits respectively. Obtain the abnormal details of the target functional abnormal circuit from the register corresponding to the target functional abnormal circuit.

14. A task execution method based on a chip that supports batch configuration registers, comprising: The processor in the chip acquires first indication information indicating multiple task execution circuits to participate in the target task, as well as task configuration information to be shared by the multiple task execution circuits. The first indication information and the task configuration information from the processor are obtained through the batch configuration circuit in the chip; Based on the first indication information and the task configuration information, the batch configuration circuit in the chip configures the first registers corresponding to the multiple task execution circuits respectively, so that the multiple task execution circuits can coordinately execute the target task.

15. A computer-readable storage medium storing a computer program that is executed by a processor to perform the task execution method based on a chip supporting bulk configuration registers as described in claim 14.

16. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the task execution method based on a chip supporting bulk configuration registers as described in claim 14.

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